From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Mar 2023 14:37:28 +0000 (+0000)
Subject: same reason for "`"s on pseudocode, Special Registers altered
X-Git-Tag: opf_rfc_ls001_v3~73
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8a619e1556e1e46e685bc707b807de7d86a0da8;p=libreriscv.git

same reason for "`"s on pseudocode, Special Registers altered
needs indentation
---

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 3ac1e719d..5483eb404 100644
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -154,7 +154,9 @@ operations.
 
 Special Registers altered:
 
+```
     CR0     (if Rc=1)
+```
 
 ----------
 
@@ -182,7 +184,9 @@ operations.
 
 Special Registers altered:
 
+```
     CR0     (if Rc=1)
+```
 
 ----------
 
@@ -212,7 +216,9 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
+```
 
 ----------
 
@@ -240,7 +246,9 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
+```
 
 ----------
 
@@ -305,8 +313,10 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
     FPCSR   (TODO: which bits?) (if IT[0]=1)
+```
 
 ### Assembly Aliases
 
@@ -368,8 +378,10 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
     FPCSR   (TODO: which bits?)
+```
 
 ### Assembly Aliases
 
@@ -654,9 +666,11 @@ that overflow.
 
 Special Registers altered:
 
+```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
     FPCSR   (TODO: which bits?)
+```
 
 ### Assembly Aliases
 
@@ -804,9 +818,11 @@ that overflow.
 
 Special Registers altered:
 
+```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
     FPCSR   (TODO: which bits?)
+```
 
 ### Assembly Aliases