From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 14 Sep 2020 13:46:36 +0000 (+0100)
Subject: rename plru input
X-Git-Tag: semi_working_ecp5~48
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8a808dd3beec2850dddbb86affa57535a6b3821;p=soc.git

rename plru input
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 25325c5b..a95e2842 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -660,7 +660,7 @@ class DCache(Elaboratable):
 
             comb += tlb_plru_acc_en.eq(r1.tlb_hit & (r1.tlb_hit_index == i))
             comb += tlb_plru.acc_en.eq(tlb_plru_acc_en)
-            comb += tlb_plru.acc.eq(r1.tlb_hit_way)
+            comb += tlb_plru.acc_i.eq(r1.tlb_hit_way)
             comb += tlb_plru_victim[i].eq(tlb_plru.lru_o)
 
     def tlb_search(self, m, tlb_req_index, r0, r0_valid,
@@ -774,7 +774,7 @@ class DCache(Elaboratable):
 
             comb += plru_acc_en.eq(r1.cache_hit & (r1.hit_index == i))
             comb += plru.acc_en.eq(plru_acc_en)
-            comb += plru.acc.eq(r1.hit_way)
+            comb += plru.acc_i.eq(r1.hit_way)
             comb += plru_victim[i].eq(plru.lru_o)
 
     def cache_tag_read(self, m, r0_stall, req_index, cache_tag_set, cache_tags):
diff --git a/src/soc/experiment/plru.py b/src/soc/experiment/plru.py
index c8a59b39..d2ba7232 100644
--- a/src/soc/experiment/plru.py
+++ b/src/soc/experiment/plru.py
@@ -8,7 +8,7 @@ class PLRU(Elaboratable):
 
     def __init__(self, BITS=2):
         self.BITS = BITS
-        self.acc = Signal(BITS)
+        self.acc_i = Signal(BITS)
         self.acc_en = Signal()
         self.lru_o = Signal(BITS)
 
@@ -43,7 +43,7 @@ class PLRU(Elaboratable):
                 node2 = Signal(self.BITS)
                 # report "GET: i:" & integer'image(i) & " node:" & 
                 # integer'image(node) & " val:" & Signal()'image(tree(node))
-                abit = self.acc[self.BITS-1-i]
+                abit = self.acc_i[self.BITS-1-i]
                 sync += tree[node].eq(~abit)
                 if i != self.BITS-1:
                     comb += node2.eq(node << 1)
@@ -56,7 +56,7 @@ class PLRU(Elaboratable):
         return m
 
     def ports(self):
-        return [self.acc_en, self.lru_o, self.acc]
+        return [self.acc_en, self.lru_o, self.acc_i]
 
 if __name__ == '__main__':
     dut = PLRU(3)