From: yimmanuel3@f4ac60d763911c3fa518755176e4b9ed455c75d8 <yimmanuel3@web>
Date: Sun, 2 Feb 2020 09:13:09 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3607
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8bb3d6aed1392bbb8950836852d20ea2ac612af;p=libreriscv.git

---

diff --git a/index.mdwn b/index.mdwn
index 7aafd82f9..75d2ee500 100644
--- a/index.mdwn
+++ b/index.mdwn
@@ -24,7 +24,7 @@ LibreSOC poses to you that it is impossible to trust a processor in a safety cri
 to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they 
 expect. An ISA level simulator is no longer satisfactory.
 
-Refer to this [IEEE_article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.
+Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.
 
 ## Still Have Questions?
 Read about the business and practical benefits of a LibreSOC below.