From: Dave Airlie Date: Mon, 5 Dec 2011 19:15:52 +0000 (+0000) Subject: radeon/r200: drop old span depth/stencil code. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8bbbcae4a22d97d1d1c22509fad423262324912;p=mesa.git radeon/r200: drop old span depth/stencil code. This is no longer used with the new renderbuffer code. Signed-off-by: Dave Airlie --- diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index b25779ecddb..ebacf8ec20f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -63,153 +63,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); - -/* r200 depth buffer is always tiled - this is the formula - according to the docs unless I typo'ed in it -*/ -#if defined(RADEON_R200) -static GLubyte *r200_depth_2byte(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset; - GLint offset; - if (rrb->has_surface) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - GLuint b; - offset = 0; - b = (((y >> 4) * (rrb->pitch >> 8) + (x >> 6))); - offset += (b >> 1) << 12; - offset += (((rrb->pitch >> 8) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11; - offset += ((y >> 2) & 0x3) << 9; - offset += ((x >> 3) & 0x1) << 8; - offset += ((x >> 4) & 0x3) << 6; - offset += ((x >> 2) & 0x1) << 5; - offset += ((y >> 1) & 0x1) << 4; - offset += ((x >> 1) & 0x1) << 3; - offset += (y & 0x1) << 2; - offset += (x & 0x1) << 1; - } - return &ptr[offset]; -} - -static GLubyte *r200_depth_4byte(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset; - GLint offset; - if (rrb->has_surface) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - GLuint b; - offset = 0; - b = (((y & 0x7ff) >> 4) * (rrb->pitch >> 7) + (x >> 5)); - offset += (b >> 1) << 12; - offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11; - offset += ((y >> 2) & 0x3) << 9; - offset += ((x >> 2) & 0x1) << 8; - offset += ((x >> 3) & 0x3) << 6; - offset += ((y >> 1) & 0x1) << 5; - offset += ((x >> 1) & 0x1) << 4; - offset += (y & 0x1) << 3; - offset += (x & 0x1) << 2; - } - return &ptr[offset]; -} -#endif - - -/* radeon tiling on r300-r500 has 4 states, - macro-linear/micro-linear - macro-linear/micro-tiled - macro-tiled /micro-linear - macro-tiled /micro-tiled - 1 byte surface - 2 byte surface - two types - we only provide 8x2 microtiling - 4 byte surface - 8/16 byte (unused) -*/ -static GLubyte *radeon_ptr_4byte(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - offset = ((y >> 4) * (rrb->pitch >> 7) + (x >> 5)) << 11; - offset += (((y >> 3) ^ (x >> 5)) & 0x1) << 10; - offset += (((y >> 4) ^ (x >> 4)) & 0x1) << 9; - offset += (((y >> 2) ^ (x >> 4)) & 0x1) << 8; - offset += (((y >> 3) ^ (x >> 3)) & 0x1) << 7; - offset += ((y >> 1) & 0x1) << 6; - offset += ((x >> 2) & 0x1) << 5; - offset += (y & 1) << 4; - offset += (x & 3) << 2; - } else { - offset = ((y >> 3) * (rrb->pitch >> 8) + (x >> 6)) << 11; - offset += (((y >> 2) ^ (x >> 6)) & 0x1) << 10; - offset += (((y >> 3) ^ (x >> 5)) & 0x1) << 9; - offset += (((y >> 1) ^ (x >> 5)) & 0x1) << 8; - offset += (((y >> 2) ^ (x >> 4)) & 0x1) << 7; - offset += (y & 1) << 6; - offset += (x & 15) << 2; - } - } else { - offset = ((y >> 1) * (rrb->pitch >> 4) + (x >> 2)) << 5; - offset += (y & 1) << 4; - offset += (x & 3) << 2; - } - } - return &ptr[offset]; -} - -static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - offset = ((y >> 4) * (rrb->pitch >> 7) + (x >> 6)) << 11; - offset += (((y >> 3) ^ (x >> 6)) & 0x1) << 10; - offset += (((y >> 4) ^ (x >> 5)) & 0x1) << 9; - offset += (((y >> 2) ^ (x >> 5)) & 0x1) << 8; - offset += (((y >> 3) ^ (x >> 4)) & 0x1) << 7; - offset += ((y >> 1) & 0x1) << 6; - offset += ((x >> 3) & 0x1) << 5; - offset += (y & 1) << 4; - offset += (x & 3) << 2; - } else { - offset = ((y >> 3) * (rrb->pitch >> 8) + (x >> 7)) << 11; - offset += (((y >> 2) ^ (x >> 7)) & 0x1) << 10; - offset += (((y >> 3) ^ (x >> 6)) & 0x1) << 9; - offset += (((y >> 1) ^ (x >> 6)) & 0x1) << 8; - offset += (((y >> 2) ^ (x >> 5)) & 0x1) << 7; - offset += (y & 1) << 6; - offset += ((x >> 4) & 0x1) << 5; - offset += (x & 15) << 2; - } - } else { - offset = ((y >> 1) * (rrb->pitch >> 4) + (x >> 3)) << 5; - offset += (y & 0x1) << 4; - offset += (x & 0x7) << 1; - } - } - return &ptr[offset]; -} - /* * Note that all information needed to access pixels in a renderbuffer * should be obtained through the gl_renderbuffer parameter, not per-context @@ -225,16 +78,6 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb, GLuint p; \ (void)p; -#define LOCAL_DEPTH_VARS \ - struct radeon_renderbuffer *rrb = (void *) rb; \ - int minx = 0, miny = 0; \ - const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \ - const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1; \ - int maxx = rb->Width; \ - int maxy = rb->Height; - -#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS - #define Y_FLIP(_y) (_y) #define HW_LOCK() @@ -320,166 +163,6 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb, #define TAG2(x,y) radeon##x##_BGRA8888##y #include "spantmp2.h" -#undef Y_FLIP -#define Y_FLIP(_y) ((_y) * yScale + yBias) -/* ================================================================ - * Depth buffer - */ - -/* The Radeon family has depth tiling on all the time, so we have to convert - * the x,y coordinates into the memory bus address (mba) in the same - * manner as the engine. In each case, the linear block address (ba) - * is calculated, and then wired with x and y to produce the final - * memory address. - * The chip will do address translation on its own if the surface registers - * are set up correctly. It is not quite enough to get it working with hyperz - * too... - */ - -/* 16-bit depth buffer functions - */ -#define VALUE_TYPE GLushort - -#if defined(RADEON_R200) -#define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)r200_depth_2byte(rrb, _x, _y) = d -#else -#define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x, _y) = d -#endif - -#if defined(RADEON_R200) -#define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)r200_depth_2byte(rrb, _x, _y) -#else -#define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x, _y) -#endif - -#define TAG(x) radeon##x##_z16 -#include "depthtmp.h" - -/* 24 bit depth - * - * Careful: It looks like the R300 uses ZZZS byte order while the R200 - * uses SZZZ for 24 bit depth, 8 bit stencil mode. - */ -#define VALUE_TYPE GLuint - -#if defined(RADEON_R200) -#define WRITE_DEPTH( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x, _y ); \ - GLuint tmp = LE32_TO_CPU(*_ptr); \ - tmp &= 0xff000000; \ - tmp |= ((d) & 0x00ffffff); \ - *_ptr = CPU_TO_LE32(tmp); \ -} while (0) -#else -#define WRITE_DEPTH( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x, _y ); \ - GLuint tmp = LE32_TO_CPU(*_ptr); \ - tmp &= 0xff000000; \ - tmp |= ((d) & 0x00ffffff); \ - *_ptr = CPU_TO_LE32(tmp); \ -} while (0) -#endif - -#if defined(RADEON_R200) -#define READ_DEPTH( d, _x, _y ) \ - do { \ - d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x, _y))) & 0x00ffffff; \ - }while(0) -#else -#define READ_DEPTH( d, _x, _y ) \ - d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x, _y))) & 0x00ffffff; -#endif - -#define TAG(x) radeon##x##_z24 -#include "depthtmp.h" - -/* 24 bit depth, 8 bit stencil depthbuffer functions - * EXT_depth_stencil - * - * Careful: It looks like the R300 uses ZZZS byte order while the R200 - * uses SZZZ for 24 bit depth, 8 bit stencil mode. - */ -#define VALUE_TYPE GLuint - -#if defined(RADEON_R200) -#define WRITE_DEPTH( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x, _y ); \ - *_ptr = CPU_TO_LE32(d); \ -} while (0) -#else -#define WRITE_DEPTH( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x, _y ); \ - *_ptr = CPU_TO_LE32(d); \ -} while (0) -#endif - -#if defined(RADEON_R200) -#define READ_DEPTH( d, _x, _y ) \ - do { \ - d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x, _y))); \ - }while(0) -#else -#define READ_DEPTH( d, _x, _y ) do { \ - d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x, _y))); \ - } while (0) -#endif - -#define TAG(x) radeon##x##_s8_z24 -#include "depthtmp.h" - -/* ================================================================ - * Stencil buffer - */ - -/* 24 bit depth, 8 bit stencil depthbuffer functions - */ -#if defined(RADEON_R200) -#define WRITE_STENCIL( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)r200_depth_4byte(rrb, _x, _y); \ - GLuint tmp = LE32_TO_CPU(*_ptr); \ - tmp &= 0x00ffffff; \ - tmp |= (((d) & 0xff) << 24); \ - *_ptr = CPU_TO_LE32(tmp); \ -} while (0) -#else -#define WRITE_STENCIL( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x, _y); \ - GLuint tmp = LE32_TO_CPU(*_ptr); \ - tmp &= 0x00ffffff; \ - tmp |= (((d) & 0xff) << 24); \ - *_ptr = CPU_TO_LE32(tmp); \ -} while (0) -#endif - -#if defined(RADEON_R200) -#define READ_STENCIL( d, _x, _y ) \ -do { \ - GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x, _y ); \ - GLuint tmp = LE32_TO_CPU(*_ptr); \ - d = (tmp & 0xff000000) >> 24; \ -} while (0) -#else -#define READ_STENCIL( d, _x, _y ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x, _y ); \ - GLuint tmp = LE32_TO_CPU(*_ptr); \ - d = (tmp & 0xff000000) >> 24; \ -} while (0) -#endif - -#define TAG(x) radeon##x##_s8_z24 -#include "stenciltmp.h" - static void radeon_renderbuffer_map(struct gl_context *ctx, struct gl_renderbuffer *rb) {