From: lkcl <lkcl@web>
Date: Sat, 24 Sep 2022 22:58:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8f32a8b4205ca4c8f572893a7b7b6f85ade3ad6;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 56dc90cd2..642e9e8d1 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -974,6 +974,7 @@ Element-width overrides are best illustrated with a packed structure
 union in the c programming language.  The following should be taken
 literally, and assume always a little-endian layout:
 
+    #pragma pack
     typedef union {
         uint8_t  b[];
         uint16_t s[];
@@ -987,6 +988,8 @@ literally, and assume always a little-endian layout:
     get_polymorphed_reg(reg, bitwidth, offset):
         el_reg_t res;
         res.l = 0; // TODO: going to need sign-extending / zero-extending
+        if !reg.isvec: // scalar has no element offset
+            offset = 0
         if bitwidth == 8:
             reg.b = int_regfile[reg].b[offset]
         elif bitwidth == 16:
@@ -995,11 +998,16 @@ literally, and assume always a little-endian layout:
             reg.i = int_regfile[reg].i[offset]
         elif bitwidth == 64:
             reg.l = int_regfile[reg].l[offset]
-        return res
+        return res & bytemask
 
     set_polymorphed_reg(reg, bitwidth, offset, val):
         if (!reg.isvec):
-            # not a vector: first element only, overwrites high bits
+            # for safety mask out hi bits
+            bytemask = (8 << bitwidth) - 1
+            val &= bytemask
+            # not a vector: first element only, overwrites high bits.
+            # and with the *Architectural* definition being LE,
+            # storing in the first DWORD works perfectly.
             int_regfile[reg].l[0] = val
         elif bitwidth == 8:
             int_regfile[reg].b[offset] = val