From: Nicolai Hähnle Date: Thu, 17 Mar 2016 01:47:47 +0000 (-0500) Subject: radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8f5d11426af0eeadf6977c3d8f3a76afe8f03c5;p=mesa.git radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2) This fixes arb_shader_image_load_store-host-mem-barrier. v2: flush TC L2 for index buffers on <= CIK (Marek) Reviewed-by: Edward O'Callaghan Reviewed-by: Marek Olšák --- diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index b8fde00c668..1245f56c08a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3537,18 +3537,28 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) if (flags & (PIPE_BARRIER_VERTEX_BUFFER | PIPE_BARRIER_SHADER_BUFFER | PIPE_BARRIER_TEXTURE | - PIPE_BARRIER_IMAGE)) { + PIPE_BARRIER_IMAGE | + PIPE_BARRIER_STREAMOUT_BUFFER)) { /* As far as I can tell, L1 contents are written back to L2 * automatically at end of shader, but the contents of other * L1 caches might still be stale. */ sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1; } + if (flags & PIPE_BARRIER_INDEX_BUFFER) { + sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1; + + /* Indices are read through TC L2 since VI. */ + if (sctx->screen->b.chip_class <= CIK) + sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; + } + if (flags & PIPE_BARRIER_FRAMEBUFFER) sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; if (flags & (PIPE_BARRIER_MAPPED_BUFFER | - PIPE_BARRIER_FRAMEBUFFER)) { + PIPE_BARRIER_FRAMEBUFFER | + PIPE_BARRIER_INDIRECT_BUFFER)) { /* Not sure if INV_GLOBAL_L2 is the best thing here. * * We need to make sure that TC L1 & L2 are written back to