From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 Apr 2022 19:38:47 +0000 (+0100)
Subject: remove soc builder
X-Git-Tag: opf_rfc_ls005_v1~2592
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8f9dc259dbbf4148a6bd35ceefb22f8023f8faa;p=libreriscv.git

remove soc builder
---

diff --git a/resources.mdwn b/resources.mdwn
index 3d9a4a93f..70d87fac3 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -349,10 +349,6 @@ Some learning resources I found in the community:
 # Python RTL Tools
 
 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
-* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
-  An SOC builder written in Python Migen DSL. Allows you to generate functional
-  RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
-  and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
 * There is a great guy, Robert Baruch, who has a good
   [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.