From: Gabriel Somlo Date: Tue, 10 Mar 2020 23:45:45 +0000 (-0400) Subject: integration/soc: add_ethernet: honor self.map["ethmac"], if present X-Git-Tag: 24jan2021_ls180~565^2~1^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9040348117061cdc40b014d6453c1e1ae7ee8bc;p=litex.git integration/soc: add_ethernet: honor self.map["ethmac"], if present Signed-off-by: Gabriel Somlo --- diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index c8abc75a..aade79db 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1044,7 +1044,8 @@ class LiteXSoC(SoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - ethmac_region = SoCRegion(size=0x2000, cached=False) + ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), + size=0x2000, cached=False) self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) self.add_csr("ethmac") self.add_interrupt("ethmac")