From: lkcl <lkcl@web>
Date: Sat, 11 Jun 2022 16:24:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1849
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a914eba1a58db63451b35cdbc613a9904ea95a11;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 2aaa8504a..adc9d1ae9 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -17,6 +17,11 @@ swizzle as well as constants 1/1.0 and 0/0.0
 
 **As a Scalar instruction**
 
+Given that XYZW Swizzle can select simultaneously between one *and four*
+register operands, a full version of this instruction would
+be an eye-popping 8 64-bit operands: 4-in, 4-out. As part of a Scalar
+ISA this not practical. A compromise is to cut the registers required
+by half.
 When part of the Scalar Power ISA (not SVP64 Vectorised)
 mv.swiz and fmv.swiz operate on four 32-bit
 quantities, reducing this instruction to 2-in, 2-out pairs of 64-bit
@@ -37,19 +42,20 @@ When RA!=RT any part of RT or RT+1 not set as a destination by
 the Swizzle will be set to zero.  A Swizzle of "..XY" would
 copy the contents RA+1 into RT, but set RT+1 to zero.
 
-When (RA,RA+1) overlaps with (RT,RT+1) and RA!=RT, the results
-are `UNDEFINED`.
+Also, making life easier, RT and RA are only permitted to be even
+(no overlapping can occur).  This makes RT (and RA) a "pair" exactly
+like `lq` and `stq`
 
 **SVP64 Vectorised**
 
-When Vectorised, TODO
+When Vectorised, the 
 
 # Format
 
 | 0.5 |6.10|11.15|16.27|28.31|  name        |
 |-----|----|-----|-----|-----|--------------|
-|PO   | RT | RA  |imm  | 0011| mv.swiz      |
-|PO   | RT | RA  |imm  | 1011| fmv.swiz     |
+|PO   | RTp| RAp |imm  | 0011| mv.swiz      |
+|PO   | RTp| RAp |imm  | 1011| fmv.swiz     |
 
 this gives a 12 bit immediate across bits 16 to 25 and 29-30.