From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 17:27:55 +0000 (-0700)
Subject: Add some more comments
X-Git-Tag: yosys-0.9~75
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a91ea6612a73568782c80bd12ce2875353e2b5c5;p=yosys.git

Add some more comments
---

diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index e56d0fa80..f52eb4ac1 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -2,9 +2,14 @@
 
 set -e
 
+# NB: *.aag and *.aig must contain a symbol table naming the primary
+#     inputs and outputs, otherwise ABC and Yosys will name them
+#     arbitrarily (and inconsistently with each other).
+
 for aag in *.aag; do
     # Since ABC cannot read *.aag, read the *.aig instead
-    # (which would have been created by the reference aig2aig utility)
+    # (which would have been created by the reference aig2aig utility,
+    #  available from http://fmv.jku.at/aiger/)
     ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
     ../../yosys -p "
 read_verilog ${aag%.*}_ref.v