From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 25 Mar 2015 18:46:12 +0000 (+0100)
Subject: Ignore celldefine directive in verilog front-end
X-Git-Tag: yosys-0.6~369
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a923a63a892b8f0c39aa740c8fe207462fe2d8c8;p=yosys.git

Ignore celldefine directive in verilog front-end
---

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 3a57514aa..8fbaa953d 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -116,6 +116,9 @@ YOSYS_NAMESPACE_END
 
 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
 
+"`celldefine"[^\n]* /* ignore `celldefine */
+"`endcelldefine"[^\n]* /* ignore `endcelldefine */
+
 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
 	char *p = yytext;
 	while (*p != 0 && *p != ' ' && *p != '\t') p++;