From: Florent Kermarrec Date: Thu, 18 Apr 2019 16:42:29 +0000 (+0200) Subject: soc/interconnect: add avalon with converters to/from native streams X-Git-Tag: 24jan2021_ls180~1325 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a92e90b215326cb2c5d2761fde641df14a6a5d7a;p=litex.git soc/interconnect: add avalon with converters to/from native streams --- diff --git a/litex/soc/interconnect/avalon.py b/litex/soc/interconnect/avalon.py new file mode 100644 index 00000000..edc2f6f1 --- /dev/null +++ b/litex/soc/interconnect/avalon.py @@ -0,0 +1,38 @@ +from migen import * + +from litex.soc.interconnect import stream + +# AvalonST to/from Native -------------------------------------------------------------------------- + +class Native2AvalonST(Module): + def __init__(self, layout, latency=2): + self.sink = sink = stream.Endpoint(layout) + self.source = source = stream.Endpoint(layout) + + # # # + + _from = sink + for n in range(latency): + _to = stream.Endpoint(layout) + self.sync += _from.connect(_to, omit={"ready"}) + if n == 0: + self.sync += _to.valid.eq(sink.valid & source.ready) + _from = _to + self.comb += _to.connect(source, omit={"ready"}) + self.comb += sink.ready.eq(source.ready) + + +class AvalonST2Native(Module): + def __init__(self, layout, latency=2): + self.sink = sink = stream.Endpoint(layout) + self.source = source = stream.Endpoint(layout) + + # # # + + buf = stream.SyncFIFO(layout, max(latency, 4)) + self.submodules += buf + self.comb += [ + sink.connect(buf.sink, omit={"ready"}), + sink.ready.eq(source.ready), + buf.source.connect(source) + ]