From: Javier Setoain <javier.setoain@arm.com>
Date: Thu, 14 Mar 2019 17:42:44 +0000 (+0000)
Subject: arch-arm: Fix use of bitwise operators on booleans
X-Git-Tag: v19.0.0.0~1003
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a93fe3f3cf2b2ad7b0c5b9916bc705a579ca231c;p=gem5.git

arch-arm: Fix use of bitwise operators on booleans

Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f63..647ceafe3 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3182,9 +3182,9 @@ let {{
     sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
                PredType.MERGE, True)
     # BIC (vectors, unpredicated)
-    bicCode = 'destElem = srcElem1 & ~srcElem2;'
     sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
     # BIC, BICS (predicates)
+    bicCode = 'destElem = srcElem1 && !srcElem2;'
     svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
                        bicCode)
     svePredLogicalInst('bics', 'PredBics', 'SimdPredAluOp', ('uint8_t',),