From: lkcl <lkcl@web>
Date: Wed, 4 Sep 2019 16:29:30 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4160
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a949ec920a1a2a1b69f431d87580ef3715e1b2e4;p=libreriscv.git

---

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index 9ddbf4a1b..413dcd5dc 100644
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -1,15 +1,15 @@
 # Simple-V (Parallelism Extension Proposal) Vector Block Format
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
-* Status: DRAFTv0.7
-* Last edited: 30 aug 2019
+* Status: DRAFTv0.7.1
+* Last edited: 2 sep 2019
 
 [[!toc ]]
 
 # Vector Block Format <a name="vliw-format"></a>
 
 This is a way to give Vector and Predication Context to a group of
-standard scalar RISC-V instructions, in a highly compact form.
+standard scalar RISC-V instructions, in a highly compact form. Program Execution Order is still preserved (unlike VLIW), just with "context" that would otherwise require much longer instructions.
 
 The format is: