From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Jan 2020 18:08:48 +0000 (-0800)
Subject: abc9: error out if flip-flop init is 1'b1 for '-dff'
X-Git-Tag: working-ls180~857^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a94b41011d5ec9514739c52b963e0bd96890973f;p=yosys.git

abc9: error out if flip-flop init is 1'b1 for '-dff'

Due to ABC sequential synthesis restriction
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index b0e2c7697..2568a6cd1 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1069,6 +1069,8 @@ struct Abc9Pass : public Pass {
 					SigSpec abc9_init = assign_map(abc9_init_wire);
 					if (!abc9_init.is_fully_const())
 						log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+					if (abc9_init == State::S1)
+						log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module));
 					r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
 					log_assert(r2.second);
 				}