From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Jul 2020 09:29:58 +0000 (+0100)
Subject: reduce number of FastRegs read ports
X-Git-Tag: semi_working_ecp5~637
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9535d3263f0cf26513d1db4ba29cb9d433d84f4;p=soc.git

reduce number of FastRegs read ports
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index be47754e..7bcf5c9c 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -73,13 +73,12 @@ class FastRegs(RegFileArray):
                         'msr': self.write_port("dest2"),
                         'fast1': self.write_port("dest3"),
                         'fast2': self.write_port("dest4"),
-                        'd_wr1': self.write_port("d_wr1")} # writing PC
-        self.r_ports = {'cia': self.read_port("src1"),
-                        'msr': self.read_port("src2"),
-                        'fast1': self.read_port("src3"),
-                        'fast2': self.read_port("src4"),
-                        'd_rd1': self.read_port("d_rd1"), # reading PC
-                        'd_rd2': self.read_port("d_rd2")} # reading MSR
+                        'd_wr1': self.write_port("d_wr1")} # writing PC (issuer)
+        self.r_ports = {'cia': self.read_port("cia"), # reading PC (issuer)
+                        'msr': self.read_port("msr"), # reading MSR (issuer)
+                        'fast1': self.read_port("src1"),
+                        'fast2': self.read_port("src2"),
+                        }
 
 
 # CR Regfile
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 10f45586..38f94077 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -56,9 +56,9 @@ class TestIssuer(Elaboratable):
         self.memerr_o = Signal(reset_less=True)
 
         # FAST regfile read /write ports for PC and MSR
-        self.fast_r_pc = self.core.regs.rf['fast'].r_ports['d_rd1'] # PC rd
+        self.fast_r_pc = self.core.regs.rf['fast'].r_ports['cia'] # PC rd
         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
-        self.fast_r_msr = self.core.regs.rf['fast'].r_ports['d_rd2'] # MSR rd
+        self.fast_r_msr = self.core.regs.rf['fast'].r_ports['msr'] # MSR rd
 
         # hack method of keeping an eye on whether branch/trap set the PC
         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']