From: Claudiu Zissulescu Date: Wed, 25 Jul 2018 14:31:16 +0000 (+0200) Subject: [ARC] Improve instruction selection for fp moves. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a96377575b546f2207c83906c68683af30fe92f7;p=gcc.git [ARC] Improve instruction selection for fp moves. Improve selection of short instruction for fp-moves. gcc/ 2018-05-17 Claudiu Zissulescu * config/arc/arc.md (movsf_insn): Add short instruction selection. * config/arc/constraints.md (CfZ): New constraint. * config/arc/fpu.md (addssf3_fpu): Use CfZ constraint. (subsf3_fpu): Likewise. (cmpsf_fpu): Likewise. (cmpsf_fpu_uneq): Likewise. From-SVN: r262971 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index db3d91bf22c..5bc31a3e2cb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2018-07-25 Claudiu Zissulescu + + * config/arc/arc.md (movsf_insn): Add short instruction selection. + * config/arc/constraints.md (CfZ): New constraint. + * config/arc/fpu.md (addssf3_fpu): Use CfZ constraint. + (subsf3_fpu): Likewise. + (cmpsf_fpu): Likewise. + (cmpsf_fpu_uneq): Likewise. + 2018-07-25 Claudiu Zissulescu * config/arc/arc.c (compact_memory_operand_p): Check for uncached diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index bfadbee6d85..181a738f3ab 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1294,19 +1294,24 @@ archs4x, archs4xd, archs4xd_slow" "if (prepare_move_operands (operands, SFmode)) DONE;") (define_insn "*movsf_insn" - [(set (match_operand:SF 0 "move_dest_operand" "=h,w,w,r,m") - (match_operand:SF 1 "move_src_operand" "hCm1,c,E,m,c"))] + [(set (match_operand:SF 0 "move_dest_operand" "=h,h, r,r, q,S,Usc,r,m") + (match_operand:SF 1 "move_src_operand" "hCfZ,E,rCfZ,E,Uts,q, E,m,r"))] "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)" "@ - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 ; %A1 - ld%U1%V1 %0,%1 - st%U0%V0 %1,%0" - [(set_attr "type" "move,move,move,load,store") - (set_attr "predicable" "no,yes,yes,no,no") - (set_attr "iscompact" "true,false,false,false,false")]) + mov%?\\t%0,%1 + mov%?\\t%0,%1 ; %A1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 ; %A1 + ld%?%U1\\t%0,%1 + st%?\\t%1,%0 + st%U0%V0\\t%1,%0 + ld%U1%V1\\t%0,%1 + st%U0%V0\\t%1,%0" + [(set_attr "type" "move,move,move,move,load,store,store,load,store") + (set_attr "predicable" "no,no,yes,yes,no,no,no,no,no") + (set_attr "length" "*,*,4,*,*,*,*,*,*") + (set_attr "iscompact" "true,true_limm,false,false,true,true,false,false,false")]) (define_expand "movdf" [(set (match_operand:DF 0 "move_dest_operand" "") diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 90c736e1be4..61b1d3f57c2 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -321,6 +321,12 @@ (and (match_code "const_double") (match_test "1"))) +(define_constraint "CfZ" + "@internal + Match a floating-point zero" + (and (match_code "const_double") + (match_test "op == CONST0_RTX (SFmode)"))) + ;; Memory constraints (define_memory_constraint "T" "@internal diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md index 9457922667e..6289e9c3f59 100644 --- a/gcc/config/arc/fpu.md +++ b/gcc/config/arc/fpu.md @@ -6,34 +6,34 @@ ;; Addition (define_insn "*addsf3_fpu" - [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") - (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F") - (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] + [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r") + (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r, r,0,r,F") + (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))] "TARGET_FP_SP_BASE && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsadd%? %0,%1,%2" - [(set_attr "length" "4,4,8,8,8") + "fsadd%?\\t%0,%1,%2" + [(set_attr "length" "4,4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu") - (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") + (set_attr "predicable" "yes,no,no,yes,no,no") + (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") ]) ;; Subtraction (define_insn "*subsf3_fpu" - [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") - (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r,0,r,F") - (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] + [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r") + (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r, r,0,r,F") + (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))] "TARGET_FP_SP_BASE && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fssub%? %0,%1,%2" - [(set_attr "length" "4,4,8,8,8") + "fssub%?\\t%0,%1,%2" + [(set_attr "length" "4,4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu") - (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") + (set_attr "predicable" "yes,no,no,yes,no,no") + (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") ]) ;; Multiplication @@ -44,7 +44,7 @@ "TARGET_FP_SP_BASE && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsmul%? %0,%1,%2" + "fsmul%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu") @@ -108,7 +108,7 @@ "TARGET_FP_SP_FUSED && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsmsub%? %0,%1,%2" + "fsmsub%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "predicable" "yes,no,yes,no,no") (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") @@ -178,7 +178,7 @@ (match_operand:DF 2 "even_register_operand" "r,r") (reg:DF ARCV2_ACC)))] "TARGET_FP_DP_FUSED" - "fdmadd%? %0,%1,%2" + "fdmadd%?\\t%0,%1,%2" [(set_attr "length" "4,4") (set_attr "predicable" "yes,no") (set_attr "cond" "canuse,nocond") @@ -191,7 +191,7 @@ (match_operand:DF 2 "even_register_operand" "r,r") (reg:DF ARCV2_ACC)))] "TARGET_FP_DP_FUSED" - "fdmsub%? %0,%1,%2" + "fdmsub%?\\t%0,%1,%2" [(set_attr "length" "4,4") (set_attr "predicable" "yes,no") (set_attr "cond" "canuse,nocond") @@ -206,7 +206,7 @@ "TARGET_FP_SP_SQRT && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsdiv%? %0,%1,%2" + "fsdiv%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu_sdiv") @@ -225,31 +225,31 @@ [(set (match_operand:SF 0 "register_operand" "=r,r") (sqrt:SF (match_operand:SF 1 "nonmemory_operand" "r,F")))] "TARGET_FP_SP_SQRT" - "fssqrt %0,%1" + "fssqrt\\t%0,%1" [(set_attr "length" "4,8") (set_attr "type" "fpu_sdiv")]) ;; Comparison (define_insn "*cmpsf_fpu" [(set (reg:CC_FPU CC_REG) - (compare:CC_FPU (match_operand:SF 0 "register_operand" "r,r") - (match_operand:SF 1 "nonmemory_operand" "r,F")))] + (compare:CC_FPU (match_operand:SF 0 "register_operand" "r, r,r") + (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] "TARGET_FP_SP_BASE" - "fscmp%? %0, %1" - [(set_attr "length" "4,8") + "fscmp%?\\t%0,%1" + [(set_attr "length" "4,4,8") (set_attr "iscompact" "false") (set_attr "cond" "set") (set_attr "type" "fpu") - (set_attr "predicable" "yes,yes")]) + (set_attr "predicable" "yes")]) (define_insn "*cmpsf_fpu_uneq" [(set (reg:CC_FPU_UNEQ CC_REG) (compare:CC_FPU_UNEQ - (match_operand:SF 0 "register_operand" "r,r") - (match_operand:SF 1 "nonmemory_operand" "r,F")))] + (match_operand:SF 0 "register_operand" "r, r,r") + (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] "TARGET_FP_SP_BASE" - "fscmp %0, %1\\n\\tmov.v.f 0,0\\t;set Z flag" - [(set_attr "length" "8,12") + "fscmp\\t%0,%1\\n\\tmov.v.f\\t0,0\\t;set Z flag" + [(set_attr "length" "8,8,12") (set_attr "iscompact" "false") (set_attr "cond" "set") (set_attr "type" "fpu")]) @@ -274,7 +274,6 @@ (set_attr "cond" "canuse,nocond") ]) - ;; Subtraction (define_insn "*subdf3_fpu" [(set (match_operand:DF 0 "even_register_operand" "=r,r")