From: Richard Sandiford <rsandifo@redhat.com>
Date: Fri, 28 May 2004 10:04:48 +0000 (+0000)
Subject: mips.md (extendsidi2): Tie the source and destination of the register alternative.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a97a3e73b5f3d0bde5350da0ffad08aa1572d3c1;p=gcc.git

mips.md (extendsidi2): Tie the source and destination of the register alternative.

	* config/mips/mips.md (extendsidi2): Tie the source and destination
	of the register alternative.  Split it into nothing.

From-SVN: r82359
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 618d6d4dc2d..31f9531ec62 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-05-28  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/mips/mips.md (extendsidi2): Tie the source and destination
+	of the register alternative.  Split it into nothing.
+
 2004-05-28  Richard Sandiford  <rsandifo@redhat.com>
 
 	* rtl.h (skip_consecutive_labels): Declare.
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 022562ddc85..3235ff58e99 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3405,16 +3405,29 @@ dsrl\t%3,%3,1\n\
 ;; Extension insns.
 ;; Those for integer source operand are ordered widest source type first.
 
-(define_insn "extendsidi2"
+;; When TARGET_64BIT, all SImode integer registers should already be in
+;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2).  We can
+;; therefore get rid of register->register instructions if we constrain
+;; the source to be in the same register as the destination.
+;;
+;; The register alternative has type "arith" so that the pre-reload
+;; scheduler will treat it as a move.  This reflects what happens if
+;; the register alternative needs a reload.
+(define_insn_and_split "extendsidi2"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
   "TARGET_64BIT"
   "@
-   sll\t%0,%1,0
+   #
    lw\t%0,%1"
-  [(set_attr "type" "shift,load")
-   (set_attr "mode" "DI")
-   (set_attr "extended_mips16" "yes,*")])
+  "&& reload_completed && register_operand (operands[1], VOIDmode)"
+  [(const_int 0)]
+{
+  emit_note (NOTE_INSN_DELETED);
+  DONE;
+}
+  [(set_attr "type" "arith,load")
+   (set_attr "mode" "DI")])
 
 ;; These patterns originally accepted general_operands, however, slightly
 ;; better code is generated by only accepting register_operands, and then