From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 21:35:40 +0000 (-0700)
Subject: Add CLKPOL == 0
X-Git-Tag: working-ls180~1085^2~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a980f0d4be218040ee2ecf42186583e416f82d91;p=yosys.git

Add CLKPOL == 0
---

diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index a4a893307..4a3a30f83 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -64,6 +64,8 @@ void reduce_chain(xilinx_srl_pm &pm)
 		c->setParam(ID(INIT), initval.as_const());
 		if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
 			c->setParam(ID(CLKPOL), 1);
+		else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
+			c->setParam(ID(CLKPOL), 0);
 		else
 			log_abort();
 		if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))