From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 9 May 2015 14:24:28 +0000 (+0200)
Subject: uart: rename wishbone to bridge
X-Git-Tag: 24jan2021_ls180~2252
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a99aa9c7fd56e97ebb316ac9b83440f522a622ad;p=litex.git

uart: rename wishbone to bridge
---

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index 99b117c8..14c9cbfa 100644
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
index c4c9e550..90f3ec88 100644
--- a/misoclib/com/litepcie/example_designs/targets/dma.py
+++ b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -7,7 +7,7 @@ from migen.genlib.misc import timeline
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint
diff --git a/misoclib/com/uart/bridge.py b/misoclib/com/uart/bridge.py
new file mode 100644
index 00000000..fc0d292e
--- /dev/null
+++ b/misoclib/com/uart/bridge.py
@@ -0,0 +1,9 @@
+from migen.fhdl.std import *
+
+from misoclib.tools.wishbone import WishboneStreamingBridge
+from misoclib.com.uart.phy.serial import UARTPHYSerial
+
+class UARTWishboneBridge(WishboneStreamingBridge):
+    def __init__(self, pads, clk_freq, baudrate=115200):
+        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
+        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
diff --git a/misoclib/com/uart/wishbone.py b/misoclib/com/uart/wishbone.py
deleted file mode 100644
index fc0d292e..00000000
--- a/misoclib/com/uart/wishbone.py
+++ /dev/null
@@ -1,9 +0,0 @@
-from migen.fhdl.std import *
-
-from misoclib.tools.wishbone import WishboneStreamingBridge
-from misoclib.com.uart.phy.serial import UARTPHYSerial
-
-class UARTWishboneBridge(WishboneStreamingBridge):
-    def __init__(self, pads, clk_freq, baudrate=115200):
-        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
-        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py
index ce7d53a1..60f7fcd9 100644
--- a/misoclib/mem/litesata/example_designs/targets/bist.py
+++ b/misoclib/mem/litesata/example_designs/targets/bist.py
@@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.mem.litesata.common import *
 from misoclib.mem.litesata.phy import LiteSATAPHY
diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index 26853f7e..f9246053 100644
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 class LiteScopeSoC(SoC, AutoCSR):
     csr_map = {