From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 27 Jan 2012 21:20:57 +0000 (+0100)
Subject: Remove explicit bus names and rely on the new automatic namer
X-Git-Tag: 24jan2021_ls180~2099^2~1048
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a99c2acfa8264e6695163b95912ac950d0eed0ca;p=litex.git

Remove explicit bus names and rely on the new automatic namer
---

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 740fcb30..4443cda3 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -10,12 +10,12 @@ _desc = [
 ]
 
 class Master(Simple):
-	def __init__(self, name=""):
-		Simple.__init__(self, _desc, False, name)
+	def __init__(self):
+		Simple.__init__(self, _desc, False)
 
 class Slave(Simple):
-	def __init__(self, name=""):
-		Simple.__init__(self, _desc, True, name)
+	def __init__(self):
+		Simple.__init__(self, _desc, True)
 
 class Interconnect:
 	def __init__(self, master, slaves):
diff --git a/migen/bus/simple.py b/migen/bus/simple.py
index e7dcc52b..4340f682 100644
--- a/migen/bus/simple.py
+++ b/migen/bus/simple.py
@@ -12,12 +12,10 @@ def get_sig_name(signal, slave):
 # 1) string: name
 # 2) int: width
 class Simple():
-	def __init__(self, desc, slave, name):
+	def __init__(self, desc, slave):
 		for signal in desc:
 			modules = self.__module__.split('.')
 			busname = modules[len(modules)-1]
-			if name:
-				busname += "_" + name
 			signame = get_sig_name(signal, slave)
 			setattr(self, signame, Signal(BV(signal[2]), busname + "_" + signame))
 	
diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index 041894b1..fa1ce454 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -18,12 +18,12 @@ _desc = [
 ]
 
 class Master(Simple):
-	def __init__(self, name=""):
-		Simple.__init__(self, _desc, False, name)
+	def __init__(self):
+		Simple.__init__(self, _desc, False)
 
 class Slave(Simple):
-	def __init__(self, name=""):
-		Simple.__init__(self, _desc, True, name)
+	def __init__(self):
+		Simple.__init__(self, _desc, True)
 
 class Arbiter:
 	def __init__(self, masters, target):
@@ -127,7 +127,7 @@ class Decoder:
 
 class InterconnectShared:
 	def __init__(self, masters, slaves, offset=0, register=False):
-		self._shared = Master("shr")
+		self._shared = Master()
 		self._arbiter = Arbiter(masters, self._shared)
 		self._decoder = Decoder(self._shared, slaves, offset, register)
 		self.addresses = self._decoder.addresses
diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py
index a0cd5629..362cce49 100644
--- a/migen/bus/wishbone2csr.py
+++ b/migen/bus/wishbone2csr.py
@@ -5,8 +5,8 @@ from migen.corelogic import timeline
 
 class WB2CSR():
 	def __init__(self):
-		self.wishbone = wishbone.Slave("to_csr")
-		self.csr = csr.Master("from_wishbone")
+		self.wishbone = wishbone.Slave()
+		self.csr = csr.Master()
 		self.timeline = timeline.Timeline(self.wishbone.cyc_i & self.wishbone.stb_i,
 			[(1, [self.csr.we_o.eq(self.wishbone.we_i)]),
 			(2, [self.wishbone.ack_o.eq(1)]),