From: Andreas Hansson <andreas.hansson@arm.com>
Date: Fri, 25 Sep 2015 11:26:58 +0000 (-0400)
Subject: mem: Add check for block status on WriteLineReq fill
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9a7002a3b3ad1e423d16ace826e80574d4ddc4f;p=gem5.git

mem: Add check for block status on WriteLineReq fill

More checks to help with understanding of functionality.
---

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index fe715fa6d..71fbb1884 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1657,6 +1657,16 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks)
         blk->status |= BlkSecure;
     blk->status |= BlkValid | BlkReadable;
 
+    // sanity check for whole-line writes, which should always be
+    // marked as writable as part of the fill, and then later marked
+    // dirty as part of satisfyCpuSideRequest
+    if (pkt->cmd == MemCmd::WriteLineReq) {
+        assert(!pkt->sharedAsserted());
+        // at the moment other caches do not respond to the
+        // invalidation requests corresponding to a whole-line write
+        assert(!pkt->memInhibitAsserted());
+    }
+
     if (!pkt->sharedAsserted()) {
         // we could get non-shared responses from memory (rather than
         // a cache) even in a read-only cache, note that we set this