From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 10 Oct 2006 02:49:58 +0000 (-0400)
Subject: Comment out code that messed up SMT (but will be needed eventually).
X-Git-Tag: m5_2.0_beta2~104^2~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9ae6c8656dc233996c81cdeb6f5c8539442af95;p=gem5.git

Comment out code that messed up SMT (but will be needed eventually).

src/cpu/o3/cpu.cc:
    Comment out reseting CPU structures for now.  This can be updated to work in the future.

--HG--
extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
---

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index d1d25dd7f..4c9a8e91f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -701,10 +701,17 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
     assert(iew.ldstQueue.getCount(tid) == 0);
 
     // Reset ROB/IQ/LSQ Entries
+
+    // Commented out for now.  This should be possible to do by
+    // telling all the pipeline stages to drain first, and then
+    // checking until the drain completes.  Once the pipeline is
+    // drained, call resetEntries(). - 10-09-06 ktlim
+/*
     if (activeThreads.size() >= 1) {
         commit.rob->resetEntries();
         iew.resetEntries();
     }
+*/
 }