From: Matt Johnston Date: Wed, 11 Aug 2021 05:11:57 +0000 (+0800) Subject: orangecrab: add Orange Crab r0.2 target X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9b467f43bae80b53d94b9067fe129651745d76a;p=microwatt.git orangecrab: add Orange Crab r0.2 target top-orangecrab0.2 is a copy of top-arty with various changes. USRMCLK is added for the SPI clock ethernet is removed Signed-off-by: Matt Johnston --- diff --git a/Makefile b/Makefile index bbd3f46..ea8fa26 100644 --- a/Makefile +++ b/Makefile @@ -148,12 +148,17 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex #MEMORY_SIZE=393216 #RAM_INIT_FILE=micropython/firmware.hex -FPGA_TARGET ?= ORANGE-CRAB +FPGA_TARGET ?= ORANGE-CRAB-0.21 # FIXME: icache RAMs aren't being inferrenced as block RAMs on ECP5 # with yosys, so make it smaller for now as a workaround. ICACHE_NUM_LINES=4 +clkgen=fpga/clk_gen_ecp5.vhd +toplevel=fpga/top-generic.vhdl +dmi_dtm=dmi_dtm_dummy.vhdl +LITEDRAM_GHDL_ARG= + # OrangeCrab with ECP85 (original v0.0 with UM5G-85 chip) ifeq ($(FPGA_TARGET), ORANGE-CRAB) RESET_LOW=true @@ -170,12 +175,14 @@ endif ifeq ($(FPGA_TARGET), ORANGE-CRAB-0.21) RESET_LOW=true CLK_INPUT=48000000 -CLK_FREQUENCY=40000000 -LPF=constraints/orange-crab.lpf +CLK_FREQUENCY=48000000 +LPF=constraints/orange-crab-0.2.lpf PACKAGE=CSFBGA285 -NEXTPNR_FLAGS=--85k --speed 8 --freq 40 +NEXTPNR_FLAGS=--85k --speed 8 --freq 48 --timing-allow-fail --ignore-loops OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg +toplevel=fpga/top-orangecrab0.2.vhdl +litedram_target=orangecrab-85-0.2 endif # ECP5-EVN @@ -190,12 +197,17 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg endif +ifneq ($(litedram_target),) +soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \ + litedram/generated/$(litedram_target)/litedram-initmem.vhdl +soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v +LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=true +endif + GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \ - -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) + -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \ + $(LITEDRAM_GHDL_ARG) -clkgen=fpga/clk_gen_ecp5.vhd -toplevel=fpga/top-generic.vhdl -dmi_dtm=dmi_dtm_dummy.vhdl ifeq ($(FPGA_TARGET), verilator) RESET_LOW=true @@ -208,10 +220,10 @@ fpga_files = fpga/soc_reset.vhdl \ fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \ nonrandom.vhdl -synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) +synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) microwatt.json: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files); synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@" diff --git a/constraints/orange-crab-0.2.lpf b/constraints/orange-crab-0.2.lpf new file mode 100644 index 0000000..dbee9a9 --- /dev/null +++ b/constraints/orange-crab-0.2.lpf @@ -0,0 +1,225 @@ +LOCATE COMP "ext_clk" SITE "A9"; +IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33; + +// LOCATE COMP "ext_rst_n" SITE "J2"; // io_13 +// IOBUF PORT "ext_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +// user_button as reset +LOCATE COMP "ext_rst_n" SITE "J17"; +IOBUF PORT "ext_rst_n" IO_TYPE=SSTL135_I; + +LOCATE COMP "usb_d_p" SITE "N1"; +LOCATE COMP "usb_d_n" SITE "M2"; +LOCATE COMP "usb_pullup" SITE "N2"; + +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; + +LOCATE COMP "led0_g" SITE "M3"; +LOCATE COMP "led0_r" SITE "K4"; +LOCATE COMP "led0_b" SITE "J3"; + +IOBUF PORT "led0_g" IO_TYPE=LVCMOS33; +IOBUF PORT "led0_g" IO_TYPE=LVCMOS33; +IOBUF PORT "led0_b" IO_TYPE=LVCMOS33; + +// discontinuous gpio numbers, match orangecrab litex platform +LOCATE COMP "pin_gpio_0" SITE "N17"; // tx +LOCATE COMP "pin_gpio_1" SITE "M18"; // rx +LOCATE COMP "pin_gpio_2" SITE "C10"; // sda +LOCATE COMP "pin_gpio_3" SITE "C9"; // scl +// +LOCATE COMP "pin_gpio_5" SITE "B10"; // io_5 +LOCATE COMP "pin_gpio_6" SITE "B9"; // ... +// +LOCATE COMP "pin_gpio_9" SITE "C8"; // +LOCATE COMP "pin_gpio_10" SITE "B8"; // +LOCATE COMP "pin_gpio_11" SITE "A8"; // +LOCATE COMP "pin_gpio_12" SITE "H2"; // +LOCATE COMP "pin_gpio_13" SITE "J2"; // io_13 +LOCATE COMP "pin_gpio_14" SITE "N15"; // miso +LOCATE COMP "pin_gpio_15" SITE "R17"; // sck +LOCATE COMP "pin_gpio_16" SITE "N16"; // mosi + +LOCATE COMP "pin_io_a0" SITE "L4"; +LOCATE COMP "pin_io_a1" SITE "N3"; +LOCATE COMP "pin_io_a2" SITE "N4"; +LOCATE COMP "pin_io_a3" SITE "H4"; +LOCATE COMP "pin_io_a4" SITE "G4"; +LOCATE COMP "pin_io_a5" SITE "T17"; + +IOBUF PORT "pin_gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_2" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_3" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_14" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_15" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_16" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a4" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a5" IO_TYPE=LVCMOS33; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +LOCATE COMP "ddram_a[1]" SITE "D2"; +LOCATE COMP "ddram_a[2]" SITE "D3"; +LOCATE COMP "ddram_a[3]" SITE "A3"; +LOCATE COMP "ddram_a[4]" SITE "A4"; +LOCATE COMP "ddram_a[5]" SITE "D4"; +LOCATE COMP "ddram_a[6]" SITE "C3"; +LOCATE COMP "ddram_a[7]" SITE "B2"; +LOCATE COMP "ddram_a[8]" SITE "B1"; +LOCATE COMP "ddram_a[9]" SITE "D1"; +LOCATE COMP "ddram_a[10]" SITE "A7"; +LOCATE COMP "ddram_a[11]" SITE "C2"; +LOCATE COMP "ddram_a[12]" SITE "B6"; +LOCATE COMP "ddram_a[13]" SITE "C1"; +LOCATE COMP "ddram_a[14]" SITE "A2"; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST; + +LOCATE COMP "ddram_ba[0]" SITE "D6"; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +LOCATE COMP "ddram_cas_n" SITE "D13"; +LOCATE COMP "ddram_cs_n" SITE "A12"; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +LOCATE COMP "ddram_ras_n" SITE "C12"; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; + +// from litex platform, termination disabled to reduce heat +LOCATE COMP "ddram_dq[0]" SITE "C17"; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; + +LOCATE COMP "ddram_dqs_n[0]" SITE "A16"; +LOCATE COMP "ddram_dqs_n[1]" SITE "H17"; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; + +LOCATE COMP "ddram_clk_p" SITE "J18"; +LOCATE COMP "ddram_clk_n" SITE "K18"; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I SLEWRATE=FAST; +IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL135D_I SLEWRATE=FAST; + +LOCATE COMP "ddram_cke" SITE "D18"; +LOCATE COMP "ddram_odt" SITE "C13"; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; + +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST; + +// We use USRMCLK instead for clk +// LOCATE COMP "spi_flash_clk" SITE "U16"; +// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_cs_n" SITE "U17"; +IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_mosi" SITE "U18"; +IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_miso" SITE "T18"; +IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_wp_n" SITE "R18"; +IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_hold_n" SITE "N18"; +IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "sdcard_data[0]" SITE "J1"; +LOCATE COMP "sdcard_data[1]" SITE "K3"; +LOCATE COMP "sdcard_data[2]" SITE "L3"; +LOCATE COMP "sdcard_data[3]" SITE "M1"; +LOCATE COMP "sdcard_cmd" SITE "K2"; +LOCATE COMP "sdcard_clk" SITE "K1"; +LOCATE COMP "sdcard_cd" SITE "L1"; + +IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33; diff --git a/fpga/top-orangecrab0.2.vhdl b/fpga/top-orangecrab0.2.vhdl new file mode 100644 index 0000000..1e02b23 --- /dev/null +++ b/fpga/top-orangecrab0.2.vhdl @@ -0,0 +1,509 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_INPUT : positive := 100000000; + CLK_FREQUENCY : positive := 100000000; + HAS_FPU : boolean := true; + HAS_BTC : boolean := true; + USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; + SCLK_STARTUPE2 : boolean := false; + SPI_FLASH_OFFSET : integer := 4194304; + SPI_FLASH_DEF_CKDV : natural := 1; + SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 512; + UART_IS_16550 : boolean := true; + HAS_UART1 : boolean := true; + USE_LITESDCARD : boolean := false; + ICACHE_NUM_LINES : natural := 64; + NGPIO : natural := 32 + ); + port( + ext_clk : in std_ulogic; + ext_rst_n : in std_ulogic; + + -- UART0 signals: + pin_gpio_0 : out std_ulogic; + pin_gpio_1 : in std_ulogic; + + -- LEDs + led0_b : out std_ulogic; + led0_g : out std_ulogic; + led0_r : out std_ulogic; + + -- SPI + spi_flash_cs_n : out std_ulogic; + spi_flash_mosi : inout std_ulogic; + spi_flash_miso : inout std_ulogic; + spi_flash_wp_n : inout std_ulogic; + spi_flash_hold_n : inout std_ulogic; + + -- SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(13 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + -- only the positive differential pin is instantiated + --ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + --ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + + ddram_gnd : out std_ulogic_vector(1 downto 0); + ddram_vccio : out std_ulogic_vector(5 downto 0) + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- External IOs from the SoC + signal wb_ext_io_in : wb_io_master_out; + signal wb_ext_io_out : wb_io_slave_out; + signal wb_ext_is_dram_csr : std_ulogic; + signal wb_ext_is_dram_init : std_ulogic; + signal wb_ext_is_sdcard : std_ulogic; + + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteSDCard connection + signal ext_irq_sdcard : std_ulogic := '0'; + signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; + signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_sddma_in : wb_io_slave_out; + signal wb_sddma_nr : wb_io_master_out; + signal wb_sddma_ir : wb_io_slave_out; + -- for conversion from non-pipelined wishbone to pipelined + signal wb_sddma_stb_sent : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + + -- Status LED + signal led0_b_pwm : std_ulogic; + signal led0_r_pwm : std_ulogic; + signal led0_g_pwm : std_ulogic; + + -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise + signal pwm_counter : std_ulogic_vector(8 downto 0); + + -- SPI flash + signal spi_sck : std_ulogic; + signal spi_cs_n : std_ulogic; + signal spi_sdat_o : std_ulogic_vector(3 downto 0); + signal spi_sdat_oe : std_ulogic_vector(3 downto 0); + signal spi_sdat_i : std_ulogic_vector(3 downto 0); + + -- GPIO + signal gpio_in : std_ulogic_vector(NGPIO - 1 downto 0); + signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0); + signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; + + COMPONENT USRMCLK + PORT( + USRMCLKI : IN STD_ULOGIC; + USRMCLKTS : IN STD_ULOGIC + ); + END COMPONENT; + attribute syn_noprune: boolean ; + attribute syn_noprune of USRMCLK: component is true; + +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_FPU => HAS_FPU, + HAS_BTC => HAS_BTC, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 256 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + HAS_SPI_FLASH => true, + SPI_FLASH_DLINES => 4, + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, + SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, + UART0_IS_16550 => UART_IS_16550, + HAS_UART1 => HAS_UART1, + HAS_SD_CARD => USE_LITESDCARD, + ICACHE_NUM_LINES => ICACHE_NUM_LINES, + NGPIO => NGPIO + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => pin_gpio_0, + uart0_rxd => pin_gpio_1, + + -- UART1 signals + --uart1_txd => uart_pmod_tx, + --uart1_rxd => uart_pmod_rx, + + -- SPI signals + spi_flash_sck => spi_sck, + spi_flash_cs_n => spi_cs_n, + spi_flash_sdat_o => spi_sdat_o, + spi_flash_sdat_oe => spi_sdat_oe, + spi_flash_sdat_i => spi_sdat_i, + + -- GPIO signals + gpio_in => gpio_in, + gpio_out => gpio_out, + gpio_dir => gpio_dir, + + -- External interrupts + ext_irq_sdcard => ext_irq_sdcard, + + -- DRAM wishbone + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + + -- IO wishbone + wb_ext_io_in => wb_ext_io_in, + wb_ext_io_out => wb_ext_io_out, + wb_ext_is_dram_csr => wb_ext_is_dram_csr, + wb_ext_is_dram_init => wb_ext_is_dram_init, + wb_ext_is_sdcard => wb_ext_is_sdcard, + + -- DMA wishbone + wishbone_dma_in => wb_sddma_in, + wishbone_dma_out => wb_sddma_out, + + alt_reset => core_alt_reset + ); + + -- SPI Flash + -- + spi_flash_cs_n <= spi_cs_n; + spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z'; + spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z'; + spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z'; + spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z'; + spi_sdat_i(0) <= spi_flash_mosi; + spi_sdat_i(1) <= spi_flash_miso; + spi_sdat_i(2) <= spi_flash_wp_n; + spi_sdat_i(3) <= spi_flash_hold_n; + + uclk: USRMCLK port map ( + USRMCLKI => spi_sck, + USRMCLKTS => '0' + ); + + nodram: if not USE_LITEDRAM generate + signal ddram_clk_dummy : std_ulogic; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => CLK_INPUT, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + led0_b_pwm <= '1'; + led0_r_pwm <= '1'; + led0_g_pwm <= '0'; + core_alt_reset <= '0'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal dram_sys_rst : std_ulogic; + signal rst_gen_rst : std_ulogic; + begin + + -- Eventually dig out the frequency from + -- litesdram generate.py sys_clk_freq + -- but for now, assert it's 48Mhz for orangecrab + assert CLK_FREQUENCY = 48000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 1 + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n, + pll_rst_out => pll_rst, + rst_out => rst_gen_rst + ); + + -- Generate SoC reset + soc_rst_gen: process(system_clk) + begin + if ext_rst_n = '0' then + soc_rst <= '1'; + elsif rising_edge(system_clk) then + soc_rst <= dram_sys_rst or not system_clk_locked; + end if; + end process; + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 24, + DRAM_ALINES => 14, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => dram_sys_rst, + core_alt_reset => core_alt_reset, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_ext_io_in, + wb_ctrl_out => wb_dram_ctrl_out, + wb_ctrl_is_csr => wb_ext_is_dram_csr, + wb_ctrl_is_init => wb_ext_is_dram_init, + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_clk_p => ddram_clk_p, + -- only the positive differential pin is instantiated + --ddram_dqs_n => ddram_dqs_n, + --ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + + ddram_reset_n => ddram_reset_n + ); + + ddram_gnd <= "00"; + -- for power consumption. + -- https://github.com/orangecrab-fpga/orangecrab-hardware/issues/19#issuecomment-683479378 + ddram_vccio <= "111111"; + + led0_b_pwm <= not dram_init_done; + led0_r_pwm <= dram_init_error; + led0_g_pwm <= dram_init_done and not dram_init_error; + + end generate; + + + -- SD card pmod + has_sdcard : if USE_LITESDCARD generate + component litesdcard_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + -- wishbone for accessing control registers + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + -- wishbone for SD card core to use for DMA + wb_dma_adr : out std_ulogic_vector(29 downto 0); + wb_dma_dat_w : out std_ulogic_vector(31 downto 0); + wb_dma_dat_r : in std_ulogic_vector(31 downto 0); + wb_dma_sel : out std_ulogic_vector(3 downto 0); + wb_dma_cyc : out std_ulogic; + wb_dma_stb : out std_ulogic; + wb_dma_ack : in std_ulogic; + wb_dma_we : out std_ulogic; + wb_dma_cti : out std_ulogic_vector(2 downto 0); + wb_dma_bte : out std_ulogic_vector(1 downto 0); + wb_dma_err : in std_ulogic; + -- connections to SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + irq : out std_ulogic + ); + end component; + + signal wb_sdcard_cyc : std_ulogic; + signal wb_sdcard_adr : std_ulogic_vector(29 downto 0); + + begin + litesdcard : litesdcard_core + port map ( + clk => system_clk, + rst => soc_rst, + wb_ctrl_adr => wb_sdcard_adr, + wb_ctrl_dat_w => wb_ext_io_in.dat, + wb_ctrl_dat_r => wb_sdcard_out.dat, + wb_ctrl_sel => wb_ext_io_in.sel, + wb_ctrl_cyc => wb_sdcard_cyc, + wb_ctrl_stb => wb_ext_io_in.stb, + wb_ctrl_ack => wb_sdcard_out.ack, + wb_ctrl_we => wb_ext_io_in.we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, + wb_dma_adr => wb_sddma_nr.adr, + wb_dma_dat_w => wb_sddma_nr.dat, + wb_dma_dat_r => wb_sddma_ir.dat, + wb_dma_sel => wb_sddma_nr.sel, + wb_dma_cyc => wb_sddma_nr.cyc, + wb_dma_stb => wb_sddma_nr.stb, + wb_dma_ack => wb_sddma_ir.ack, + wb_dma_we => wb_sddma_nr.we, + wb_dma_cti => open, + wb_dma_bte => open, + wb_dma_err => '0', + sdcard_data => sdcard_data, + sdcard_cmd => sdcard_cmd, + sdcard_clk => sdcard_clk, + sdcard_cd => sdcard_cd, + irq => ext_irq_sdcard + ); + + -- Gate cyc with chip select from SoC + wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard; + + wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(15 downto 2); + + wb_sdcard_out.stall <= not wb_sdcard_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_sddma_out <= wb_sddma_nr; + if wb_sddma_stb_sent = '1' or + (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then + wb_sddma_out.stb <= '0'; + end if; + if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then + wb_sddma_stb_sent <= '0'; + elsif wb_sddma_in.stall = '0' then + wb_sddma_stb_sent <= wb_sddma_nr.stb; + end if; + wb_sddma_ir <= wb_sddma_in; + end if; + end process; + + end generate; + + -- Mux WB response on the IO bus + wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else + wb_dram_ctrl_out; + + leds_pwm : process(system_clk) + begin + if rising_edge(system_clk) then + pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1); + if pwm_counter(8 downto 4) = "00000" then + led0_b <= led0_b_pwm; + led0_r <= led0_r_pwm; + led0_g <= led0_g_pwm; + else + led0_b <= '0'; + led0_r <= '0'; + led0_g <= '0'; + end if; + end if; + end process; + +end architecture behaviour;