From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 May 2021 10:52:53 +0000 (+0100)
Subject: connect MSR.PR to PortInterface in LDSTCompUnit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9b4d828401b6784881143905bc12b727f6ff4a5;p=soc.git

connect MSR.PR to PortInterface in LDSTCompUnit
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index b29947b5..7dfdb15e 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -95,11 +95,14 @@ from soc.fu.regspec import RegSpecAPI
 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
 from openpower.decoder.power_decoder2 import Data
+from openpower.consts import MSR
+
 
 # TODO: LDSTInputData and LDSTOutputData really should be used
 # here, to make things more like the other CompUnits.  currently,
 # also, RegSpecAPI is used explicitly here
 
+
 class LDSTCompUnitRecord(CompUnitRecord):
     def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
         CompUnitRecord.__init__(self, opsubset, rwid,
@@ -501,6 +504,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
         comb += self.exc_o.eq(pi.exc_o)  # exception occurred
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
+        # connect MSR.PR for priv/virt operation
+        comb += pi.msr_pr.eq(oper_r.msr[MSR.PR])
 
         # byte-reverse on LD
         revnorev = Signal(64, reset_less=True)