From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 12:20:00 +0000 (+0000)
Subject: comment about por_clk
X-Git-Tag: LS180_RC3~27^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9cd04a63db28ffd335465751bd99c3b3025508f;p=soclayout.git

comment about por_clk
---

diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py
index 816b1de..6e90700 100644
--- a/experiments9/tsmc_c018/doDesign.py
+++ b/experiments9/tsmc_c018/doDesign.py
@@ -228,6 +228,7 @@ def scriptMain (**kw):
         ls180Conf.coreSize = (coreSizeX, coreSizeY)
         ls180Conf.chipSize = (coreSizeX + chipBorder + u(5.0), coreSizeY + chipBorder - u(0.04) )
        #ls180Conf.useHTree( 'core.subckt_12941_test_issuer.ti_coresync_clk' )
+        # XXX this is probably just por_clk not core.por_clk
         ls180Conf.useHTree( 'core.por_clk' )
         ls180Conf.useHTree( 'jtag_tck_from_pad' )