From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 19 Jan 2022 17:17:40 +0000 (+0000)
Subject: comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9e40b696f5d4f243efecffd758090439b89f005;p=soc.git

comments
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 507302f4..d9c398b4 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -159,6 +159,7 @@ class NonProductionCore(ControlBase):
             # urr store I-Cache in core so it is easier to get at
             self.icache = lsi.icache
 
+        # alternative reset values for STATE regs
         self.msr_at_reset = 0x0
         if hasattr(pspec, "msr_reset") and isinstance(pspec.msr_reset, int):
             self.msr_at_reset = pspec.msr_reset