From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 May 2023 20:46:18 +0000 (+0100)
Subject: fix sv_analysis ldux, missing s/d:RA
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9f462e21f685cc249ff84842a6e58c6f240e756;p=openpower-isa.git

fix sv_analysis ldux, missing s/d:RA
---

diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv
index 3494baca..e554c433 100644
--- a/openpower/isatables/LDSTRM-2P-2S1D.csv
+++ b/openpower/isatables/LDSTRM-2P-2S1D.csv
@@ -26,14 +26,14 @@ sthu,LDST_IMM,,2P,EXTRA3,EN,d:RA;s:RA,s:RS,0,0,RA_OR_ZERO,0,RS,0,0,0,RA
 stfsu,LDST_IMM,,2P,EXTRA3,EN,d:RA;s:RA,s:FRS,0,0,RA,0,FRS,0,0,0,RA
 stfdu,LDST_IMM,,2P,EXTRA3,EN,d:RA;s:RA,s:FRS,0,0,RA,0,FRS,0,0,0,RA
 stdu,LDST_IMM,,2P,EXTRA3,EN,d:RA;s:RA,s:RS,0,0,RA_OR_ZERO,0,RS,0,0,0,RA
-ldux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lwzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lbzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lhzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lwaux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lhaux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lfsux,LDST_IDX,,2P,EXTRA2,EN,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA
-lfdux,LDST_IDX,,2P,EXTRA2,EN,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA
+ldux,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA;d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lwzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA;d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lbzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA;d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lhzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA;d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lwaux,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA;d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lhaux,LDST_IDX,,2P,EXTRA2,EN,d:RT,s:RA;d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lfsux,LDST_IDX,,2P,EXTRA2,EN,d:FRT,s:RA;d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA
+lfdux,LDST_IDX,,2P,EXTRA2,EN,d:FRT,s:RA;d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA
 stdux,LDST_IDX,,2P,EXTRA3,EN,s:RS;s:RA;d:RA,s:RB,0,0,RA_OR_ZERO,RB,RS,0,0,0,RA
 stwux,LDST_IDX,,2P,EXTRA3,EN,s:RS;s:RA;d:RA,s:RB,0,0,RA_OR_ZERO,RB,RS,0,0,0,RA
 stbux,LDST_IDX,,2P,EXTRA3,EN,s:RS;s:RA;d:RA,s:RB,0,0,RA_OR_ZERO,RB,RS,0,0,0,RA
diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index 01dda3a8..4a79aee4 100644
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -453,7 +453,7 @@ def extra_classifier(insn_name, value, name, res, regs):
         elif 'u' in insn_name:  # ldux etc.
             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
             res['0'] = dRT    # RT: Rdest1_EXTRA2
-            res['1'] = 'd:RA'  # RA: Rdest2_EXTRA2
+            res['1'] = 's:RA;d:RA'  # RA: Rdest2_EXTRA2
             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA2
         else:
             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type