From: Kazu Hirata <kazu@cs.umass.edu>
Date: Fri, 9 Jan 2004 15:49:29 +0000 (+0000)
Subject: re PR target/13380 (An unrecognized insn.)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9f99e78e4690d676396fe37e35179fb7edca725;p=gcc.git

re PR target/13380 (An unrecognized insn.)

	PR target/13380.
	* gcc.c-torture/compile/20040109-1.c: New.

From-SVN: r75587
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dd32bd96ec4..6b905bc442b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-01-09  Kazu Hirata  <kazu@cs.umass.edu>
+
+	PR target/13380.
+	* gcc.c-torture/compile/20040109-1.c: New.
+
 2004-01-08  Stuart Hastings  <stuart@apple.com>
 
 	* testsuite/gcc.dg/20020523-2.c (bail_if_no_sse): Moved cpu-ID code...
diff --git a/gcc/testsuite/gcc.c-torture/compile/20040109-1.c b/gcc/testsuite/gcc.c-torture/compile/20040109-1.c
new file mode 100644
index 00000000000..028bd17c070
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/20040109-1.c
@@ -0,0 +1,25 @@
+/* PR target/13380.
+   On m32r, the condition code register, (reg:SI 17), was replaced with
+   a pseudo reg, which would cause an unrecognized insn.  */
+
+void
+foo (unsigned int a, unsigned int b)
+{
+  if (a > b)
+    {
+      while (a)
+	{
+	  switch (b)
+	    {
+	    default:
+	      a = 0;
+	    case 2:
+	      a = 0;
+	    case 1:
+	      a = 0;
+	    case 0:
+	      ;
+	    }
+	}
+    }
+}