From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 5 Aug 2019 07:08:56 +0000 (+0200)
Subject: wishbone/SRAM: make read_only emited verilog code compatible with all tools
X-Git-Tag: 24jan2021_ls180~1071
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a9fe2788a2308aa59d13cb505d4ad7e10797f45a;p=litex.git

wishbone/SRAM: make read_only emited verilog code compatible with all tools

Quartus was not able to implement ROM correctly, see #228
---

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index c874eeb4..dc242f44 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -653,7 +653,8 @@ class SRAM(Module):
         ###
 
         # memory
-        port = self.mem.get_port(write_capable=not read_only, we_granularity=8)
+        port = self.mem.get_port(write_capable=not read_only, we_granularity=8,
+            mode=READ_FIRST if read_only else WRITE_FIRST)
         self.specials += self.mem, port
         # generate write enable signal
         if not read_only: