From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Jul 2021 17:12:13 +0000 (+0100)
Subject: add temporary SV pseudocode
X-Git-Tag: xlen-bcd~354
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa01065fc0213f6d2eee1e368afa845e5220a57e;p=openpower-isa.git

add temporary SV pseudocode
---

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index e2482b37..843c45ed 100644
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -33,3 +33,28 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
+# svremap
+
+SVM-Form
+
+* svstate SVxd, SVyd, SVRM
+
+Pseudo-code:
+
+    # hack: clear out all SVSHAPEs and set them up for multiply
+    SVSHAPE0[0:31] <- [0] * 32
+    SVSHAPE1[0:31] <- [0] * 32
+    SVSHAPE2[0:31] <- [0] * 32
+    SVSHAPE3[0:31] <- [0] * 32
+    # set up FRT and FRB
+    SVSHAPE0[0:5] <- (0b0 || SVxd)   # xdim
+    SVSHAPE3[0:5] <- (0b0 || SVxd)   # xdim
+    # set up FRA
+    SVSHAPE0[0:5] <- (0b0 || SVxd)   # xdim
+    SVSHAPE0[6:11] <- (0b0 || SVyd)  # ydim
+    SVSHAPE0[18:20] <- 0b010          # permute y,x,z
+
+Special Registers Altered:
+
+    None
+
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 37f14d1e..1b658639 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -277,6 +277,7 @@ _insns = [
     "rlwimi", "rlwinm",    "rlwnm",
     "setb",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
+    "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",