From: Anton Blanchard <anton@linux.ibm.com>
Date: Thu, 4 Aug 2022 11:26:17 +0000 (+1000)
Subject: litedram: Regenerate
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa1d2b16d726cd4bc4f568d514d80a3c8021926c;p=microwatt.git

litedram: Regenerate

Regenerate from upstream litex. Something in the update has improved
memory read and write performance quite a lot on my Nexys Video:

Before:

  Write speed: 83.2MiB/s
   Read speed: 140.4MiB/s

After:

  Write speed: 352.1MiB/s
   Read speed: 218.5MiB/s

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init
index 1b6e88e..9006b18 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.init
+++ b/litedram/generated/acorn-cle-215/litedram_core.init
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@@ -1858,17 +1870,15 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
-2d2d2d2d2d2d2d2d
-0000000000000000
-4d4152446574694c
-6620746c69756220
-6567694d206d6f72
-646e61207325206e
-2520586574694c20
-0000000000000a73
 20676e69746f6f42
 415242206d6f7266
 0000000a2e2e2e4d
+3135636632333936
+0000000000000000
+4d4152446574694c
+6620746c69756220
+6574694c206d6f72
+0000000a73252058
 6620676e69797254
 0a2e2e2e6873616c
 0000000000000000
diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v
index da66195..bea0247 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.v
+++ b/litedram/generated/acorn-cle-215/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-01-14 08:32:13
+// LiteX sha1 : 6932fc51
+// Date       : 2022-08-04 21:07:00
 //------------------------------------------------------------------------------
 
 
@@ -69,4079 +69,4498 @@ module litedram_core (
 // Signals
 //------------------------------------------------------------------------------
 
-reg  main_rst = 1'd0;
+reg  rst_1 = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
 wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
-wire main_reset;
-reg  main_power_down = 1'd0;
-wire main_locked;
-wire main_clkin;
-wire main_clkout0;
-wire main_clkout_buf0;
-wire main_clkout1;
-wire main_clkout_buf1;
-wire main_clkout2;
-wire main_clkout_buf2;
-wire main_clkout3;
-wire main_clkout_buf3;
-reg  [3:0] main_reset_counter = 4'd15;
-reg  main_ic_reset = 1'd1;
-reg  main_a7ddrphy_rst_storage = 1'd0;
-reg  main_a7ddrphy_rst_re = 1'd0;
-reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg  main_a7ddrphy_wlevel_en_re = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
-wire main_a7ddrphy_wlevel_strobe_r;
-reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg  main_a7ddrphy_dly_sel_re = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_rst_r;
-reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_inc_r;
-reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg  main_a7ddrphy_rdphase_re = 1'd0;
-reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg  main_a7ddrphy_wrphase_re = 1'd0;
-wire [15:0] main_a7ddrphy_dfi_p0_address;
-wire [2:0] main_a7ddrphy_dfi_p0_bank;
-wire main_a7ddrphy_dfi_p0_cas_n;
-wire main_a7ddrphy_dfi_p0_cs_n;
-wire main_a7ddrphy_dfi_p0_ras_n;
-wire main_a7ddrphy_dfi_p0_we_n;
-wire main_a7ddrphy_dfi_p0_cke;
-wire main_a7ddrphy_dfi_p0_odt;
-wire main_a7ddrphy_dfi_p0_reset_n;
-wire main_a7ddrphy_dfi_p0_act_n;
-wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
-wire main_a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
-wire main_a7ddrphy_dfi_p0_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p0_rddata_valid;
-wire [15:0] main_a7ddrphy_dfi_p1_address;
-wire [2:0] main_a7ddrphy_dfi_p1_bank;
-wire main_a7ddrphy_dfi_p1_cas_n;
-wire main_a7ddrphy_dfi_p1_cs_n;
-wire main_a7ddrphy_dfi_p1_ras_n;
-wire main_a7ddrphy_dfi_p1_we_n;
-wire main_a7ddrphy_dfi_p1_cke;
-wire main_a7ddrphy_dfi_p1_odt;
-wire main_a7ddrphy_dfi_p1_reset_n;
-wire main_a7ddrphy_dfi_p1_act_n;
-wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
-wire main_a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
-wire main_a7ddrphy_dfi_p1_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p1_rddata_valid;
-wire [15:0] main_a7ddrphy_dfi_p2_address;
-wire [2:0] main_a7ddrphy_dfi_p2_bank;
-wire main_a7ddrphy_dfi_p2_cas_n;
-wire main_a7ddrphy_dfi_p2_cs_n;
-wire main_a7ddrphy_dfi_p2_ras_n;
-wire main_a7ddrphy_dfi_p2_we_n;
-wire main_a7ddrphy_dfi_p2_cke;
-wire main_a7ddrphy_dfi_p2_odt;
-wire main_a7ddrphy_dfi_p2_reset_n;
-wire main_a7ddrphy_dfi_p2_act_n;
-wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
-wire main_a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
-wire main_a7ddrphy_dfi_p2_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p2_rddata_valid;
-wire [15:0] main_a7ddrphy_dfi_p3_address;
-wire [2:0] main_a7ddrphy_dfi_p3_bank;
-wire main_a7ddrphy_dfi_p3_cas_n;
-wire main_a7ddrphy_dfi_p3_cs_n;
-wire main_a7ddrphy_dfi_p3_ras_n;
-wire main_a7ddrphy_dfi_p3_we_n;
-wire main_a7ddrphy_dfi_p3_cke;
-wire main_a7ddrphy_dfi_p3_odt;
-wire main_a7ddrphy_dfi_p3_reset_n;
-wire main_a7ddrphy_dfi_p3_act_n;
-wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
-wire main_a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
-wire main_a7ddrphy_dfi_p3_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p3_rddata_valid;
-wire main_a7ddrphy_sd_clk_se_nodelay;
-reg  main_a7ddrphy_dqs_oe = 1'd0;
-wire main_a7ddrphy_dqs_preamble;
-wire main_a7ddrphy_dqs_postamble;
-wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_dqspattern0 = 1'd0;
-reg  main_a7ddrphy_dqspattern1 = 1'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
-wire main_a7ddrphy_dqs_o_no_delay0;
-wire main_a7ddrphy_dqs_t0;
-reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
-wire main_a7ddrphy0;
-wire main_a7ddrphy_dqs_o_no_delay1;
-wire main_a7ddrphy_dqs_t1;
-reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
-wire main_a7ddrphy1;
-reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
-wire main_a7ddrphy_dq_oe;
-wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire main_a7ddrphy_dq_o_nodelay0;
-wire main_a7ddrphy_dq_i_nodelay0;
-wire main_a7ddrphy_dq_i_delayed0;
-wire main_a7ddrphy_dq_t0;
-reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip03;
-reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay1;
-wire main_a7ddrphy_dq_i_nodelay1;
-wire main_a7ddrphy_dq_i_delayed1;
-wire main_a7ddrphy_dq_t1;
-reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip13;
-reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay2;
-wire main_a7ddrphy_dq_i_nodelay2;
-wire main_a7ddrphy_dq_i_delayed2;
-wire main_a7ddrphy_dq_t2;
-reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip21;
-reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay3;
-wire main_a7ddrphy_dq_i_nodelay3;
-wire main_a7ddrphy_dq_i_delayed3;
-wire main_a7ddrphy_dq_t3;
-reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip31;
-reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay4;
-wire main_a7ddrphy_dq_i_nodelay4;
-wire main_a7ddrphy_dq_i_delayed4;
-wire main_a7ddrphy_dq_t4;
-reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip41;
-reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay5;
-wire main_a7ddrphy_dq_i_nodelay5;
-wire main_a7ddrphy_dq_i_delayed5;
-wire main_a7ddrphy_dq_t5;
-reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip51;
-reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay6;
-wire main_a7ddrphy_dq_i_nodelay6;
-wire main_a7ddrphy_dq_i_delayed6;
-wire main_a7ddrphy_dq_t6;
-reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip61;
-reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay7;
-wire main_a7ddrphy_dq_i_nodelay7;
-wire main_a7ddrphy_dq_i_delayed7;
-wire main_a7ddrphy_dq_t7;
-reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip71;
-reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay8;
-wire main_a7ddrphy_dq_i_nodelay8;
-wire main_a7ddrphy_dq_i_delayed8;
-wire main_a7ddrphy_dq_t8;
-reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip81;
-reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay9;
-wire main_a7ddrphy_dq_i_nodelay9;
-wire main_a7ddrphy_dq_i_delayed9;
-wire main_a7ddrphy_dq_t9;
-reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip91;
-reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay10;
-wire main_a7ddrphy_dq_i_nodelay10;
-wire main_a7ddrphy_dq_i_delayed10;
-wire main_a7ddrphy_dq_t10;
-reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip101;
-reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay11;
-wire main_a7ddrphy_dq_i_nodelay11;
-wire main_a7ddrphy_dq_i_delayed11;
-wire main_a7ddrphy_dq_t11;
-reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip111;
-reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay12;
-wire main_a7ddrphy_dq_i_nodelay12;
-wire main_a7ddrphy_dq_i_delayed12;
-wire main_a7ddrphy_dq_t12;
-reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip121;
-reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay13;
-wire main_a7ddrphy_dq_i_nodelay13;
-wire main_a7ddrphy_dq_i_delayed13;
-wire main_a7ddrphy_dq_t13;
-reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip131;
-reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay14;
-wire main_a7ddrphy_dq_i_nodelay14;
-wire main_a7ddrphy_dq_i_delayed14;
-wire main_a7ddrphy_dq_t14;
-reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip141;
-reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay15;
-wire main_a7ddrphy_dq_i_nodelay15;
-wire main_a7ddrphy_dq_i_delayed15;
-wire main_a7ddrphy_dq_t15;
-reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip151;
-reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [15:0] main_litedramcore_inti_p0_address;
-wire [2:0] main_litedramcore_inti_p0_bank;
-reg  main_litedramcore_inti_p0_cas_n = 1'd1;
-reg  main_litedramcore_inti_p0_cs_n = 1'd1;
-reg  main_litedramcore_inti_p0_ras_n = 1'd1;
-reg  main_litedramcore_inti_p0_we_n = 1'd1;
-wire main_litedramcore_inti_p0_cke;
-wire main_litedramcore_inti_p0_odt;
-wire main_litedramcore_inti_p0_reset_n;
-reg  main_litedramcore_inti_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p0_wrdata;
-wire main_litedramcore_inti_p0_wrdata_en;
-wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
-wire main_litedramcore_inti_p0_rddata_en;
-reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [15:0] main_litedramcore_inti_p1_address;
-wire [2:0] main_litedramcore_inti_p1_bank;
-reg  main_litedramcore_inti_p1_cas_n = 1'd1;
-reg  main_litedramcore_inti_p1_cs_n = 1'd1;
-reg  main_litedramcore_inti_p1_ras_n = 1'd1;
-reg  main_litedramcore_inti_p1_we_n = 1'd1;
-wire main_litedramcore_inti_p1_cke;
-wire main_litedramcore_inti_p1_odt;
-wire main_litedramcore_inti_p1_reset_n;
-reg  main_litedramcore_inti_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p1_wrdata;
-wire main_litedramcore_inti_p1_wrdata_en;
-wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
-wire main_litedramcore_inti_p1_rddata_en;
-reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [15:0] main_litedramcore_inti_p2_address;
-wire [2:0] main_litedramcore_inti_p2_bank;
-reg  main_litedramcore_inti_p2_cas_n = 1'd1;
-reg  main_litedramcore_inti_p2_cs_n = 1'd1;
-reg  main_litedramcore_inti_p2_ras_n = 1'd1;
-reg  main_litedramcore_inti_p2_we_n = 1'd1;
-wire main_litedramcore_inti_p2_cke;
-wire main_litedramcore_inti_p2_odt;
-wire main_litedramcore_inti_p2_reset_n;
-reg  main_litedramcore_inti_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p2_wrdata;
-wire main_litedramcore_inti_p2_wrdata_en;
-wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
-wire main_litedramcore_inti_p2_rddata_en;
-reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [15:0] main_litedramcore_inti_p3_address;
-wire [2:0] main_litedramcore_inti_p3_bank;
-reg  main_litedramcore_inti_p3_cas_n = 1'd1;
-reg  main_litedramcore_inti_p3_cs_n = 1'd1;
-reg  main_litedramcore_inti_p3_ras_n = 1'd1;
-reg  main_litedramcore_inti_p3_we_n = 1'd1;
-wire main_litedramcore_inti_p3_cke;
-wire main_litedramcore_inti_p3_odt;
-wire main_litedramcore_inti_p3_reset_n;
-reg  main_litedramcore_inti_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p3_wrdata;
-wire main_litedramcore_inti_p3_wrdata_en;
-wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
-wire main_litedramcore_inti_p3_rddata_en;
-reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
-wire [15:0] main_litedramcore_slave_p0_address;
-wire [2:0] main_litedramcore_slave_p0_bank;
-wire main_litedramcore_slave_p0_cas_n;
-wire main_litedramcore_slave_p0_cs_n;
-wire main_litedramcore_slave_p0_ras_n;
-wire main_litedramcore_slave_p0_we_n;
-wire main_litedramcore_slave_p0_cke;
-wire main_litedramcore_slave_p0_odt;
-wire main_litedramcore_slave_p0_reset_n;
-wire main_litedramcore_slave_p0_act_n;
-wire [31:0] main_litedramcore_slave_p0_wrdata;
-wire main_litedramcore_slave_p0_wrdata_en;
-wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
-wire main_litedramcore_slave_p0_rddata_en;
-reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [15:0] main_litedramcore_slave_p1_address;
-wire [2:0] main_litedramcore_slave_p1_bank;
-wire main_litedramcore_slave_p1_cas_n;
-wire main_litedramcore_slave_p1_cs_n;
-wire main_litedramcore_slave_p1_ras_n;
-wire main_litedramcore_slave_p1_we_n;
-wire main_litedramcore_slave_p1_cke;
-wire main_litedramcore_slave_p1_odt;
-wire main_litedramcore_slave_p1_reset_n;
-wire main_litedramcore_slave_p1_act_n;
-wire [31:0] main_litedramcore_slave_p1_wrdata;
-wire main_litedramcore_slave_p1_wrdata_en;
-wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
-wire main_litedramcore_slave_p1_rddata_en;
-reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [15:0] main_litedramcore_slave_p2_address;
-wire [2:0] main_litedramcore_slave_p2_bank;
-wire main_litedramcore_slave_p2_cas_n;
-wire main_litedramcore_slave_p2_cs_n;
-wire main_litedramcore_slave_p2_ras_n;
-wire main_litedramcore_slave_p2_we_n;
-wire main_litedramcore_slave_p2_cke;
-wire main_litedramcore_slave_p2_odt;
-wire main_litedramcore_slave_p2_reset_n;
-wire main_litedramcore_slave_p2_act_n;
-wire [31:0] main_litedramcore_slave_p2_wrdata;
-wire main_litedramcore_slave_p2_wrdata_en;
-wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
-wire main_litedramcore_slave_p2_rddata_en;
-reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [15:0] main_litedramcore_slave_p3_address;
-wire [2:0] main_litedramcore_slave_p3_bank;
-wire main_litedramcore_slave_p3_cas_n;
-wire main_litedramcore_slave_p3_cs_n;
-wire main_litedramcore_slave_p3_ras_n;
-wire main_litedramcore_slave_p3_we_n;
-wire main_litedramcore_slave_p3_cke;
-wire main_litedramcore_slave_p3_odt;
-wire main_litedramcore_slave_p3_reset_n;
-wire main_litedramcore_slave_p3_act_n;
-wire [31:0] main_litedramcore_slave_p3_wrdata;
-wire main_litedramcore_slave_p3_wrdata_en;
-wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
-wire main_litedramcore_slave_p3_rddata_en;
-reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg  [15:0] main_litedramcore_master_p0_address = 16'd0;
-reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg  main_litedramcore_master_p0_cas_n = 1'd1;
-reg  main_litedramcore_master_p0_cs_n = 1'd1;
-reg  main_litedramcore_master_p0_ras_n = 1'd1;
-reg  main_litedramcore_master_p0_we_n = 1'd1;
-reg  main_litedramcore_master_p0_cke = 1'd0;
-reg  main_litedramcore_master_p0_odt = 1'd0;
-reg  main_litedramcore_master_p0_reset_n = 1'd0;
-reg  main_litedramcore_master_p0_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p0_rddata;
-wire main_litedramcore_master_p0_rddata_valid;
-reg  [15:0] main_litedramcore_master_p1_address = 16'd0;
-reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg  main_litedramcore_master_p1_cas_n = 1'd1;
-reg  main_litedramcore_master_p1_cs_n = 1'd1;
-reg  main_litedramcore_master_p1_ras_n = 1'd1;
-reg  main_litedramcore_master_p1_we_n = 1'd1;
-reg  main_litedramcore_master_p1_cke = 1'd0;
-reg  main_litedramcore_master_p1_odt = 1'd0;
-reg  main_litedramcore_master_p1_reset_n = 1'd0;
-reg  main_litedramcore_master_p1_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p1_rddata;
-wire main_litedramcore_master_p1_rddata_valid;
-reg  [15:0] main_litedramcore_master_p2_address = 16'd0;
-reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg  main_litedramcore_master_p2_cas_n = 1'd1;
-reg  main_litedramcore_master_p2_cs_n = 1'd1;
-reg  main_litedramcore_master_p2_ras_n = 1'd1;
-reg  main_litedramcore_master_p2_we_n = 1'd1;
-reg  main_litedramcore_master_p2_cke = 1'd0;
-reg  main_litedramcore_master_p2_odt = 1'd0;
-reg  main_litedramcore_master_p2_reset_n = 1'd0;
-reg  main_litedramcore_master_p2_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p2_rddata;
-wire main_litedramcore_master_p2_rddata_valid;
-reg  [15:0] main_litedramcore_master_p3_address = 16'd0;
-reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg  main_litedramcore_master_p3_cas_n = 1'd1;
-reg  main_litedramcore_master_p3_cs_n = 1'd1;
-reg  main_litedramcore_master_p3_ras_n = 1'd1;
-reg  main_litedramcore_master_p3_we_n = 1'd1;
-reg  main_litedramcore_master_p3_cke = 1'd0;
-reg  main_litedramcore_master_p3_odt = 1'd0;
-reg  main_litedramcore_master_p3_reset_n = 1'd0;
-reg  main_litedramcore_master_p3_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p3_rddata;
-wire main_litedramcore_master_p3_rddata_valid;
-wire main_litedramcore_sel;
-wire main_litedramcore_cke;
-wire main_litedramcore_odt;
-wire main_litedramcore_reset_n;
-reg  [3:0] main_litedramcore_storage = 4'd1;
-reg  main_litedramcore_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector0_command_issue_r;
-reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg  [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0;
-reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector0_rddata_we;
-reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector1_command_issue_r;
-reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg  [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0;
-reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector1_rddata_we;
-reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector2_command_issue_r;
-reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg  [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0;
-reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector2_rddata_we;
-reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector3_command_issue_r;
-reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg  [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0;
-reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector3_rddata_we;
-reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire main_litedramcore_interface_bank0_valid;
-wire main_litedramcore_interface_bank0_ready;
-wire main_litedramcore_interface_bank0_we;
-wire [22:0] main_litedramcore_interface_bank0_addr;
-wire main_litedramcore_interface_bank0_lock;
-wire main_litedramcore_interface_bank0_wdata_ready;
-wire main_litedramcore_interface_bank0_rdata_valid;
-wire main_litedramcore_interface_bank1_valid;
-wire main_litedramcore_interface_bank1_ready;
-wire main_litedramcore_interface_bank1_we;
-wire [22:0] main_litedramcore_interface_bank1_addr;
-wire main_litedramcore_interface_bank1_lock;
-wire main_litedramcore_interface_bank1_wdata_ready;
-wire main_litedramcore_interface_bank1_rdata_valid;
-wire main_litedramcore_interface_bank2_valid;
-wire main_litedramcore_interface_bank2_ready;
-wire main_litedramcore_interface_bank2_we;
-wire [22:0] main_litedramcore_interface_bank2_addr;
-wire main_litedramcore_interface_bank2_lock;
-wire main_litedramcore_interface_bank2_wdata_ready;
-wire main_litedramcore_interface_bank2_rdata_valid;
-wire main_litedramcore_interface_bank3_valid;
-wire main_litedramcore_interface_bank3_ready;
-wire main_litedramcore_interface_bank3_we;
-wire [22:0] main_litedramcore_interface_bank3_addr;
-wire main_litedramcore_interface_bank3_lock;
-wire main_litedramcore_interface_bank3_wdata_ready;
-wire main_litedramcore_interface_bank3_rdata_valid;
-wire main_litedramcore_interface_bank4_valid;
-wire main_litedramcore_interface_bank4_ready;
-wire main_litedramcore_interface_bank4_we;
-wire [22:0] main_litedramcore_interface_bank4_addr;
-wire main_litedramcore_interface_bank4_lock;
-wire main_litedramcore_interface_bank4_wdata_ready;
-wire main_litedramcore_interface_bank4_rdata_valid;
-wire main_litedramcore_interface_bank5_valid;
-wire main_litedramcore_interface_bank5_ready;
-wire main_litedramcore_interface_bank5_we;
-wire [22:0] main_litedramcore_interface_bank5_addr;
-wire main_litedramcore_interface_bank5_lock;
-wire main_litedramcore_interface_bank5_wdata_ready;
-wire main_litedramcore_interface_bank5_rdata_valid;
-wire main_litedramcore_interface_bank6_valid;
-wire main_litedramcore_interface_bank6_ready;
-wire main_litedramcore_interface_bank6_we;
-wire [22:0] main_litedramcore_interface_bank6_addr;
-wire main_litedramcore_interface_bank6_lock;
-wire main_litedramcore_interface_bank6_wdata_ready;
-wire main_litedramcore_interface_bank6_rdata_valid;
-wire main_litedramcore_interface_bank7_valid;
-wire main_litedramcore_interface_bank7_ready;
-wire main_litedramcore_interface_bank7_we;
-wire [22:0] main_litedramcore_interface_bank7_addr;
-wire main_litedramcore_interface_bank7_lock;
-wire main_litedramcore_interface_bank7_wdata_ready;
-wire main_litedramcore_interface_bank7_rdata_valid;
-reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] main_litedramcore_interface_rdata;
-reg  [15:0] main_litedramcore_dfi_p0_address = 16'd0;
-reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p0_we_n = 1'd1;
-wire main_litedramcore_dfi_p0_cke;
-wire main_litedramcore_dfi_p0_odt;
-wire main_litedramcore_dfi_p0_reset_n;
-reg  main_litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p0_rddata;
-wire main_litedramcore_dfi_p0_rddata_valid;
-reg  [15:0] main_litedramcore_dfi_p1_address = 16'd0;
-reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p1_we_n = 1'd1;
-wire main_litedramcore_dfi_p1_cke;
-wire main_litedramcore_dfi_p1_odt;
-wire main_litedramcore_dfi_p1_reset_n;
-reg  main_litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p1_rddata;
-wire main_litedramcore_dfi_p1_rddata_valid;
-reg  [15:0] main_litedramcore_dfi_p2_address = 16'd0;
-reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p2_we_n = 1'd1;
-wire main_litedramcore_dfi_p2_cke;
-wire main_litedramcore_dfi_p2_odt;
-wire main_litedramcore_dfi_p2_reset_n;
-reg  main_litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p2_rddata;
-wire main_litedramcore_dfi_p2_rddata_valid;
-reg  [15:0] main_litedramcore_dfi_p3_address = 16'd0;
-reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p3_we_n = 1'd1;
-wire main_litedramcore_dfi_p3_cke;
-wire main_litedramcore_dfi_p3_odt;
-wire main_litedramcore_dfi_p3_reset_n;
-reg  main_litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p3_rddata;
-wire main_litedramcore_dfi_p3_rddata_valid;
-reg  main_litedramcore_cmd_valid = 1'd0;
-reg  main_litedramcore_cmd_ready = 1'd0;
-reg  main_litedramcore_cmd_last = 1'd0;
-reg  [15:0] main_litedramcore_cmd_payload_a = 16'd0;
-reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg  main_litedramcore_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_cmd_payload_we = 1'd0;
-reg  main_litedramcore_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_cmd_payload_is_write = 1'd0;
-wire main_litedramcore_wants_refresh;
-wire main_litedramcore_wants_zqcs;
-wire main_litedramcore_timer_wait;
-wire main_litedramcore_timer_done0;
-wire [9:0] main_litedramcore_timer_count0;
-wire main_litedramcore_timer_done1;
-reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
-wire main_litedramcore_postponer_req_i;
-reg  main_litedramcore_postponer_req_o = 1'd0;
-reg  main_litedramcore_postponer_count = 1'd0;
-reg  main_litedramcore_sequencer_start0 = 1'd0;
-wire main_litedramcore_sequencer_done0;
-wire main_litedramcore_sequencer_start1;
-reg  main_litedramcore_sequencer_done1 = 1'd0;
-reg  [6:0] main_litedramcore_sequencer_counter = 7'd0;
-reg  main_litedramcore_sequencer_count = 1'd0;
-wire main_litedramcore_zqcs_timer_wait;
-wire main_litedramcore_zqcs_timer_done0;
-wire [26:0] main_litedramcore_zqcs_timer_count0;
-wire main_litedramcore_zqcs_timer_done1;
-reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg  main_litedramcore_zqcs_executer_start = 1'd0;
-reg  main_litedramcore_zqcs_executer_done = 1'd0;
-reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
-wire main_litedramcore_bankmachine0_req_valid;
-wire main_litedramcore_bankmachine0_req_ready;
-wire main_litedramcore_bankmachine0_req_we;
-wire [22:0] main_litedramcore_bankmachine0_req_addr;
-wire main_litedramcore_bankmachine0_req_lock;
-reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine0_refresh_req;
-reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine0_row = 16'd0;
-reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
-wire main_litedramcore_bankmachine0_row_hit;
-reg  main_litedramcore_bankmachine0_row_open = 1'd0;
-reg  main_litedramcore_bankmachine0_row_close = 1'd0;
-reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine1_req_valid;
-wire main_litedramcore_bankmachine1_req_ready;
-wire main_litedramcore_bankmachine1_req_we;
-wire [22:0] main_litedramcore_bankmachine1_req_addr;
-wire main_litedramcore_bankmachine1_req_lock;
-reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine1_refresh_req;
-reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine1_row = 16'd0;
-reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
-wire main_litedramcore_bankmachine1_row_hit;
-reg  main_litedramcore_bankmachine1_row_open = 1'd0;
-reg  main_litedramcore_bankmachine1_row_close = 1'd0;
-reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine2_req_valid;
-wire main_litedramcore_bankmachine2_req_ready;
-wire main_litedramcore_bankmachine2_req_we;
-wire [22:0] main_litedramcore_bankmachine2_req_addr;
-wire main_litedramcore_bankmachine2_req_lock;
-reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine2_refresh_req;
-reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine2_row = 16'd0;
-reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
-wire main_litedramcore_bankmachine2_row_hit;
-reg  main_litedramcore_bankmachine2_row_open = 1'd0;
-reg  main_litedramcore_bankmachine2_row_close = 1'd0;
-reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine3_req_valid;
-wire main_litedramcore_bankmachine3_req_ready;
-wire main_litedramcore_bankmachine3_req_we;
-wire [22:0] main_litedramcore_bankmachine3_req_addr;
-wire main_litedramcore_bankmachine3_req_lock;
-reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine3_refresh_req;
-reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine3_row = 16'd0;
-reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
-wire main_litedramcore_bankmachine3_row_hit;
-reg  main_litedramcore_bankmachine3_row_open = 1'd0;
-reg  main_litedramcore_bankmachine3_row_close = 1'd0;
-reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine4_req_valid;
-wire main_litedramcore_bankmachine4_req_ready;
-wire main_litedramcore_bankmachine4_req_we;
-wire [22:0] main_litedramcore_bankmachine4_req_addr;
-wire main_litedramcore_bankmachine4_req_lock;
-reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine4_refresh_req;
-reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine4_row = 16'd0;
-reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
-wire main_litedramcore_bankmachine4_row_hit;
-reg  main_litedramcore_bankmachine4_row_open = 1'd0;
-reg  main_litedramcore_bankmachine4_row_close = 1'd0;
-reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine5_req_valid;
-wire main_litedramcore_bankmachine5_req_ready;
-wire main_litedramcore_bankmachine5_req_we;
-wire [22:0] main_litedramcore_bankmachine5_req_addr;
-wire main_litedramcore_bankmachine5_req_lock;
-reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine5_refresh_req;
-reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine5_row = 16'd0;
-reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
-wire main_litedramcore_bankmachine5_row_hit;
-reg  main_litedramcore_bankmachine5_row_open = 1'd0;
-reg  main_litedramcore_bankmachine5_row_close = 1'd0;
-reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine6_req_valid;
-wire main_litedramcore_bankmachine6_req_ready;
-wire main_litedramcore_bankmachine6_req_we;
-wire [22:0] main_litedramcore_bankmachine6_req_addr;
-wire main_litedramcore_bankmachine6_req_lock;
-reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine6_refresh_req;
-reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine6_row = 16'd0;
-reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
-wire main_litedramcore_bankmachine6_row_hit;
-reg  main_litedramcore_bankmachine6_row_open = 1'd0;
-reg  main_litedramcore_bankmachine6_row_close = 1'd0;
-reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine7_req_valid;
-wire main_litedramcore_bankmachine7_req_ready;
-wire main_litedramcore_bankmachine7_req_we;
-wire [22:0] main_litedramcore_bankmachine7_req_addr;
-wire main_litedramcore_bankmachine7_req_lock;
-reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine7_refresh_req;
-reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg  [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0;
-wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg  [22:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0;
-reg  [15:0] main_litedramcore_bankmachine7_row = 16'd0;
-reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
-wire main_litedramcore_bankmachine7_row_hit;
-reg  main_litedramcore_bankmachine7_row_open = 1'd0;
-reg  main_litedramcore_bankmachine7_row_close = 1'd0;
-reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
-wire main_litedramcore_ras_allowed;
-wire main_litedramcore_cas_allowed;
-wire [1:0] main_litedramcore_rdcmdphase;
-wire [1:0] main_litedramcore_wrcmdphase;
-reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_valid;
-reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [15:0] main_litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire main_litedramcore_choose_cmd_cmd_payload_is_read;
-wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_cmd_request;
-reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
-wire main_litedramcore_choose_cmd_ce;
-reg  main_litedramcore_choose_req_want_reads = 1'd0;
-reg  main_litedramcore_choose_req_want_writes = 1'd0;
-reg  main_litedramcore_choose_req_want_cmds = 1'd0;
-reg  main_litedramcore_choose_req_want_activates = 1'd0;
-wire main_litedramcore_choose_req_cmd_valid;
-reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
-wire [15:0] main_litedramcore_choose_req_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_req_cmd_payload_is_cmd;
-wire main_litedramcore_choose_req_cmd_payload_is_read;
-wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_req_request;
-reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
-wire main_litedramcore_choose_req_ce;
-reg  [15:0] main_litedramcore_nop_a = 16'd0;
-reg  [2:0] main_litedramcore_nop_ba = 3'd0;
-reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg  main_litedramcore_steerer0 = 1'd1;
-reg  main_litedramcore_steerer1 = 1'd1;
-reg  main_litedramcore_steerer2 = 1'd1;
-reg  main_litedramcore_steerer3 = 1'd1;
-reg  main_litedramcore_steerer4 = 1'd1;
-reg  main_litedramcore_steerer5 = 1'd1;
-reg  main_litedramcore_steerer6 = 1'd1;
-reg  main_litedramcore_steerer7 = 1'd1;
-wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
-reg  main_litedramcore_trrdcon_count = 1'd0;
-wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] main_litedramcore_tfawcon_count;
-reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
-wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
-reg  main_litedramcore_tccdcon_count = 1'd0;
-wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
-wire main_litedramcore_read_available;
-wire main_litedramcore_write_available;
-reg  main_litedramcore_en0 = 1'd0;
-wire main_litedramcore_max_time0;
-reg  [4:0] main_litedramcore_time0 = 5'd0;
-reg  main_litedramcore_en1 = 1'd0;
-wire main_litedramcore_max_time1;
-reg  [3:0] main_litedramcore_time1 = 4'd0;
-wire main_litedramcore_go_to_refresh;
-reg  main_init_done_storage = 1'd0;
-reg  main_init_done_re = 1'd0;
-reg  main_init_error_storage = 1'd0;
-reg  main_init_error_re = 1'd0;
-wire [29:0] main_wb_bus_adr;
-wire [31:0] main_wb_bus_dat_w;
-wire [31:0] main_wb_bus_dat_r;
-wire [3:0] main_wb_bus_sel;
-wire main_wb_bus_cyc;
-wire main_wb_bus_stb;
-wire main_wb_bus_ack;
-wire main_wb_bus_we;
-wire [2:0] main_wb_bus_cti;
-wire [1:0] main_wb_bus_bte;
-wire main_wb_bus_err;
-wire main_user_enable;
-wire main_user_port_cmd_valid;
-wire main_user_port_cmd_ready;
-wire main_user_port_cmd_payload_we;
-wire [25:0] main_user_port_cmd_payload_addr;
-wire main_user_port_wdata_valid;
-wire main_user_port_wdata_ready;
-wire [127:0] main_user_port_wdata_payload_data;
-wire [15:0] main_user_port_wdata_payload_we;
-wire main_user_port_rdata_valid;
-wire main_user_port_rdata_ready;
-wire [127:0] main_user_port_rdata_payload_data;
-wire builder_reset0;
-wire builder_reset1;
-wire builder_reset2;
-wire builder_reset3;
-wire builder_reset4;
-wire builder_reset5;
-wire builder_reset6;
-wire builder_reset7;
-wire builder_pll_fb;
-reg  [1:0] builder_refresher_state = 2'd0;
-reg  [1:0] builder_refresher_next_state = 2'd0;
-reg  [3:0] builder_bankmachine0_state = 4'd0;
-reg  [3:0] builder_bankmachine0_next_state = 4'd0;
-reg  [3:0] builder_bankmachine1_state = 4'd0;
-reg  [3:0] builder_bankmachine1_next_state = 4'd0;
-reg  [3:0] builder_bankmachine2_state = 4'd0;
-reg  [3:0] builder_bankmachine2_next_state = 4'd0;
-reg  [3:0] builder_bankmachine3_state = 4'd0;
-reg  [3:0] builder_bankmachine3_next_state = 4'd0;
-reg  [3:0] builder_bankmachine4_state = 4'd0;
-reg  [3:0] builder_bankmachine4_next_state = 4'd0;
-reg  [3:0] builder_bankmachine5_state = 4'd0;
-reg  [3:0] builder_bankmachine5_next_state = 4'd0;
-reg  [3:0] builder_bankmachine6_state = 4'd0;
-reg  [3:0] builder_bankmachine6_next_state = 4'd0;
-reg  [3:0] builder_bankmachine7_state = 4'd0;
-reg  [3:0] builder_bankmachine7_next_state = 4'd0;
-reg  [3:0] builder_multiplexer_state = 4'd0;
-reg  [3:0] builder_multiplexer_next_state = 4'd0;
-wire builder_roundrobin0_request;
-wire builder_roundrobin0_grant;
-wire builder_roundrobin0_ce;
-wire builder_roundrobin1_request;
-wire builder_roundrobin1_grant;
-wire builder_roundrobin1_ce;
-wire builder_roundrobin2_request;
-wire builder_roundrobin2_grant;
-wire builder_roundrobin2_ce;
-wire builder_roundrobin3_request;
-wire builder_roundrobin3_grant;
-wire builder_roundrobin3_ce;
-wire builder_roundrobin4_request;
-wire builder_roundrobin4_grant;
-wire builder_roundrobin4_ce;
-wire builder_roundrobin5_request;
-wire builder_roundrobin5_grant;
-wire builder_roundrobin5_ce;
-wire builder_roundrobin6_request;
-wire builder_roundrobin6_grant;
-wire builder_roundrobin6_ce;
-wire builder_roundrobin7_request;
-wire builder_roundrobin7_grant;
-wire builder_roundrobin7_ce;
-reg  builder_locked0 = 1'd0;
-reg  builder_locked1 = 1'd0;
-reg  builder_locked2 = 1'd0;
-reg  builder_locked3 = 1'd0;
-reg  builder_locked4 = 1'd0;
-reg  builder_locked5 = 1'd0;
-reg  builder_locked6 = 1'd0;
-reg  builder_locked7 = 1'd0;
-reg  builder_new_master_wdata_ready0 = 1'd0;
-reg  builder_new_master_wdata_ready1 = 1'd0;
-reg  builder_new_master_rdata_valid0 = 1'd0;
-reg  builder_new_master_rdata_valid1 = 1'd0;
-reg  builder_new_master_rdata_valid2 = 1'd0;
-reg  builder_new_master_rdata_valid3 = 1'd0;
-reg  builder_new_master_rdata_valid4 = 1'd0;
-reg  builder_new_master_rdata_valid5 = 1'd0;
-reg  builder_new_master_rdata_valid6 = 1'd0;
-reg  builder_new_master_rdata_valid7 = 1'd0;
-reg  builder_new_master_rdata_valid8 = 1'd0;
-reg  [13:0] builder_litedramcore_adr = 14'd0;
-reg  builder_litedramcore_we = 1'd0;
-reg  [31:0] builder_litedramcore_dat_w = 32'd0;
-wire [31:0] builder_litedramcore_dat_r;
-wire [29:0] builder_litedramcore_wishbone_adr;
-wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] builder_litedramcore_wishbone_sel;
-wire builder_litedramcore_wishbone_cyc;
-wire builder_litedramcore_wishbone_stb;
-reg  builder_litedramcore_wishbone_ack = 1'd0;
-wire builder_litedramcore_wishbone_we;
-wire [2:0] builder_litedramcore_wishbone_cti;
-wire [1:0] builder_litedramcore_wishbone_bte;
-reg  builder_litedramcore_wishbone_err = 1'd0;
-wire [13:0] builder_interface0_bank_bus_adr;
-wire builder_interface0_bank_bus_we;
-wire [31:0] builder_interface0_bank_bus_dat_w;
-reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank0_init_done0_re = 1'd0;
-wire builder_csrbank0_init_done0_r;
-reg  builder_csrbank0_init_done0_we = 1'd0;
-wire builder_csrbank0_init_done0_w;
-reg  builder_csrbank0_init_error0_re = 1'd0;
-wire builder_csrbank0_init_error0_r;
-reg  builder_csrbank0_init_error0_we = 1'd0;
-wire builder_csrbank0_init_error0_w;
-wire builder_csrbank0_sel;
-wire [13:0] builder_interface1_bank_bus_adr;
-wire builder_interface1_bank_bus_we;
-wire [31:0] builder_interface1_bank_bus_dat_w;
-reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank1_rst0_re = 1'd0;
-wire builder_csrbank1_rst0_r;
-reg  builder_csrbank1_rst0_we = 1'd0;
-wire builder_csrbank1_rst0_w;
-reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg  builder_csrbank1_wlevel_en0_re = 1'd0;
-wire builder_csrbank1_wlevel_en0_r;
-reg  builder_csrbank1_wlevel_en0_we = 1'd0;
-wire builder_csrbank1_wlevel_en0_w;
-reg  builder_csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_r;
-reg  builder_csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_w;
-reg  builder_csrbank1_rdphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_r;
-reg  builder_csrbank1_rdphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_w;
-reg  builder_csrbank1_wrphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_r;
-reg  builder_csrbank1_wrphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_w;
-wire builder_csrbank1_sel;
-wire [13:0] builder_interface2_bank_bus_adr;
-wire builder_interface2_bank_bus_we;
-wire [31:0] builder_interface2_bank_bus_dat_w;
-reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_r;
-reg  builder_csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_w;
-reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi0_address0_r;
-reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi0_address0_w;
-reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
-reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
-reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi1_address0_r;
-reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi1_address0_w;
-reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
-reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
-reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi2_address0_r;
-reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi2_address0_w;
-reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
-reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
-reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi3_address0_r;
-reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [15:0] builder_csrbank2_dfii_pi3_address0_w;
-reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
-reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
-wire builder_csrbank2_sel;
-wire [13:0] builder_csr_interconnect_adr;
-wire builder_csr_interconnect_we;
-wire [31:0] builder_csr_interconnect_dat_w;
-wire [31:0] builder_csr_interconnect_dat_r;
-reg  [1:0] builder_state = 2'd0;
-reg  [1:0] builder_next_state = 2'd0;
-reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
-reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg  builder_litedramcore_we_next_value2 = 1'd0;
-reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg  builder_rhs_array_muxed0 = 1'd0;
-reg  [15:0] builder_rhs_array_muxed1 = 16'd0;
-reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg  builder_rhs_array_muxed3 = 1'd0;
-reg  builder_rhs_array_muxed4 = 1'd0;
-reg  builder_rhs_array_muxed5 = 1'd0;
-reg  builder_t_array_muxed0 = 1'd0;
-reg  builder_t_array_muxed1 = 1'd0;
-reg  builder_t_array_muxed2 = 1'd0;
-reg  builder_rhs_array_muxed6 = 1'd0;
-reg  [15:0] builder_rhs_array_muxed7 = 16'd0;
-reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg  builder_rhs_array_muxed9 = 1'd0;
-reg  builder_rhs_array_muxed10 = 1'd0;
-reg  builder_rhs_array_muxed11 = 1'd0;
-reg  builder_t_array_muxed3 = 1'd0;
-reg  builder_t_array_muxed4 = 1'd0;
-reg  builder_t_array_muxed5 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed12 = 23'd0;
-reg  builder_rhs_array_muxed13 = 1'd0;
-reg  builder_rhs_array_muxed14 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed15 = 23'd0;
-reg  builder_rhs_array_muxed16 = 1'd0;
-reg  builder_rhs_array_muxed17 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed18 = 23'd0;
-reg  builder_rhs_array_muxed19 = 1'd0;
-reg  builder_rhs_array_muxed20 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed21 = 23'd0;
-reg  builder_rhs_array_muxed22 = 1'd0;
-reg  builder_rhs_array_muxed23 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed24 = 23'd0;
-reg  builder_rhs_array_muxed25 = 1'd0;
-reg  builder_rhs_array_muxed26 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed27 = 23'd0;
-reg  builder_rhs_array_muxed28 = 1'd0;
-reg  builder_rhs_array_muxed29 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed30 = 23'd0;
-reg  builder_rhs_array_muxed31 = 1'd0;
-reg  builder_rhs_array_muxed32 = 1'd0;
-reg  [22:0] builder_rhs_array_muxed33 = 23'd0;
-reg  builder_rhs_array_muxed34 = 1'd0;
-reg  builder_rhs_array_muxed35 = 1'd0;
-reg  [2:0] builder_array_muxed0 = 3'd0;
-reg  [15:0] builder_array_muxed1 = 16'd0;
-reg  builder_array_muxed2 = 1'd0;
-reg  builder_array_muxed3 = 1'd0;
-reg  builder_array_muxed4 = 1'd0;
-reg  builder_array_muxed5 = 1'd0;
-reg  builder_array_muxed6 = 1'd0;
-reg  [2:0] builder_array_muxed7 = 3'd0;
-reg  [15:0] builder_array_muxed8 = 16'd0;
-reg  builder_array_muxed9 = 1'd0;
-reg  builder_array_muxed10 = 1'd0;
-reg  builder_array_muxed11 = 1'd0;
-reg  builder_array_muxed12 = 1'd0;
-reg  builder_array_muxed13 = 1'd0;
-reg  [2:0] builder_array_muxed14 = 3'd0;
-reg  [15:0] builder_array_muxed15 = 16'd0;
-reg  builder_array_muxed16 = 1'd0;
-reg  builder_array_muxed17 = 1'd0;
-reg  builder_array_muxed18 = 1'd0;
-reg  builder_array_muxed19 = 1'd0;
-reg  builder_array_muxed20 = 1'd0;
-reg  [2:0] builder_array_muxed21 = 3'd0;
-reg  [15:0] builder_array_muxed22 = 16'd0;
-reg  builder_array_muxed23 = 1'd0;
-reg  builder_array_muxed24 = 1'd0;
-reg  builder_array_muxed25 = 1'd0;
-reg  builder_array_muxed26 = 1'd0;
-reg  builder_array_muxed27 = 1'd0;
-wire builder_xilinxasyncresetsynchronizerimpl0;
-wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl1;
-wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2;
-wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2_expr;
-wire builder_xilinxasyncresetsynchronizerimpl3;
-wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire reset;
+reg  power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg  [3:0] reset_counter = 4'd15;
+reg  ic_reset = 1'd1;
+reg  a7ddrphy_rst_storage = 1'd0;
+reg  a7ddrphy_rst_re = 1'd0;
+reg  [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg  a7ddrphy_dly_sel_re = 1'd0;
+reg  [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  a7ddrphy_wlevel_en_storage = 1'd0;
+reg  a7ddrphy_wlevel_en_re = 1'd0;
+reg  a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg  a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg  a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg  a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg  a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg  a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg  a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg  a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg  a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg  a7ddrphy_wrphase_re = 1'd0;
+wire [15:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [15:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [15:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [15:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg  a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_dqspattern0 = 1'd0;
+reg  a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg  [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg  [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg  [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg  [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg  [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg  [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg  [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg  [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg  [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg  [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg  [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg  [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg  [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg  [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg  [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg  [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg  [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg  [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg  [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg  [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg  [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg  [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg  [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg  [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg  [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg  [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg  [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg  [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg  [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg  [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg  [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg  [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg  [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg  [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg  [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [15:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg  [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg  litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [15:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg  [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg  litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [15:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg  [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg  litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [15:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg  [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg  litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [15:0] litedramcore_master_p0_address = 16'd0;
+reg  [2:0] litedramcore_master_p0_bank = 3'd0;
+reg  litedramcore_master_p0_cas_n = 1'd1;
+reg  litedramcore_master_p0_cs_n = 1'd1;
+reg  litedramcore_master_p0_ras_n = 1'd1;
+reg  litedramcore_master_p0_we_n = 1'd1;
+reg  litedramcore_master_p0_cke = 1'd0;
+reg  litedramcore_master_p0_odt = 1'd0;
+reg  litedramcore_master_p0_reset_n = 1'd0;
+reg  litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg  litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg  [15:0] litedramcore_master_p1_address = 16'd0;
+reg  [2:0] litedramcore_master_p1_bank = 3'd0;
+reg  litedramcore_master_p1_cas_n = 1'd1;
+reg  litedramcore_master_p1_cs_n = 1'd1;
+reg  litedramcore_master_p1_ras_n = 1'd1;
+reg  litedramcore_master_p1_we_n = 1'd1;
+reg  litedramcore_master_p1_cke = 1'd0;
+reg  litedramcore_master_p1_odt = 1'd0;
+reg  litedramcore_master_p1_reset_n = 1'd0;
+reg  litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg  litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg  [15:0] litedramcore_master_p2_address = 16'd0;
+reg  [2:0] litedramcore_master_p2_bank = 3'd0;
+reg  litedramcore_master_p2_cas_n = 1'd1;
+reg  litedramcore_master_p2_cs_n = 1'd1;
+reg  litedramcore_master_p2_ras_n = 1'd1;
+reg  litedramcore_master_p2_we_n = 1'd1;
+reg  litedramcore_master_p2_cke = 1'd0;
+reg  litedramcore_master_p2_odt = 1'd0;
+reg  litedramcore_master_p2_reset_n = 1'd0;
+reg  litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg  litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg  [15:0] litedramcore_master_p3_address = 16'd0;
+reg  [2:0] litedramcore_master_p3_bank = 3'd0;
+reg  litedramcore_master_p3_cas_n = 1'd1;
+reg  litedramcore_master_p3_cs_n = 1'd1;
+reg  litedramcore_master_p3_ras_n = 1'd1;
+reg  litedramcore_master_p3_we_n = 1'd1;
+reg  litedramcore_master_p3_cke = 1'd0;
+reg  litedramcore_master_p3_odt = 1'd0;
+reg  litedramcore_master_p3_reset_n = 1'd0;
+reg  litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg  litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [15:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg  litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg  litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [15:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg  litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg  litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [15:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg  litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg  litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [15:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg  litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg  litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg  [15:0] litedramcore_ext_dfi_p0_address = 16'd0;
+reg  [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg  litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cke = 1'd0;
+reg  litedramcore_ext_dfi_p0_odt = 1'd0;
+reg  litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg  [15:0] litedramcore_ext_dfi_p1_address = 16'd0;
+reg  [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg  litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cke = 1'd0;
+reg  litedramcore_ext_dfi_p1_odt = 1'd0;
+reg  litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg  [15:0] litedramcore_ext_dfi_p2_address = 16'd0;
+reg  [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg  litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cke = 1'd0;
+reg  litedramcore_ext_dfi_p2_odt = 1'd0;
+reg  litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg  [15:0] litedramcore_ext_dfi_p3_address = 16'd0;
+reg  [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg  litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cke = 1'd0;
+reg  litedramcore_ext_dfi_p3_odt = 1'd0;
+reg  litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg  litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg  [3:0] litedramcore_storage = 4'd1;
+reg  litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  litedramcore_phaseinjector0_command_re = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg  litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [15:0] litedramcore_phaseinjector0_address_storage = 16'd0;
+reg  litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg  litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  litedramcore_phaseinjector1_command_re = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg  litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [15:0] litedramcore_phaseinjector1_address_storage = 16'd0;
+reg  litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg  litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  litedramcore_phaseinjector2_command_re = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg  litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [15:0] litedramcore_phaseinjector2_address_storage = 16'd0;
+reg  litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg  litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  litedramcore_phaseinjector3_command_re = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg  litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [15:0] litedramcore_phaseinjector3_address_storage = 16'd0;
+reg  litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg  litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [22:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [22:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [22:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [22:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [22:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [22:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [22:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [22:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg  [127:0] litedramcore_interface_wdata = 128'd0;
+reg  [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg  [15:0] litedramcore_dfi_p0_address = 16'd0;
+reg  [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg  litedramcore_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg  litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg  litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg  litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg  [15:0] litedramcore_dfi_p1_address = 16'd0;
+reg  [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg  litedramcore_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg  litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg  litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg  litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg  [15:0] litedramcore_dfi_p2_address = 16'd0;
+reg  [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg  litedramcore_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg  litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg  litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg  litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg  [15:0] litedramcore_dfi_p3_address = 16'd0;
+reg  [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg  litedramcore_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg  litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg  litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg  litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg  litedramcore_cmd_valid = 1'd0;
+reg  litedramcore_cmd_ready = 1'd0;
+reg  litedramcore_cmd_last = 1'd0;
+reg  [15:0] litedramcore_cmd_payload_a = 16'd0;
+reg  [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg  litedramcore_cmd_payload_cas = 1'd0;
+reg  litedramcore_cmd_payload_ras = 1'd0;
+reg  litedramcore_cmd_payload_we = 1'd0;
+reg  litedramcore_cmd_payload_is_read = 1'd0;
+reg  litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg  [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg  litedramcore_postponer_req_o = 1'd0;
+reg  litedramcore_postponer_count = 1'd0;
+reg  litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg  litedramcore_sequencer_done1 = 1'd0;
+reg  [6:0] litedramcore_sequencer_counter = 7'd0;
+reg  litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg  [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  litedramcore_zqcs_executer_start = 1'd0;
+reg  litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [22:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg  litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg  litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg  litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg  [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine0_row = 16'd0;
+reg  litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg  litedramcore_bankmachine0_row_open = 1'd0;
+reg  litedramcore_bankmachine0_row_close = 1'd0;
+reg  litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [22:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg  litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg  litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg  litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg  [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine1_row = 16'd0;
+reg  litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg  litedramcore_bankmachine1_row_open = 1'd0;
+reg  litedramcore_bankmachine1_row_close = 1'd0;
+reg  litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [22:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg  litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg  litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg  litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg  [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine2_row = 16'd0;
+reg  litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg  litedramcore_bankmachine2_row_open = 1'd0;
+reg  litedramcore_bankmachine2_row_close = 1'd0;
+reg  litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [22:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg  litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg  litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg  litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg  [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine3_row = 16'd0;
+reg  litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg  litedramcore_bankmachine3_row_open = 1'd0;
+reg  litedramcore_bankmachine3_row_close = 1'd0;
+reg  litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [22:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg  litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg  litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg  litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg  [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine4_row = 16'd0;
+reg  litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg  litedramcore_bankmachine4_row_open = 1'd0;
+reg  litedramcore_bankmachine4_row_close = 1'd0;
+reg  litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [22:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg  litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg  litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg  litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg  [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine5_row = 16'd0;
+reg  litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg  litedramcore_bankmachine5_row_open = 1'd0;
+reg  litedramcore_bankmachine5_row_close = 1'd0;
+reg  litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [22:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg  litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg  litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg  litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg  [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine6_row = 16'd0;
+reg  litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg  litedramcore_bankmachine6_row_open = 1'd0;
+reg  litedramcore_bankmachine6_row_close = 1'd0;
+reg  litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [22:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg  litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg  litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg  litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg  [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [22:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [22:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0;
+reg  [15:0] litedramcore_bankmachine7_row = 16'd0;
+reg  litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg  litedramcore_bankmachine7_row_open = 1'd0;
+reg  litedramcore_bankmachine7_row_close = 1'd0;
+reg  litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg  litedramcore_choose_cmd_want_reads = 1'd0;
+reg  litedramcore_choose_cmd_want_writes = 1'd0;
+reg  litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg  litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [15:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg  litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg  [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg  litedramcore_choose_req_want_reads = 1'd0;
+reg  litedramcore_choose_req_want_writes = 1'd0;
+reg  litedramcore_choose_req_want_cmds = 1'd0;
+reg  litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg  litedramcore_choose_req_cmd_ready = 1'd0;
+wire [15:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg  litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg  [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg  [15:0] litedramcore_nop_a = 16'd0;
+reg  [2:0] litedramcore_nop_ba = 3'd0;
+reg  [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg  litedramcore_steerer0 = 1'd1;
+reg  litedramcore_steerer1 = 1'd1;
+reg  litedramcore_steerer2 = 1'd1;
+reg  litedramcore_steerer3 = 1'd1;
+reg  litedramcore_steerer4 = 1'd1;
+reg  litedramcore_steerer5 = 1'd1;
+reg  litedramcore_steerer6 = 1'd1;
+reg  litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_trrdcon_ready = 1'd0;
+reg  litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg  [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tccdcon_ready = 1'd0;
+reg  litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg  litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg  [4:0] litedramcore_time0 = 5'd0;
+reg  litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg  [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg  init_done_storage = 1'd0;
+reg  init_done_re = 1'd0;
+reg  init_error_storage = 1'd0;
+reg  init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [25:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg  [13:0] litedramcore_adr = 14'd0;
+reg  litedramcore_we = 1'd0;
+reg  [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg  [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg  litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg  litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg  [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg  csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg  csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg  csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg  csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg  [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg  csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg  csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg  csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg  csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg  csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg  csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg  csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg  csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg  csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg  csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg  csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg  csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg  [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg  csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg  csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg  csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg  csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg  csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi0_address0_r;
+reg  csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi0_address0_w;
+reg  csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg  csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg  csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg  csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg  csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg  csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg  csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg  csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg  csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi1_address0_r;
+reg  csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi1_address0_w;
+reg  csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg  csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg  csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg  csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg  csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg  csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg  csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg  csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg  csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi2_address0_r;
+reg  csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi2_address0_w;
+reg  csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg  csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg  csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg  csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg  csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg  csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg  csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg  csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg  csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi3_address0_r;
+reg  csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi3_address0_w;
+reg  csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg  csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg  csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg  csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg  csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg  csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg  [1:0] litedramcore_refresher_state = 2'd0;
+reg  [1:0] litedramcore_refresher_next_state = 2'd0;
+reg  [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg  litedramcore_locked0 = 1'd0;
+reg  litedramcore_locked1 = 1'd0;
+reg  litedramcore_locked2 = 1'd0;
+reg  litedramcore_locked3 = 1'd0;
+reg  litedramcore_locked4 = 1'd0;
+reg  litedramcore_locked5 = 1'd0;
+reg  litedramcore_locked6 = 1'd0;
+reg  litedramcore_locked7 = 1'd0;
+reg  litedramcore_new_master_wdata_ready0 = 1'd0;
+reg  litedramcore_new_master_wdata_ready1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid0 = 1'd0;
+reg  litedramcore_new_master_rdata_valid1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid2 = 1'd0;
+reg  litedramcore_new_master_rdata_valid3 = 1'd0;
+reg  litedramcore_new_master_rdata_valid4 = 1'd0;
+reg  litedramcore_new_master_rdata_valid5 = 1'd0;
+reg  litedramcore_new_master_rdata_valid6 = 1'd0;
+reg  litedramcore_new_master_rdata_valid7 = 1'd0;
+reg  litedramcore_new_master_rdata_valid8 = 1'd0;
+reg  [1:0] litedramcore_state = 2'd0;
+reg  [1:0] litedramcore_next_state = 2'd0;
+reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg  litedramcore_adr_next_value_ce1 = 1'd0;
+reg  litedramcore_we_next_value2 = 1'd0;
+reg  litedramcore_we_next_value_ce2 = 1'd0;
+reg  rhs_array_muxed0 = 1'd0;
+reg  [15:0] rhs_array_muxed1 = 16'd0;
+reg  [2:0] rhs_array_muxed2 = 3'd0;
+reg  rhs_array_muxed3 = 1'd0;
+reg  rhs_array_muxed4 = 1'd0;
+reg  rhs_array_muxed5 = 1'd0;
+reg  t_array_muxed0 = 1'd0;
+reg  t_array_muxed1 = 1'd0;
+reg  t_array_muxed2 = 1'd0;
+reg  rhs_array_muxed6 = 1'd0;
+reg  [15:0] rhs_array_muxed7 = 16'd0;
+reg  [2:0] rhs_array_muxed8 = 3'd0;
+reg  rhs_array_muxed9 = 1'd0;
+reg  rhs_array_muxed10 = 1'd0;
+reg  rhs_array_muxed11 = 1'd0;
+reg  t_array_muxed3 = 1'd0;
+reg  t_array_muxed4 = 1'd0;
+reg  t_array_muxed5 = 1'd0;
+reg  [22:0] rhs_array_muxed12 = 23'd0;
+reg  rhs_array_muxed13 = 1'd0;
+reg  rhs_array_muxed14 = 1'd0;
+reg  [22:0] rhs_array_muxed15 = 23'd0;
+reg  rhs_array_muxed16 = 1'd0;
+reg  rhs_array_muxed17 = 1'd0;
+reg  [22:0] rhs_array_muxed18 = 23'd0;
+reg  rhs_array_muxed19 = 1'd0;
+reg  rhs_array_muxed20 = 1'd0;
+reg  [22:0] rhs_array_muxed21 = 23'd0;
+reg  rhs_array_muxed22 = 1'd0;
+reg  rhs_array_muxed23 = 1'd0;
+reg  [22:0] rhs_array_muxed24 = 23'd0;
+reg  rhs_array_muxed25 = 1'd0;
+reg  rhs_array_muxed26 = 1'd0;
+reg  [22:0] rhs_array_muxed27 = 23'd0;
+reg  rhs_array_muxed28 = 1'd0;
+reg  rhs_array_muxed29 = 1'd0;
+reg  [22:0] rhs_array_muxed30 = 23'd0;
+reg  rhs_array_muxed31 = 1'd0;
+reg  rhs_array_muxed32 = 1'd0;
+reg  [22:0] rhs_array_muxed33 = 23'd0;
+reg  rhs_array_muxed34 = 1'd0;
+reg  rhs_array_muxed35 = 1'd0;
+reg  [2:0] array_muxed0 = 3'd0;
+reg  [15:0] array_muxed1 = 16'd0;
+reg  array_muxed2 = 1'd0;
+reg  array_muxed3 = 1'd0;
+reg  array_muxed4 = 1'd0;
+reg  array_muxed5 = 1'd0;
+reg  array_muxed6 = 1'd0;
+reg  [2:0] array_muxed7 = 3'd0;
+reg  [15:0] array_muxed8 = 16'd0;
+reg  array_muxed9 = 1'd0;
+reg  array_muxed10 = 1'd0;
+reg  array_muxed11 = 1'd0;
+reg  array_muxed12 = 1'd0;
+reg  array_muxed13 = 1'd0;
+reg  [2:0] array_muxed14 = 3'd0;
+reg  [15:0] array_muxed15 = 16'd0;
+reg  array_muxed16 = 1'd0;
+reg  array_muxed17 = 1'd0;
+reg  array_muxed18 = 1'd0;
+reg  array_muxed19 = 1'd0;
+reg  array_muxed20 = 1'd0;
+reg  [2:0] array_muxed21 = 3'd0;
+reg  [15:0] array_muxed22 = 16'd0;
+reg  array_muxed23 = 1'd0;
+reg  array_muxed24 = 1'd0;
+reg  array_muxed25 = 1'd0;
+reg  array_muxed26 = 1'd0;
+reg  array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = main_init_done_storage;
-assign init_error = main_init_error_storage;
-assign main_wb_bus_adr = wb_ctrl_adr;
-assign main_wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = main_wb_bus_dat_r;
-assign main_wb_bus_sel = wb_ctrl_sel;
-assign main_wb_bus_cyc = wb_ctrl_cyc;
-assign main_wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = main_wb_bus_ack;
-assign main_wb_bus_we = wb_ctrl_we;
-assign main_wb_bus_cti = wb_ctrl_cti;
-assign main_wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = main_wb_bus_err;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_enable = 1'd1;
-assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
-assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
-assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
-assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
-assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
-assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
-assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = (rst | main_rst);
-assign pll_locked = main_locked;
-assign main_clkin = clk;
-assign iodelay_clk = main_clkout_buf0;
-assign sys_clk = main_clkout_buf1;
-assign sys4x_clk = main_clkout_buf2;
-assign sys4x_dqs_clk = main_clkout_buf3;
-assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
-assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-always @(*) begin
-	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
-	main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
-	main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
-	main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
-	main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
-	main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
-	main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
-	main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
-	main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
-	main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
-	main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
-	main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
-	main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
-	main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
-	main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
-	main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
-	main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
-	main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
-	main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
-	main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
-	main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
-	main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
-	main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
-	main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
-	main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
-	main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
-	main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
-	main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
-	main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
-	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
-	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
-	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
-	main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
-	main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
-	main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
-	main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
-	main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
-	main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
-	main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
-	main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
-	main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
-	main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
-	main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
-	main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
-	main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
-	main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
-	main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
-	main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
-	main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
-	main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
-	main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
-	main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
-	main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
-	main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
-	main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
-	main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
-	main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
-	main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
-	main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
-	main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
-	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
-	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
-	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
-	main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
-	main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
-	main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
-	main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
-	main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
-	main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
-	main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
-	main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
-	main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
-	main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
-	main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
-	main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
-	main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
-	main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
-	main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
-	main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
-	main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
-	main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
-	main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
-	main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
-	main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
-	main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
-	main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
-	main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
-	main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
-	main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
-	main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
-	main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
-	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
-	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
-	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
-	main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
-	main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
-	main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
-	main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
-	main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
-	main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
-	main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
-	main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
-	main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
-	main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
-	main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
-	main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
-	main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
-	main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
-	main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
-	main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
-	main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
-	main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
-	main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
-	main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
-	main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
-	main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
-	main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
-	main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
-	main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
-	main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
-	main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
-	main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
-	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
-	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
-	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-end
-assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-	main_a7ddrphy_dqs_oe <= 1'd0;
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqs_oe <= 1'd1;
-	end else begin
-		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
-	end
-end
-assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-always @(*) begin
-	main_a7ddrphy_dqspattern_o0 <= 8'd0;
-	main_a7ddrphy_dqspattern_o0 <= 7'd85;
-	if (main_a7ddrphy_dqspattern0) begin
-		main_a7ddrphy_dqspattern_o0 <= 5'd21;
-	end
-	if (main_a7ddrphy_dqspattern1) begin
-		main_a7ddrphy_dqspattern_o0 <= 7'd84;
-	end
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqspattern_o0 <= 1'd0;
-		if (main_a7ddrphy_wlevel_strobe_re) begin
-			main_a7ddrphy_dqspattern_o0 <= 1'd1;
-		end
-	end
-end
-always @(*) begin
-	main_a7ddrphy_bitslip00 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value0)
+assign user_enable = 1'd1;
+assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
+assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
+assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
+assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign reset = (rst | rst_1);
+assign pll_locked = locked;
+assign clkin = clk;
+assign iodelay_clk = clkout_buf0;
+assign sys_clk = clkout_buf1;
+assign sys4x_clk = clkout_buf2;
+assign sys4x_dqs_clk = clkout_buf3;
+assign ddram_ba = a7ddrphy_pads_ba;
+assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
+assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
+always @(*) begin
+	a7ddrphy_dfi_p0_rddata <= 32'd0;
+	a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+	a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+	a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+	a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+	a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+	a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+	a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+	a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+	a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+	a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+	a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+	a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+	a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+	a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+	a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+	a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+	a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+	a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+	a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+	a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+	a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+	a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+	a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+	a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+	a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+	a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+	a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+	a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+	a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+	a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+	a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+	a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+	a7ddrphy_dfi_p1_rddata <= 32'd0;
+	a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+	a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+	a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+	a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+	a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+	a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+	a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+	a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+	a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+	a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+	a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+	a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+	a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+	a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+	a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+	a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+	a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+	a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+	a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+	a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+	a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+	a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+	a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+	a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+	a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+	a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+	a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+	a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+	a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+	a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+	a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+	a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+	a7ddrphy_dfi_p2_rddata <= 32'd0;
+	a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+	a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+	a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+	a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+	a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+	a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+	a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+	a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+	a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+	a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+	a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+	a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+	a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+	a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+	a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+	a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+	a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+	a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+	a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+	a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+	a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+	a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+	a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+	a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+	a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+	a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+	a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+	a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+	a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+	a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+	a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+	a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+	a7ddrphy_dfi_p3_rddata <= 32'd0;
+	a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+	a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+	a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+	a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+	a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+	a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+	a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+	a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+	a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+	a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+	a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+	a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+	a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+	a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+	a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+	a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+	a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+	a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+	a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+	a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+	a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+	a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+	a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+	a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+	a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+	a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+	a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+	a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+	a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+	a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+	a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+	a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+end
+assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+	a7ddrphy_dqs_oe <= 1'd0;
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqs_oe <= 1'd1;
+	end else begin
+		a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+	end
+end
+assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+always @(*) begin
+	a7ddrphy_dqspattern_o0 <= 8'd0;
+	a7ddrphy_dqspattern_o0 <= 7'd85;
+	if (a7ddrphy_dqspattern0) begin
+		a7ddrphy_dqspattern_o0 <= 5'd21;
+	end
+	if (a7ddrphy_dqspattern1) begin
+		a7ddrphy_dqspattern_o0 <= 7'd84;
+	end
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqspattern_o0 <= 1'd0;
+		if (a7ddrphy_wlevel_strobe_re) begin
+			a7ddrphy_dqspattern_o0 <= 1'd1;
+		end
+	end
+end
+always @(*) begin
+	a7ddrphy_bitslip00 <= 8'd0;
+	case (a7ddrphy_bitslip0_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip10 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value0)
+	a7ddrphy_bitslip10 <= 8'd0;
+	case (a7ddrphy_bitslip1_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip01 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value1)
+	a7ddrphy_bitslip01 <= 8'd0;
+	case (a7ddrphy_bitslip0_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip11 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value1)
+	a7ddrphy_bitslip11 <= 8'd0;
+	case (a7ddrphy_bitslip1_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip02 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value2)
+	a7ddrphy_bitslip02 <= 8'd0;
+	case (a7ddrphy_bitslip0_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip04 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value3)
+	a7ddrphy_bitslip04 <= 8'd0;
+	case (a7ddrphy_bitslip0_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip12 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value2)
+	a7ddrphy_bitslip12 <= 8'd0;
+	case (a7ddrphy_bitslip1_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip14 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value3)
+	a7ddrphy_bitslip14 <= 8'd0;
+	case (a7ddrphy_bitslip1_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip20 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value0)
+	a7ddrphy_bitslip20 <= 8'd0;
+	case (a7ddrphy_bitslip2_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip22 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value1)
+	a7ddrphy_bitslip22 <= 8'd0;
+	case (a7ddrphy_bitslip2_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip30 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value0)
+	a7ddrphy_bitslip30 <= 8'd0;
+	case (a7ddrphy_bitslip3_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip32 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value1)
+	a7ddrphy_bitslip32 <= 8'd0;
+	case (a7ddrphy_bitslip3_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip40 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value0)
+	a7ddrphy_bitslip40 <= 8'd0;
+	case (a7ddrphy_bitslip4_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip42 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value1)
+	a7ddrphy_bitslip42 <= 8'd0;
+	case (a7ddrphy_bitslip4_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip50 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value0)
+	a7ddrphy_bitslip50 <= 8'd0;
+	case (a7ddrphy_bitslip5_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip52 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value1)
+	a7ddrphy_bitslip52 <= 8'd0;
+	case (a7ddrphy_bitslip5_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip60 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value0)
+	a7ddrphy_bitslip60 <= 8'd0;
+	case (a7ddrphy_bitslip6_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip62 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value1)
+	a7ddrphy_bitslip62 <= 8'd0;
+	case (a7ddrphy_bitslip6_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip70 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value0)
+	a7ddrphy_bitslip70 <= 8'd0;
+	case (a7ddrphy_bitslip7_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip72 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value1)
+	a7ddrphy_bitslip72 <= 8'd0;
+	case (a7ddrphy_bitslip7_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip80 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value0)
+	a7ddrphy_bitslip80 <= 8'd0;
+	case (a7ddrphy_bitslip8_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip82 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value1)
+	a7ddrphy_bitslip82 <= 8'd0;
+	case (a7ddrphy_bitslip8_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip90 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value0)
+	a7ddrphy_bitslip90 <= 8'd0;
+	case (a7ddrphy_bitslip9_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip92 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value1)
+	a7ddrphy_bitslip92 <= 8'd0;
+	case (a7ddrphy_bitslip9_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip100 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value0)
+	a7ddrphy_bitslip100 <= 8'd0;
+	case (a7ddrphy_bitslip10_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip102 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value1)
+	a7ddrphy_bitslip102 <= 8'd0;
+	case (a7ddrphy_bitslip10_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip110 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value0)
+	a7ddrphy_bitslip110 <= 8'd0;
+	case (a7ddrphy_bitslip11_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip112 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value1)
+	a7ddrphy_bitslip112 <= 8'd0;
+	case (a7ddrphy_bitslip11_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip120 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value0)
+	a7ddrphy_bitslip120 <= 8'd0;
+	case (a7ddrphy_bitslip12_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip122 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value1)
+	a7ddrphy_bitslip122 <= 8'd0;
+	case (a7ddrphy_bitslip12_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip130 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value0)
+	a7ddrphy_bitslip130 <= 8'd0;
+	case (a7ddrphy_bitslip13_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip132 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value1)
+	a7ddrphy_bitslip132 <= 8'd0;
+	case (a7ddrphy_bitslip13_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip140 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value0)
+	a7ddrphy_bitslip140 <= 8'd0;
+	case (a7ddrphy_bitslip14_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip142 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value1)
+	a7ddrphy_bitslip142 <= 8'd0;
+	case (a7ddrphy_bitslip14_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip150 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value0)
+	a7ddrphy_bitslip150 <= 8'd0;
+	case (a7ddrphy_bitslip15_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip152 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value1)
+	a7ddrphy_bitslip152 <= 8'd0;
+	case (a7ddrphy_bitslip15_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
-		end
-		1'd1: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
-		end
-		2'd2: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
-		end
-		2'd3: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
-		end
-		3'd4: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
-		end
-		3'd5: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
-		end
-		3'd6: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
-		end
-		3'd7: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
-		end
-	endcase
-end
-assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
-assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
-assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
-assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
-assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
-assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
-assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
-assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
-assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
-assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
-assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
-assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
-assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
-assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
-assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
-assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
-assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
-assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
-assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
-assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
-assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
-assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
-assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
-assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
-assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
-assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
-assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
-assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
-assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
-assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
-assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
-assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
-assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
-assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
-assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
-assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
-assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
-assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
-assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
-assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
-assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
-assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
-assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
-assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
-assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
-assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
-assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
-assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
-assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
-assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
-assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
-assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
-assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
-assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
-assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
-assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
-assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
-assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
-assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
-assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
-assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
-assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
-assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
-assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
-assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
-assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
-assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
-assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
-assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
-assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
-assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
-assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
-assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
-assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
-assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
-assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
-assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
-assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
-assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
-assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
-assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
-assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
-assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
-assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
-assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
-assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
-assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
-assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
-assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
-assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
-assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
-assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
-assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
-assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
-assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
-assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
-assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
-assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
-assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
-assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
-assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
-assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
-assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
-assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
-assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
-assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
-assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
-assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
-assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
-assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
-assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
-assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
-assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
-assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
-assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
-assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
-assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
-assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
-assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
-assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
-assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
-assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
-assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
-assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
-assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
-assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
-assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
-assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+		end
+		1'd1: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+		end
+		2'd2: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+		end
+		2'd3: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+		end
+		3'd4: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+		end
+		3'd5: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+		end
+		3'd6: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+		end
+		3'd7: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+		end
+	endcase
+end
+assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
+assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
+assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
+assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+	litedramcore_master_p3_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+		end else begin
+			litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+		end
+	end else begin
+		litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+	end
+end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+	litedramcore_master_p3_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+		end else begin
+			litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+		litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p3_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+		end else begin
+			litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+	litedramcore_master_p3_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+		end else begin
+			litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+		litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p3_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+		end else begin
+			litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
+	litedramcore_master_p3_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+		end else begin
+			litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
+		litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
+	litedramcore_master_p3_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+		end else begin
+			litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+		litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_address <= 16'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+	litedramcore_master_p3_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+		end else begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+		litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
+	litedramcore_master_p3_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+		end else begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
+		litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
+	litedramcore_master_p3_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+		end else begin
+			litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
+		litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+	litedramcore_csr_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
+		litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+	litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
+		litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+	litedramcore_csr_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
+		litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
+	litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
+		litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	litedramcore_csr_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
+		litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
+	litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
+		litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
+	litedramcore_csr_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
+		litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
+	litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
+		litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
+	litedramcore_ext_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
+	litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_ext_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
+	litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_ext_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
+	litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	litedramcore_slave_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_address <= 16'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
+	litedramcore_slave_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
+	litedramcore_ext_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
+	litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+	litedramcore_slave_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
+	litedramcore_slave_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
+	litedramcore_slave_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	litedramcore_slave_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
+	litedramcore_slave_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
+	litedramcore_slave_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
+	litedramcore_master_p0_address <= 16'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+		end else begin
+			litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+		end
 	end else begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
+		litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
+	litedramcore_master_p0_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+		end else begin
+			litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+		end
 	end else begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
+		litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
+	litedramcore_master_p0_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+		end else begin
+			litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+		end
+	end else begin
+		litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+		end else begin
+			litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
+		litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
+	litedramcore_master_p0_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+		end else begin
+			litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+		end
+	end else begin
+		litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+		end else begin
+			litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
+		litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p0_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+		end else begin
+			litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
+		litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
+	litedramcore_master_p0_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+		end else begin
+			litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
+		litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p0_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+		end else begin
+			litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+		litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
+	litedramcore_master_p0_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+		end else begin
+			litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
+		litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
+	litedramcore_master_p0_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+		end else begin
+			litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
+		litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_address <= 16'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
+	litedramcore_master_p0_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+		end else begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
+		litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
+	litedramcore_master_p0_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+		end else begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+		end
+	end else begin
+		litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+		end else begin
+			litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+		end
+	end else begin
+		litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+	end
+end
+always @(*) begin
+	litedramcore_master_p1_address <= 16'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+		end else begin
+			litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+		end
+	end else begin
+		litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+	end
+end
+always @(*) begin
+	litedramcore_master_p1_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+		end else begin
+			litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+		end
+	end else begin
+		litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+	end
+end
+always @(*) begin
+	litedramcore_master_p1_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+		end else begin
+			litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+		end
+	end else begin
+		litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p1_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+		end else begin
+			litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
+		litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
+	litedramcore_master_p1_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+		end else begin
+			litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
+		litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+	litedramcore_master_p1_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+		end else begin
+			litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
+		litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	litedramcore_master_p1_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+		end else begin
+			litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+		end
 	end else begin
+		litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
+	litedramcore_master_p1_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+		end else begin
+			litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+		end
 	end else begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
+		litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
+	litedramcore_master_p1_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+		end else begin
+			litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+		end
 	end else begin
+		litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
+	litedramcore_master_p1_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+		end else begin
+			litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
+		litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	litedramcore_master_p1_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+		end else begin
+			litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+		end
 	end else begin
+		litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
+	litedramcore_master_p1_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+		end else begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
+		litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
+	litedramcore_master_p1_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+		end else begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
+		litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
+	litedramcore_master_p1_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+		end else begin
+			litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
+		litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
+	litedramcore_master_p2_address <= 16'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+		end else begin
+			litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+		end
 	end else begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
+		litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
+	litedramcore_master_p2_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+		end else begin
+			litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
+		litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+		end else begin
+			litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
+		litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
+	litedramcore_master_p2_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+		end else begin
+			litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
+		litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+		end else begin
+			litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+		litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
+	litedramcore_master_p2_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+		end else begin
+			litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
+		litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
+	litedramcore_master_p2_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+		end else begin
+			litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+		end
 	end else begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
+		litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_address <= 16'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
+	litedramcore_master_p2_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+		end else begin
+			litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
+		litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
+	litedramcore_master_p2_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+		end else begin
+			litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
+		litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
+	litedramcore_master_p2_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+		end else begin
+			litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
+		litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+	litedramcore_master_p2_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+		end else begin
+			litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
+		litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
+	litedramcore_master_p2_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+		end else begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
+		litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
+	litedramcore_master_p2_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+		end else begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+		end
 	end else begin
+		litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
+	litedramcore_master_p2_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+		end else begin
+			litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
+		litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
+	litedramcore_master_p3_address <= 16'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+		end else begin
+			litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+		end
 	end else begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
+		litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
+	litedramcore_master_p3_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+		end else begin
+			litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+		end
 	end else begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
+		litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
+	litedramcore_master_p3_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+		end else begin
+			litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
+		litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
+	litedramcore_master_p3_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+		end else begin
+			litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
+		litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
 	end
 end
-assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p2_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p3_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p0_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p1_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p2_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p3_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+	litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+	litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+	litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	litedramcore_csr_dfi_p0_we_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
-assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
-assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]);
-assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
-assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
-assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
+assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
+assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+	litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+	litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+	litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	litedramcore_csr_dfi_p1_we_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
-assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
-assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]);
-assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
-assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
-assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
+assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
+assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+	litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p2_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+	litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p2_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	litedramcore_csr_dfi_p2_we_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		litedramcore_csr_dfi_p2_we_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
-assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
-assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]);
-assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
-assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
-assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
+assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
+assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+	litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p3_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+	litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+	litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p3_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	litedramcore_csr_dfi_p3_we_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		litedramcore_csr_dfi_p3_we_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
-assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
-assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]);
-assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]);
-assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
-assign main_litedramcore_inti_p3_wrdata_mask = 1'd0;
-assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
-assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
-assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
-assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
-assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
-assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
-assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
-assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
-assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
-assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
-assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
-assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
-assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
-assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
-assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
-assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
-assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
-assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
-assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
-assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
-assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
-assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
-assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
-assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
-assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
-assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
-assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
-assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
-assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
-assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
-assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
-assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
-assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
-assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
-assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
-assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
-assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
-assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
-assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
-assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
-assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
-assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
-assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
-assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
-assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
-assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
-assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
-assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
-assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
-assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
-assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
-assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
-assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
-assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
-assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
-assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
-assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
-assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
-assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
-assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
-assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
-assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
-assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
-assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
-assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
-assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
-assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
-assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
-assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-always @(*) begin
-	builder_refresher_next_state <= 2'd0;
-	builder_refresher_next_state <= builder_refresher_state;
-	case (builder_refresher_state)
-		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				builder_refresher_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					builder_refresher_next_state <= 2'd3;
+assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
+assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
+assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+always @(*) begin
+	litedramcore_refresher_next_state <= 2'd0;
+	litedramcore_refresher_next_state <= litedramcore_refresher_state;
+	case (litedramcore_refresher_state)
+		1'd1: begin
+			if (litedramcore_cmd_ready) begin
+				litedramcore_refresher_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_refresher_next_state <= 2'd3;
 				end else begin
-					builder_refresher_next_state <= 1'd0;
+					litedramcore_refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				builder_refresher_next_state <= 1'd0;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
-				if (main_litedramcore_wants_refresh) begin
-					builder_refresher_next_state <= 1'd1;
+				if (litedramcore_wants_refresh) begin
+					litedramcore_refresher_next_state <= 1'd1;
 				end
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_valid <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
+			litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
 				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
+					litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_valid <= 1'd0;
 			end
 		end
 		default: begin
@@ -4149,14 +4568,14 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_zqcs_executer_start <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
 				end
 			end
@@ -4168,21 +4587,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_last <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
+					litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_last <= 1'd1;
 			end
 		end
 		default: begin
@@ -4190,11 +4609,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_sequencer_start0 <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
+			if (litedramcore_cmd_ready) begin
+				litedramcore_sequencer_start0 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4205,127 +4624,127 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
-assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
-assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7];
+	litedramcore_bankmachine0_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+		litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7];
 	end else begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
-assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
-assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+	litedramcore_bankmachine0_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+	litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine0_next_state <= 4'd0;
-	builder_bankmachine0_next_state <= builder_bankmachine0_state;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_next_state <= 4'd0;
+	litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd7;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine0_refresh_req)) begin
-				builder_bankmachine0_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine0_refresh_req)) begin
+				litedramcore_bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine0_next_state <= 3'd6;
+			litedramcore_bankmachine0_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine0_next_state <= 2'd3;
+			litedramcore_bankmachine0_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine0_next_state <= 4'd8;
+			litedramcore_bankmachine0_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine0_next_state <= 1'd0;
+			litedramcore_bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-				builder_bankmachine0_next_state <= 3'd4;
+			if (litedramcore_bankmachine0_refresh_req) begin
+				litedramcore_bankmachine0_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
-								builder_bankmachine0_next_state <= 2'd2;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+								litedramcore_bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine0_next_state <= 1'd1;
+							litedramcore_bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine0_next_state <= 2'd3;
+						litedramcore_bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4333,8 +4752,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4352,14 +4771,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+								litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -4371,8 +4790,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4380,9 +4799,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -4393,23 +4809,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -4422,12 +4847,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+							end else begin
+							end
 						end else begin
 						end
 					end else begin
@@ -4438,16 +4866,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_open <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -4460,22 +4885,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_close <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			if (litedramcore_bankmachine0_twtpcon_ready) begin
+				litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -4490,13 +4930,19 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -4509,12 +4955,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4525,18 +4971,41 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_open <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_open <= 1'd1;
 			end
 		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4554,15 +5023,79 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_close <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd2: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4580,11 +5113,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4602,13 +5135,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4621,22 +5154,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4650,38 +5183,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+		litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7];
+	end else begin
+		litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+always @(*) begin
+	litedramcore_bankmachine1_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_next_state <= 4'd0;
+	litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine1_refresh_req)) begin
+				litedramcore_bankmachine1_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+				litedramcore_bankmachine1_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+								litedramcore_bankmachine1_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4689,8 +5311,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4708,14 +5330,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -4727,8 +5349,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4746,13 +5368,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4764,127 +5386,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
-assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
-assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7];
-	end else begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
-assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine1_next_state <= 4'd0;
-	builder_bankmachine1_next_state <= builder_bankmachine1_state;
-	case (builder_bankmachine1_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd5;
-				end
-			end
+always @(*) begin
+	litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine1_state)
+		1'd1: begin
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				builder_bankmachine1_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine1_refresh_req)) begin
-				builder_bankmachine1_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-				builder_bankmachine1_next_state <= 3'd4;
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
-								builder_bankmachine1_next_state <= 2'd2;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+							end else begin
 							end
 						end else begin
-							builder_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4892,8 +5425,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4911,14 +5444,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+								litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -4930,8 +5463,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4939,8 +5472,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine1_twtpcon_ready) begin
+				litedramcore_bankmachine1_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -4956,18 +5489,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4981,12 +5514,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4997,15 +5530,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_open <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_open <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5023,18 +5556,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_close <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_close <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5049,8 +5582,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5068,12 +5601,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5084,18 +5617,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5113,11 +5646,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5135,13 +5668,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5154,22 +5687,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5184,15 +5713,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5203,56 +5739,130 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+		litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7];
+	end else begin
+		litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+always @(*) begin
+	litedramcore_bankmachine2_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine2_next_state <= 4'd0;
+	litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine2_refresh_req)) begin
+				litedramcore_bankmachine2_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+				litedramcore_bankmachine2_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-							end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+								litedramcore_bankmachine2_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5260,16 +5870,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -5282,12 +5889,27 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5305,13 +5927,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5323,127 +5945,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
-assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7];
-	end else begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
-assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine2_next_state <= 4'd0;
-	builder_bankmachine2_next_state <= builder_bankmachine2_state;
-	case (builder_bankmachine2_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd5;
-				end
-			end
+always @(*) begin
+	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				builder_bankmachine2_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine2_refresh_req)) begin
-				builder_bankmachine2_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-				builder_bankmachine2_next_state <= 3'd4;
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
-								builder_bankmachine2_next_state <= 2'd2;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+							end else begin
 							end
 						end else begin
-							builder_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5451,8 +5984,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5470,14 +6003,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
 							end
 						end else begin
 						end
@@ -5489,18 +6022,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5515,21 +6048,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (litedramcore_bankmachine2_twtpcon_ready) begin
+				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -5540,31 +6070,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5578,19 +6099,31 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_open <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_open <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_open <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5608,18 +6141,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_close <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_close <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5634,8 +6167,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5653,12 +6186,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5669,18 +6202,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5698,11 +6231,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5720,13 +6253,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5739,22 +6272,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5768,38 +6301,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+		litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7];
+	end else begin
+		litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+always @(*) begin
+	litedramcore_bankmachine3_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine3_next_state <= 4'd0;
+	litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine3_refresh_req)) begin
+				litedramcore_bankmachine3_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+				litedramcore_bankmachine3_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+								litedramcore_bankmachine3_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5807,8 +6429,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5826,14 +6448,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5845,8 +6467,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5864,13 +6486,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5882,127 +6504,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
-assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
-assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7];
-	end else begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
-assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine3_next_state <= 4'd0;
-	builder_bankmachine3_next_state <= builder_bankmachine3_state;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd5;
-				end
-			end
+always @(*) begin
+	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine3_state)
+		1'd1: begin
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				builder_bankmachine3_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine3_refresh_req)) begin
-				builder_bankmachine3_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-				builder_bankmachine3_next_state <= 3'd4;
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
-								builder_bankmachine3_next_state <= 2'd2;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+							end else begin
 							end
 						end else begin
-							builder_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6010,8 +6543,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6029,14 +6562,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+								litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -6048,8 +6581,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6057,8 +6590,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine3_twtpcon_ready) begin
+				litedramcore_bankmachine3_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -6074,18 +6607,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6099,12 +6632,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6115,15 +6648,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_open <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6141,18 +6674,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_close <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_open <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6167,18 +6700,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_close <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6193,8 +6726,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6212,12 +6745,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6228,18 +6761,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6257,11 +6790,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6279,13 +6812,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6298,22 +6831,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6327,38 +6860,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+		litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7];
+	end else begin
+		litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+always @(*) begin
+	litedramcore_bankmachine4_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine4_next_state <= 4'd0;
+	litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine4_refresh_req)) begin
+				litedramcore_bankmachine4_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+				litedramcore_bankmachine4_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+								litedramcore_bankmachine4_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6366,8 +6988,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6385,14 +7007,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6404,8 +7026,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6423,13 +7045,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6441,127 +7063,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
-assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
-assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7];
-	end else begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
-assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine4_next_state <= 4'd0;
-	builder_bankmachine4_next_state <= builder_bankmachine4_state;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd5;
-				end
-			end
+always @(*) begin
+	litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				builder_bankmachine4_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine4_refresh_req)) begin
-				builder_bankmachine4_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-				builder_bankmachine4_next_state <= 3'd4;
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
-								builder_bankmachine4_next_state <= 2'd2;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+							end else begin
 							end
 						end else begin
-							builder_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6569,8 +7102,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6588,14 +7121,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+								litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
 						end
@@ -6607,18 +7140,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (litedramcore_bankmachine4_twtpcon_ready) begin
+				litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -6633,18 +7166,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6655,22 +7191,31 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_open <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6684,34 +7229,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_close <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6726,18 +7259,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6748,17 +7278,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6771,35 +7319,20 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -6812,22 +7345,41 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6838,41 +7390,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6886,38 +7419,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+		litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7];
+	end else begin
+		litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+always @(*) begin
+	litedramcore_bankmachine5_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine5_next_state <= 4'd0;
+	litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine5_refresh_req)) begin
+				litedramcore_bankmachine5_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+				litedramcore_bankmachine5_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+								litedramcore_bankmachine5_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6925,8 +7547,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6944,14 +7566,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6963,13 +7585,16 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6982,145 +7607,41 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
-assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
-assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7];
-	end else begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
-assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine5_next_state <= 4'd0;
-	builder_bankmachine5_next_state <= builder_bankmachine5_state;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd5;
-				end
-			end
+always @(*) begin
+	litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine5_state)
+		1'd1: begin
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				builder_bankmachine5_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-				builder_bankmachine5_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-				builder_bankmachine5_next_state <= 3'd4;
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-								builder_bankmachine5_next_state <= 2'd2;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+							end else begin
 							end
 						end else begin
-							builder_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7128,8 +7649,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7147,14 +7668,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
 							end
 						end else begin
 						end
@@ -7166,16 +7687,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -7188,12 +7706,27 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7201,8 +7734,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine5_twtpcon_ready) begin
+				litedramcore_bankmachine5_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -7218,18 +7751,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7243,12 +7776,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7259,15 +7792,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_open <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_open <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_open <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7285,18 +7818,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_close <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_close <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7311,8 +7844,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7330,12 +7863,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7346,18 +7879,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7375,11 +7908,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7397,13 +7930,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7416,22 +7949,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7445,38 +7978,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+	litedramcore_bankmachine6_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+		litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7];
+	end else begin
+		litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+always @(*) begin
+	litedramcore_bankmachine6_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine6_next_state <= 4'd0;
+	litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine6_refresh_req)) begin
+				litedramcore_bankmachine6_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+				litedramcore_bankmachine6_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+								litedramcore_bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7484,8 +8106,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7503,14 +8125,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7522,8 +8144,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7541,13 +8163,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7559,127 +8181,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
-assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
-assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7];
-	end else begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
-assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine6_next_state <= 4'd0;
-	builder_bankmachine6_next_state <= builder_bankmachine6_state;
-	case (builder_bankmachine6_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd5;
-				end
-			end
+always @(*) begin
+	litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine6_state)
+		1'd1: begin
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				builder_bankmachine6_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine6_refresh_req)) begin
-				builder_bankmachine6_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-				builder_bankmachine6_next_state <= 3'd4;
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
-								builder_bankmachine6_next_state <= 2'd2;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+							end else begin
 							end
 						end else begin
-							builder_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7687,8 +8220,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7706,14 +8239,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+								litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
 							end
 						end else begin
 						end
@@ -7725,18 +8258,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7751,21 +8284,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (litedramcore_bankmachine6_twtpcon_ready) begin
+				litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7776,31 +8306,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7814,19 +8335,31 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_open <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7844,18 +8377,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_close <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7870,8 +8403,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7889,12 +8422,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7905,18 +8438,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7934,11 +8467,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7956,13 +8489,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7975,22 +8508,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8004,38 +8537,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+	litedramcore_bankmachine7_cmd_payload_a <= 16'd0;
+	if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+		litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7];
+	end else begin
+		litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+always @(*) begin
+	litedramcore_bankmachine7_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7])) begin
+			litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine7_next_state <= 4'd0;
+	litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine7_refresh_req)) begin
+				litedramcore_bankmachine7_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+				litedramcore_bankmachine7_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+								litedramcore_bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8043,8 +8665,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8062,14 +8684,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8081,8 +8703,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8100,13 +8722,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8118,127 +8740,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
-assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
-assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_a <= 16'd0;
-	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7];
-	end else begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
-assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[22:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7])) begin
-			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine7_next_state <= 4'd0;
-	builder_bankmachine7_next_state <= builder_bankmachine7_state;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd5;
-				end
-			end
+always @(*) begin
+	litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine7_state)
+		1'd1: begin
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				builder_bankmachine7_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine7_refresh_req)) begin
-				builder_bankmachine7_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-				builder_bankmachine7_next_state <= 3'd4;
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
-								builder_bankmachine7_next_state <= 2'd2;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+							end else begin
 							end
 						end else begin
-							builder_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8246,8 +8779,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8265,14 +8798,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+								litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -8284,8 +8817,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8293,8 +8826,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine7_twtpcon_ready) begin
+				litedramcore_bankmachine7_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -8310,18 +8843,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8335,12 +8868,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8351,15 +8884,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_open <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_open <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8377,76 +8910,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_close <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
-		end
-		2'd2: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_open <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8464,21 +8936,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_close <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-			end
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8493,12 +8962,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -8515,15 +8981,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8534,22 +8997,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8564,48 +9026,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 			end
 		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
 		2'd2: begin
 		end
 		2'd3: begin
@@ -8621,13 +9048,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8640,15 +9067,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8659,284 +9093,269 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
-assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
-assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
-assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
-assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
-assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
-assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
-assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
-assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
-assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
-assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
-assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
-assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
+assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
 always @(*) begin
-	main_litedramcore_choose_cmd_valids <= 8'd0;
-	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids <= 8'd0;
+	litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
 end
-assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
-assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
-assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
-assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
-assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
-assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
-assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
+	litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
+	litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
+	litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	litedramcore_bankmachine0_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	litedramcore_bankmachine1_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	litedramcore_bankmachine2_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	litedramcore_bankmachine3_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	litedramcore_bankmachine4_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	litedramcore_bankmachine5_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	litedramcore_bankmachine6_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	litedramcore_bankmachine7_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
 end
-assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-	main_litedramcore_choose_req_valids <= 8'd0;
-	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids <= 8'd0;
+	litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
 end
-assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
-assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
-assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
-assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
-assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
-assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
-assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
+	litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
+	litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
+	litedramcore_choose_req_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
 	end
 end
-assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
-assign main_litedramcore_dfi_p0_reset_n = 1'd1;
-assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}};
-assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}};
-assign main_litedramcore_dfi_p1_reset_n = 1'd1;
-assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}};
-assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}};
-assign main_litedramcore_dfi_p2_reset_n = 1'd1;
-assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}};
-assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}};
-assign main_litedramcore_dfi_p3_reset_n = 1'd1;
-assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
-assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
-assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
 always @(*) begin
-	builder_multiplexer_next_state <= 4'd0;
-	builder_multiplexer_next_state <= builder_multiplexer_state;
-	case (builder_multiplexer_state)
+	litedramcore_multiplexer_next_state <= 4'd0;
+	litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (main_litedramcore_read_available) begin
-				if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
-					builder_multiplexer_next_state <= 2'd3;
+			if (litedramcore_read_available) begin
+				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+					litedramcore_multiplexer_next_state <= 2'd3;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
-			if (main_litedramcore_cmd_last) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_cmd_last) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_twtrcon_ready) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_twtrcon_ready) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			builder_multiplexer_next_state <= 3'd5;
+			litedramcore_multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			builder_multiplexer_next_state <= 3'd6;
+			litedramcore_multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_multiplexer_next_state <= 3'd7;
+			litedramcore_multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			builder_multiplexer_next_state <= 4'd8;
+			litedramcore_multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_multiplexer_next_state <= 4'd9;
+			litedramcore_multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			builder_multiplexer_next_state <= 4'd10;
+			litedramcore_multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			builder_multiplexer_next_state <= 1'd1;
+			litedramcore_multiplexer_next_state <= 1'd1;
 		end
 		default: begin
-			if (main_litedramcore_write_available) begin
-				if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
-					builder_multiplexer_next_state <= 3'd4;
+			if (litedramcore_write_available) begin
+				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+					litedramcore_multiplexer_next_state <= 3'd4;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel0 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel0 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
+			if ((litedramcore_wrcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 		2'd2: begin
-			main_litedramcore_steerer_sel0 <= 2'd3;
+			litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -8955,23 +9374,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
+			if ((litedramcore_rdcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
+			litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -8994,15 +9413,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel1 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if ((litedramcore_wrcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9024,26 +9443,26 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if ((litedramcore_rdcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel2 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel2 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
+			if ((litedramcore_wrcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9065,23 +9484,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
+			if ((litedramcore_rdcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_want_activates <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			if (1'd0) begin
 			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
 			end
 		end
 		2'd2: begin
@@ -9105,21 +9524,21 @@ always @(*) begin
 		default: begin
 			if (1'd0) begin
 			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel3 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if ((litedramcore_wrcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9141,19 +9560,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if ((litedramcore_rdcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en0 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9175,17 +9594,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			litedramcore_en0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			if (1'd0) begin
 			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
 			end
 		end
 		2'd2: begin
@@ -9209,14 +9628,14 @@ always @(*) begin
 		default: begin
 			if (1'd0) begin
 			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_reads <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9238,15 +9657,15 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en1 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			litedramcore_en1 <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9271,14 +9690,10 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_writes <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9299,19 +9714,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -9332,1987 +9746,2016 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+			end
 		end
 	endcase
 end
-assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
-assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12;
-assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13;
-assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14;
-assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
-assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15;
-assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16;
-assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17;
-assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
-assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18;
-assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19;
-assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20;
-assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
-assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21;
-assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22;
-assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23;
-assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
-assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24;
-assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25;
-assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26;
-assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
-assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27;
-assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28;
-assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29;
-assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
-assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30;
-assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31;
-assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32;
-assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
-assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33;
-assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34;
-assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
-assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
-assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
-assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
+assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 16'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata <= 128'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			litedramcore_interface_wdata <= user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_interface_wdata <= 128'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata_we <= 16'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 end
-assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
-assign builder_roundrobin0_grant = 1'd0;
-assign builder_roundrobin1_grant = 1'd0;
-assign builder_roundrobin2_grant = 1'd0;
-assign builder_roundrobin3_grant = 1'd0;
-assign builder_roundrobin4_grant = 1'd0;
-assign builder_roundrobin5_grant = 1'd0;
-assign builder_roundrobin6_grant = 1'd0;
-assign builder_roundrobin7_grant = 1'd0;
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-	builder_next_state <= 2'd0;
-	builder_next_state <= builder_state;
-	case (builder_state)
+	litedramcore_next_state <= 2'd0;
+	litedramcore_next_state <= litedramcore_state;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_next_state <= 2'd2;
+			litedramcore_next_state <= 2'd2;
 		end
 		2'd2: begin
-			builder_next_state <= 1'd0;
+			litedramcore_next_state <= 1'd0;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_next_state <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_dat_r <= 32'd0;
-	case (builder_state)
+	litedramcore_adr_next_value1 <= 14'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 32'd0;
-	case (builder_state)
+	litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_dat_r <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
-	case (builder_state)
+	litedramcore_we_next_value2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value1 <= 14'd0;
-	case (builder_state)
+	litedramcore_we_next_value_ce2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value1 <= 1'd0;
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_ack <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value2 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
-			end
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value_ce2 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value_ce2 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
-assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
-assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
-assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r;
-assign builder_litedramcore_wishbone_sel = main_wb_bus_sel;
-assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc;
-assign builder_litedramcore_wishbone_stb = main_wb_bus_stb;
-assign main_wb_bus_ack = builder_litedramcore_wishbone_ack;
-assign builder_litedramcore_wishbone_we = main_wb_bus_we;
-assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
-assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
-assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
-assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_done0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_done0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_re <= interface0_bank_bus_we;
 	end
 end
-assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_error0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_error0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
-assign builder_csrbank0_init_done0_w = main_init_done_storage;
-assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
-assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rst0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rst0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+	csrbank1_dly_sel0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_dly_sel0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+	csrbank1_half_sys8x_taps0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_half_sys8x_taps0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wlevel_en0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+	csrbank1_wlevel_en0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wlevel_strobe_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wlevel_strobe_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rdphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rdphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wrphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_wrphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
-assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
-assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
+assign csrbank1_rst0_w = a7ddrphy_rst_storage;
+assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
+assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
+assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
+assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
+assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_control0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_control0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[15:0];
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[15:0];
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[15:0];
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[15:0];
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_sel = main_litedramcore_storage[0];
-assign main_litedramcore_cke = main_litedramcore_storage[1];
-assign main_litedramcore_odt = main_litedramcore_storage[2];
-assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[15:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[15:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[15:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[15:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
-assign builder_csr_interconnect_adr = builder_litedramcore_adr;
-assign builder_csr_interconnect_we = builder_litedramcore_we;
-assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
-assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r;
-assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-always @(*) begin
-	builder_rhs_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+assign litedramcore_sel = litedramcore_storage[0];
+assign litedramcore_cke = litedramcore_storage[1];
+assign litedramcore_odt = litedramcore_storage[2];
+assign litedramcore_reset_n = litedramcore_storage[3];
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
+assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
+assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
+assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
+assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
+assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[15:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
+assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
+assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
+assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
+assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
+assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
+assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
+assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[15:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
+assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
+assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
+assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
+assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
+assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
+assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
+assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
+assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[15:0];
+assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
+assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
+assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
+assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
+assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
+assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
+assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
+assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
+assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[15:0];
+assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
+assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
+assign csr_interconnect_adr = litedramcore_adr;
+assign csr_interconnect_we = litedramcore_we;
+assign csr_interconnect_dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = csr_interconnect_dat_r;
+assign interface0_bank_bus_adr = csr_interconnect_adr;
+assign interface1_bank_bus_adr = csr_interconnect_adr;
+assign interface2_bank_bus_adr = csr_interconnect_adr;
+assign interface0_bank_bus_we = csr_interconnect_we;
+assign interface1_bank_bus_we = csr_interconnect_we;
+assign interface2_bank_bus_we = csr_interconnect_we;
+assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
+assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+always @(*) begin
+	rhs_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed1 <= 16'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed1 <= 16'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed2 <= 3'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed2 <= 3'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed1 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed1 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed2 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed2 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed6 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed6 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed7 <= 16'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed7 <= 16'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed8 <= 3'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed8 <= 3'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed9 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed9 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed10 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed10 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed11 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed11 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed12 <= 23'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed12 <= 23'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed13 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed13 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed13 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed14 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed14 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed15 <= 23'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed15 <= 23'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed16 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed16 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed16 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed17 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed17 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed18 <= 23'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed18 <= 23'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed19 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed19 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed19 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed20 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed20 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed21 <= 23'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed21 <= 23'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed22 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed22 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed22 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed23 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed23 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed24 <= 23'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed24 <= 23'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed25 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed25 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed25 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed26 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed26 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed27 <= 23'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed27 <= 23'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed28 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed28 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed28 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed29 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed29 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed30 <= 23'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed30 <= 23'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed31 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed31 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed31 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed32 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed32 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed33 <= 23'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed33 <= 23'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed34 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed34 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed34 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed35 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed35 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed0 <= 3'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed0 <= 3'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed0 <= main_litedramcore_nop_ba[2:0];
+			array_muxed0 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed1 <= 16'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed1 <= 16'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed1 <= main_litedramcore_nop_a;
+			array_muxed1 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
+			array_muxed1 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed2 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed2 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed2 <= 1'd0;
+			array_muxed2 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed3 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed3 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed3 <= 1'd0;
+			array_muxed3 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed4 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed4 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed4 <= 1'd0;
+			array_muxed4 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed5 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed5 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed5 <= 1'd0;
+			array_muxed5 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed6 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed6 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed6 <= 1'd0;
+			array_muxed6 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed7 <= 3'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed7 <= 3'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed7 <= main_litedramcore_nop_ba[2:0];
+			array_muxed7 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed8 <= 16'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed8 <= 16'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed8 <= main_litedramcore_nop_a;
+			array_muxed8 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
+			array_muxed8 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed9 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed9 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed9 <= 1'd0;
+			array_muxed9 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed10 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed10 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed10 <= 1'd0;
+			array_muxed10 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed11 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed11 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed11 <= 1'd0;
+			array_muxed11 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed12 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed12 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed12 <= 1'd0;
+			array_muxed12 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed13 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed13 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed13 <= 1'd0;
+			array_muxed13 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed14 <= 3'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed14 <= 3'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed14 <= main_litedramcore_nop_ba[2:0];
+			array_muxed14 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed15 <= 16'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed15 <= 16'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed15 <= main_litedramcore_nop_a;
+			array_muxed15 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
+			array_muxed15 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed16 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed16 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed16 <= 1'd0;
+			array_muxed16 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed17 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed17 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed17 <= 1'd0;
+			array_muxed17 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed18 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed18 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed18 <= 1'd0;
+			array_muxed18 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed19 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed19 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed19 <= 1'd0;
+			array_muxed19 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed20 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed20 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed20 <= 1'd0;
+			array_muxed20 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed21 <= 3'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed21 <= 3'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed21 <= main_litedramcore_nop_ba[2:0];
+			array_muxed21 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed22 <= 16'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed22 <= 16'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed22 <= main_litedramcore_nop_a;
+			array_muxed22 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
+			array_muxed22 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed23 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed23 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed23 <= 1'd0;
+			array_muxed23 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed24 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed24 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed24 <= 1'd0;
+			array_muxed24 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed25 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed25 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed25 <= 1'd0;
+			array_muxed25 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed26 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed26 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed26 <= 1'd0;
+			array_muxed26 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed27 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed27 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed27 <= 1'd0;
+			array_muxed27 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
+assign xilinxasyncresetsynchronizerimpl0 = (~locked);
+assign xilinxasyncresetsynchronizerimpl1 = (~locked);
+assign xilinxasyncresetsynchronizerimpl2 = (~locked);
+assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 
 
 //------------------------------------------------------------------------------
@@ -11320,1044 +11763,1044 @@ assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-	if ((main_reset_counter != 1'd0)) begin
-		main_reset_counter <= (main_reset_counter - 1'd1);
+	if ((reset_counter != 1'd0)) begin
+		reset_counter <= (reset_counter - 1'd1);
 	end else begin
-		main_ic_reset <= 1'd0;
+		ic_reset <= 1'd0;
 	end
 	if (iodelay_rst) begin
-		main_reset_counter <= 4'd15;
-		main_ic_reset <= 1'd1;
+		reset_counter <= 4'd15;
+		ic_reset <= 1'd1;
 	end
 end
 
 always @(posedge sys_clk) begin
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-	main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+	a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
+	a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
+	a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
+	a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
+	a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
+	a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
+	a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
+	a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
+	a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
+	a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
+	a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
+	a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
+	a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
+	a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
+	a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
+	a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
+	a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
+	a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
+	a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
+	a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
+	a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
+	a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
+	a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
+	a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
+	a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
+	a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
+	a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
+	a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
+	a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
+	a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
+	a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
+	a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
+	a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
+	a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
+	a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
+	a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
-	main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
-	main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
-	main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
-	main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
-	main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
-	main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
-	main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
-	main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
-	main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
-	main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
-	main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
-	if (main_litedramcore_inti_p0_rddata_valid) begin
-		main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata;
+	a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+	a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+	a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+	a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+	a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+	a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+	a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+	a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+	a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+	a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+	a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+	a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+	if (litedramcore_csr_dfi_p0_rddata_valid) begin
+		litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
 	end
-	if (main_litedramcore_inti_p1_rddata_valid) begin
-		main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata;
+	if (litedramcore_csr_dfi_p1_rddata_valid) begin
+		litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
 	end
-	if (main_litedramcore_inti_p2_rddata_valid) begin
-		main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata;
+	if (litedramcore_csr_dfi_p2_rddata_valid) begin
+		litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
 	end
-	if (main_litedramcore_inti_p3_rddata_valid) begin
-		main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata;
-	end
-	if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
-		main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
+	if (litedramcore_csr_dfi_p3_rddata_valid) begin
+		litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+	end
+	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_timer_count1 <= 10'd781;
+		litedramcore_timer_count1 <= 10'd781;
 	end
-	main_litedramcore_postponer_req_o <= 1'd0;
-	if (main_litedramcore_postponer_req_i) begin
-		main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
-		if ((main_litedramcore_postponer_count == 1'd0)) begin
-			main_litedramcore_postponer_count <= 1'd0;
-			main_litedramcore_postponer_req_o <= 1'd1;
-		end
+	litedramcore_postponer_req_o <= 1'd0;
+	if (litedramcore_postponer_req_i) begin
+		litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+		if ((litedramcore_postponer_count == 1'd0)) begin
+			litedramcore_postponer_count <= 1'd0;
+			litedramcore_postponer_req_o <= 1'd1;
+		end
 	end
-	if (main_litedramcore_sequencer_start0) begin
-		main_litedramcore_sequencer_count <= 1'd0;
-	end else begin
-		if (main_litedramcore_sequencer_done1) begin
-			if ((main_litedramcore_sequencer_count != 1'd0)) begin
-				main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
-			end
-		end
-	end
-	main_litedramcore_cmd_payload_a <= 1'd0;
-	main_litedramcore_cmd_payload_ba <= 1'd0;
-	main_litedramcore_cmd_payload_cas <= 1'd0;
-	main_litedramcore_cmd_payload_ras <= 1'd0;
-	main_litedramcore_cmd_payload_we <= 1'd0;
-	main_litedramcore_sequencer_done1 <= 1'd0;
-	if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd1;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-	end
-	if ((main_litedramcore_sequencer_counter == 7'd73)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 7'd73)) begin
-		main_litedramcore_sequencer_counter <= 1'd0;
-	end else begin
-		if ((main_litedramcore_sequencer_counter != 1'd0)) begin
-			main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1);
+	if (litedramcore_sequencer_start0) begin
+		litedramcore_sequencer_count <= 1'd0;
+	end else begin
+		if (litedramcore_sequencer_done1) begin
+			if ((litedramcore_sequencer_count != 1'd0)) begin
+				litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+			end
+		end
+	end
+	litedramcore_cmd_payload_a <= 1'd0;
+	litedramcore_cmd_payload_ba <= 1'd0;
+	litedramcore_cmd_payload_cas <= 1'd0;
+	litedramcore_cmd_payload_ras <= 1'd0;
+	litedramcore_cmd_payload_we <= 1'd0;
+	litedramcore_sequencer_done1 <= 1'd0;
+	if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd1;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd0;
+	end
+	if ((litedramcore_sequencer_counter == 7'd73)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 7'd73)) begin
+		litedramcore_sequencer_counter <= 1'd0;
+	end else begin
+		if ((litedramcore_sequencer_counter != 1'd0)) begin
+			litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_sequencer_start1) begin
-				main_litedramcore_sequencer_counter <= 1'd1;
+			if (litedramcore_sequencer_start1) begin
+				litedramcore_sequencer_counter <= 1'd1;
 			end
 		end
 	end
-	if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
-		main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
+	if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+		litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
 	end
-	main_litedramcore_zqcs_executer_done <= 1'd0;
-	if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	litedramcore_zqcs_executer_done <= 1'd0;
+	if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_zqcs_executer_done <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_zqcs_executer_done <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_zqcs_executer_counter <= 1'd0;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_zqcs_executer_counter <= 1'd0;
 	end else begin
-		if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin
-			main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1);
+		if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+			litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_zqcs_executer_start) begin
-				main_litedramcore_zqcs_executer_counter <= 1'd1;
+			if (litedramcore_zqcs_executer_start) begin
+				litedramcore_zqcs_executer_counter <= 1'd1;
 			end
 		end
 	end
-	builder_refresher_state <= builder_refresher_next_state;
-	if (main_litedramcore_bankmachine0_row_close) begin
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
+	litedramcore_refresher_state <= litedramcore_refresher_next_state;
+	if (litedramcore_bankmachine0_row_close) begin
+		litedramcore_bankmachine0_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine0_row_open) begin
-			main_litedramcore_bankmachine0_row_opened <= 1'd1;
-			main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine0_row_open) begin
+			litedramcore_bankmachine0_row_opened <= 1'd1;
+			litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+		litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+		litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine0_twtpcon_valid) begin
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine0_twtpcon_valid) begin
+		litedramcore_bankmachine0_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
-			main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+			litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trccon_valid) begin
-		main_litedramcore_bankmachine0_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine0_trccon_valid) begin
+		litedramcore_bankmachine0_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+			litedramcore_bankmachine0_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+			litedramcore_bankmachine0_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
-			main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trccon_ready)) begin
+			litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trascon_valid) begin
-		main_litedramcore_bankmachine0_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine0_trascon_valid) begin
+		litedramcore_bankmachine0_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+			litedramcore_bankmachine0_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+			litedramcore_bankmachine0_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
-			main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trascon_ready)) begin
+			litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine0_state <= builder_bankmachine0_next_state;
-	if (main_litedramcore_bankmachine1_row_close) begin
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
+	litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+	if (litedramcore_bankmachine1_row_close) begin
+		litedramcore_bankmachine1_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine1_row_open) begin
-			main_litedramcore_bankmachine1_row_opened <= 1'd1;
-			main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine1_row_open) begin
+			litedramcore_bankmachine1_row_opened <= 1'd1;
+			litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+		litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+		litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine1_twtpcon_valid) begin
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine1_twtpcon_valid) begin
+		litedramcore_bankmachine1_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
-			main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+			litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trccon_valid) begin
-		main_litedramcore_bankmachine1_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine1_trccon_valid) begin
+		litedramcore_bankmachine1_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+			litedramcore_bankmachine1_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+			litedramcore_bankmachine1_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
-			main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trccon_ready)) begin
+			litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trascon_valid) begin
-		main_litedramcore_bankmachine1_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine1_trascon_valid) begin
+		litedramcore_bankmachine1_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+			litedramcore_bankmachine1_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+			litedramcore_bankmachine1_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
-			main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trascon_ready)) begin
+			litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine1_state <= builder_bankmachine1_next_state;
-	if (main_litedramcore_bankmachine2_row_close) begin
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
+	litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+	if (litedramcore_bankmachine2_row_close) begin
+		litedramcore_bankmachine2_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine2_row_open) begin
-			main_litedramcore_bankmachine2_row_opened <= 1'd1;
-			main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine2_row_open) begin
+			litedramcore_bankmachine2_row_opened <= 1'd1;
+			litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+		litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+		litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine2_twtpcon_valid) begin
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine2_twtpcon_valid) begin
+		litedramcore_bankmachine2_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
-			main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+			litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trccon_valid) begin
-		main_litedramcore_bankmachine2_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine2_trccon_valid) begin
+		litedramcore_bankmachine2_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+			litedramcore_bankmachine2_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+			litedramcore_bankmachine2_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
-			main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trccon_ready)) begin
+			litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trascon_valid) begin
-		main_litedramcore_bankmachine2_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine2_trascon_valid) begin
+		litedramcore_bankmachine2_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+			litedramcore_bankmachine2_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+			litedramcore_bankmachine2_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
-			main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trascon_ready)) begin
+			litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine2_state <= builder_bankmachine2_next_state;
-	if (main_litedramcore_bankmachine3_row_close) begin
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
+	litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+	if (litedramcore_bankmachine3_row_close) begin
+		litedramcore_bankmachine3_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine3_row_open) begin
-			main_litedramcore_bankmachine3_row_opened <= 1'd1;
-			main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine3_row_open) begin
+			litedramcore_bankmachine3_row_opened <= 1'd1;
+			litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+		litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+		litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine3_twtpcon_valid) begin
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine3_twtpcon_valid) begin
+		litedramcore_bankmachine3_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
-			main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+			litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trccon_valid) begin
-		main_litedramcore_bankmachine3_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine3_trccon_valid) begin
+		litedramcore_bankmachine3_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+			litedramcore_bankmachine3_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+			litedramcore_bankmachine3_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
-			main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trccon_ready)) begin
+			litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trascon_valid) begin
-		main_litedramcore_bankmachine3_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine3_trascon_valid) begin
+		litedramcore_bankmachine3_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+			litedramcore_bankmachine3_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+			litedramcore_bankmachine3_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
-			main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trascon_ready)) begin
+			litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine3_state <= builder_bankmachine3_next_state;
-	if (main_litedramcore_bankmachine4_row_close) begin
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
+	litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+	if (litedramcore_bankmachine4_row_close) begin
+		litedramcore_bankmachine4_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine4_row_open) begin
-			main_litedramcore_bankmachine4_row_opened <= 1'd1;
-			main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine4_row_open) begin
+			litedramcore_bankmachine4_row_opened <= 1'd1;
+			litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+		litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+		litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine4_twtpcon_valid) begin
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine4_twtpcon_valid) begin
+		litedramcore_bankmachine4_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
-			main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+			litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trccon_valid) begin
-		main_litedramcore_bankmachine4_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine4_trccon_valid) begin
+		litedramcore_bankmachine4_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+			litedramcore_bankmachine4_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+			litedramcore_bankmachine4_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
-			main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trccon_ready)) begin
+			litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trascon_valid) begin
-		main_litedramcore_bankmachine4_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine4_trascon_valid) begin
+		litedramcore_bankmachine4_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+			litedramcore_bankmachine4_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+			litedramcore_bankmachine4_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
-			main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trascon_ready)) begin
+			litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine4_state <= builder_bankmachine4_next_state;
-	if (main_litedramcore_bankmachine5_row_close) begin
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
+	litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+	if (litedramcore_bankmachine5_row_close) begin
+		litedramcore_bankmachine5_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine5_row_open) begin
-			main_litedramcore_bankmachine5_row_opened <= 1'd1;
-			main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine5_row_open) begin
+			litedramcore_bankmachine5_row_opened <= 1'd1;
+			litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+		litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+		litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine5_twtpcon_valid) begin
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine5_twtpcon_valid) begin
+		litedramcore_bankmachine5_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
-			main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+			litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trccon_valid) begin
-		main_litedramcore_bankmachine5_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine5_trccon_valid) begin
+		litedramcore_bankmachine5_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+			litedramcore_bankmachine5_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+			litedramcore_bankmachine5_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
-			main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trccon_ready)) begin
+			litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trascon_valid) begin
-		main_litedramcore_bankmachine5_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine5_trascon_valid) begin
+		litedramcore_bankmachine5_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+			litedramcore_bankmachine5_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+			litedramcore_bankmachine5_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
-			main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trascon_ready)) begin
+			litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine5_state <= builder_bankmachine5_next_state;
-	if (main_litedramcore_bankmachine6_row_close) begin
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
+	litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+	if (litedramcore_bankmachine6_row_close) begin
+		litedramcore_bankmachine6_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine6_row_open) begin
-			main_litedramcore_bankmachine6_row_opened <= 1'd1;
-			main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine6_row_open) begin
+			litedramcore_bankmachine6_row_opened <= 1'd1;
+			litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+		litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+		litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine6_twtpcon_valid) begin
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine6_twtpcon_valid) begin
+		litedramcore_bankmachine6_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
-			main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+			litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trccon_valid) begin
-		main_litedramcore_bankmachine6_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine6_trccon_valid) begin
+		litedramcore_bankmachine6_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+			litedramcore_bankmachine6_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+			litedramcore_bankmachine6_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
-			main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trccon_ready)) begin
+			litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trascon_valid) begin
-		main_litedramcore_bankmachine6_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine6_trascon_valid) begin
+		litedramcore_bankmachine6_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+			litedramcore_bankmachine6_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+			litedramcore_bankmachine6_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
-			main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trascon_ready)) begin
+			litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine6_state <= builder_bankmachine6_next_state;
-	if (main_litedramcore_bankmachine7_row_close) begin
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
+	litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+	if (litedramcore_bankmachine7_row_close) begin
+		litedramcore_bankmachine7_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine7_row_open) begin
-			main_litedramcore_bankmachine7_row_opened <= 1'd1;
-			main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7];
+		if (litedramcore_bankmachine7_row_open) begin
+			litedramcore_bankmachine7_row_opened <= 1'd1;
+			litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+		litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+		litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine7_twtpcon_valid) begin
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine7_twtpcon_valid) begin
+		litedramcore_bankmachine7_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
-			main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+			litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trccon_valid) begin
-		main_litedramcore_bankmachine7_trccon_count <= 3'd6;
+	if (litedramcore_bankmachine7_trccon_valid) begin
+		litedramcore_bankmachine7_trccon_count <= 3'd6;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+			litedramcore_bankmachine7_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+			litedramcore_bankmachine7_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
-			main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trccon_ready)) begin
+			litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trascon_valid) begin
-		main_litedramcore_bankmachine7_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine7_trascon_valid) begin
+		litedramcore_bankmachine7_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+			litedramcore_bankmachine7_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+			litedramcore_bankmachine7_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
-			main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trascon_ready)) begin
+			litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine7_state <= builder_bankmachine7_next_state;
-	if ((~main_litedramcore_en0)) begin
-		main_litedramcore_time0 <= 5'd31;
+	litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+	if ((~litedramcore_en0)) begin
+		litedramcore_time0 <= 5'd31;
 	end else begin
-		if ((~main_litedramcore_max_time0)) begin
-			main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
+		if ((~litedramcore_max_time0)) begin
+			litedramcore_time0 <= (litedramcore_time0 - 1'd1);
 		end
 	end
-	if ((~main_litedramcore_en1)) begin
-		main_litedramcore_time1 <= 4'd15;
+	if ((~litedramcore_en1)) begin
+		litedramcore_time1 <= 4'd15;
 	end else begin
-		if ((~main_litedramcore_max_time1)) begin
-			main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
+		if ((~litedramcore_max_time1)) begin
+			litedramcore_time1 <= (litedramcore_time1 - 1'd1);
 		end
 	end
-	if (main_litedramcore_choose_cmd_ce) begin
-		case (main_litedramcore_choose_cmd_grant)
+	if (litedramcore_choose_cmd_ce) begin
+		case (litedramcore_choose_cmd_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_cmd_request[1]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd1;
+				if (litedramcore_choose_cmd_request[1]) begin
+					litedramcore_choose_cmd_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[2]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd2;
+					if (litedramcore_choose_cmd_request[2]) begin
+						litedramcore_choose_cmd_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[3]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd3;
+						if (litedramcore_choose_cmd_request[3]) begin
+							litedramcore_choose_cmd_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[4]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd4;
+							if (litedramcore_choose_cmd_request[4]) begin
+								litedramcore_choose_cmd_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[5]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd5;
+								if (litedramcore_choose_cmd_request[5]) begin
+									litedramcore_choose_cmd_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[6]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd6;
+									if (litedramcore_choose_cmd_request[6]) begin
+										litedramcore_choose_cmd_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[7]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd7;
+										if (litedramcore_choose_cmd_request[7]) begin
+											litedramcore_choose_cmd_grant <= 3'd7;
 										end
 									end
 								end
@@ -12367,26 +12810,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_cmd_request[2]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd2;
+				if (litedramcore_choose_cmd_request[2]) begin
+					litedramcore_choose_cmd_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[3]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd3;
+					if (litedramcore_choose_cmd_request[3]) begin
+						litedramcore_choose_cmd_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[4]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd4;
+						if (litedramcore_choose_cmd_request[4]) begin
+							litedramcore_choose_cmd_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[5]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd5;
+							if (litedramcore_choose_cmd_request[5]) begin
+								litedramcore_choose_cmd_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[6]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd6;
+								if (litedramcore_choose_cmd_request[6]) begin
+									litedramcore_choose_cmd_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[7]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd7;
+									if (litedramcore_choose_cmd_request[7]) begin
+										litedramcore_choose_cmd_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[0]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd0;
+										if (litedramcore_choose_cmd_request[0]) begin
+											litedramcore_choose_cmd_grant <= 1'd0;
 										end
 									end
 								end
@@ -12396,26 +12839,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_cmd_request[3]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd3;
+				if (litedramcore_choose_cmd_request[3]) begin
+					litedramcore_choose_cmd_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[4]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd4;
+					if (litedramcore_choose_cmd_request[4]) begin
+						litedramcore_choose_cmd_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[5]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd5;
+						if (litedramcore_choose_cmd_request[5]) begin
+							litedramcore_choose_cmd_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[6]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd6;
+							if (litedramcore_choose_cmd_request[6]) begin
+								litedramcore_choose_cmd_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[7]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd7;
+								if (litedramcore_choose_cmd_request[7]) begin
+									litedramcore_choose_cmd_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[0]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd0;
+									if (litedramcore_choose_cmd_request[0]) begin
+										litedramcore_choose_cmd_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[1]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd1;
+										if (litedramcore_choose_cmd_request[1]) begin
+											litedramcore_choose_cmd_grant <= 1'd1;
 										end
 									end
 								end
@@ -12425,26 +12868,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_cmd_request[4]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd4;
+				if (litedramcore_choose_cmd_request[4]) begin
+					litedramcore_choose_cmd_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[5]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd5;
+					if (litedramcore_choose_cmd_request[5]) begin
+						litedramcore_choose_cmd_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[6]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd6;
+						if (litedramcore_choose_cmd_request[6]) begin
+							litedramcore_choose_cmd_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[7]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd7;
+							if (litedramcore_choose_cmd_request[7]) begin
+								litedramcore_choose_cmd_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[0]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd0;
+								if (litedramcore_choose_cmd_request[0]) begin
+									litedramcore_choose_cmd_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[1]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd1;
+									if (litedramcore_choose_cmd_request[1]) begin
+										litedramcore_choose_cmd_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[2]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd2;
+										if (litedramcore_choose_cmd_request[2]) begin
+											litedramcore_choose_cmd_grant <= 2'd2;
 										end
 									end
 								end
@@ -12454,26 +12897,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_cmd_request[5]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd5;
+				if (litedramcore_choose_cmd_request[5]) begin
+					litedramcore_choose_cmd_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[6]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd6;
+					if (litedramcore_choose_cmd_request[6]) begin
+						litedramcore_choose_cmd_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[7]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd7;
+						if (litedramcore_choose_cmd_request[7]) begin
+							litedramcore_choose_cmd_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[0]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd0;
+							if (litedramcore_choose_cmd_request[0]) begin
+								litedramcore_choose_cmd_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[1]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd1;
+								if (litedramcore_choose_cmd_request[1]) begin
+									litedramcore_choose_cmd_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[2]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd2;
+									if (litedramcore_choose_cmd_request[2]) begin
+										litedramcore_choose_cmd_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[3]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd3;
+										if (litedramcore_choose_cmd_request[3]) begin
+											litedramcore_choose_cmd_grant <= 2'd3;
 										end
 									end
 								end
@@ -12483,26 +12926,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_cmd_request[6]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd6;
+				if (litedramcore_choose_cmd_request[6]) begin
+					litedramcore_choose_cmd_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[7]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd7;
+					if (litedramcore_choose_cmd_request[7]) begin
+						litedramcore_choose_cmd_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[0]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd0;
+						if (litedramcore_choose_cmd_request[0]) begin
+							litedramcore_choose_cmd_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[1]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd1;
+							if (litedramcore_choose_cmd_request[1]) begin
+								litedramcore_choose_cmd_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[2]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd2;
+								if (litedramcore_choose_cmd_request[2]) begin
+									litedramcore_choose_cmd_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[3]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd3;
+									if (litedramcore_choose_cmd_request[3]) begin
+										litedramcore_choose_cmd_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[4]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd4;
+										if (litedramcore_choose_cmd_request[4]) begin
+											litedramcore_choose_cmd_grant <= 3'd4;
 										end
 									end
 								end
@@ -12512,26 +12955,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_cmd_request[7]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd7;
+				if (litedramcore_choose_cmd_request[7]) begin
+					litedramcore_choose_cmd_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[0]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd0;
+					if (litedramcore_choose_cmd_request[0]) begin
+						litedramcore_choose_cmd_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[1]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd1;
+						if (litedramcore_choose_cmd_request[1]) begin
+							litedramcore_choose_cmd_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[2]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd2;
+							if (litedramcore_choose_cmd_request[2]) begin
+								litedramcore_choose_cmd_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[3]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd3;
+								if (litedramcore_choose_cmd_request[3]) begin
+									litedramcore_choose_cmd_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[4]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd4;
+									if (litedramcore_choose_cmd_request[4]) begin
+										litedramcore_choose_cmd_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[5]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd5;
+										if (litedramcore_choose_cmd_request[5]) begin
+											litedramcore_choose_cmd_grant <= 3'd5;
 										end
 									end
 								end
@@ -12541,26 +12984,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_cmd_request[0]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd0;
+				if (litedramcore_choose_cmd_request[0]) begin
+					litedramcore_choose_cmd_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[1]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd1;
+					if (litedramcore_choose_cmd_request[1]) begin
+						litedramcore_choose_cmd_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[2]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd2;
+						if (litedramcore_choose_cmd_request[2]) begin
+							litedramcore_choose_cmd_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[3]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd3;
+							if (litedramcore_choose_cmd_request[3]) begin
+								litedramcore_choose_cmd_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[4]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd4;
+								if (litedramcore_choose_cmd_request[4]) begin
+									litedramcore_choose_cmd_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[5]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd5;
+									if (litedramcore_choose_cmd_request[5]) begin
+										litedramcore_choose_cmd_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[6]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd6;
+										if (litedramcore_choose_cmd_request[6]) begin
+											litedramcore_choose_cmd_grant <= 3'd6;
 										end
 									end
 								end
@@ -12571,29 +13014,29 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	if (main_litedramcore_choose_req_ce) begin
-		case (main_litedramcore_choose_req_grant)
+	if (litedramcore_choose_req_ce) begin
+		case (litedramcore_choose_req_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_req_request[1]) begin
-					main_litedramcore_choose_req_grant <= 1'd1;
+				if (litedramcore_choose_req_request[1]) begin
+					litedramcore_choose_req_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_req_request[2]) begin
-						main_litedramcore_choose_req_grant <= 2'd2;
+					if (litedramcore_choose_req_request[2]) begin
+						litedramcore_choose_req_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_req_request[3]) begin
-							main_litedramcore_choose_req_grant <= 2'd3;
+						if (litedramcore_choose_req_request[3]) begin
+							litedramcore_choose_req_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_req_request[4]) begin
-								main_litedramcore_choose_req_grant <= 3'd4;
+							if (litedramcore_choose_req_request[4]) begin
+								litedramcore_choose_req_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_req_request[5]) begin
-									main_litedramcore_choose_req_grant <= 3'd5;
+								if (litedramcore_choose_req_request[5]) begin
+									litedramcore_choose_req_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_req_request[6]) begin
-										main_litedramcore_choose_req_grant <= 3'd6;
+									if (litedramcore_choose_req_request[6]) begin
+										litedramcore_choose_req_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_req_request[7]) begin
-											main_litedramcore_choose_req_grant <= 3'd7;
+										if (litedramcore_choose_req_request[7]) begin
+											litedramcore_choose_req_grant <= 3'd7;
 										end
 									end
 								end
@@ -12603,26 +13046,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_req_request[2]) begin
-					main_litedramcore_choose_req_grant <= 2'd2;
+				if (litedramcore_choose_req_request[2]) begin
+					litedramcore_choose_req_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_req_request[3]) begin
-						main_litedramcore_choose_req_grant <= 2'd3;
+					if (litedramcore_choose_req_request[3]) begin
+						litedramcore_choose_req_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_req_request[4]) begin
-							main_litedramcore_choose_req_grant <= 3'd4;
+						if (litedramcore_choose_req_request[4]) begin
+							litedramcore_choose_req_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_req_request[5]) begin
-								main_litedramcore_choose_req_grant <= 3'd5;
+							if (litedramcore_choose_req_request[5]) begin
+								litedramcore_choose_req_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_req_request[6]) begin
-									main_litedramcore_choose_req_grant <= 3'd6;
+								if (litedramcore_choose_req_request[6]) begin
+									litedramcore_choose_req_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_req_request[7]) begin
-										main_litedramcore_choose_req_grant <= 3'd7;
+									if (litedramcore_choose_req_request[7]) begin
+										litedramcore_choose_req_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_req_request[0]) begin
-											main_litedramcore_choose_req_grant <= 1'd0;
+										if (litedramcore_choose_req_request[0]) begin
+											litedramcore_choose_req_grant <= 1'd0;
 										end
 									end
 								end
@@ -12632,26 +13075,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_req_request[3]) begin
-					main_litedramcore_choose_req_grant <= 2'd3;
+				if (litedramcore_choose_req_request[3]) begin
+					litedramcore_choose_req_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_req_request[4]) begin
-						main_litedramcore_choose_req_grant <= 3'd4;
+					if (litedramcore_choose_req_request[4]) begin
+						litedramcore_choose_req_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_req_request[5]) begin
-							main_litedramcore_choose_req_grant <= 3'd5;
+						if (litedramcore_choose_req_request[5]) begin
+							litedramcore_choose_req_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_req_request[6]) begin
-								main_litedramcore_choose_req_grant <= 3'd6;
+							if (litedramcore_choose_req_request[6]) begin
+								litedramcore_choose_req_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_req_request[7]) begin
-									main_litedramcore_choose_req_grant <= 3'd7;
+								if (litedramcore_choose_req_request[7]) begin
+									litedramcore_choose_req_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_req_request[0]) begin
-										main_litedramcore_choose_req_grant <= 1'd0;
+									if (litedramcore_choose_req_request[0]) begin
+										litedramcore_choose_req_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_req_request[1]) begin
-											main_litedramcore_choose_req_grant <= 1'd1;
+										if (litedramcore_choose_req_request[1]) begin
+											litedramcore_choose_req_grant <= 1'd1;
 										end
 									end
 								end
@@ -12661,26 +13104,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_req_request[4]) begin
-					main_litedramcore_choose_req_grant <= 3'd4;
+				if (litedramcore_choose_req_request[4]) begin
+					litedramcore_choose_req_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_req_request[5]) begin
-						main_litedramcore_choose_req_grant <= 3'd5;
+					if (litedramcore_choose_req_request[5]) begin
+						litedramcore_choose_req_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_req_request[6]) begin
-							main_litedramcore_choose_req_grant <= 3'd6;
+						if (litedramcore_choose_req_request[6]) begin
+							litedramcore_choose_req_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_req_request[7]) begin
-								main_litedramcore_choose_req_grant <= 3'd7;
+							if (litedramcore_choose_req_request[7]) begin
+								litedramcore_choose_req_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_req_request[0]) begin
-									main_litedramcore_choose_req_grant <= 1'd0;
+								if (litedramcore_choose_req_request[0]) begin
+									litedramcore_choose_req_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_req_request[1]) begin
-										main_litedramcore_choose_req_grant <= 1'd1;
+									if (litedramcore_choose_req_request[1]) begin
+										litedramcore_choose_req_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_req_request[2]) begin
-											main_litedramcore_choose_req_grant <= 2'd2;
+										if (litedramcore_choose_req_request[2]) begin
+											litedramcore_choose_req_grant <= 2'd2;
 										end
 									end
 								end
@@ -12690,26 +13133,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_req_request[5]) begin
-					main_litedramcore_choose_req_grant <= 3'd5;
+				if (litedramcore_choose_req_request[5]) begin
+					litedramcore_choose_req_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_req_request[6]) begin
-						main_litedramcore_choose_req_grant <= 3'd6;
+					if (litedramcore_choose_req_request[6]) begin
+						litedramcore_choose_req_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_req_request[7]) begin
-							main_litedramcore_choose_req_grant <= 3'd7;
+						if (litedramcore_choose_req_request[7]) begin
+							litedramcore_choose_req_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_req_request[0]) begin
-								main_litedramcore_choose_req_grant <= 1'd0;
+							if (litedramcore_choose_req_request[0]) begin
+								litedramcore_choose_req_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_req_request[1]) begin
-									main_litedramcore_choose_req_grant <= 1'd1;
+								if (litedramcore_choose_req_request[1]) begin
+									litedramcore_choose_req_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_req_request[2]) begin
-										main_litedramcore_choose_req_grant <= 2'd2;
+									if (litedramcore_choose_req_request[2]) begin
+										litedramcore_choose_req_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_req_request[3]) begin
-											main_litedramcore_choose_req_grant <= 2'd3;
+										if (litedramcore_choose_req_request[3]) begin
+											litedramcore_choose_req_grant <= 2'd3;
 										end
 									end
 								end
@@ -12719,26 +13162,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_req_request[6]) begin
-					main_litedramcore_choose_req_grant <= 3'd6;
+				if (litedramcore_choose_req_request[6]) begin
+					litedramcore_choose_req_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_req_request[7]) begin
-						main_litedramcore_choose_req_grant <= 3'd7;
+					if (litedramcore_choose_req_request[7]) begin
+						litedramcore_choose_req_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_req_request[0]) begin
-							main_litedramcore_choose_req_grant <= 1'd0;
+						if (litedramcore_choose_req_request[0]) begin
+							litedramcore_choose_req_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_req_request[1]) begin
-								main_litedramcore_choose_req_grant <= 1'd1;
+							if (litedramcore_choose_req_request[1]) begin
+								litedramcore_choose_req_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_req_request[2]) begin
-									main_litedramcore_choose_req_grant <= 2'd2;
+								if (litedramcore_choose_req_request[2]) begin
+									litedramcore_choose_req_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_req_request[3]) begin
-										main_litedramcore_choose_req_grant <= 2'd3;
+									if (litedramcore_choose_req_request[3]) begin
+										litedramcore_choose_req_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_req_request[4]) begin
-											main_litedramcore_choose_req_grant <= 3'd4;
+										if (litedramcore_choose_req_request[4]) begin
+											litedramcore_choose_req_grant <= 3'd4;
 										end
 									end
 								end
@@ -12748,26 +13191,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_req_request[7]) begin
-					main_litedramcore_choose_req_grant <= 3'd7;
+				if (litedramcore_choose_req_request[7]) begin
+					litedramcore_choose_req_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_req_request[0]) begin
-						main_litedramcore_choose_req_grant <= 1'd0;
+					if (litedramcore_choose_req_request[0]) begin
+						litedramcore_choose_req_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_req_request[1]) begin
-							main_litedramcore_choose_req_grant <= 1'd1;
+						if (litedramcore_choose_req_request[1]) begin
+							litedramcore_choose_req_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_req_request[2]) begin
-								main_litedramcore_choose_req_grant <= 2'd2;
+							if (litedramcore_choose_req_request[2]) begin
+								litedramcore_choose_req_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_req_request[3]) begin
-									main_litedramcore_choose_req_grant <= 2'd3;
+								if (litedramcore_choose_req_request[3]) begin
+									litedramcore_choose_req_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_req_request[4]) begin
-										main_litedramcore_choose_req_grant <= 3'd4;
+									if (litedramcore_choose_req_request[4]) begin
+										litedramcore_choose_req_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_req_request[5]) begin
-											main_litedramcore_choose_req_grant <= 3'd5;
+										if (litedramcore_choose_req_request[5]) begin
+											litedramcore_choose_req_grant <= 3'd5;
 										end
 									end
 								end
@@ -12777,26 +13220,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_req_request[0]) begin
-					main_litedramcore_choose_req_grant <= 1'd0;
+				if (litedramcore_choose_req_request[0]) begin
+					litedramcore_choose_req_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_req_request[1]) begin
-						main_litedramcore_choose_req_grant <= 1'd1;
+					if (litedramcore_choose_req_request[1]) begin
+						litedramcore_choose_req_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_req_request[2]) begin
-							main_litedramcore_choose_req_grant <= 2'd2;
+						if (litedramcore_choose_req_request[2]) begin
+							litedramcore_choose_req_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_req_request[3]) begin
-								main_litedramcore_choose_req_grant <= 2'd3;
+							if (litedramcore_choose_req_request[3]) begin
+								litedramcore_choose_req_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_req_request[4]) begin
-									main_litedramcore_choose_req_grant <= 3'd4;
+								if (litedramcore_choose_req_request[4]) begin
+									litedramcore_choose_req_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_req_request[5]) begin
-										main_litedramcore_choose_req_grant <= 3'd5;
+									if (litedramcore_choose_req_request[5]) begin
+										litedramcore_choose_req_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_req_request[6]) begin
-											main_litedramcore_choose_req_grant <= 3'd6;
+										if (litedramcore_choose_req_request[6]) begin
+											litedramcore_choose_req_grant <= 3'd6;
 										end
 									end
 								end
@@ -12807,644 +13250,644 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	main_litedramcore_dfi_p0_cs_n <= 1'd0;
-	main_litedramcore_dfi_p0_bank <= builder_array_muxed0;
-	main_litedramcore_dfi_p0_address <= builder_array_muxed1;
-	main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2);
-	main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3);
-	main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4);
-	main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5;
-	main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6;
-	main_litedramcore_dfi_p1_cs_n <= 1'd0;
-	main_litedramcore_dfi_p1_bank <= builder_array_muxed7;
-	main_litedramcore_dfi_p1_address <= builder_array_muxed8;
-	main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9);
-	main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10);
-	main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11);
-	main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12;
-	main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13;
-	main_litedramcore_dfi_p2_cs_n <= 1'd0;
-	main_litedramcore_dfi_p2_bank <= builder_array_muxed14;
-	main_litedramcore_dfi_p2_address <= builder_array_muxed15;
-	main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16);
-	main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17);
-	main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18);
-	main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19;
-	main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20;
-	main_litedramcore_dfi_p3_cs_n <= 1'd0;
-	main_litedramcore_dfi_p3_bank <= builder_array_muxed21;
-	main_litedramcore_dfi_p3_address <= builder_array_muxed22;
-	main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23);
-	main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24);
-	main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25);
-	main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26;
-	main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27;
-	if (main_litedramcore_trrdcon_valid) begin
-		main_litedramcore_trrdcon_count <= 1'd1;
+	litedramcore_dfi_p0_cs_n <= 1'd0;
+	litedramcore_dfi_p0_bank <= array_muxed0;
+	litedramcore_dfi_p0_address <= array_muxed1;
+	litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+	litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+	litedramcore_dfi_p0_we_n <= (~array_muxed4);
+	litedramcore_dfi_p0_rddata_en <= array_muxed5;
+	litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+	litedramcore_dfi_p1_cs_n <= 1'd0;
+	litedramcore_dfi_p1_bank <= array_muxed7;
+	litedramcore_dfi_p1_address <= array_muxed8;
+	litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+	litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+	litedramcore_dfi_p1_we_n <= (~array_muxed11);
+	litedramcore_dfi_p1_rddata_en <= array_muxed12;
+	litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+	litedramcore_dfi_p2_cs_n <= 1'd0;
+	litedramcore_dfi_p2_bank <= array_muxed14;
+	litedramcore_dfi_p2_address <= array_muxed15;
+	litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+	litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+	litedramcore_dfi_p2_we_n <= (~array_muxed18);
+	litedramcore_dfi_p2_rddata_en <= array_muxed19;
+	litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+	litedramcore_dfi_p3_cs_n <= 1'd0;
+	litedramcore_dfi_p3_bank <= array_muxed21;
+	litedramcore_dfi_p3_address <= array_muxed22;
+	litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+	litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+	litedramcore_dfi_p3_we_n <= (~array_muxed25);
+	litedramcore_dfi_p3_rddata_en <= array_muxed26;
+	litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+	if (litedramcore_trrdcon_valid) begin
+		litedramcore_trrdcon_count <= 1'd1;
 		if (1'd0) begin
-			main_litedramcore_trrdcon_ready <= 1'd1;
+			litedramcore_trrdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_trrdcon_ready <= 1'd0;
+			litedramcore_trrdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_trrdcon_ready)) begin
-			main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
-			if ((main_litedramcore_trrdcon_count == 1'd1)) begin
-				main_litedramcore_trrdcon_ready <= 1'd1;
+		if ((~litedramcore_trrdcon_ready)) begin
+			litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+			if ((litedramcore_trrdcon_count == 1'd1)) begin
+				litedramcore_trrdcon_ready <= 1'd1;
 			end
 		end
 	end
-	main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
-	if ((main_litedramcore_tfawcon_count < 3'd4)) begin
-		if ((main_litedramcore_tfawcon_count == 2'd3)) begin
-			main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
+	litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+	if ((litedramcore_tfawcon_count < 3'd4)) begin
+		if ((litedramcore_tfawcon_count == 2'd3)) begin
+			litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
 		end else begin
-			main_litedramcore_tfawcon_ready <= 1'd1;
+			litedramcore_tfawcon_ready <= 1'd1;
 		end
 	end
-	if (main_litedramcore_tccdcon_valid) begin
-		main_litedramcore_tccdcon_count <= 1'd0;
+	if (litedramcore_tccdcon_valid) begin
+		litedramcore_tccdcon_count <= 1'd0;
 		if (1'd1) begin
-			main_litedramcore_tccdcon_ready <= 1'd1;
+			litedramcore_tccdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_tccdcon_ready <= 1'd0;
+			litedramcore_tccdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_tccdcon_ready)) begin
-			main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
-			if ((main_litedramcore_tccdcon_count == 1'd1)) begin
-				main_litedramcore_tccdcon_ready <= 1'd1;
+		if ((~litedramcore_tccdcon_ready)) begin
+			litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+			if ((litedramcore_tccdcon_count == 1'd1)) begin
+				litedramcore_tccdcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_twtrcon_valid) begin
-		main_litedramcore_twtrcon_count <= 3'd4;
+	if (litedramcore_twtrcon_valid) begin
+		litedramcore_twtrcon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_twtrcon_ready <= 1'd1;
+			litedramcore_twtrcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_twtrcon_ready <= 1'd0;
+			litedramcore_twtrcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_twtrcon_ready)) begin
-			main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
-			if ((main_litedramcore_twtrcon_count == 1'd1)) begin
-				main_litedramcore_twtrcon_ready <= 1'd1;
+		if ((~litedramcore_twtrcon_ready)) begin
+			litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+			if ((litedramcore_twtrcon_count == 1'd1)) begin
+				litedramcore_twtrcon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_multiplexer_state <= builder_multiplexer_next_state;
-	builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
-	builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
-	builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
-	builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
-	builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
-	builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
-	builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
-	builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
-	builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
-	builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
-	builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
-	builder_state <= builder_next_state;
-	if (builder_litedramcore_dat_w_next_value_ce0) begin
-		builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0;
+	litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+	litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+	litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+	litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+	litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+	litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+	litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+	litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+	litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+	litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+	litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+	litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+	litedramcore_state <= litedramcore_next_state;
+	if (litedramcore_dat_w_next_value_ce0) begin
+		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
 	end
-	if (builder_litedramcore_adr_next_value_ce1) begin
-		builder_litedramcore_adr <= builder_litedramcore_adr_next_value1;
+	if (litedramcore_adr_next_value_ce1) begin
+		litedramcore_adr <= litedramcore_adr_next_value1;
 	end
-	if (builder_litedramcore_we_next_value_ce2) begin
-		builder_litedramcore_we <= builder_litedramcore_we_next_value2;
+	if (litedramcore_we_next_value_ce2) begin
+		litedramcore_we <= litedramcore_we_next_value2;
 	end
-	builder_interface0_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank0_sel) begin
-		case (builder_interface0_bank_bus_adr[8:0])
+	interface0_bank_bus_dat_r <= 1'd0;
+	if (csrbank0_sel) begin
+		case (interface0_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
 			end
 			1'd1: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank0_init_done0_re) begin
-		main_init_done_storage <= builder_csrbank0_init_done0_r;
+	if (csrbank0_init_done0_re) begin
+		init_done_storage <= csrbank0_init_done0_r;
 	end
-	main_init_done_re <= builder_csrbank0_init_done0_re;
-	if (builder_csrbank0_init_error0_re) begin
-		main_init_error_storage <= builder_csrbank0_init_error0_r;
+	init_done_re <= csrbank0_init_done0_re;
+	if (csrbank0_init_error0_re) begin
+		init_error_storage <= csrbank0_init_error0_r;
 	end
-	main_init_error_re <= builder_csrbank0_init_error0_re;
-	builder_interface1_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank1_sel) begin
-		case (builder_interface1_bank_bus_adr[8:0])
+	init_error_re <= csrbank0_init_error0_re;
+	interface1_bank_bus_dat_r <= 1'd0;
+	if (csrbank1_sel) begin
+		case (interface1_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rst0_w;
 			end
 			1'd1: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
 			end
 			2'd2: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
+				interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
 			end
 			2'd3: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
+				interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
 			end
 			3'd4: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
 			end
 			3'd5: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
 			end
 			3'd6: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
 			end
 			3'd7: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
 			end
 			4'd8: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
 			end
 			4'd9: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
 			end
 			4'd10: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
 			end
 			4'd11: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
 			end
 			4'd12: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank1_rst0_re) begin
-		main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
+	if (csrbank1_rst0_re) begin
+		a7ddrphy_rst_storage <= csrbank1_rst0_r;
 	end
-	main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
-	if (builder_csrbank1_half_sys8x_taps0_re) begin
-		main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+	a7ddrphy_rst_re <= csrbank1_rst0_re;
+	if (csrbank1_dly_sel0_re) begin
+		a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
 	end
-	main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
-	if (builder_csrbank1_wlevel_en0_re) begin
-		main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
+	a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+	if (csrbank1_half_sys8x_taps0_re) begin
+		a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
 	end
-	main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
-	if (builder_csrbank1_dly_sel0_re) begin
-		main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+	a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+	if (csrbank1_wlevel_en0_re) begin
+		a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
 	end
-	main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
-	if (builder_csrbank1_rdphase0_re) begin
-		main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+	a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+	if (csrbank1_rdphase0_re) begin
+		a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
 	end
-	main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
-	if (builder_csrbank1_wrphase0_re) begin
-		main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+	a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+	if (csrbank1_wrphase0_re) begin
+		a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
 	end
-	main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
-	builder_interface2_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank2_sel) begin
-		case (builder_interface2_bank_bus_adr[8:0])
+	a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+	interface2_bank_bus_dat_r <= 1'd0;
+	if (csrbank2_sel) begin
+		case (interface2_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
 			end
 			1'd1: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
 			end
 			2'd2: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
 			end
 			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
 			end
 			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
 			end
 			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
 			end
 			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
 			end
 			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
-	if (builder_csrbank2_dfii_control0_re) begin
-		main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+	if (csrbank2_dfii_control0_re) begin
+		litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
 	end
-	main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
-	if (builder_csrbank2_dfii_pi0_command0_re) begin
-		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
+	litedramcore_re <= csrbank2_dfii_control0_re;
+	if (csrbank2_dfii_pi0_command0_re) begin
+		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
 	end
-	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[15:0] <= builder_csrbank2_dfii_pi0_address0_r;
+	litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+	if (csrbank2_dfii_pi0_address0_re) begin
+		litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r;
 	end
-	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
-	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+	litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+	if (csrbank2_dfii_pi0_baddress0_re) begin
+		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
 	end
-	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+	litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+	if (csrbank2_dfii_pi0_wrdata0_re) begin
+		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
-	if (builder_csrbank2_dfii_pi1_command0_re) begin
-		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
+	litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+	litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+	if (csrbank2_dfii_pi1_command0_re) begin
+		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
 	end
-	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[15:0] <= builder_csrbank2_dfii_pi1_address0_r;
+	litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+	if (csrbank2_dfii_pi1_address0_re) begin
+		litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r;
 	end
-	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
-	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+	litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+	if (csrbank2_dfii_pi1_baddress0_re) begin
+		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
 	end
-	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+	litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+	if (csrbank2_dfii_pi1_wrdata0_re) begin
+		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
-	if (builder_csrbank2_dfii_pi2_command0_re) begin
-		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
+	litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+	litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+	if (csrbank2_dfii_pi2_command0_re) begin
+		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
 	end
-	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[15:0] <= builder_csrbank2_dfii_pi2_address0_r;
+	litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+	if (csrbank2_dfii_pi2_address0_re) begin
+		litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r;
 	end
-	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
-	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+	litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+	if (csrbank2_dfii_pi2_baddress0_re) begin
+		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
 	end
-	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+	litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+	if (csrbank2_dfii_pi2_wrdata0_re) begin
+		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
-	if (builder_csrbank2_dfii_pi3_command0_re) begin
-		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
+	litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+	litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+	if (csrbank2_dfii_pi3_command0_re) begin
+		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
 	end
-	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[15:0] <= builder_csrbank2_dfii_pi3_address0_r;
+	litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+	if (csrbank2_dfii_pi3_address0_re) begin
+		litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r;
 	end
-	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
-	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+	litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+	if (csrbank2_dfii_pi3_baddress0_re) begin
+		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
 	end
-	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+	litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+	if (csrbank2_dfii_pi3_wrdata0_re) begin
+		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
+	litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+	litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
-		main_a7ddrphy_rst_storage <= 1'd0;
-		main_a7ddrphy_rst_re <= 1'd0;
-		main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-		main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
-		main_a7ddrphy_wlevel_en_storage <= 1'd0;
-		main_a7ddrphy_wlevel_en_re <= 1'd0;
-		main_a7ddrphy_dly_sel_storage <= 2'd0;
-		main_a7ddrphy_dly_sel_re <= 1'd0;
-		main_a7ddrphy_rdphase_storage <= 2'd2;
-		main_a7ddrphy_rdphase_re <= 1'd0;
-		main_a7ddrphy_wrphase_storage <= 2'd3;
-		main_a7ddrphy_wrphase_re <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_dqspattern_o1 <= 8'd0;
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
-		main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-		main_litedramcore_storage <= 4'd1;
-		main_litedramcore_re <= 1'd0;
-		main_litedramcore_phaseinjector0_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector0_command_re <= 1'd0;
-		main_litedramcore_phaseinjector0_address_re <= 1'd0;
-		main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector1_command_re <= 1'd0;
-		main_litedramcore_phaseinjector1_address_re <= 1'd0;
-		main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector2_command_re <= 1'd0;
-		main_litedramcore_phaseinjector2_address_re <= 1'd0;
-		main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector3_command_re <= 1'd0;
-		main_litedramcore_phaseinjector3_address_re <= 1'd0;
-		main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
-		main_litedramcore_dfi_p0_address <= 16'd0;
-		main_litedramcore_dfi_p0_bank <= 3'd0;
-		main_litedramcore_dfi_p0_cas_n <= 1'd1;
-		main_litedramcore_dfi_p0_cs_n <= 1'd1;
-		main_litedramcore_dfi_p0_ras_n <= 1'd1;
-		main_litedramcore_dfi_p0_we_n <= 1'd1;
-		main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p0_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p1_address <= 16'd0;
-		main_litedramcore_dfi_p1_bank <= 3'd0;
-		main_litedramcore_dfi_p1_cas_n <= 1'd1;
-		main_litedramcore_dfi_p1_cs_n <= 1'd1;
-		main_litedramcore_dfi_p1_ras_n <= 1'd1;
-		main_litedramcore_dfi_p1_we_n <= 1'd1;
-		main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p1_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p2_address <= 16'd0;
-		main_litedramcore_dfi_p2_bank <= 3'd0;
-		main_litedramcore_dfi_p2_cas_n <= 1'd1;
-		main_litedramcore_dfi_p2_cs_n <= 1'd1;
-		main_litedramcore_dfi_p2_ras_n <= 1'd1;
-		main_litedramcore_dfi_p2_we_n <= 1'd1;
-		main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p2_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p3_address <= 16'd0;
-		main_litedramcore_dfi_p3_bank <= 3'd0;
-		main_litedramcore_dfi_p3_cas_n <= 1'd1;
-		main_litedramcore_dfi_p3_cs_n <= 1'd1;
-		main_litedramcore_dfi_p3_ras_n <= 1'd1;
-		main_litedramcore_dfi_p3_we_n <= 1'd1;
-		main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p3_rddata_en <= 1'd0;
-		main_litedramcore_cmd_payload_a <= 16'd0;
-		main_litedramcore_cmd_payload_ba <= 3'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_timer_count1 <= 10'd781;
-		main_litedramcore_postponer_req_o <= 1'd0;
-		main_litedramcore_postponer_count <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd0;
-		main_litedramcore_sequencer_counter <= 7'd0;
-		main_litedramcore_sequencer_count <= 1'd0;
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
-		main_litedramcore_zqcs_executer_done <= 1'd0;
-		main_litedramcore_zqcs_executer_counter <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine0_row <= 16'd0;
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine1_row <= 16'd0;
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine2_row <= 16'd0;
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine3_row <= 16'd0;
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine4_row <= 16'd0;
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine5_row <= 16'd0;
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine6_row <= 16'd0;
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 23'd0;
-		main_litedramcore_bankmachine7_row <= 16'd0;
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trascon_count <= 3'd0;
-		main_litedramcore_choose_cmd_grant <= 3'd0;
-		main_litedramcore_choose_req_grant <= 3'd0;
-		main_litedramcore_trrdcon_ready <= 1'd0;
-		main_litedramcore_trrdcon_count <= 1'd0;
-		main_litedramcore_tfawcon_ready <= 1'd1;
-		main_litedramcore_tfawcon_window <= 5'd0;
-		main_litedramcore_tccdcon_ready <= 1'd0;
-		main_litedramcore_tccdcon_count <= 1'd0;
-		main_litedramcore_twtrcon_ready <= 1'd0;
-		main_litedramcore_twtrcon_count <= 3'd0;
-		main_litedramcore_time0 <= 5'd0;
-		main_litedramcore_time1 <= 4'd0;
-		main_init_done_storage <= 1'd0;
-		main_init_done_re <= 1'd0;
-		main_init_error_storage <= 1'd0;
-		main_init_error_re <= 1'd0;
-		builder_refresher_state <= 2'd0;
-		builder_bankmachine0_state <= 4'd0;
-		builder_bankmachine1_state <= 4'd0;
-		builder_bankmachine2_state <= 4'd0;
-		builder_bankmachine3_state <= 4'd0;
-		builder_bankmachine4_state <= 4'd0;
-		builder_bankmachine5_state <= 4'd0;
-		builder_bankmachine6_state <= 4'd0;
-		builder_bankmachine7_state <= 4'd0;
-		builder_multiplexer_state <= 4'd0;
-		builder_new_master_wdata_ready0 <= 1'd0;
-		builder_new_master_wdata_ready1 <= 1'd0;
-		builder_new_master_rdata_valid0 <= 1'd0;
-		builder_new_master_rdata_valid1 <= 1'd0;
-		builder_new_master_rdata_valid2 <= 1'd0;
-		builder_new_master_rdata_valid3 <= 1'd0;
-		builder_new_master_rdata_valid4 <= 1'd0;
-		builder_new_master_rdata_valid5 <= 1'd0;
-		builder_new_master_rdata_valid6 <= 1'd0;
-		builder_new_master_rdata_valid7 <= 1'd0;
-		builder_new_master_rdata_valid8 <= 1'd0;
-		builder_litedramcore_we <= 1'd0;
-		builder_state <= 2'd0;
+		a7ddrphy_rst_storage <= 1'd0;
+		a7ddrphy_rst_re <= 1'd0;
+		a7ddrphy_dly_sel_storage <= 2'd0;
+		a7ddrphy_dly_sel_re <= 1'd0;
+		a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+		a7ddrphy_half_sys8x_taps_re <= 1'd0;
+		a7ddrphy_wlevel_en_storage <= 1'd0;
+		a7ddrphy_wlevel_en_re <= 1'd0;
+		a7ddrphy_rdphase_storage <= 2'd2;
+		a7ddrphy_rdphase_re <= 1'd0;
+		a7ddrphy_wrphase_storage <= 2'd3;
+		a7ddrphy_wrphase_re <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_dqspattern_o1 <= 8'd0;
+		a7ddrphy_bitslip0_value0 <= 3'd7;
+		a7ddrphy_bitslip1_value0 <= 3'd7;
+		a7ddrphy_bitslip0_value1 <= 3'd7;
+		a7ddrphy_bitslip1_value1 <= 3'd7;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_bitslip0_value2 <= 3'd7;
+		a7ddrphy_bitslip0_value3 <= 3'd7;
+		a7ddrphy_bitslip1_value2 <= 3'd7;
+		a7ddrphy_bitslip1_value3 <= 3'd7;
+		a7ddrphy_bitslip2_value0 <= 3'd7;
+		a7ddrphy_bitslip2_value1 <= 3'd7;
+		a7ddrphy_bitslip3_value0 <= 3'd7;
+		a7ddrphy_bitslip3_value1 <= 3'd7;
+		a7ddrphy_bitslip4_value0 <= 3'd7;
+		a7ddrphy_bitslip4_value1 <= 3'd7;
+		a7ddrphy_bitslip5_value0 <= 3'd7;
+		a7ddrphy_bitslip5_value1 <= 3'd7;
+		a7ddrphy_bitslip6_value0 <= 3'd7;
+		a7ddrphy_bitslip6_value1 <= 3'd7;
+		a7ddrphy_bitslip7_value0 <= 3'd7;
+		a7ddrphy_bitslip7_value1 <= 3'd7;
+		a7ddrphy_bitslip8_value0 <= 3'd7;
+		a7ddrphy_bitslip8_value1 <= 3'd7;
+		a7ddrphy_bitslip9_value0 <= 3'd7;
+		a7ddrphy_bitslip9_value1 <= 3'd7;
+		a7ddrphy_bitslip10_value0 <= 3'd7;
+		a7ddrphy_bitslip10_value1 <= 3'd7;
+		a7ddrphy_bitslip11_value0 <= 3'd7;
+		a7ddrphy_bitslip11_value1 <= 3'd7;
+		a7ddrphy_bitslip12_value0 <= 3'd7;
+		a7ddrphy_bitslip12_value1 <= 3'd7;
+		a7ddrphy_bitslip13_value0 <= 3'd7;
+		a7ddrphy_bitslip13_value1 <= 3'd7;
+		a7ddrphy_bitslip14_value0 <= 3'd7;
+		a7ddrphy_bitslip14_value1 <= 3'd7;
+		a7ddrphy_bitslip15_value0 <= 3'd7;
+		a7ddrphy_bitslip15_value1 <= 3'd7;
+		a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+		litedramcore_storage <= 4'd1;
+		litedramcore_re <= 1'd0;
+		litedramcore_phaseinjector0_command_storage <= 6'd0;
+		litedramcore_phaseinjector0_command_re <= 1'd0;
+		litedramcore_phaseinjector0_address_re <= 1'd0;
+		litedramcore_phaseinjector0_baddress_re <= 1'd0;
+		litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector0_rddata_status <= 32'd0;
+		litedramcore_phaseinjector0_rddata_re <= 1'd0;
+		litedramcore_phaseinjector1_command_storage <= 6'd0;
+		litedramcore_phaseinjector1_command_re <= 1'd0;
+		litedramcore_phaseinjector1_address_re <= 1'd0;
+		litedramcore_phaseinjector1_baddress_re <= 1'd0;
+		litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector1_rddata_status <= 32'd0;
+		litedramcore_phaseinjector1_rddata_re <= 1'd0;
+		litedramcore_phaseinjector2_command_storage <= 6'd0;
+		litedramcore_phaseinjector2_command_re <= 1'd0;
+		litedramcore_phaseinjector2_address_re <= 1'd0;
+		litedramcore_phaseinjector2_baddress_re <= 1'd0;
+		litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector2_rddata_status <= 32'd0;
+		litedramcore_phaseinjector2_rddata_re <= 1'd0;
+		litedramcore_phaseinjector3_command_storage <= 6'd0;
+		litedramcore_phaseinjector3_command_re <= 1'd0;
+		litedramcore_phaseinjector3_address_re <= 1'd0;
+		litedramcore_phaseinjector3_baddress_re <= 1'd0;
+		litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector3_rddata_status <= 32'd0;
+		litedramcore_phaseinjector3_rddata_re <= 1'd0;
+		litedramcore_dfi_p0_address <= 16'd0;
+		litedramcore_dfi_p0_bank <= 3'd0;
+		litedramcore_dfi_p0_cas_n <= 1'd1;
+		litedramcore_dfi_p0_cs_n <= 1'd1;
+		litedramcore_dfi_p0_ras_n <= 1'd1;
+		litedramcore_dfi_p0_we_n <= 1'd1;
+		litedramcore_dfi_p0_wrdata_en <= 1'd0;
+		litedramcore_dfi_p0_rddata_en <= 1'd0;
+		litedramcore_dfi_p1_address <= 16'd0;
+		litedramcore_dfi_p1_bank <= 3'd0;
+		litedramcore_dfi_p1_cas_n <= 1'd1;
+		litedramcore_dfi_p1_cs_n <= 1'd1;
+		litedramcore_dfi_p1_ras_n <= 1'd1;
+		litedramcore_dfi_p1_we_n <= 1'd1;
+		litedramcore_dfi_p1_wrdata_en <= 1'd0;
+		litedramcore_dfi_p1_rddata_en <= 1'd0;
+		litedramcore_dfi_p2_address <= 16'd0;
+		litedramcore_dfi_p2_bank <= 3'd0;
+		litedramcore_dfi_p2_cas_n <= 1'd1;
+		litedramcore_dfi_p2_cs_n <= 1'd1;
+		litedramcore_dfi_p2_ras_n <= 1'd1;
+		litedramcore_dfi_p2_we_n <= 1'd1;
+		litedramcore_dfi_p2_wrdata_en <= 1'd0;
+		litedramcore_dfi_p2_rddata_en <= 1'd0;
+		litedramcore_dfi_p3_address <= 16'd0;
+		litedramcore_dfi_p3_bank <= 3'd0;
+		litedramcore_dfi_p3_cas_n <= 1'd1;
+		litedramcore_dfi_p3_cs_n <= 1'd1;
+		litedramcore_dfi_p3_ras_n <= 1'd1;
+		litedramcore_dfi_p3_we_n <= 1'd1;
+		litedramcore_dfi_p3_wrdata_en <= 1'd0;
+		litedramcore_dfi_p3_rddata_en <= 1'd0;
+		litedramcore_cmd_payload_a <= 16'd0;
+		litedramcore_cmd_payload_ba <= 3'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_timer_count1 <= 10'd781;
+		litedramcore_postponer_req_o <= 1'd0;
+		litedramcore_postponer_count <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd0;
+		litedramcore_sequencer_counter <= 7'd0;
+		litedramcore_sequencer_count <= 1'd0;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_executer_done <= 1'd0;
+		litedramcore_zqcs_executer_counter <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine0_row <= 16'd0;
+		litedramcore_bankmachine0_row_opened <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine0_trccon_ready <= 1'd0;
+		litedramcore_bankmachine0_trccon_count <= 3'd0;
+		litedramcore_bankmachine0_trascon_ready <= 1'd0;
+		litedramcore_bankmachine0_trascon_count <= 3'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine1_row <= 16'd0;
+		litedramcore_bankmachine1_row_opened <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine1_trccon_ready <= 1'd0;
+		litedramcore_bankmachine1_trccon_count <= 3'd0;
+		litedramcore_bankmachine1_trascon_ready <= 1'd0;
+		litedramcore_bankmachine1_trascon_count <= 3'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine2_row <= 16'd0;
+		litedramcore_bankmachine2_row_opened <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine2_trccon_ready <= 1'd0;
+		litedramcore_bankmachine2_trccon_count <= 3'd0;
+		litedramcore_bankmachine2_trascon_ready <= 1'd0;
+		litedramcore_bankmachine2_trascon_count <= 3'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine3_row <= 16'd0;
+		litedramcore_bankmachine3_row_opened <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine3_trccon_ready <= 1'd0;
+		litedramcore_bankmachine3_trccon_count <= 3'd0;
+		litedramcore_bankmachine3_trascon_ready <= 1'd0;
+		litedramcore_bankmachine3_trascon_count <= 3'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine4_row <= 16'd0;
+		litedramcore_bankmachine4_row_opened <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine4_trccon_ready <= 1'd0;
+		litedramcore_bankmachine4_trccon_count <= 3'd0;
+		litedramcore_bankmachine4_trascon_ready <= 1'd0;
+		litedramcore_bankmachine4_trascon_count <= 3'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine5_row <= 16'd0;
+		litedramcore_bankmachine5_row_opened <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine5_trccon_ready <= 1'd0;
+		litedramcore_bankmachine5_trccon_count <= 3'd0;
+		litedramcore_bankmachine5_trascon_ready <= 1'd0;
+		litedramcore_bankmachine5_trascon_count <= 3'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine6_row <= 16'd0;
+		litedramcore_bankmachine6_row_opened <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine6_trccon_ready <= 1'd0;
+		litedramcore_bankmachine6_trccon_count <= 3'd0;
+		litedramcore_bankmachine6_trascon_ready <= 1'd0;
+		litedramcore_bankmachine6_trascon_count <= 3'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 23'd0;
+		litedramcore_bankmachine7_row <= 16'd0;
+		litedramcore_bankmachine7_row_opened <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine7_trccon_ready <= 1'd0;
+		litedramcore_bankmachine7_trccon_count <= 3'd0;
+		litedramcore_bankmachine7_trascon_ready <= 1'd0;
+		litedramcore_bankmachine7_trascon_count <= 3'd0;
+		litedramcore_choose_cmd_grant <= 3'd0;
+		litedramcore_choose_req_grant <= 3'd0;
+		litedramcore_trrdcon_ready <= 1'd0;
+		litedramcore_trrdcon_count <= 1'd0;
+		litedramcore_tfawcon_ready <= 1'd1;
+		litedramcore_tfawcon_window <= 5'd0;
+		litedramcore_tccdcon_ready <= 1'd0;
+		litedramcore_tccdcon_count <= 1'd0;
+		litedramcore_twtrcon_ready <= 1'd0;
+		litedramcore_twtrcon_count <= 3'd0;
+		litedramcore_time0 <= 5'd0;
+		litedramcore_time1 <= 4'd0;
+		init_done_storage <= 1'd0;
+		init_done_re <= 1'd0;
+		init_error_storage <= 1'd0;
+		init_error_re <= 1'd0;
+		litedramcore_we <= 1'd0;
+		litedramcore_refresher_state <= 2'd0;
+		litedramcore_bankmachine0_state <= 4'd0;
+		litedramcore_bankmachine1_state <= 4'd0;
+		litedramcore_bankmachine2_state <= 4'd0;
+		litedramcore_bankmachine3_state <= 4'd0;
+		litedramcore_bankmachine4_state <= 4'd0;
+		litedramcore_bankmachine5_state <= 4'd0;
+		litedramcore_bankmachine6_state <= 4'd0;
+		litedramcore_bankmachine7_state <= 4'd0;
+		litedramcore_multiplexer_state <= 4'd0;
+		litedramcore_new_master_wdata_ready0 <= 1'd0;
+		litedramcore_new_master_wdata_ready1 <= 1'd0;
+		litedramcore_new_master_rdata_valid0 <= 1'd0;
+		litedramcore_new_master_rdata_valid1 <= 1'd0;
+		litedramcore_new_master_rdata_valid2 <= 1'd0;
+		litedramcore_new_master_rdata_valid3 <= 1'd0;
+		litedramcore_new_master_rdata_valid4 <= 1'd0;
+		litedramcore_new_master_rdata_valid5 <= 1'd0;
+		litedramcore_new_master_rdata_valid6 <= 1'd0;
+		litedramcore_new_master_rdata_valid7 <= 1'd0;
+		litedramcore_new_master_rdata_valid8 <= 1'd0;
+		litedramcore_state <= 2'd0;
 	end
 end
 
@@ -13454,28 +13897,28 @@ end
 //------------------------------------------------------------------------------
 
 BUFG BUFG(
-	.I(main_clkout0),
-	.O(main_clkout_buf0)
+	.I(clkout0),
+	.O(clkout_buf0)
 );
 
 BUFG BUFG_1(
-	.I(main_clkout1),
-	.O(main_clkout_buf1)
+	.I(clkout1),
+	.O(clkout_buf1)
 );
 
 BUFG BUFG_2(
-	.I(main_clkout2),
-	.O(main_clkout_buf2)
+	.I(clkout2),
+	.O(clkout_buf2)
 );
 
 BUFG BUFG_3(
-	.I(main_clkout3),
-	.O(main_clkout_buf3)
+	.I(clkout3),
+	.O(clkout_buf3)
 );
 
 IDELAYCTRL IDELAYCTRL(
 	.REFCLK(iodelay_clk),
-	.RST(main_ic_reset)
+	.RST(ic_reset)
 );
 
 OSERDESE2 #(
@@ -13496,12 +13939,12 @@ OSERDESE2 #(
 	.D7(1'd0),
 	.D8(1'd1),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(main_a7ddrphy_sd_clk_se_nodelay)
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_sd_clk_se_nodelay)
 );
 
 OBUFDS OBUFDS(
-	.I(main_a7ddrphy_sd_clk_se_nodelay),
+	.I(a7ddrphy_sd_clk_se_nodelay),
 	.O(ddram_clk_p),
 	.OB(ddram_clk_n)
 );
@@ -13515,16 +13958,16 @@ OSERDESE2 #(
 ) OSERDESE2_1 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_reset_n),
-	.D2(main_a7ddrphy_dfi_p0_reset_n),
-	.D3(main_a7ddrphy_dfi_p1_reset_n),
-	.D4(main_a7ddrphy_dfi_p1_reset_n),
-	.D5(main_a7ddrphy_dfi_p2_reset_n),
-	.D6(main_a7ddrphy_dfi_p2_reset_n),
-	.D7(main_a7ddrphy_dfi_p3_reset_n),
-	.D8(main_a7ddrphy_dfi_p3_reset_n),
+	.D1(a7ddrphy_dfi_p0_reset_n),
+	.D2(a7ddrphy_dfi_p0_reset_n),
+	.D3(a7ddrphy_dfi_p1_reset_n),
+	.D4(a7ddrphy_dfi_p1_reset_n),
+	.D5(a7ddrphy_dfi_p2_reset_n),
+	.D6(a7ddrphy_dfi_p2_reset_n),
+	.D7(a7ddrphy_dfi_p3_reset_n),
+	.D8(a7ddrphy_dfi_p3_reset_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_reset_n)
 );
 
@@ -13537,16 +13980,16 @@ OSERDESE2 #(
 ) OSERDESE2_2 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cs_n),
-	.D2(main_a7ddrphy_dfi_p0_cs_n),
-	.D3(main_a7ddrphy_dfi_p1_cs_n),
-	.D4(main_a7ddrphy_dfi_p1_cs_n),
-	.D5(main_a7ddrphy_dfi_p2_cs_n),
-	.D6(main_a7ddrphy_dfi_p2_cs_n),
-	.D7(main_a7ddrphy_dfi_p3_cs_n),
-	.D8(main_a7ddrphy_dfi_p3_cs_n),
+	.D1(a7ddrphy_dfi_p0_cs_n),
+	.D2(a7ddrphy_dfi_p0_cs_n),
+	.D3(a7ddrphy_dfi_p1_cs_n),
+	.D4(a7ddrphy_dfi_p1_cs_n),
+	.D5(a7ddrphy_dfi_p2_cs_n),
+	.D6(a7ddrphy_dfi_p2_cs_n),
+	.D7(a7ddrphy_dfi_p3_cs_n),
+	.D8(a7ddrphy_dfi_p3_cs_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cs_n)
 );
 
@@ -13559,16 +14002,16 @@ OSERDESE2 #(
 ) OSERDESE2_3 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[0]),
-	.D2(main_a7ddrphy_dfi_p0_address[0]),
-	.D3(main_a7ddrphy_dfi_p1_address[0]),
-	.D4(main_a7ddrphy_dfi_p1_address[0]),
-	.D5(main_a7ddrphy_dfi_p2_address[0]),
-	.D6(main_a7ddrphy_dfi_p2_address[0]),
-	.D7(main_a7ddrphy_dfi_p3_address[0]),
-	.D8(main_a7ddrphy_dfi_p3_address[0]),
+	.D1(a7ddrphy_dfi_p0_address[0]),
+	.D2(a7ddrphy_dfi_p0_address[0]),
+	.D3(a7ddrphy_dfi_p1_address[0]),
+	.D4(a7ddrphy_dfi_p1_address[0]),
+	.D5(a7ddrphy_dfi_p2_address[0]),
+	.D6(a7ddrphy_dfi_p2_address[0]),
+	.D7(a7ddrphy_dfi_p3_address[0]),
+	.D8(a7ddrphy_dfi_p3_address[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[0])
 );
 
@@ -13581,16 +14024,16 @@ OSERDESE2 #(
 ) OSERDESE2_4 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[1]),
-	.D2(main_a7ddrphy_dfi_p0_address[1]),
-	.D3(main_a7ddrphy_dfi_p1_address[1]),
-	.D4(main_a7ddrphy_dfi_p1_address[1]),
-	.D5(main_a7ddrphy_dfi_p2_address[1]),
-	.D6(main_a7ddrphy_dfi_p2_address[1]),
-	.D7(main_a7ddrphy_dfi_p3_address[1]),
-	.D8(main_a7ddrphy_dfi_p3_address[1]),
+	.D1(a7ddrphy_dfi_p0_address[1]),
+	.D2(a7ddrphy_dfi_p0_address[1]),
+	.D3(a7ddrphy_dfi_p1_address[1]),
+	.D4(a7ddrphy_dfi_p1_address[1]),
+	.D5(a7ddrphy_dfi_p2_address[1]),
+	.D6(a7ddrphy_dfi_p2_address[1]),
+	.D7(a7ddrphy_dfi_p3_address[1]),
+	.D8(a7ddrphy_dfi_p3_address[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[1])
 );
 
@@ -13603,16 +14046,16 @@ OSERDESE2 #(
 ) OSERDESE2_5 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[2]),
-	.D2(main_a7ddrphy_dfi_p0_address[2]),
-	.D3(main_a7ddrphy_dfi_p1_address[2]),
-	.D4(main_a7ddrphy_dfi_p1_address[2]),
-	.D5(main_a7ddrphy_dfi_p2_address[2]),
-	.D6(main_a7ddrphy_dfi_p2_address[2]),
-	.D7(main_a7ddrphy_dfi_p3_address[2]),
-	.D8(main_a7ddrphy_dfi_p3_address[2]),
+	.D1(a7ddrphy_dfi_p0_address[2]),
+	.D2(a7ddrphy_dfi_p0_address[2]),
+	.D3(a7ddrphy_dfi_p1_address[2]),
+	.D4(a7ddrphy_dfi_p1_address[2]),
+	.D5(a7ddrphy_dfi_p2_address[2]),
+	.D6(a7ddrphy_dfi_p2_address[2]),
+	.D7(a7ddrphy_dfi_p3_address[2]),
+	.D8(a7ddrphy_dfi_p3_address[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[2])
 );
 
@@ -13625,16 +14068,16 @@ OSERDESE2 #(
 ) OSERDESE2_6 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[3]),
-	.D2(main_a7ddrphy_dfi_p0_address[3]),
-	.D3(main_a7ddrphy_dfi_p1_address[3]),
-	.D4(main_a7ddrphy_dfi_p1_address[3]),
-	.D5(main_a7ddrphy_dfi_p2_address[3]),
-	.D6(main_a7ddrphy_dfi_p2_address[3]),
-	.D7(main_a7ddrphy_dfi_p3_address[3]),
-	.D8(main_a7ddrphy_dfi_p3_address[3]),
+	.D1(a7ddrphy_dfi_p0_address[3]),
+	.D2(a7ddrphy_dfi_p0_address[3]),
+	.D3(a7ddrphy_dfi_p1_address[3]),
+	.D4(a7ddrphy_dfi_p1_address[3]),
+	.D5(a7ddrphy_dfi_p2_address[3]),
+	.D6(a7ddrphy_dfi_p2_address[3]),
+	.D7(a7ddrphy_dfi_p3_address[3]),
+	.D8(a7ddrphy_dfi_p3_address[3]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[3])
 );
 
@@ -13647,16 +14090,16 @@ OSERDESE2 #(
 ) OSERDESE2_7 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[4]),
-	.D2(main_a7ddrphy_dfi_p0_address[4]),
-	.D3(main_a7ddrphy_dfi_p1_address[4]),
-	.D4(main_a7ddrphy_dfi_p1_address[4]),
-	.D5(main_a7ddrphy_dfi_p2_address[4]),
-	.D6(main_a7ddrphy_dfi_p2_address[4]),
-	.D7(main_a7ddrphy_dfi_p3_address[4]),
-	.D8(main_a7ddrphy_dfi_p3_address[4]),
+	.D1(a7ddrphy_dfi_p0_address[4]),
+	.D2(a7ddrphy_dfi_p0_address[4]),
+	.D3(a7ddrphy_dfi_p1_address[4]),
+	.D4(a7ddrphy_dfi_p1_address[4]),
+	.D5(a7ddrphy_dfi_p2_address[4]),
+	.D6(a7ddrphy_dfi_p2_address[4]),
+	.D7(a7ddrphy_dfi_p3_address[4]),
+	.D8(a7ddrphy_dfi_p3_address[4]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[4])
 );
 
@@ -13669,16 +14112,16 @@ OSERDESE2 #(
 ) OSERDESE2_8 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[5]),
-	.D2(main_a7ddrphy_dfi_p0_address[5]),
-	.D3(main_a7ddrphy_dfi_p1_address[5]),
-	.D4(main_a7ddrphy_dfi_p1_address[5]),
-	.D5(main_a7ddrphy_dfi_p2_address[5]),
-	.D6(main_a7ddrphy_dfi_p2_address[5]),
-	.D7(main_a7ddrphy_dfi_p3_address[5]),
-	.D8(main_a7ddrphy_dfi_p3_address[5]),
+	.D1(a7ddrphy_dfi_p0_address[5]),
+	.D2(a7ddrphy_dfi_p0_address[5]),
+	.D3(a7ddrphy_dfi_p1_address[5]),
+	.D4(a7ddrphy_dfi_p1_address[5]),
+	.D5(a7ddrphy_dfi_p2_address[5]),
+	.D6(a7ddrphy_dfi_p2_address[5]),
+	.D7(a7ddrphy_dfi_p3_address[5]),
+	.D8(a7ddrphy_dfi_p3_address[5]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[5])
 );
 
@@ -13691,16 +14134,16 @@ OSERDESE2 #(
 ) OSERDESE2_9 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[6]),
-	.D2(main_a7ddrphy_dfi_p0_address[6]),
-	.D3(main_a7ddrphy_dfi_p1_address[6]),
-	.D4(main_a7ddrphy_dfi_p1_address[6]),
-	.D5(main_a7ddrphy_dfi_p2_address[6]),
-	.D6(main_a7ddrphy_dfi_p2_address[6]),
-	.D7(main_a7ddrphy_dfi_p3_address[6]),
-	.D8(main_a7ddrphy_dfi_p3_address[6]),
+	.D1(a7ddrphy_dfi_p0_address[6]),
+	.D2(a7ddrphy_dfi_p0_address[6]),
+	.D3(a7ddrphy_dfi_p1_address[6]),
+	.D4(a7ddrphy_dfi_p1_address[6]),
+	.D5(a7ddrphy_dfi_p2_address[6]),
+	.D6(a7ddrphy_dfi_p2_address[6]),
+	.D7(a7ddrphy_dfi_p3_address[6]),
+	.D8(a7ddrphy_dfi_p3_address[6]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[6])
 );
 
@@ -13713,16 +14156,16 @@ OSERDESE2 #(
 ) OSERDESE2_10 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[7]),
-	.D2(main_a7ddrphy_dfi_p0_address[7]),
-	.D3(main_a7ddrphy_dfi_p1_address[7]),
-	.D4(main_a7ddrphy_dfi_p1_address[7]),
-	.D5(main_a7ddrphy_dfi_p2_address[7]),
-	.D6(main_a7ddrphy_dfi_p2_address[7]),
-	.D7(main_a7ddrphy_dfi_p3_address[7]),
-	.D8(main_a7ddrphy_dfi_p3_address[7]),
+	.D1(a7ddrphy_dfi_p0_address[7]),
+	.D2(a7ddrphy_dfi_p0_address[7]),
+	.D3(a7ddrphy_dfi_p1_address[7]),
+	.D4(a7ddrphy_dfi_p1_address[7]),
+	.D5(a7ddrphy_dfi_p2_address[7]),
+	.D6(a7ddrphy_dfi_p2_address[7]),
+	.D7(a7ddrphy_dfi_p3_address[7]),
+	.D8(a7ddrphy_dfi_p3_address[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[7])
 );
 
@@ -13735,16 +14178,16 @@ OSERDESE2 #(
 ) OSERDESE2_11 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[8]),
-	.D2(main_a7ddrphy_dfi_p0_address[8]),
-	.D3(main_a7ddrphy_dfi_p1_address[8]),
-	.D4(main_a7ddrphy_dfi_p1_address[8]),
-	.D5(main_a7ddrphy_dfi_p2_address[8]),
-	.D6(main_a7ddrphy_dfi_p2_address[8]),
-	.D7(main_a7ddrphy_dfi_p3_address[8]),
-	.D8(main_a7ddrphy_dfi_p3_address[8]),
+	.D1(a7ddrphy_dfi_p0_address[8]),
+	.D2(a7ddrphy_dfi_p0_address[8]),
+	.D3(a7ddrphy_dfi_p1_address[8]),
+	.D4(a7ddrphy_dfi_p1_address[8]),
+	.D5(a7ddrphy_dfi_p2_address[8]),
+	.D6(a7ddrphy_dfi_p2_address[8]),
+	.D7(a7ddrphy_dfi_p3_address[8]),
+	.D8(a7ddrphy_dfi_p3_address[8]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[8])
 );
 
@@ -13757,16 +14200,16 @@ OSERDESE2 #(
 ) OSERDESE2_12 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[9]),
-	.D2(main_a7ddrphy_dfi_p0_address[9]),
-	.D3(main_a7ddrphy_dfi_p1_address[9]),
-	.D4(main_a7ddrphy_dfi_p1_address[9]),
-	.D5(main_a7ddrphy_dfi_p2_address[9]),
-	.D6(main_a7ddrphy_dfi_p2_address[9]),
-	.D7(main_a7ddrphy_dfi_p3_address[9]),
-	.D8(main_a7ddrphy_dfi_p3_address[9]),
+	.D1(a7ddrphy_dfi_p0_address[9]),
+	.D2(a7ddrphy_dfi_p0_address[9]),
+	.D3(a7ddrphy_dfi_p1_address[9]),
+	.D4(a7ddrphy_dfi_p1_address[9]),
+	.D5(a7ddrphy_dfi_p2_address[9]),
+	.D6(a7ddrphy_dfi_p2_address[9]),
+	.D7(a7ddrphy_dfi_p3_address[9]),
+	.D8(a7ddrphy_dfi_p3_address[9]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[9])
 );
 
@@ -13779,16 +14222,16 @@ OSERDESE2 #(
 ) OSERDESE2_13 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[10]),
-	.D2(main_a7ddrphy_dfi_p0_address[10]),
-	.D3(main_a7ddrphy_dfi_p1_address[10]),
-	.D4(main_a7ddrphy_dfi_p1_address[10]),
-	.D5(main_a7ddrphy_dfi_p2_address[10]),
-	.D6(main_a7ddrphy_dfi_p2_address[10]),
-	.D7(main_a7ddrphy_dfi_p3_address[10]),
-	.D8(main_a7ddrphy_dfi_p3_address[10]),
+	.D1(a7ddrphy_dfi_p0_address[10]),
+	.D2(a7ddrphy_dfi_p0_address[10]),
+	.D3(a7ddrphy_dfi_p1_address[10]),
+	.D4(a7ddrphy_dfi_p1_address[10]),
+	.D5(a7ddrphy_dfi_p2_address[10]),
+	.D6(a7ddrphy_dfi_p2_address[10]),
+	.D7(a7ddrphy_dfi_p3_address[10]),
+	.D8(a7ddrphy_dfi_p3_address[10]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[10])
 );
 
@@ -13801,16 +14244,16 @@ OSERDESE2 #(
 ) OSERDESE2_14 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[11]),
-	.D2(main_a7ddrphy_dfi_p0_address[11]),
-	.D3(main_a7ddrphy_dfi_p1_address[11]),
-	.D4(main_a7ddrphy_dfi_p1_address[11]),
-	.D5(main_a7ddrphy_dfi_p2_address[11]),
-	.D6(main_a7ddrphy_dfi_p2_address[11]),
-	.D7(main_a7ddrphy_dfi_p3_address[11]),
-	.D8(main_a7ddrphy_dfi_p3_address[11]),
+	.D1(a7ddrphy_dfi_p0_address[11]),
+	.D2(a7ddrphy_dfi_p0_address[11]),
+	.D3(a7ddrphy_dfi_p1_address[11]),
+	.D4(a7ddrphy_dfi_p1_address[11]),
+	.D5(a7ddrphy_dfi_p2_address[11]),
+	.D6(a7ddrphy_dfi_p2_address[11]),
+	.D7(a7ddrphy_dfi_p3_address[11]),
+	.D8(a7ddrphy_dfi_p3_address[11]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[11])
 );
 
@@ -13823,16 +14266,16 @@ OSERDESE2 #(
 ) OSERDESE2_15 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[12]),
-	.D2(main_a7ddrphy_dfi_p0_address[12]),
-	.D3(main_a7ddrphy_dfi_p1_address[12]),
-	.D4(main_a7ddrphy_dfi_p1_address[12]),
-	.D5(main_a7ddrphy_dfi_p2_address[12]),
-	.D6(main_a7ddrphy_dfi_p2_address[12]),
-	.D7(main_a7ddrphy_dfi_p3_address[12]),
-	.D8(main_a7ddrphy_dfi_p3_address[12]),
+	.D1(a7ddrphy_dfi_p0_address[12]),
+	.D2(a7ddrphy_dfi_p0_address[12]),
+	.D3(a7ddrphy_dfi_p1_address[12]),
+	.D4(a7ddrphy_dfi_p1_address[12]),
+	.D5(a7ddrphy_dfi_p2_address[12]),
+	.D6(a7ddrphy_dfi_p2_address[12]),
+	.D7(a7ddrphy_dfi_p3_address[12]),
+	.D8(a7ddrphy_dfi_p3_address[12]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[12])
 );
 
@@ -13845,16 +14288,16 @@ OSERDESE2 #(
 ) OSERDESE2_16 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[13]),
-	.D2(main_a7ddrphy_dfi_p0_address[13]),
-	.D3(main_a7ddrphy_dfi_p1_address[13]),
-	.D4(main_a7ddrphy_dfi_p1_address[13]),
-	.D5(main_a7ddrphy_dfi_p2_address[13]),
-	.D6(main_a7ddrphy_dfi_p2_address[13]),
-	.D7(main_a7ddrphy_dfi_p3_address[13]),
-	.D8(main_a7ddrphy_dfi_p3_address[13]),
+	.D1(a7ddrphy_dfi_p0_address[13]),
+	.D2(a7ddrphy_dfi_p0_address[13]),
+	.D3(a7ddrphy_dfi_p1_address[13]),
+	.D4(a7ddrphy_dfi_p1_address[13]),
+	.D5(a7ddrphy_dfi_p2_address[13]),
+	.D6(a7ddrphy_dfi_p2_address[13]),
+	.D7(a7ddrphy_dfi_p3_address[13]),
+	.D8(a7ddrphy_dfi_p3_address[13]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[13])
 );
 
@@ -13867,16 +14310,16 @@ OSERDESE2 #(
 ) OSERDESE2_17 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[14]),
-	.D2(main_a7ddrphy_dfi_p0_address[14]),
-	.D3(main_a7ddrphy_dfi_p1_address[14]),
-	.D4(main_a7ddrphy_dfi_p1_address[14]),
-	.D5(main_a7ddrphy_dfi_p2_address[14]),
-	.D6(main_a7ddrphy_dfi_p2_address[14]),
-	.D7(main_a7ddrphy_dfi_p3_address[14]),
-	.D8(main_a7ddrphy_dfi_p3_address[14]),
+	.D1(a7ddrphy_dfi_p0_address[14]),
+	.D2(a7ddrphy_dfi_p0_address[14]),
+	.D3(a7ddrphy_dfi_p1_address[14]),
+	.D4(a7ddrphy_dfi_p1_address[14]),
+	.D5(a7ddrphy_dfi_p2_address[14]),
+	.D6(a7ddrphy_dfi_p2_address[14]),
+	.D7(a7ddrphy_dfi_p3_address[14]),
+	.D8(a7ddrphy_dfi_p3_address[14]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[14])
 );
 
@@ -13889,16 +14332,16 @@ OSERDESE2 #(
 ) OSERDESE2_18 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[15]),
-	.D2(main_a7ddrphy_dfi_p0_address[15]),
-	.D3(main_a7ddrphy_dfi_p1_address[15]),
-	.D4(main_a7ddrphy_dfi_p1_address[15]),
-	.D5(main_a7ddrphy_dfi_p2_address[15]),
-	.D6(main_a7ddrphy_dfi_p2_address[15]),
-	.D7(main_a7ddrphy_dfi_p3_address[15]),
-	.D8(main_a7ddrphy_dfi_p3_address[15]),
+	.D1(a7ddrphy_dfi_p0_address[15]),
+	.D2(a7ddrphy_dfi_p0_address[15]),
+	.D3(a7ddrphy_dfi_p1_address[15]),
+	.D4(a7ddrphy_dfi_p1_address[15]),
+	.D5(a7ddrphy_dfi_p2_address[15]),
+	.D6(a7ddrphy_dfi_p2_address[15]),
+	.D7(a7ddrphy_dfi_p3_address[15]),
+	.D8(a7ddrphy_dfi_p3_address[15]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[15])
 );
 
@@ -13911,17 +14354,17 @@ OSERDESE2 #(
 ) OSERDESE2_19 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[0]),
-	.D2(main_a7ddrphy_dfi_p0_bank[0]),
-	.D3(main_a7ddrphy_dfi_p1_bank[0]),
-	.D4(main_a7ddrphy_dfi_p1_bank[0]),
-	.D5(main_a7ddrphy_dfi_p2_bank[0]),
-	.D6(main_a7ddrphy_dfi_p2_bank[0]),
-	.D7(main_a7ddrphy_dfi_p3_bank[0]),
-	.D8(main_a7ddrphy_dfi_p3_bank[0]),
+	.D1(a7ddrphy_dfi_p0_bank[0]),
+	.D2(a7ddrphy_dfi_p0_bank[0]),
+	.D3(a7ddrphy_dfi_p1_bank[0]),
+	.D4(a7ddrphy_dfi_p1_bank[0]),
+	.D5(a7ddrphy_dfi_p2_bank[0]),
+	.D6(a7ddrphy_dfi_p2_bank[0]),
+	.D7(a7ddrphy_dfi_p3_bank[0]),
+	.D8(a7ddrphy_dfi_p3_bank[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[0])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[0])
 );
 
 OSERDESE2 #(
@@ -13933,17 +14376,17 @@ OSERDESE2 #(
 ) OSERDESE2_20 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[1]),
-	.D2(main_a7ddrphy_dfi_p0_bank[1]),
-	.D3(main_a7ddrphy_dfi_p1_bank[1]),
-	.D4(main_a7ddrphy_dfi_p1_bank[1]),
-	.D5(main_a7ddrphy_dfi_p2_bank[1]),
-	.D6(main_a7ddrphy_dfi_p2_bank[1]),
-	.D7(main_a7ddrphy_dfi_p3_bank[1]),
-	.D8(main_a7ddrphy_dfi_p3_bank[1]),
+	.D1(a7ddrphy_dfi_p0_bank[1]),
+	.D2(a7ddrphy_dfi_p0_bank[1]),
+	.D3(a7ddrphy_dfi_p1_bank[1]),
+	.D4(a7ddrphy_dfi_p1_bank[1]),
+	.D5(a7ddrphy_dfi_p2_bank[1]),
+	.D6(a7ddrphy_dfi_p2_bank[1]),
+	.D7(a7ddrphy_dfi_p3_bank[1]),
+	.D8(a7ddrphy_dfi_p3_bank[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[1])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[1])
 );
 
 OSERDESE2 #(
@@ -13955,17 +14398,17 @@ OSERDESE2 #(
 ) OSERDESE2_21 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[2]),
-	.D2(main_a7ddrphy_dfi_p0_bank[2]),
-	.D3(main_a7ddrphy_dfi_p1_bank[2]),
-	.D4(main_a7ddrphy_dfi_p1_bank[2]),
-	.D5(main_a7ddrphy_dfi_p2_bank[2]),
-	.D6(main_a7ddrphy_dfi_p2_bank[2]),
-	.D7(main_a7ddrphy_dfi_p3_bank[2]),
-	.D8(main_a7ddrphy_dfi_p3_bank[2]),
+	.D1(a7ddrphy_dfi_p0_bank[2]),
+	.D2(a7ddrphy_dfi_p0_bank[2]),
+	.D3(a7ddrphy_dfi_p1_bank[2]),
+	.D4(a7ddrphy_dfi_p1_bank[2]),
+	.D5(a7ddrphy_dfi_p2_bank[2]),
+	.D6(a7ddrphy_dfi_p2_bank[2]),
+	.D7(a7ddrphy_dfi_p3_bank[2]),
+	.D8(a7ddrphy_dfi_p3_bank[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[2])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[2])
 );
 
 OSERDESE2 #(
@@ -13977,16 +14420,16 @@ OSERDESE2 #(
 ) OSERDESE2_22 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_ras_n),
-	.D2(main_a7ddrphy_dfi_p0_ras_n),
-	.D3(main_a7ddrphy_dfi_p1_ras_n),
-	.D4(main_a7ddrphy_dfi_p1_ras_n),
-	.D5(main_a7ddrphy_dfi_p2_ras_n),
-	.D6(main_a7ddrphy_dfi_p2_ras_n),
-	.D7(main_a7ddrphy_dfi_p3_ras_n),
-	.D8(main_a7ddrphy_dfi_p3_ras_n),
+	.D1(a7ddrphy_dfi_p0_ras_n),
+	.D2(a7ddrphy_dfi_p0_ras_n),
+	.D3(a7ddrphy_dfi_p1_ras_n),
+	.D4(a7ddrphy_dfi_p1_ras_n),
+	.D5(a7ddrphy_dfi_p2_ras_n),
+	.D6(a7ddrphy_dfi_p2_ras_n),
+	.D7(a7ddrphy_dfi_p3_ras_n),
+	.D8(a7ddrphy_dfi_p3_ras_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_ras_n)
 );
 
@@ -13999,16 +14442,16 @@ OSERDESE2 #(
 ) OSERDESE2_23 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cas_n),
-	.D2(main_a7ddrphy_dfi_p0_cas_n),
-	.D3(main_a7ddrphy_dfi_p1_cas_n),
-	.D4(main_a7ddrphy_dfi_p1_cas_n),
-	.D5(main_a7ddrphy_dfi_p2_cas_n),
-	.D6(main_a7ddrphy_dfi_p2_cas_n),
-	.D7(main_a7ddrphy_dfi_p3_cas_n),
-	.D8(main_a7ddrphy_dfi_p3_cas_n),
+	.D1(a7ddrphy_dfi_p0_cas_n),
+	.D2(a7ddrphy_dfi_p0_cas_n),
+	.D3(a7ddrphy_dfi_p1_cas_n),
+	.D4(a7ddrphy_dfi_p1_cas_n),
+	.D5(a7ddrphy_dfi_p2_cas_n),
+	.D6(a7ddrphy_dfi_p2_cas_n),
+	.D7(a7ddrphy_dfi_p3_cas_n),
+	.D8(a7ddrphy_dfi_p3_cas_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cas_n)
 );
 
@@ -14021,16 +14464,16 @@ OSERDESE2 #(
 ) OSERDESE2_24 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_we_n),
-	.D2(main_a7ddrphy_dfi_p0_we_n),
-	.D3(main_a7ddrphy_dfi_p1_we_n),
-	.D4(main_a7ddrphy_dfi_p1_we_n),
-	.D5(main_a7ddrphy_dfi_p2_we_n),
-	.D6(main_a7ddrphy_dfi_p2_we_n),
-	.D7(main_a7ddrphy_dfi_p3_we_n),
-	.D8(main_a7ddrphy_dfi_p3_we_n),
+	.D1(a7ddrphy_dfi_p0_we_n),
+	.D2(a7ddrphy_dfi_p0_we_n),
+	.D3(a7ddrphy_dfi_p1_we_n),
+	.D4(a7ddrphy_dfi_p1_we_n),
+	.D5(a7ddrphy_dfi_p2_we_n),
+	.D6(a7ddrphy_dfi_p2_we_n),
+	.D7(a7ddrphy_dfi_p3_we_n),
+	.D8(a7ddrphy_dfi_p3_we_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_we_n)
 );
 
@@ -14043,16 +14486,16 @@ OSERDESE2 #(
 ) OSERDESE2_25 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cke),
-	.D2(main_a7ddrphy_dfi_p0_cke),
-	.D3(main_a7ddrphy_dfi_p1_cke),
-	.D4(main_a7ddrphy_dfi_p1_cke),
-	.D5(main_a7ddrphy_dfi_p2_cke),
-	.D6(main_a7ddrphy_dfi_p2_cke),
-	.D7(main_a7ddrphy_dfi_p3_cke),
-	.D8(main_a7ddrphy_dfi_p3_cke),
+	.D1(a7ddrphy_dfi_p0_cke),
+	.D2(a7ddrphy_dfi_p0_cke),
+	.D3(a7ddrphy_dfi_p1_cke),
+	.D4(a7ddrphy_dfi_p1_cke),
+	.D5(a7ddrphy_dfi_p2_cke),
+	.D6(a7ddrphy_dfi_p2_cke),
+	.D7(a7ddrphy_dfi_p3_cke),
+	.D8(a7ddrphy_dfi_p3_cke),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cke)
 );
 
@@ -14065,16 +14508,16 @@ OSERDESE2 #(
 ) OSERDESE2_26 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_odt),
-	.D2(main_a7ddrphy_dfi_p0_odt),
-	.D3(main_a7ddrphy_dfi_p1_odt),
-	.D4(main_a7ddrphy_dfi_p1_odt),
-	.D5(main_a7ddrphy_dfi_p2_odt),
-	.D6(main_a7ddrphy_dfi_p2_odt),
-	.D7(main_a7ddrphy_dfi_p3_odt),
-	.D8(main_a7ddrphy_dfi_p3_odt),
+	.D1(a7ddrphy_dfi_p0_odt),
+	.D2(a7ddrphy_dfi_p0_odt),
+	.D3(a7ddrphy_dfi_p1_odt),
+	.D4(a7ddrphy_dfi_p1_odt),
+	.D5(a7ddrphy_dfi_p2_odt),
+	.D6(a7ddrphy_dfi_p2_odt),
+	.D7(a7ddrphy_dfi_p3_odt),
+	.D8(a7ddrphy_dfi_p3_odt),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_odt)
 );
 
@@ -14087,26 +14530,26 @@ OSERDESE2 #(
 ) OSERDESE2_27 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip00[0]),
-	.D2(main_a7ddrphy_bitslip00[1]),
-	.D3(main_a7ddrphy_bitslip00[2]),
-	.D4(main_a7ddrphy_bitslip00[3]),
-	.D5(main_a7ddrphy_bitslip00[4]),
-	.D6(main_a7ddrphy_bitslip00[5]),
-	.D7(main_a7ddrphy_bitslip00[6]),
-	.D8(main_a7ddrphy_bitslip00[7]),
+	.D1(a7ddrphy_bitslip00[0]),
+	.D2(a7ddrphy_bitslip00[1]),
+	.D3(a7ddrphy_bitslip00[2]),
+	.D4(a7ddrphy_bitslip00[3]),
+	.D5(a7ddrphy_bitslip00[4]),
+	.D6(a7ddrphy_bitslip00[5]),
+	.D7(a7ddrphy_bitslip00[6]),
+	.D8(a7ddrphy_bitslip00[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy0),
-	.OQ(main_a7ddrphy_dqs_o_no_delay0),
-	.TQ(main_a7ddrphy_dqs_t0)
+	.OFB(a7ddrphy0),
+	.OQ(a7ddrphy_dqs_o_no_delay0),
+	.TQ(a7ddrphy_dqs_t0)
 );
 
 IOBUFDS IOBUFDS(
-	.I(main_a7ddrphy_dqs_o_no_delay0),
-	.T(main_a7ddrphy_dqs_t0),
+	.I(a7ddrphy_dqs_o_no_delay0),
+	.T(a7ddrphy_dqs_t0),
 	.IO(ddram_dqs_p[0]),
 	.IOB(ddram_dqs_n[0])
 );
@@ -14120,26 +14563,26 @@ OSERDESE2 #(
 ) OSERDESE2_28 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip10[0]),
-	.D2(main_a7ddrphy_bitslip10[1]),
-	.D3(main_a7ddrphy_bitslip10[2]),
-	.D4(main_a7ddrphy_bitslip10[3]),
-	.D5(main_a7ddrphy_bitslip10[4]),
-	.D6(main_a7ddrphy_bitslip10[5]),
-	.D7(main_a7ddrphy_bitslip10[6]),
-	.D8(main_a7ddrphy_bitslip10[7]),
+	.D1(a7ddrphy_bitslip10[0]),
+	.D2(a7ddrphy_bitslip10[1]),
+	.D3(a7ddrphy_bitslip10[2]),
+	.D4(a7ddrphy_bitslip10[3]),
+	.D5(a7ddrphy_bitslip10[4]),
+	.D6(a7ddrphy_bitslip10[5]),
+	.D7(a7ddrphy_bitslip10[6]),
+	.D8(a7ddrphy_bitslip10[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy1),
-	.OQ(main_a7ddrphy_dqs_o_no_delay1),
-	.TQ(main_a7ddrphy_dqs_t1)
+	.OFB(a7ddrphy1),
+	.OQ(a7ddrphy_dqs_o_no_delay1),
+	.TQ(a7ddrphy_dqs_t1)
 );
 
 IOBUFDS IOBUFDS_1(
-	.I(main_a7ddrphy_dqs_o_no_delay1),
-	.T(main_a7ddrphy_dqs_t1),
+	.I(a7ddrphy_dqs_o_no_delay1),
+	.T(a7ddrphy_dqs_t1),
 	.IO(ddram_dqs_p[1]),
 	.IOB(ddram_dqs_n[1])
 );
@@ -14153,16 +14596,16 @@ OSERDESE2 #(
 ) OSERDESE2_29 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip01[0]),
-	.D2(main_a7ddrphy_bitslip01[1]),
-	.D3(main_a7ddrphy_bitslip01[2]),
-	.D4(main_a7ddrphy_bitslip01[3]),
-	.D5(main_a7ddrphy_bitslip01[4]),
-	.D6(main_a7ddrphy_bitslip01[5]),
-	.D7(main_a7ddrphy_bitslip01[6]),
-	.D8(main_a7ddrphy_bitslip01[7]),
+	.D1(a7ddrphy_bitslip01[0]),
+	.D2(a7ddrphy_bitslip01[1]),
+	.D3(a7ddrphy_bitslip01[2]),
+	.D4(a7ddrphy_bitslip01[3]),
+	.D5(a7ddrphy_bitslip01[4]),
+	.D6(a7ddrphy_bitslip01[5]),
+	.D7(a7ddrphy_bitslip01[6]),
+	.D8(a7ddrphy_bitslip01[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[0])
 );
 
@@ -14175,16 +14618,16 @@ OSERDESE2 #(
 ) OSERDESE2_30 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip11[0]),
-	.D2(main_a7ddrphy_bitslip11[1]),
-	.D3(main_a7ddrphy_bitslip11[2]),
-	.D4(main_a7ddrphy_bitslip11[3]),
-	.D5(main_a7ddrphy_bitslip11[4]),
-	.D6(main_a7ddrphy_bitslip11[5]),
-	.D7(main_a7ddrphy_bitslip11[6]),
-	.D8(main_a7ddrphy_bitslip11[7]),
+	.D1(a7ddrphy_bitslip11[0]),
+	.D2(a7ddrphy_bitslip11[1]),
+	.D3(a7ddrphy_bitslip11[2]),
+	.D4(a7ddrphy_bitslip11[3]),
+	.D5(a7ddrphy_bitslip11[4]),
+	.D6(a7ddrphy_bitslip11[5]),
+	.D7(a7ddrphy_bitslip11[6]),
+	.D8(a7ddrphy_bitslip11[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[1])
 );
 
@@ -14197,20 +14640,20 @@ OSERDESE2 #(
 ) OSERDESE2_31 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip02[0]),
-	.D2(main_a7ddrphy_bitslip02[1]),
-	.D3(main_a7ddrphy_bitslip02[2]),
-	.D4(main_a7ddrphy_bitslip02[3]),
-	.D5(main_a7ddrphy_bitslip02[4]),
-	.D6(main_a7ddrphy_bitslip02[5]),
-	.D7(main_a7ddrphy_bitslip02[6]),
-	.D8(main_a7ddrphy_bitslip02[7]),
+	.D1(a7ddrphy_bitslip02[0]),
+	.D2(a7ddrphy_bitslip02[1]),
+	.D3(a7ddrphy_bitslip02[2]),
+	.D4(a7ddrphy_bitslip02[3]),
+	.D5(a7ddrphy_bitslip02[4]),
+	.D6(a7ddrphy_bitslip02[5]),
+	.D7(a7ddrphy_bitslip02[6]),
+	.D8(a7ddrphy_bitslip02[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay0),
-	.TQ(main_a7ddrphy_dq_t0)
+	.OQ(a7ddrphy_dq_o_nodelay0),
+	.TQ(a7ddrphy_dq_t0)
 );
 
 ISERDESE2 #(
@@ -14226,16 +14669,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip03[7]),
-	.Q2(main_a7ddrphy_bitslip03[6]),
-	.Q3(main_a7ddrphy_bitslip03[5]),
-	.Q4(main_a7ddrphy_bitslip03[4]),
-	.Q5(main_a7ddrphy_bitslip03[3]),
-	.Q6(main_a7ddrphy_bitslip03[2]),
-	.Q7(main_a7ddrphy_bitslip03[1]),
-	.Q8(main_a7ddrphy_bitslip03[0])
+	.DDLY(a7ddrphy_dq_i_delayed0),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip03[7]),
+	.Q2(a7ddrphy_bitslip03[6]),
+	.Q3(a7ddrphy_bitslip03[5]),
+	.Q4(a7ddrphy_bitslip03[4]),
+	.Q5(a7ddrphy_bitslip03[3]),
+	.Q6(a7ddrphy_bitslip03[2]),
+	.Q7(a7ddrphy_bitslip03[1]),
+	.Q8(a7ddrphy_bitslip03[0])
 );
 
 IDELAYE2 #(
@@ -14249,19 +14692,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay0),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay0),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed0)
+	.DATAOUT(a7ddrphy_dq_i_delayed0)
 );
 
 IOBUF IOBUF(
-	.I(main_a7ddrphy_dq_o_nodelay0),
-	.T(main_a7ddrphy_dq_t0),
+	.I(a7ddrphy_dq_o_nodelay0),
+	.T(a7ddrphy_dq_t0),
 	.IO(ddram_dq[0]),
-	.O(main_a7ddrphy_dq_i_nodelay0)
+	.O(a7ddrphy_dq_i_nodelay0)
 );
 
 OSERDESE2 #(
@@ -14273,20 +14716,20 @@ OSERDESE2 #(
 ) OSERDESE2_32 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip12[0]),
-	.D2(main_a7ddrphy_bitslip12[1]),
-	.D3(main_a7ddrphy_bitslip12[2]),
-	.D4(main_a7ddrphy_bitslip12[3]),
-	.D5(main_a7ddrphy_bitslip12[4]),
-	.D6(main_a7ddrphy_bitslip12[5]),
-	.D7(main_a7ddrphy_bitslip12[6]),
-	.D8(main_a7ddrphy_bitslip12[7]),
+	.D1(a7ddrphy_bitslip12[0]),
+	.D2(a7ddrphy_bitslip12[1]),
+	.D3(a7ddrphy_bitslip12[2]),
+	.D4(a7ddrphy_bitslip12[3]),
+	.D5(a7ddrphy_bitslip12[4]),
+	.D6(a7ddrphy_bitslip12[5]),
+	.D7(a7ddrphy_bitslip12[6]),
+	.D8(a7ddrphy_bitslip12[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay1),
-	.TQ(main_a7ddrphy_dq_t1)
+	.OQ(a7ddrphy_dq_o_nodelay1),
+	.TQ(a7ddrphy_dq_t1)
 );
 
 ISERDESE2 #(
@@ -14302,16 +14745,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip13[7]),
-	.Q2(main_a7ddrphy_bitslip13[6]),
-	.Q3(main_a7ddrphy_bitslip13[5]),
-	.Q4(main_a7ddrphy_bitslip13[4]),
-	.Q5(main_a7ddrphy_bitslip13[3]),
-	.Q6(main_a7ddrphy_bitslip13[2]),
-	.Q7(main_a7ddrphy_bitslip13[1]),
-	.Q8(main_a7ddrphy_bitslip13[0])
+	.DDLY(a7ddrphy_dq_i_delayed1),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip13[7]),
+	.Q2(a7ddrphy_bitslip13[6]),
+	.Q3(a7ddrphy_bitslip13[5]),
+	.Q4(a7ddrphy_bitslip13[4]),
+	.Q5(a7ddrphy_bitslip13[3]),
+	.Q6(a7ddrphy_bitslip13[2]),
+	.Q7(a7ddrphy_bitslip13[1]),
+	.Q8(a7ddrphy_bitslip13[0])
 );
 
 IDELAYE2 #(
@@ -14325,19 +14768,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_1 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay1),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay1),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed1)
+	.DATAOUT(a7ddrphy_dq_i_delayed1)
 );
 
 IOBUF IOBUF_1(
-	.I(main_a7ddrphy_dq_o_nodelay1),
-	.T(main_a7ddrphy_dq_t1),
+	.I(a7ddrphy_dq_o_nodelay1),
+	.T(a7ddrphy_dq_t1),
 	.IO(ddram_dq[1]),
-	.O(main_a7ddrphy_dq_i_nodelay1)
+	.O(a7ddrphy_dq_i_nodelay1)
 );
 
 OSERDESE2 #(
@@ -14349,20 +14792,20 @@ OSERDESE2 #(
 ) OSERDESE2_33 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip20[0]),
-	.D2(main_a7ddrphy_bitslip20[1]),
-	.D3(main_a7ddrphy_bitslip20[2]),
-	.D4(main_a7ddrphy_bitslip20[3]),
-	.D5(main_a7ddrphy_bitslip20[4]),
-	.D6(main_a7ddrphy_bitslip20[5]),
-	.D7(main_a7ddrphy_bitslip20[6]),
-	.D8(main_a7ddrphy_bitslip20[7]),
+	.D1(a7ddrphy_bitslip20[0]),
+	.D2(a7ddrphy_bitslip20[1]),
+	.D3(a7ddrphy_bitslip20[2]),
+	.D4(a7ddrphy_bitslip20[3]),
+	.D5(a7ddrphy_bitslip20[4]),
+	.D6(a7ddrphy_bitslip20[5]),
+	.D7(a7ddrphy_bitslip20[6]),
+	.D8(a7ddrphy_bitslip20[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay2),
-	.TQ(main_a7ddrphy_dq_t2)
+	.OQ(a7ddrphy_dq_o_nodelay2),
+	.TQ(a7ddrphy_dq_t2)
 );
 
 ISERDESE2 #(
@@ -14378,16 +14821,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip21[7]),
-	.Q2(main_a7ddrphy_bitslip21[6]),
-	.Q3(main_a7ddrphy_bitslip21[5]),
-	.Q4(main_a7ddrphy_bitslip21[4]),
-	.Q5(main_a7ddrphy_bitslip21[3]),
-	.Q6(main_a7ddrphy_bitslip21[2]),
-	.Q7(main_a7ddrphy_bitslip21[1]),
-	.Q8(main_a7ddrphy_bitslip21[0])
+	.DDLY(a7ddrphy_dq_i_delayed2),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip21[7]),
+	.Q2(a7ddrphy_bitslip21[6]),
+	.Q3(a7ddrphy_bitslip21[5]),
+	.Q4(a7ddrphy_bitslip21[4]),
+	.Q5(a7ddrphy_bitslip21[3]),
+	.Q6(a7ddrphy_bitslip21[2]),
+	.Q7(a7ddrphy_bitslip21[1]),
+	.Q8(a7ddrphy_bitslip21[0])
 );
 
 IDELAYE2 #(
@@ -14401,19 +14844,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay2),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay2),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed2)
+	.DATAOUT(a7ddrphy_dq_i_delayed2)
 );
 
 IOBUF IOBUF_2(
-	.I(main_a7ddrphy_dq_o_nodelay2),
-	.T(main_a7ddrphy_dq_t2),
+	.I(a7ddrphy_dq_o_nodelay2),
+	.T(a7ddrphy_dq_t2),
 	.IO(ddram_dq[2]),
-	.O(main_a7ddrphy_dq_i_nodelay2)
+	.O(a7ddrphy_dq_i_nodelay2)
 );
 
 OSERDESE2 #(
@@ -14425,20 +14868,20 @@ OSERDESE2 #(
 ) OSERDESE2_34 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip30[0]),
-	.D2(main_a7ddrphy_bitslip30[1]),
-	.D3(main_a7ddrphy_bitslip30[2]),
-	.D4(main_a7ddrphy_bitslip30[3]),
-	.D5(main_a7ddrphy_bitslip30[4]),
-	.D6(main_a7ddrphy_bitslip30[5]),
-	.D7(main_a7ddrphy_bitslip30[6]),
-	.D8(main_a7ddrphy_bitslip30[7]),
+	.D1(a7ddrphy_bitslip30[0]),
+	.D2(a7ddrphy_bitslip30[1]),
+	.D3(a7ddrphy_bitslip30[2]),
+	.D4(a7ddrphy_bitslip30[3]),
+	.D5(a7ddrphy_bitslip30[4]),
+	.D6(a7ddrphy_bitslip30[5]),
+	.D7(a7ddrphy_bitslip30[6]),
+	.D8(a7ddrphy_bitslip30[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay3),
-	.TQ(main_a7ddrphy_dq_t3)
+	.OQ(a7ddrphy_dq_o_nodelay3),
+	.TQ(a7ddrphy_dq_t3)
 );
 
 ISERDESE2 #(
@@ -14454,16 +14897,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip31[7]),
-	.Q2(main_a7ddrphy_bitslip31[6]),
-	.Q3(main_a7ddrphy_bitslip31[5]),
-	.Q4(main_a7ddrphy_bitslip31[4]),
-	.Q5(main_a7ddrphy_bitslip31[3]),
-	.Q6(main_a7ddrphy_bitslip31[2]),
-	.Q7(main_a7ddrphy_bitslip31[1]),
-	.Q8(main_a7ddrphy_bitslip31[0])
+	.DDLY(a7ddrphy_dq_i_delayed3),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip31[7]),
+	.Q2(a7ddrphy_bitslip31[6]),
+	.Q3(a7ddrphy_bitslip31[5]),
+	.Q4(a7ddrphy_bitslip31[4]),
+	.Q5(a7ddrphy_bitslip31[3]),
+	.Q6(a7ddrphy_bitslip31[2]),
+	.Q7(a7ddrphy_bitslip31[1]),
+	.Q8(a7ddrphy_bitslip31[0])
 );
 
 IDELAYE2 #(
@@ -14477,19 +14920,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_3 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay3),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay3),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed3)
+	.DATAOUT(a7ddrphy_dq_i_delayed3)
 );
 
 IOBUF IOBUF_3(
-	.I(main_a7ddrphy_dq_o_nodelay3),
-	.T(main_a7ddrphy_dq_t3),
+	.I(a7ddrphy_dq_o_nodelay3),
+	.T(a7ddrphy_dq_t3),
 	.IO(ddram_dq[3]),
-	.O(main_a7ddrphy_dq_i_nodelay3)
+	.O(a7ddrphy_dq_i_nodelay3)
 );
 
 OSERDESE2 #(
@@ -14501,20 +14944,20 @@ OSERDESE2 #(
 ) OSERDESE2_35 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip40[0]),
-	.D2(main_a7ddrphy_bitslip40[1]),
-	.D3(main_a7ddrphy_bitslip40[2]),
-	.D4(main_a7ddrphy_bitslip40[3]),
-	.D5(main_a7ddrphy_bitslip40[4]),
-	.D6(main_a7ddrphy_bitslip40[5]),
-	.D7(main_a7ddrphy_bitslip40[6]),
-	.D8(main_a7ddrphy_bitslip40[7]),
+	.D1(a7ddrphy_bitslip40[0]),
+	.D2(a7ddrphy_bitslip40[1]),
+	.D3(a7ddrphy_bitslip40[2]),
+	.D4(a7ddrphy_bitslip40[3]),
+	.D5(a7ddrphy_bitslip40[4]),
+	.D6(a7ddrphy_bitslip40[5]),
+	.D7(a7ddrphy_bitslip40[6]),
+	.D8(a7ddrphy_bitslip40[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay4),
-	.TQ(main_a7ddrphy_dq_t4)
+	.OQ(a7ddrphy_dq_o_nodelay4),
+	.TQ(a7ddrphy_dq_t4)
 );
 
 ISERDESE2 #(
@@ -14530,16 +14973,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip41[7]),
-	.Q2(main_a7ddrphy_bitslip41[6]),
-	.Q3(main_a7ddrphy_bitslip41[5]),
-	.Q4(main_a7ddrphy_bitslip41[4]),
-	.Q5(main_a7ddrphy_bitslip41[3]),
-	.Q6(main_a7ddrphy_bitslip41[2]),
-	.Q7(main_a7ddrphy_bitslip41[1]),
-	.Q8(main_a7ddrphy_bitslip41[0])
+	.DDLY(a7ddrphy_dq_i_delayed4),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip41[7]),
+	.Q2(a7ddrphy_bitslip41[6]),
+	.Q3(a7ddrphy_bitslip41[5]),
+	.Q4(a7ddrphy_bitslip41[4]),
+	.Q5(a7ddrphy_bitslip41[3]),
+	.Q6(a7ddrphy_bitslip41[2]),
+	.Q7(a7ddrphy_bitslip41[1]),
+	.Q8(a7ddrphy_bitslip41[0])
 );
 
 IDELAYE2 #(
@@ -14553,19 +14996,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_4 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay4),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay4),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed4)
+	.DATAOUT(a7ddrphy_dq_i_delayed4)
 );
 
 IOBUF IOBUF_4(
-	.I(main_a7ddrphy_dq_o_nodelay4),
-	.T(main_a7ddrphy_dq_t4),
+	.I(a7ddrphy_dq_o_nodelay4),
+	.T(a7ddrphy_dq_t4),
 	.IO(ddram_dq[4]),
-	.O(main_a7ddrphy_dq_i_nodelay4)
+	.O(a7ddrphy_dq_i_nodelay4)
 );
 
 OSERDESE2 #(
@@ -14577,20 +15020,20 @@ OSERDESE2 #(
 ) OSERDESE2_36 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip50[0]),
-	.D2(main_a7ddrphy_bitslip50[1]),
-	.D3(main_a7ddrphy_bitslip50[2]),
-	.D4(main_a7ddrphy_bitslip50[3]),
-	.D5(main_a7ddrphy_bitslip50[4]),
-	.D6(main_a7ddrphy_bitslip50[5]),
-	.D7(main_a7ddrphy_bitslip50[6]),
-	.D8(main_a7ddrphy_bitslip50[7]),
+	.D1(a7ddrphy_bitslip50[0]),
+	.D2(a7ddrphy_bitslip50[1]),
+	.D3(a7ddrphy_bitslip50[2]),
+	.D4(a7ddrphy_bitslip50[3]),
+	.D5(a7ddrphy_bitslip50[4]),
+	.D6(a7ddrphy_bitslip50[5]),
+	.D7(a7ddrphy_bitslip50[6]),
+	.D8(a7ddrphy_bitslip50[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay5),
-	.TQ(main_a7ddrphy_dq_t5)
+	.OQ(a7ddrphy_dq_o_nodelay5),
+	.TQ(a7ddrphy_dq_t5)
 );
 
 ISERDESE2 #(
@@ -14606,16 +15049,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip51[7]),
-	.Q2(main_a7ddrphy_bitslip51[6]),
-	.Q3(main_a7ddrphy_bitslip51[5]),
-	.Q4(main_a7ddrphy_bitslip51[4]),
-	.Q5(main_a7ddrphy_bitslip51[3]),
-	.Q6(main_a7ddrphy_bitslip51[2]),
-	.Q7(main_a7ddrphy_bitslip51[1]),
-	.Q8(main_a7ddrphy_bitslip51[0])
+	.DDLY(a7ddrphy_dq_i_delayed5),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip51[7]),
+	.Q2(a7ddrphy_bitslip51[6]),
+	.Q3(a7ddrphy_bitslip51[5]),
+	.Q4(a7ddrphy_bitslip51[4]),
+	.Q5(a7ddrphy_bitslip51[3]),
+	.Q6(a7ddrphy_bitslip51[2]),
+	.Q7(a7ddrphy_bitslip51[1]),
+	.Q8(a7ddrphy_bitslip51[0])
 );
 
 IDELAYE2 #(
@@ -14629,19 +15072,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_5 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay5),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay5),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed5)
+	.DATAOUT(a7ddrphy_dq_i_delayed5)
 );
 
 IOBUF IOBUF_5(
-	.I(main_a7ddrphy_dq_o_nodelay5),
-	.T(main_a7ddrphy_dq_t5),
+	.I(a7ddrphy_dq_o_nodelay5),
+	.T(a7ddrphy_dq_t5),
 	.IO(ddram_dq[5]),
-	.O(main_a7ddrphy_dq_i_nodelay5)
+	.O(a7ddrphy_dq_i_nodelay5)
 );
 
 OSERDESE2 #(
@@ -14653,20 +15096,20 @@ OSERDESE2 #(
 ) OSERDESE2_37 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip60[0]),
-	.D2(main_a7ddrphy_bitslip60[1]),
-	.D3(main_a7ddrphy_bitslip60[2]),
-	.D4(main_a7ddrphy_bitslip60[3]),
-	.D5(main_a7ddrphy_bitslip60[4]),
-	.D6(main_a7ddrphy_bitslip60[5]),
-	.D7(main_a7ddrphy_bitslip60[6]),
-	.D8(main_a7ddrphy_bitslip60[7]),
+	.D1(a7ddrphy_bitslip60[0]),
+	.D2(a7ddrphy_bitslip60[1]),
+	.D3(a7ddrphy_bitslip60[2]),
+	.D4(a7ddrphy_bitslip60[3]),
+	.D5(a7ddrphy_bitslip60[4]),
+	.D6(a7ddrphy_bitslip60[5]),
+	.D7(a7ddrphy_bitslip60[6]),
+	.D8(a7ddrphy_bitslip60[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay6),
-	.TQ(main_a7ddrphy_dq_t6)
+	.OQ(a7ddrphy_dq_o_nodelay6),
+	.TQ(a7ddrphy_dq_t6)
 );
 
 ISERDESE2 #(
@@ -14682,16 +15125,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip61[7]),
-	.Q2(main_a7ddrphy_bitslip61[6]),
-	.Q3(main_a7ddrphy_bitslip61[5]),
-	.Q4(main_a7ddrphy_bitslip61[4]),
-	.Q5(main_a7ddrphy_bitslip61[3]),
-	.Q6(main_a7ddrphy_bitslip61[2]),
-	.Q7(main_a7ddrphy_bitslip61[1]),
-	.Q8(main_a7ddrphy_bitslip61[0])
+	.DDLY(a7ddrphy_dq_i_delayed6),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip61[7]),
+	.Q2(a7ddrphy_bitslip61[6]),
+	.Q3(a7ddrphy_bitslip61[5]),
+	.Q4(a7ddrphy_bitslip61[4]),
+	.Q5(a7ddrphy_bitslip61[3]),
+	.Q6(a7ddrphy_bitslip61[2]),
+	.Q7(a7ddrphy_bitslip61[1]),
+	.Q8(a7ddrphy_bitslip61[0])
 );
 
 IDELAYE2 #(
@@ -14705,19 +15148,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_6 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay6),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay6),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed6)
+	.DATAOUT(a7ddrphy_dq_i_delayed6)
 );
 
 IOBUF IOBUF_6(
-	.I(main_a7ddrphy_dq_o_nodelay6),
-	.T(main_a7ddrphy_dq_t6),
+	.I(a7ddrphy_dq_o_nodelay6),
+	.T(a7ddrphy_dq_t6),
 	.IO(ddram_dq[6]),
-	.O(main_a7ddrphy_dq_i_nodelay6)
+	.O(a7ddrphy_dq_i_nodelay6)
 );
 
 OSERDESE2 #(
@@ -14729,20 +15172,20 @@ OSERDESE2 #(
 ) OSERDESE2_38 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip70[0]),
-	.D2(main_a7ddrphy_bitslip70[1]),
-	.D3(main_a7ddrphy_bitslip70[2]),
-	.D4(main_a7ddrphy_bitslip70[3]),
-	.D5(main_a7ddrphy_bitslip70[4]),
-	.D6(main_a7ddrphy_bitslip70[5]),
-	.D7(main_a7ddrphy_bitslip70[6]),
-	.D8(main_a7ddrphy_bitslip70[7]),
+	.D1(a7ddrphy_bitslip70[0]),
+	.D2(a7ddrphy_bitslip70[1]),
+	.D3(a7ddrphy_bitslip70[2]),
+	.D4(a7ddrphy_bitslip70[3]),
+	.D5(a7ddrphy_bitslip70[4]),
+	.D6(a7ddrphy_bitslip70[5]),
+	.D7(a7ddrphy_bitslip70[6]),
+	.D8(a7ddrphy_bitslip70[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay7),
-	.TQ(main_a7ddrphy_dq_t7)
+	.OQ(a7ddrphy_dq_o_nodelay7),
+	.TQ(a7ddrphy_dq_t7)
 );
 
 ISERDESE2 #(
@@ -14758,16 +15201,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip71[7]),
-	.Q2(main_a7ddrphy_bitslip71[6]),
-	.Q3(main_a7ddrphy_bitslip71[5]),
-	.Q4(main_a7ddrphy_bitslip71[4]),
-	.Q5(main_a7ddrphy_bitslip71[3]),
-	.Q6(main_a7ddrphy_bitslip71[2]),
-	.Q7(main_a7ddrphy_bitslip71[1]),
-	.Q8(main_a7ddrphy_bitslip71[0])
+	.DDLY(a7ddrphy_dq_i_delayed7),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip71[7]),
+	.Q2(a7ddrphy_bitslip71[6]),
+	.Q3(a7ddrphy_bitslip71[5]),
+	.Q4(a7ddrphy_bitslip71[4]),
+	.Q5(a7ddrphy_bitslip71[3]),
+	.Q6(a7ddrphy_bitslip71[2]),
+	.Q7(a7ddrphy_bitslip71[1]),
+	.Q8(a7ddrphy_bitslip71[0])
 );
 
 IDELAYE2 #(
@@ -14781,19 +15224,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_7 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay7),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay7),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed7)
+	.DATAOUT(a7ddrphy_dq_i_delayed7)
 );
 
 IOBUF IOBUF_7(
-	.I(main_a7ddrphy_dq_o_nodelay7),
-	.T(main_a7ddrphy_dq_t7),
+	.I(a7ddrphy_dq_o_nodelay7),
+	.T(a7ddrphy_dq_t7),
 	.IO(ddram_dq[7]),
-	.O(main_a7ddrphy_dq_i_nodelay7)
+	.O(a7ddrphy_dq_i_nodelay7)
 );
 
 OSERDESE2 #(
@@ -14805,20 +15248,20 @@ OSERDESE2 #(
 ) OSERDESE2_39 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip80[0]),
-	.D2(main_a7ddrphy_bitslip80[1]),
-	.D3(main_a7ddrphy_bitslip80[2]),
-	.D4(main_a7ddrphy_bitslip80[3]),
-	.D5(main_a7ddrphy_bitslip80[4]),
-	.D6(main_a7ddrphy_bitslip80[5]),
-	.D7(main_a7ddrphy_bitslip80[6]),
-	.D8(main_a7ddrphy_bitslip80[7]),
+	.D1(a7ddrphy_bitslip80[0]),
+	.D2(a7ddrphy_bitslip80[1]),
+	.D3(a7ddrphy_bitslip80[2]),
+	.D4(a7ddrphy_bitslip80[3]),
+	.D5(a7ddrphy_bitslip80[4]),
+	.D6(a7ddrphy_bitslip80[5]),
+	.D7(a7ddrphy_bitslip80[6]),
+	.D8(a7ddrphy_bitslip80[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay8),
-	.TQ(main_a7ddrphy_dq_t8)
+	.OQ(a7ddrphy_dq_o_nodelay8),
+	.TQ(a7ddrphy_dq_t8)
 );
 
 ISERDESE2 #(
@@ -14834,16 +15277,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip81[7]),
-	.Q2(main_a7ddrphy_bitslip81[6]),
-	.Q3(main_a7ddrphy_bitslip81[5]),
-	.Q4(main_a7ddrphy_bitslip81[4]),
-	.Q5(main_a7ddrphy_bitslip81[3]),
-	.Q6(main_a7ddrphy_bitslip81[2]),
-	.Q7(main_a7ddrphy_bitslip81[1]),
-	.Q8(main_a7ddrphy_bitslip81[0])
+	.DDLY(a7ddrphy_dq_i_delayed8),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip81[7]),
+	.Q2(a7ddrphy_bitslip81[6]),
+	.Q3(a7ddrphy_bitslip81[5]),
+	.Q4(a7ddrphy_bitslip81[4]),
+	.Q5(a7ddrphy_bitslip81[3]),
+	.Q6(a7ddrphy_bitslip81[2]),
+	.Q7(a7ddrphy_bitslip81[1]),
+	.Q8(a7ddrphy_bitslip81[0])
 );
 
 IDELAYE2 #(
@@ -14857,19 +15300,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_8 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay8),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay8),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed8)
+	.DATAOUT(a7ddrphy_dq_i_delayed8)
 );
 
 IOBUF IOBUF_8(
-	.I(main_a7ddrphy_dq_o_nodelay8),
-	.T(main_a7ddrphy_dq_t8),
+	.I(a7ddrphy_dq_o_nodelay8),
+	.T(a7ddrphy_dq_t8),
 	.IO(ddram_dq[8]),
-	.O(main_a7ddrphy_dq_i_nodelay8)
+	.O(a7ddrphy_dq_i_nodelay8)
 );
 
 OSERDESE2 #(
@@ -14881,20 +15324,20 @@ OSERDESE2 #(
 ) OSERDESE2_40 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip90[0]),
-	.D2(main_a7ddrphy_bitslip90[1]),
-	.D3(main_a7ddrphy_bitslip90[2]),
-	.D4(main_a7ddrphy_bitslip90[3]),
-	.D5(main_a7ddrphy_bitslip90[4]),
-	.D6(main_a7ddrphy_bitslip90[5]),
-	.D7(main_a7ddrphy_bitslip90[6]),
-	.D8(main_a7ddrphy_bitslip90[7]),
+	.D1(a7ddrphy_bitslip90[0]),
+	.D2(a7ddrphy_bitslip90[1]),
+	.D3(a7ddrphy_bitslip90[2]),
+	.D4(a7ddrphy_bitslip90[3]),
+	.D5(a7ddrphy_bitslip90[4]),
+	.D6(a7ddrphy_bitslip90[5]),
+	.D7(a7ddrphy_bitslip90[6]),
+	.D8(a7ddrphy_bitslip90[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay9),
-	.TQ(main_a7ddrphy_dq_t9)
+	.OQ(a7ddrphy_dq_o_nodelay9),
+	.TQ(a7ddrphy_dq_t9)
 );
 
 ISERDESE2 #(
@@ -14910,16 +15353,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip91[7]),
-	.Q2(main_a7ddrphy_bitslip91[6]),
-	.Q3(main_a7ddrphy_bitslip91[5]),
-	.Q4(main_a7ddrphy_bitslip91[4]),
-	.Q5(main_a7ddrphy_bitslip91[3]),
-	.Q6(main_a7ddrphy_bitslip91[2]),
-	.Q7(main_a7ddrphy_bitslip91[1]),
-	.Q8(main_a7ddrphy_bitslip91[0])
+	.DDLY(a7ddrphy_dq_i_delayed9),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip91[7]),
+	.Q2(a7ddrphy_bitslip91[6]),
+	.Q3(a7ddrphy_bitslip91[5]),
+	.Q4(a7ddrphy_bitslip91[4]),
+	.Q5(a7ddrphy_bitslip91[3]),
+	.Q6(a7ddrphy_bitslip91[2]),
+	.Q7(a7ddrphy_bitslip91[1]),
+	.Q8(a7ddrphy_bitslip91[0])
 );
 
 IDELAYE2 #(
@@ -14933,19 +15376,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_9 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay9),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay9),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed9)
+	.DATAOUT(a7ddrphy_dq_i_delayed9)
 );
 
 IOBUF IOBUF_9(
-	.I(main_a7ddrphy_dq_o_nodelay9),
-	.T(main_a7ddrphy_dq_t9),
+	.I(a7ddrphy_dq_o_nodelay9),
+	.T(a7ddrphy_dq_t9),
 	.IO(ddram_dq[9]),
-	.O(main_a7ddrphy_dq_i_nodelay9)
+	.O(a7ddrphy_dq_i_nodelay9)
 );
 
 OSERDESE2 #(
@@ -14957,20 +15400,20 @@ OSERDESE2 #(
 ) OSERDESE2_41 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip100[0]),
-	.D2(main_a7ddrphy_bitslip100[1]),
-	.D3(main_a7ddrphy_bitslip100[2]),
-	.D4(main_a7ddrphy_bitslip100[3]),
-	.D5(main_a7ddrphy_bitslip100[4]),
-	.D6(main_a7ddrphy_bitslip100[5]),
-	.D7(main_a7ddrphy_bitslip100[6]),
-	.D8(main_a7ddrphy_bitslip100[7]),
+	.D1(a7ddrphy_bitslip100[0]),
+	.D2(a7ddrphy_bitslip100[1]),
+	.D3(a7ddrphy_bitslip100[2]),
+	.D4(a7ddrphy_bitslip100[3]),
+	.D5(a7ddrphy_bitslip100[4]),
+	.D6(a7ddrphy_bitslip100[5]),
+	.D7(a7ddrphy_bitslip100[6]),
+	.D8(a7ddrphy_bitslip100[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay10),
-	.TQ(main_a7ddrphy_dq_t10)
+	.OQ(a7ddrphy_dq_o_nodelay10),
+	.TQ(a7ddrphy_dq_t10)
 );
 
 ISERDESE2 #(
@@ -14986,16 +15429,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip101[7]),
-	.Q2(main_a7ddrphy_bitslip101[6]),
-	.Q3(main_a7ddrphy_bitslip101[5]),
-	.Q4(main_a7ddrphy_bitslip101[4]),
-	.Q5(main_a7ddrphy_bitslip101[3]),
-	.Q6(main_a7ddrphy_bitslip101[2]),
-	.Q7(main_a7ddrphy_bitslip101[1]),
-	.Q8(main_a7ddrphy_bitslip101[0])
+	.DDLY(a7ddrphy_dq_i_delayed10),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip101[7]),
+	.Q2(a7ddrphy_bitslip101[6]),
+	.Q3(a7ddrphy_bitslip101[5]),
+	.Q4(a7ddrphy_bitslip101[4]),
+	.Q5(a7ddrphy_bitslip101[3]),
+	.Q6(a7ddrphy_bitslip101[2]),
+	.Q7(a7ddrphy_bitslip101[1]),
+	.Q8(a7ddrphy_bitslip101[0])
 );
 
 IDELAYE2 #(
@@ -15009,19 +15452,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_10 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay10),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay10),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed10)
+	.DATAOUT(a7ddrphy_dq_i_delayed10)
 );
 
 IOBUF IOBUF_10(
-	.I(main_a7ddrphy_dq_o_nodelay10),
-	.T(main_a7ddrphy_dq_t10),
+	.I(a7ddrphy_dq_o_nodelay10),
+	.T(a7ddrphy_dq_t10),
 	.IO(ddram_dq[10]),
-	.O(main_a7ddrphy_dq_i_nodelay10)
+	.O(a7ddrphy_dq_i_nodelay10)
 );
 
 OSERDESE2 #(
@@ -15033,20 +15476,20 @@ OSERDESE2 #(
 ) OSERDESE2_42 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip110[0]),
-	.D2(main_a7ddrphy_bitslip110[1]),
-	.D3(main_a7ddrphy_bitslip110[2]),
-	.D4(main_a7ddrphy_bitslip110[3]),
-	.D5(main_a7ddrphy_bitslip110[4]),
-	.D6(main_a7ddrphy_bitslip110[5]),
-	.D7(main_a7ddrphy_bitslip110[6]),
-	.D8(main_a7ddrphy_bitslip110[7]),
+	.D1(a7ddrphy_bitslip110[0]),
+	.D2(a7ddrphy_bitslip110[1]),
+	.D3(a7ddrphy_bitslip110[2]),
+	.D4(a7ddrphy_bitslip110[3]),
+	.D5(a7ddrphy_bitslip110[4]),
+	.D6(a7ddrphy_bitslip110[5]),
+	.D7(a7ddrphy_bitslip110[6]),
+	.D8(a7ddrphy_bitslip110[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay11),
-	.TQ(main_a7ddrphy_dq_t11)
+	.OQ(a7ddrphy_dq_o_nodelay11),
+	.TQ(a7ddrphy_dq_t11)
 );
 
 ISERDESE2 #(
@@ -15062,16 +15505,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip111[7]),
-	.Q2(main_a7ddrphy_bitslip111[6]),
-	.Q3(main_a7ddrphy_bitslip111[5]),
-	.Q4(main_a7ddrphy_bitslip111[4]),
-	.Q5(main_a7ddrphy_bitslip111[3]),
-	.Q6(main_a7ddrphy_bitslip111[2]),
-	.Q7(main_a7ddrphy_bitslip111[1]),
-	.Q8(main_a7ddrphy_bitslip111[0])
+	.DDLY(a7ddrphy_dq_i_delayed11),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip111[7]),
+	.Q2(a7ddrphy_bitslip111[6]),
+	.Q3(a7ddrphy_bitslip111[5]),
+	.Q4(a7ddrphy_bitslip111[4]),
+	.Q5(a7ddrphy_bitslip111[3]),
+	.Q6(a7ddrphy_bitslip111[2]),
+	.Q7(a7ddrphy_bitslip111[1]),
+	.Q8(a7ddrphy_bitslip111[0])
 );
 
 IDELAYE2 #(
@@ -15085,19 +15528,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_11 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay11),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay11),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed11)
+	.DATAOUT(a7ddrphy_dq_i_delayed11)
 );
 
 IOBUF IOBUF_11(
-	.I(main_a7ddrphy_dq_o_nodelay11),
-	.T(main_a7ddrphy_dq_t11),
+	.I(a7ddrphy_dq_o_nodelay11),
+	.T(a7ddrphy_dq_t11),
 	.IO(ddram_dq[11]),
-	.O(main_a7ddrphy_dq_i_nodelay11)
+	.O(a7ddrphy_dq_i_nodelay11)
 );
 
 OSERDESE2 #(
@@ -15109,20 +15552,20 @@ OSERDESE2 #(
 ) OSERDESE2_43 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip120[0]),
-	.D2(main_a7ddrphy_bitslip120[1]),
-	.D3(main_a7ddrphy_bitslip120[2]),
-	.D4(main_a7ddrphy_bitslip120[3]),
-	.D5(main_a7ddrphy_bitslip120[4]),
-	.D6(main_a7ddrphy_bitslip120[5]),
-	.D7(main_a7ddrphy_bitslip120[6]),
-	.D8(main_a7ddrphy_bitslip120[7]),
+	.D1(a7ddrphy_bitslip120[0]),
+	.D2(a7ddrphy_bitslip120[1]),
+	.D3(a7ddrphy_bitslip120[2]),
+	.D4(a7ddrphy_bitslip120[3]),
+	.D5(a7ddrphy_bitslip120[4]),
+	.D6(a7ddrphy_bitslip120[5]),
+	.D7(a7ddrphy_bitslip120[6]),
+	.D8(a7ddrphy_bitslip120[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay12),
-	.TQ(main_a7ddrphy_dq_t12)
+	.OQ(a7ddrphy_dq_o_nodelay12),
+	.TQ(a7ddrphy_dq_t12)
 );
 
 ISERDESE2 #(
@@ -15138,16 +15581,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip121[7]),
-	.Q2(main_a7ddrphy_bitslip121[6]),
-	.Q3(main_a7ddrphy_bitslip121[5]),
-	.Q4(main_a7ddrphy_bitslip121[4]),
-	.Q5(main_a7ddrphy_bitslip121[3]),
-	.Q6(main_a7ddrphy_bitslip121[2]),
-	.Q7(main_a7ddrphy_bitslip121[1]),
-	.Q8(main_a7ddrphy_bitslip121[0])
+	.DDLY(a7ddrphy_dq_i_delayed12),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip121[7]),
+	.Q2(a7ddrphy_bitslip121[6]),
+	.Q3(a7ddrphy_bitslip121[5]),
+	.Q4(a7ddrphy_bitslip121[4]),
+	.Q5(a7ddrphy_bitslip121[3]),
+	.Q6(a7ddrphy_bitslip121[2]),
+	.Q7(a7ddrphy_bitslip121[1]),
+	.Q8(a7ddrphy_bitslip121[0])
 );
 
 IDELAYE2 #(
@@ -15161,19 +15604,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_12 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay12),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay12),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed12)
+	.DATAOUT(a7ddrphy_dq_i_delayed12)
 );
 
 IOBUF IOBUF_12(
-	.I(main_a7ddrphy_dq_o_nodelay12),
-	.T(main_a7ddrphy_dq_t12),
+	.I(a7ddrphy_dq_o_nodelay12),
+	.T(a7ddrphy_dq_t12),
 	.IO(ddram_dq[12]),
-	.O(main_a7ddrphy_dq_i_nodelay12)
+	.O(a7ddrphy_dq_i_nodelay12)
 );
 
 OSERDESE2 #(
@@ -15185,20 +15628,20 @@ OSERDESE2 #(
 ) OSERDESE2_44 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip130[0]),
-	.D2(main_a7ddrphy_bitslip130[1]),
-	.D3(main_a7ddrphy_bitslip130[2]),
-	.D4(main_a7ddrphy_bitslip130[3]),
-	.D5(main_a7ddrphy_bitslip130[4]),
-	.D6(main_a7ddrphy_bitslip130[5]),
-	.D7(main_a7ddrphy_bitslip130[6]),
-	.D8(main_a7ddrphy_bitslip130[7]),
+	.D1(a7ddrphy_bitslip130[0]),
+	.D2(a7ddrphy_bitslip130[1]),
+	.D3(a7ddrphy_bitslip130[2]),
+	.D4(a7ddrphy_bitslip130[3]),
+	.D5(a7ddrphy_bitslip130[4]),
+	.D6(a7ddrphy_bitslip130[5]),
+	.D7(a7ddrphy_bitslip130[6]),
+	.D8(a7ddrphy_bitslip130[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay13),
-	.TQ(main_a7ddrphy_dq_t13)
+	.OQ(a7ddrphy_dq_o_nodelay13),
+	.TQ(a7ddrphy_dq_t13)
 );
 
 ISERDESE2 #(
@@ -15214,16 +15657,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip131[7]),
-	.Q2(main_a7ddrphy_bitslip131[6]),
-	.Q3(main_a7ddrphy_bitslip131[5]),
-	.Q4(main_a7ddrphy_bitslip131[4]),
-	.Q5(main_a7ddrphy_bitslip131[3]),
-	.Q6(main_a7ddrphy_bitslip131[2]),
-	.Q7(main_a7ddrphy_bitslip131[1]),
-	.Q8(main_a7ddrphy_bitslip131[0])
+	.DDLY(a7ddrphy_dq_i_delayed13),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip131[7]),
+	.Q2(a7ddrphy_bitslip131[6]),
+	.Q3(a7ddrphy_bitslip131[5]),
+	.Q4(a7ddrphy_bitslip131[4]),
+	.Q5(a7ddrphy_bitslip131[3]),
+	.Q6(a7ddrphy_bitslip131[2]),
+	.Q7(a7ddrphy_bitslip131[1]),
+	.Q8(a7ddrphy_bitslip131[0])
 );
 
 IDELAYE2 #(
@@ -15237,19 +15680,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_13 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay13),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay13),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed13)
+	.DATAOUT(a7ddrphy_dq_i_delayed13)
 );
 
 IOBUF IOBUF_13(
-	.I(main_a7ddrphy_dq_o_nodelay13),
-	.T(main_a7ddrphy_dq_t13),
+	.I(a7ddrphy_dq_o_nodelay13),
+	.T(a7ddrphy_dq_t13),
 	.IO(ddram_dq[13]),
-	.O(main_a7ddrphy_dq_i_nodelay13)
+	.O(a7ddrphy_dq_i_nodelay13)
 );
 
 OSERDESE2 #(
@@ -15261,20 +15704,20 @@ OSERDESE2 #(
 ) OSERDESE2_45 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip140[0]),
-	.D2(main_a7ddrphy_bitslip140[1]),
-	.D3(main_a7ddrphy_bitslip140[2]),
-	.D4(main_a7ddrphy_bitslip140[3]),
-	.D5(main_a7ddrphy_bitslip140[4]),
-	.D6(main_a7ddrphy_bitslip140[5]),
-	.D7(main_a7ddrphy_bitslip140[6]),
-	.D8(main_a7ddrphy_bitslip140[7]),
+	.D1(a7ddrphy_bitslip140[0]),
+	.D2(a7ddrphy_bitslip140[1]),
+	.D3(a7ddrphy_bitslip140[2]),
+	.D4(a7ddrphy_bitslip140[3]),
+	.D5(a7ddrphy_bitslip140[4]),
+	.D6(a7ddrphy_bitslip140[5]),
+	.D7(a7ddrphy_bitslip140[6]),
+	.D8(a7ddrphy_bitslip140[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay14),
-	.TQ(main_a7ddrphy_dq_t14)
+	.OQ(a7ddrphy_dq_o_nodelay14),
+	.TQ(a7ddrphy_dq_t14)
 );
 
 ISERDESE2 #(
@@ -15290,16 +15733,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip141[7]),
-	.Q2(main_a7ddrphy_bitslip141[6]),
-	.Q3(main_a7ddrphy_bitslip141[5]),
-	.Q4(main_a7ddrphy_bitslip141[4]),
-	.Q5(main_a7ddrphy_bitslip141[3]),
-	.Q6(main_a7ddrphy_bitslip141[2]),
-	.Q7(main_a7ddrphy_bitslip141[1]),
-	.Q8(main_a7ddrphy_bitslip141[0])
+	.DDLY(a7ddrphy_dq_i_delayed14),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip141[7]),
+	.Q2(a7ddrphy_bitslip141[6]),
+	.Q3(a7ddrphy_bitslip141[5]),
+	.Q4(a7ddrphy_bitslip141[4]),
+	.Q5(a7ddrphy_bitslip141[3]),
+	.Q6(a7ddrphy_bitslip141[2]),
+	.Q7(a7ddrphy_bitslip141[1]),
+	.Q8(a7ddrphy_bitslip141[0])
 );
 
 IDELAYE2 #(
@@ -15313,19 +15756,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_14 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay14),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay14),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed14)
+	.DATAOUT(a7ddrphy_dq_i_delayed14)
 );
 
 IOBUF IOBUF_14(
-	.I(main_a7ddrphy_dq_o_nodelay14),
-	.T(main_a7ddrphy_dq_t14),
+	.I(a7ddrphy_dq_o_nodelay14),
+	.T(a7ddrphy_dq_t14),
 	.IO(ddram_dq[14]),
-	.O(main_a7ddrphy_dq_i_nodelay14)
+	.O(a7ddrphy_dq_i_nodelay14)
 );
 
 OSERDESE2 #(
@@ -15337,20 +15780,20 @@ OSERDESE2 #(
 ) OSERDESE2_46 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip150[0]),
-	.D2(main_a7ddrphy_bitslip150[1]),
-	.D3(main_a7ddrphy_bitslip150[2]),
-	.D4(main_a7ddrphy_bitslip150[3]),
-	.D5(main_a7ddrphy_bitslip150[4]),
-	.D6(main_a7ddrphy_bitslip150[5]),
-	.D7(main_a7ddrphy_bitslip150[6]),
-	.D8(main_a7ddrphy_bitslip150[7]),
+	.D1(a7ddrphy_bitslip150[0]),
+	.D2(a7ddrphy_bitslip150[1]),
+	.D3(a7ddrphy_bitslip150[2]),
+	.D4(a7ddrphy_bitslip150[3]),
+	.D5(a7ddrphy_bitslip150[4]),
+	.D6(a7ddrphy_bitslip150[5]),
+	.D7(a7ddrphy_bitslip150[6]),
+	.D8(a7ddrphy_bitslip150[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay15),
-	.TQ(main_a7ddrphy_dq_t15)
+	.OQ(a7ddrphy_dq_o_nodelay15),
+	.TQ(a7ddrphy_dq_t15)
 );
 
 ISERDESE2 #(
@@ -15366,16 +15809,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip151[7]),
-	.Q2(main_a7ddrphy_bitslip151[6]),
-	.Q3(main_a7ddrphy_bitslip151[5]),
-	.Q4(main_a7ddrphy_bitslip151[4]),
-	.Q5(main_a7ddrphy_bitslip151[3]),
-	.Q6(main_a7ddrphy_bitslip151[2]),
-	.Q7(main_a7ddrphy_bitslip151[1]),
-	.Q8(main_a7ddrphy_bitslip151[0])
+	.DDLY(a7ddrphy_dq_i_delayed15),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip151[7]),
+	.Q2(a7ddrphy_bitslip151[6]),
+	.Q3(a7ddrphy_bitslip151[5]),
+	.Q4(a7ddrphy_bitslip151[4]),
+	.Q5(a7ddrphy_bitslip151[3]),
+	.Q6(a7ddrphy_bitslip151[2]),
+	.Q7(a7ddrphy_bitslip151[1]),
+	.Q8(a7ddrphy_bitslip151[0])
 );
 
 IDELAYE2 #(
@@ -15389,19 +15832,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_15 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay15),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay15),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed15)
+	.DATAOUT(a7ddrphy_dq_i_delayed15)
 );
 
 IOBUF IOBUF_15(
-	.I(main_a7ddrphy_dq_o_nodelay15),
-	.T(main_a7ddrphy_dq_t15),
+	.I(a7ddrphy_dq_o_nodelay15),
+	.T(a7ddrphy_dq_t15),
 	.IO(ddram_dq[15]),
-	.O(main_a7ddrphy_dq_i_nodelay15)
+	.O(a7ddrphy_dq_i_nodelay15)
 );
 
 //------------------------------------------------------------------------------
@@ -15412,14 +15855,14 @@ IOBUF IOBUF_15(
 reg [25:0] storage[0:15];
 reg [25:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
-		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+		storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+	storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15430,14 +15873,14 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [25:0] storage_1[0:15];
 reg [25:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
-		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+		storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15448,14 +15891,14 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [25:0] storage_2[0:15];
 reg [25:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
-		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+		storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15466,14 +15909,14 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [25:0] storage_3[0:15];
 reg [25:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
-		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+		storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15484,14 +15927,14 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [25:0] storage_4[0:15];
 reg [25:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
-		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+		storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15502,14 +15945,14 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [25:0] storage_5[0:15];
 reg [25:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
-		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+		storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15520,14 +15963,14 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [25:0] storage_6[0:15];
 reg [25:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
-		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+		storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15538,62 +15981,78 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [25:0] storage_7[0:15];
 reg [25:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
-		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+		storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
 
-FD FD(
-	.C(main_clkin),
-	.D(main_reset),
-	.Q(builder_reset0)
+FDCE FDCE(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(reset),
+	.Q(litedramcore_reset0)
 );
 
-FD FD_1(
-	.C(main_clkin),
-	.D(builder_reset0),
-	.Q(builder_reset1)
+FDCE FDCE_1(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset0),
+	.Q(litedramcore_reset1)
 );
 
-FD FD_2(
-	.C(main_clkin),
-	.D(builder_reset1),
-	.Q(builder_reset2)
+FDCE FDCE_2(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset1),
+	.Q(litedramcore_reset2)
 );
 
-FD FD_3(
-	.C(main_clkin),
-	.D(builder_reset2),
-	.Q(builder_reset3)
+FDCE FDCE_3(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset2),
+	.Q(litedramcore_reset3)
 );
 
-FD FD_4(
-	.C(main_clkin),
-	.D(builder_reset3),
-	.Q(builder_reset4)
+FDCE FDCE_4(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset3),
+	.Q(litedramcore_reset4)
 );
 
-FD FD_5(
-	.C(main_clkin),
-	.D(builder_reset4),
-	.Q(builder_reset5)
+FDCE FDCE_5(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset4),
+	.Q(litedramcore_reset5)
 );
 
-FD FD_6(
-	.C(main_clkin),
-	.D(builder_reset5),
-	.Q(builder_reset6)
+FDCE FDCE_6(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset5),
+	.Q(litedramcore_reset6)
 );
 
-FD FD_7(
-	.C(main_clkin),
-	.D(builder_reset6),
-	.Q(builder_reset7)
+FDCE FDCE_7(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset6),
+	.Q(litedramcore_reset7)
 );
 
 PLLE2_ADV #(
@@ -15611,16 +16070,16 @@ PLLE2_ADV #(
 	.REF_JITTER1(0.01),
 	.STARTUP_WAIT("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(builder_pll_fb),
-	.CLKIN1(main_clkin),
-	.PWRDWN(main_power_down),
-	.RST(builder_reset7),
-	.CLKFBOUT(builder_pll_fb),
-	.CLKOUT0(main_clkout0),
-	.CLKOUT1(main_clkout1),
-	.CLKOUT2(main_clkout2),
-	.CLKOUT3(main_clkout3),
-	.LOCKED(main_locked)
+	.CLKFBIN(litedramcore_pll_fb),
+	.CLKIN1(clkin),
+	.PWRDWN(power_down),
+	.RST(litedramcore_reset7),
+	.CLKFBOUT(litedramcore_pll_fb),
+	.CLKOUT0(clkout0),
+	.CLKOUT1(clkout1),
+	.CLKOUT2(clkout2),
+	.CLKOUT3(clkout3),
+	.LOCKED(locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15629,8 +16088,8 @@ PLLE2_ADV #(
 	.C(iodelay_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
-	.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl0),
+	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15638,8 +16097,8 @@ PLLE2_ADV #(
 ) FDPE_1 (
 	.C(iodelay_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
+	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl0),
 	.Q(iodelay_rst)
 );
 
@@ -15649,8 +16108,8 @@ PLLE2_ADV #(
 	.C(sys_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
-	.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl1),
+	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15658,8 +16117,8 @@ PLLE2_ADV #(
 ) FDPE_3 (
 	.C(sys_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
+	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl1),
 	.Q(sys_rst)
 );
 
@@ -15669,8 +16128,8 @@ PLLE2_ADV #(
 	.C(sys4x_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15678,9 +16137,9 @@ PLLE2_ADV #(
 ) FDPE_5 (
 	.C(sys4x_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_expr)
+	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15689,8 +16148,8 @@ PLLE2_ADV #(
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15698,13 +16157,13 @@ PLLE2_ADV #(
 ) FDPE_7 (
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_expr)
+	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-01-14 08:32:13.
+//  Auto-Generated by LiteX on 2022-08-04 21:07:00.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init
index 1b6e88e..9006b18 100644
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10e0658cff00
+618c10d8658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -519,213 +519,215 @@ a64b5a7d14004a39
 0000000000000000
 3c4c000100000000
 7c0802a63842adc4
-fbe1fff8fbc1fff0
-f821ff51f8010010
-f88100d83bc10020
+f8010010fbe1fff8
+f88100d8f821ff51
 38800080f8a100e0
 f8c100e87c651b78
-38c100d87fc3f378
+38c100d838610020
 f90100f8f8e100f0
 f9410108f9210100
-6000000048002159
-7fc3f3787c7f1b78
-6000000048001b7d
+6000000048002135
+386100207c7f1b78
+6000000048001b4d
 7fe3fb78382100b0
-00000000480027d4
-0000028001000000
+000000004800283c
+0000018001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842ad203c4c0001
-7d8000267c0802a6
-9181000848002711
-48001b79f821fed1
+3842ad283c4c0001
+7d6000267c0802a6
+9161000848002775
+48001b49f821fed1
 3c62ffff60000000
-4bffff3938637a90
+4bffff4138637af0
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637ab0
-3c62ffff4bffff15
-38637ad07bff0020
-7c0004ac4bffff05
+63ff000838637b10
+3c62ffff4bffff1d
+38637b307bff0020
+7c0004ac4bffff0d
 73e900017fe0feea
 3c62ffff41820010
-4bfffee938637ae8
-4e00000073e90002
+4bfffef138637b48
+4d80000073e90002
 3c62ffff41820010
-4bfffed138637af0
-4d80000073e90004
+4bfffed938637b50
+4e00000073e90004
 3c62ffff41820010
-4bfffeb938637af8
+4bfffec138637b58
 4d00000073e90008
 3c62ffff41820010
-4bfffea138637b00
+4bfffea938637b60
 4182001073e90010
-38637b103c62ffff
-73ff01004bfffe8d
+38637b703c62ffff
+73ff01004bfffe95
 3c62ffff41820010
-4bfffe7938637b20
-3b7b7b283f62ffff
-4bfffe697f63db78
-3c80c000418e0028
+4bfffe8138637b80
+3b7b7b883f62ffff
+4bfffe717f63db78
+3c80c00041920028
 7884002060840010
 7c8026ea7c0004ac
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diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index cad0120..593bee2 100644
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-01-14 08:32:09
+// LiteX sha1 : 6932fc51
+// Date       : 2022-08-04 21:06:55
 //------------------------------------------------------------------------------
 
 
@@ -69,4263 +69,4682 @@ module litedram_core (
 // Signals
 //------------------------------------------------------------------------------
 
-reg  main_rst = 1'd0;
+reg  rst_1 = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
 wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
-wire main_reset;
-reg  main_power_down = 1'd0;
-wire main_locked;
-wire main_clkin;
-wire main_clkout0;
-wire main_clkout_buf0;
-wire main_clkout1;
-wire main_clkout_buf1;
-wire main_clkout2;
-wire main_clkout_buf2;
-wire main_clkout3;
-wire main_clkout_buf3;
-reg  [3:0] main_reset_counter = 4'd15;
-reg  main_ic_reset = 1'd1;
-reg  main_a7ddrphy_rst_storage = 1'd0;
-reg  main_a7ddrphy_rst_re = 1'd0;
-reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg  main_a7ddrphy_wlevel_en_re = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
-wire main_a7ddrphy_wlevel_strobe_r;
-reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg  main_a7ddrphy_dly_sel_re = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_rst_r;
-reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_inc_r;
-reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg  main_a7ddrphy_rdphase_re = 1'd0;
-reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg  main_a7ddrphy_wrphase_re = 1'd0;
-wire [13:0] main_a7ddrphy_dfi_p0_address;
-wire [2:0] main_a7ddrphy_dfi_p0_bank;
-wire main_a7ddrphy_dfi_p0_cas_n;
-wire main_a7ddrphy_dfi_p0_cs_n;
-wire main_a7ddrphy_dfi_p0_ras_n;
-wire main_a7ddrphy_dfi_p0_we_n;
-wire main_a7ddrphy_dfi_p0_cke;
-wire main_a7ddrphy_dfi_p0_odt;
-wire main_a7ddrphy_dfi_p0_reset_n;
-wire main_a7ddrphy_dfi_p0_act_n;
-wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
-wire main_a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
-wire main_a7ddrphy_dfi_p0_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p0_rddata_valid;
-wire [13:0] main_a7ddrphy_dfi_p1_address;
-wire [2:0] main_a7ddrphy_dfi_p1_bank;
-wire main_a7ddrphy_dfi_p1_cas_n;
-wire main_a7ddrphy_dfi_p1_cs_n;
-wire main_a7ddrphy_dfi_p1_ras_n;
-wire main_a7ddrphy_dfi_p1_we_n;
-wire main_a7ddrphy_dfi_p1_cke;
-wire main_a7ddrphy_dfi_p1_odt;
-wire main_a7ddrphy_dfi_p1_reset_n;
-wire main_a7ddrphy_dfi_p1_act_n;
-wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
-wire main_a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
-wire main_a7ddrphy_dfi_p1_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p1_rddata_valid;
-wire [13:0] main_a7ddrphy_dfi_p2_address;
-wire [2:0] main_a7ddrphy_dfi_p2_bank;
-wire main_a7ddrphy_dfi_p2_cas_n;
-wire main_a7ddrphy_dfi_p2_cs_n;
-wire main_a7ddrphy_dfi_p2_ras_n;
-wire main_a7ddrphy_dfi_p2_we_n;
-wire main_a7ddrphy_dfi_p2_cke;
-wire main_a7ddrphy_dfi_p2_odt;
-wire main_a7ddrphy_dfi_p2_reset_n;
-wire main_a7ddrphy_dfi_p2_act_n;
-wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
-wire main_a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
-wire main_a7ddrphy_dfi_p2_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p2_rddata_valid;
-wire [13:0] main_a7ddrphy_dfi_p3_address;
-wire [2:0] main_a7ddrphy_dfi_p3_bank;
-wire main_a7ddrphy_dfi_p3_cas_n;
-wire main_a7ddrphy_dfi_p3_cs_n;
-wire main_a7ddrphy_dfi_p3_ras_n;
-wire main_a7ddrphy_dfi_p3_we_n;
-wire main_a7ddrphy_dfi_p3_cke;
-wire main_a7ddrphy_dfi_p3_odt;
-wire main_a7ddrphy_dfi_p3_reset_n;
-wire main_a7ddrphy_dfi_p3_act_n;
-wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
-wire main_a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
-wire main_a7ddrphy_dfi_p3_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p3_rddata_valid;
-wire main_a7ddrphy_sd_clk_se_nodelay;
-reg  main_a7ddrphy_dqs_oe = 1'd0;
-wire main_a7ddrphy_dqs_preamble;
-wire main_a7ddrphy_dqs_postamble;
-wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_dqspattern0 = 1'd0;
-reg  main_a7ddrphy_dqspattern1 = 1'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
-wire main_a7ddrphy_dqs_o_no_delay0;
-wire main_a7ddrphy_dqs_t0;
-reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
-wire main_a7ddrphy0;
-wire main_a7ddrphy_dqs_o_no_delay1;
-wire main_a7ddrphy_dqs_t1;
-reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
-wire main_a7ddrphy1;
-reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
-wire main_a7ddrphy_dq_oe;
-wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire main_a7ddrphy_dq_o_nodelay0;
-wire main_a7ddrphy_dq_i_nodelay0;
-wire main_a7ddrphy_dq_i_delayed0;
-wire main_a7ddrphy_dq_t0;
-reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip03;
-reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay1;
-wire main_a7ddrphy_dq_i_nodelay1;
-wire main_a7ddrphy_dq_i_delayed1;
-wire main_a7ddrphy_dq_t1;
-reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip13;
-reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay2;
-wire main_a7ddrphy_dq_i_nodelay2;
-wire main_a7ddrphy_dq_i_delayed2;
-wire main_a7ddrphy_dq_t2;
-reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip21;
-reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay3;
-wire main_a7ddrphy_dq_i_nodelay3;
-wire main_a7ddrphy_dq_i_delayed3;
-wire main_a7ddrphy_dq_t3;
-reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip31;
-reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay4;
-wire main_a7ddrphy_dq_i_nodelay4;
-wire main_a7ddrphy_dq_i_delayed4;
-wire main_a7ddrphy_dq_t4;
-reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip41;
-reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay5;
-wire main_a7ddrphy_dq_i_nodelay5;
-wire main_a7ddrphy_dq_i_delayed5;
-wire main_a7ddrphy_dq_t5;
-reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip51;
-reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay6;
-wire main_a7ddrphy_dq_i_nodelay6;
-wire main_a7ddrphy_dq_i_delayed6;
-wire main_a7ddrphy_dq_t6;
-reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip61;
-reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay7;
-wire main_a7ddrphy_dq_i_nodelay7;
-wire main_a7ddrphy_dq_i_delayed7;
-wire main_a7ddrphy_dq_t7;
-reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip71;
-reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay8;
-wire main_a7ddrphy_dq_i_nodelay8;
-wire main_a7ddrphy_dq_i_delayed8;
-wire main_a7ddrphy_dq_t8;
-reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip81;
-reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay9;
-wire main_a7ddrphy_dq_i_nodelay9;
-wire main_a7ddrphy_dq_i_delayed9;
-wire main_a7ddrphy_dq_t9;
-reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip91;
-reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay10;
-wire main_a7ddrphy_dq_i_nodelay10;
-wire main_a7ddrphy_dq_i_delayed10;
-wire main_a7ddrphy_dq_t10;
-reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip101;
-reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay11;
-wire main_a7ddrphy_dq_i_nodelay11;
-wire main_a7ddrphy_dq_i_delayed11;
-wire main_a7ddrphy_dq_t11;
-reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip111;
-reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay12;
-wire main_a7ddrphy_dq_i_nodelay12;
-wire main_a7ddrphy_dq_i_delayed12;
-wire main_a7ddrphy_dq_t12;
-reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip121;
-reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay13;
-wire main_a7ddrphy_dq_i_nodelay13;
-wire main_a7ddrphy_dq_i_delayed13;
-wire main_a7ddrphy_dq_t13;
-reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip131;
-reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay14;
-wire main_a7ddrphy_dq_i_nodelay14;
-wire main_a7ddrphy_dq_i_delayed14;
-wire main_a7ddrphy_dq_t14;
-reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip141;
-reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay15;
-wire main_a7ddrphy_dq_i_nodelay15;
-wire main_a7ddrphy_dq_i_delayed15;
-wire main_a7ddrphy_dq_t15;
-reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip151;
-reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [13:0] main_litedramcore_inti_p0_address;
-wire [2:0] main_litedramcore_inti_p0_bank;
-reg  main_litedramcore_inti_p0_cas_n = 1'd1;
-reg  main_litedramcore_inti_p0_cs_n = 1'd1;
-reg  main_litedramcore_inti_p0_ras_n = 1'd1;
-reg  main_litedramcore_inti_p0_we_n = 1'd1;
-wire main_litedramcore_inti_p0_cke;
-wire main_litedramcore_inti_p0_odt;
-wire main_litedramcore_inti_p0_reset_n;
-reg  main_litedramcore_inti_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p0_wrdata;
-wire main_litedramcore_inti_p0_wrdata_en;
-wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
-wire main_litedramcore_inti_p0_rddata_en;
-reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_inti_p1_address;
-wire [2:0] main_litedramcore_inti_p1_bank;
-reg  main_litedramcore_inti_p1_cas_n = 1'd1;
-reg  main_litedramcore_inti_p1_cs_n = 1'd1;
-reg  main_litedramcore_inti_p1_ras_n = 1'd1;
-reg  main_litedramcore_inti_p1_we_n = 1'd1;
-wire main_litedramcore_inti_p1_cke;
-wire main_litedramcore_inti_p1_odt;
-wire main_litedramcore_inti_p1_reset_n;
-reg  main_litedramcore_inti_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p1_wrdata;
-wire main_litedramcore_inti_p1_wrdata_en;
-wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
-wire main_litedramcore_inti_p1_rddata_en;
-reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_inti_p2_address;
-wire [2:0] main_litedramcore_inti_p2_bank;
-reg  main_litedramcore_inti_p2_cas_n = 1'd1;
-reg  main_litedramcore_inti_p2_cs_n = 1'd1;
-reg  main_litedramcore_inti_p2_ras_n = 1'd1;
-reg  main_litedramcore_inti_p2_we_n = 1'd1;
-wire main_litedramcore_inti_p2_cke;
-wire main_litedramcore_inti_p2_odt;
-wire main_litedramcore_inti_p2_reset_n;
-reg  main_litedramcore_inti_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p2_wrdata;
-wire main_litedramcore_inti_p2_wrdata_en;
-wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
-wire main_litedramcore_inti_p2_rddata_en;
-reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_inti_p3_address;
-wire [2:0] main_litedramcore_inti_p3_bank;
-reg  main_litedramcore_inti_p3_cas_n = 1'd1;
-reg  main_litedramcore_inti_p3_cs_n = 1'd1;
-reg  main_litedramcore_inti_p3_ras_n = 1'd1;
-reg  main_litedramcore_inti_p3_we_n = 1'd1;
-wire main_litedramcore_inti_p3_cke;
-wire main_litedramcore_inti_p3_odt;
-wire main_litedramcore_inti_p3_reset_n;
-reg  main_litedramcore_inti_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p3_wrdata;
-wire main_litedramcore_inti_p3_wrdata_en;
-wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
-wire main_litedramcore_inti_p3_rddata_en;
-reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p0_address;
-wire [2:0] main_litedramcore_slave_p0_bank;
-wire main_litedramcore_slave_p0_cas_n;
-wire main_litedramcore_slave_p0_cs_n;
-wire main_litedramcore_slave_p0_ras_n;
-wire main_litedramcore_slave_p0_we_n;
-wire main_litedramcore_slave_p0_cke;
-wire main_litedramcore_slave_p0_odt;
-wire main_litedramcore_slave_p0_reset_n;
-wire main_litedramcore_slave_p0_act_n;
-wire [31:0] main_litedramcore_slave_p0_wrdata;
-wire main_litedramcore_slave_p0_wrdata_en;
-wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
-wire main_litedramcore_slave_p0_rddata_en;
-reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p1_address;
-wire [2:0] main_litedramcore_slave_p1_bank;
-wire main_litedramcore_slave_p1_cas_n;
-wire main_litedramcore_slave_p1_cs_n;
-wire main_litedramcore_slave_p1_ras_n;
-wire main_litedramcore_slave_p1_we_n;
-wire main_litedramcore_slave_p1_cke;
-wire main_litedramcore_slave_p1_odt;
-wire main_litedramcore_slave_p1_reset_n;
-wire main_litedramcore_slave_p1_act_n;
-wire [31:0] main_litedramcore_slave_p1_wrdata;
-wire main_litedramcore_slave_p1_wrdata_en;
-wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
-wire main_litedramcore_slave_p1_rddata_en;
-reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p2_address;
-wire [2:0] main_litedramcore_slave_p2_bank;
-wire main_litedramcore_slave_p2_cas_n;
-wire main_litedramcore_slave_p2_cs_n;
-wire main_litedramcore_slave_p2_ras_n;
-wire main_litedramcore_slave_p2_we_n;
-wire main_litedramcore_slave_p2_cke;
-wire main_litedramcore_slave_p2_odt;
-wire main_litedramcore_slave_p2_reset_n;
-wire main_litedramcore_slave_p2_act_n;
-wire [31:0] main_litedramcore_slave_p2_wrdata;
-wire main_litedramcore_slave_p2_wrdata_en;
-wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
-wire main_litedramcore_slave_p2_rddata_en;
-reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p3_address;
-wire [2:0] main_litedramcore_slave_p3_bank;
-wire main_litedramcore_slave_p3_cas_n;
-wire main_litedramcore_slave_p3_cs_n;
-wire main_litedramcore_slave_p3_ras_n;
-wire main_litedramcore_slave_p3_we_n;
-wire main_litedramcore_slave_p3_cke;
-wire main_litedramcore_slave_p3_odt;
-wire main_litedramcore_slave_p3_reset_n;
-wire main_litedramcore_slave_p3_act_n;
-wire [31:0] main_litedramcore_slave_p3_wrdata;
-wire main_litedramcore_slave_p3_wrdata_en;
-wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
-wire main_litedramcore_slave_p3_rddata_en;
-reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg  [13:0] main_litedramcore_master_p0_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg  main_litedramcore_master_p0_cas_n = 1'd1;
-reg  main_litedramcore_master_p0_cs_n = 1'd1;
-reg  main_litedramcore_master_p0_ras_n = 1'd1;
-reg  main_litedramcore_master_p0_we_n = 1'd1;
-reg  main_litedramcore_master_p0_cke = 1'd0;
-reg  main_litedramcore_master_p0_odt = 1'd0;
-reg  main_litedramcore_master_p0_reset_n = 1'd0;
-reg  main_litedramcore_master_p0_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p0_rddata;
-wire main_litedramcore_master_p0_rddata_valid;
-reg  [13:0] main_litedramcore_master_p1_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg  main_litedramcore_master_p1_cas_n = 1'd1;
-reg  main_litedramcore_master_p1_cs_n = 1'd1;
-reg  main_litedramcore_master_p1_ras_n = 1'd1;
-reg  main_litedramcore_master_p1_we_n = 1'd1;
-reg  main_litedramcore_master_p1_cke = 1'd0;
-reg  main_litedramcore_master_p1_odt = 1'd0;
-reg  main_litedramcore_master_p1_reset_n = 1'd0;
-reg  main_litedramcore_master_p1_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p1_rddata;
-wire main_litedramcore_master_p1_rddata_valid;
-reg  [13:0] main_litedramcore_master_p2_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg  main_litedramcore_master_p2_cas_n = 1'd1;
-reg  main_litedramcore_master_p2_cs_n = 1'd1;
-reg  main_litedramcore_master_p2_ras_n = 1'd1;
-reg  main_litedramcore_master_p2_we_n = 1'd1;
-reg  main_litedramcore_master_p2_cke = 1'd0;
-reg  main_litedramcore_master_p2_odt = 1'd0;
-reg  main_litedramcore_master_p2_reset_n = 1'd0;
-reg  main_litedramcore_master_p2_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p2_rddata;
-wire main_litedramcore_master_p2_rddata_valid;
-reg  [13:0] main_litedramcore_master_p3_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg  main_litedramcore_master_p3_cas_n = 1'd1;
-reg  main_litedramcore_master_p3_cs_n = 1'd1;
-reg  main_litedramcore_master_p3_ras_n = 1'd1;
-reg  main_litedramcore_master_p3_we_n = 1'd1;
-reg  main_litedramcore_master_p3_cke = 1'd0;
-reg  main_litedramcore_master_p3_odt = 1'd0;
-reg  main_litedramcore_master_p3_reset_n = 1'd0;
-reg  main_litedramcore_master_p3_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p3_rddata;
-wire main_litedramcore_master_p3_rddata_valid;
-wire main_litedramcore_sel;
-wire main_litedramcore_cke;
-wire main_litedramcore_odt;
-wire main_litedramcore_reset_n;
-reg  [3:0] main_litedramcore_storage = 4'd1;
-reg  main_litedramcore_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector0_command_issue_r;
-reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector0_rddata_we;
-reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector1_command_issue_r;
-reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector1_rddata_we;
-reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector2_command_issue_r;
-reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector2_rddata_we;
-reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector3_command_issue_r;
-reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector3_rddata_we;
-reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire main_litedramcore_interface_bank0_valid;
-wire main_litedramcore_interface_bank0_ready;
-wire main_litedramcore_interface_bank0_we;
-wire [20:0] main_litedramcore_interface_bank0_addr;
-wire main_litedramcore_interface_bank0_lock;
-wire main_litedramcore_interface_bank0_wdata_ready;
-wire main_litedramcore_interface_bank0_rdata_valid;
-wire main_litedramcore_interface_bank1_valid;
-wire main_litedramcore_interface_bank1_ready;
-wire main_litedramcore_interface_bank1_we;
-wire [20:0] main_litedramcore_interface_bank1_addr;
-wire main_litedramcore_interface_bank1_lock;
-wire main_litedramcore_interface_bank1_wdata_ready;
-wire main_litedramcore_interface_bank1_rdata_valid;
-wire main_litedramcore_interface_bank2_valid;
-wire main_litedramcore_interface_bank2_ready;
-wire main_litedramcore_interface_bank2_we;
-wire [20:0] main_litedramcore_interface_bank2_addr;
-wire main_litedramcore_interface_bank2_lock;
-wire main_litedramcore_interface_bank2_wdata_ready;
-wire main_litedramcore_interface_bank2_rdata_valid;
-wire main_litedramcore_interface_bank3_valid;
-wire main_litedramcore_interface_bank3_ready;
-wire main_litedramcore_interface_bank3_we;
-wire [20:0] main_litedramcore_interface_bank3_addr;
-wire main_litedramcore_interface_bank3_lock;
-wire main_litedramcore_interface_bank3_wdata_ready;
-wire main_litedramcore_interface_bank3_rdata_valid;
-wire main_litedramcore_interface_bank4_valid;
-wire main_litedramcore_interface_bank4_ready;
-wire main_litedramcore_interface_bank4_we;
-wire [20:0] main_litedramcore_interface_bank4_addr;
-wire main_litedramcore_interface_bank4_lock;
-wire main_litedramcore_interface_bank4_wdata_ready;
-wire main_litedramcore_interface_bank4_rdata_valid;
-wire main_litedramcore_interface_bank5_valid;
-wire main_litedramcore_interface_bank5_ready;
-wire main_litedramcore_interface_bank5_we;
-wire [20:0] main_litedramcore_interface_bank5_addr;
-wire main_litedramcore_interface_bank5_lock;
-wire main_litedramcore_interface_bank5_wdata_ready;
-wire main_litedramcore_interface_bank5_rdata_valid;
-wire main_litedramcore_interface_bank6_valid;
-wire main_litedramcore_interface_bank6_ready;
-wire main_litedramcore_interface_bank6_we;
-wire [20:0] main_litedramcore_interface_bank6_addr;
-wire main_litedramcore_interface_bank6_lock;
-wire main_litedramcore_interface_bank6_wdata_ready;
-wire main_litedramcore_interface_bank6_rdata_valid;
-wire main_litedramcore_interface_bank7_valid;
-wire main_litedramcore_interface_bank7_ready;
-wire main_litedramcore_interface_bank7_we;
-wire [20:0] main_litedramcore_interface_bank7_addr;
-wire main_litedramcore_interface_bank7_lock;
-wire main_litedramcore_interface_bank7_wdata_ready;
-wire main_litedramcore_interface_bank7_rdata_valid;
-reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] main_litedramcore_interface_rdata;
-reg  [13:0] main_litedramcore_dfi_p0_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p0_we_n = 1'd1;
-wire main_litedramcore_dfi_p0_cke;
-wire main_litedramcore_dfi_p0_odt;
-wire main_litedramcore_dfi_p0_reset_n;
-reg  main_litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p0_rddata;
-wire main_litedramcore_dfi_p0_rddata_valid;
-reg  [13:0] main_litedramcore_dfi_p1_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p1_we_n = 1'd1;
-wire main_litedramcore_dfi_p1_cke;
-wire main_litedramcore_dfi_p1_odt;
-wire main_litedramcore_dfi_p1_reset_n;
-reg  main_litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p1_rddata;
-wire main_litedramcore_dfi_p1_rddata_valid;
-reg  [13:0] main_litedramcore_dfi_p2_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p2_we_n = 1'd1;
-wire main_litedramcore_dfi_p2_cke;
-wire main_litedramcore_dfi_p2_odt;
-wire main_litedramcore_dfi_p2_reset_n;
-reg  main_litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p2_rddata;
-wire main_litedramcore_dfi_p2_rddata_valid;
-reg  [13:0] main_litedramcore_dfi_p3_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p3_we_n = 1'd1;
-wire main_litedramcore_dfi_p3_cke;
-wire main_litedramcore_dfi_p3_odt;
-wire main_litedramcore_dfi_p3_reset_n;
-reg  main_litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p3_rddata;
-wire main_litedramcore_dfi_p3_rddata_valid;
-reg  main_litedramcore_cmd_valid = 1'd0;
-reg  main_litedramcore_cmd_ready = 1'd0;
-reg  main_litedramcore_cmd_last = 1'd0;
-reg  [13:0] main_litedramcore_cmd_payload_a = 14'd0;
-reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg  main_litedramcore_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_cmd_payload_we = 1'd0;
-reg  main_litedramcore_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_cmd_payload_is_write = 1'd0;
-wire main_litedramcore_wants_refresh;
-wire main_litedramcore_wants_zqcs;
-wire main_litedramcore_timer_wait;
-wire main_litedramcore_timer_done0;
-wire [9:0] main_litedramcore_timer_count0;
-wire main_litedramcore_timer_done1;
-reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
-wire main_litedramcore_postponer_req_i;
-reg  main_litedramcore_postponer_req_o = 1'd0;
-reg  main_litedramcore_postponer_count = 1'd0;
-reg  main_litedramcore_sequencer_start0 = 1'd0;
-wire main_litedramcore_sequencer_done0;
-wire main_litedramcore_sequencer_start1;
-reg  main_litedramcore_sequencer_done1 = 1'd0;
-reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg  main_litedramcore_sequencer_count = 1'd0;
-wire main_litedramcore_zqcs_timer_wait;
-wire main_litedramcore_zqcs_timer_done0;
-wire [26:0] main_litedramcore_zqcs_timer_count0;
-wire main_litedramcore_zqcs_timer_done1;
-reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg  main_litedramcore_zqcs_executer_start = 1'd0;
-reg  main_litedramcore_zqcs_executer_done = 1'd0;
-reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
-wire main_litedramcore_bankmachine0_req_valid;
-wire main_litedramcore_bankmachine0_req_ready;
-wire main_litedramcore_bankmachine0_req_we;
-wire [20:0] main_litedramcore_bankmachine0_req_addr;
-wire main_litedramcore_bankmachine0_req_lock;
-reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine0_refresh_req;
-reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine0_row = 14'd0;
-reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
-wire main_litedramcore_bankmachine0_row_hit;
-reg  main_litedramcore_bankmachine0_row_open = 1'd0;
-reg  main_litedramcore_bankmachine0_row_close = 1'd0;
-reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine1_req_valid;
-wire main_litedramcore_bankmachine1_req_ready;
-wire main_litedramcore_bankmachine1_req_we;
-wire [20:0] main_litedramcore_bankmachine1_req_addr;
-wire main_litedramcore_bankmachine1_req_lock;
-reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine1_refresh_req;
-reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine1_row = 14'd0;
-reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
-wire main_litedramcore_bankmachine1_row_hit;
-reg  main_litedramcore_bankmachine1_row_open = 1'd0;
-reg  main_litedramcore_bankmachine1_row_close = 1'd0;
-reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine2_req_valid;
-wire main_litedramcore_bankmachine2_req_ready;
-wire main_litedramcore_bankmachine2_req_we;
-wire [20:0] main_litedramcore_bankmachine2_req_addr;
-wire main_litedramcore_bankmachine2_req_lock;
-reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine2_refresh_req;
-reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine2_row = 14'd0;
-reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
-wire main_litedramcore_bankmachine2_row_hit;
-reg  main_litedramcore_bankmachine2_row_open = 1'd0;
-reg  main_litedramcore_bankmachine2_row_close = 1'd0;
-reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine3_req_valid;
-wire main_litedramcore_bankmachine3_req_ready;
-wire main_litedramcore_bankmachine3_req_we;
-wire [20:0] main_litedramcore_bankmachine3_req_addr;
-wire main_litedramcore_bankmachine3_req_lock;
-reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine3_refresh_req;
-reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine3_row = 14'd0;
-reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
-wire main_litedramcore_bankmachine3_row_hit;
-reg  main_litedramcore_bankmachine3_row_open = 1'd0;
-reg  main_litedramcore_bankmachine3_row_close = 1'd0;
-reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine4_req_valid;
-wire main_litedramcore_bankmachine4_req_ready;
-wire main_litedramcore_bankmachine4_req_we;
-wire [20:0] main_litedramcore_bankmachine4_req_addr;
-wire main_litedramcore_bankmachine4_req_lock;
-reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine4_refresh_req;
-reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine4_row = 14'd0;
-reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
-wire main_litedramcore_bankmachine4_row_hit;
-reg  main_litedramcore_bankmachine4_row_open = 1'd0;
-reg  main_litedramcore_bankmachine4_row_close = 1'd0;
-reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine5_req_valid;
-wire main_litedramcore_bankmachine5_req_ready;
-wire main_litedramcore_bankmachine5_req_we;
-wire [20:0] main_litedramcore_bankmachine5_req_addr;
-wire main_litedramcore_bankmachine5_req_lock;
-reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine5_refresh_req;
-reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine5_row = 14'd0;
-reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
-wire main_litedramcore_bankmachine5_row_hit;
-reg  main_litedramcore_bankmachine5_row_open = 1'd0;
-reg  main_litedramcore_bankmachine5_row_close = 1'd0;
-reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine6_req_valid;
-wire main_litedramcore_bankmachine6_req_ready;
-wire main_litedramcore_bankmachine6_req_we;
-wire [20:0] main_litedramcore_bankmachine6_req_addr;
-wire main_litedramcore_bankmachine6_req_lock;
-reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine6_refresh_req;
-reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine6_row = 14'd0;
-reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
-wire main_litedramcore_bankmachine6_row_hit;
-reg  main_litedramcore_bankmachine6_row_open = 1'd0;
-reg  main_litedramcore_bankmachine6_row_close = 1'd0;
-reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine7_req_valid;
-wire main_litedramcore_bankmachine7_req_ready;
-wire main_litedramcore_bankmachine7_req_we;
-wire [20:0] main_litedramcore_bankmachine7_req_addr;
-wire main_litedramcore_bankmachine7_req_lock;
-reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine7_refresh_req;
-reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine7_row = 14'd0;
-reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
-wire main_litedramcore_bankmachine7_row_hit;
-reg  main_litedramcore_bankmachine7_row_open = 1'd0;
-reg  main_litedramcore_bankmachine7_row_close = 1'd0;
-reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
-wire main_litedramcore_ras_allowed;
-wire main_litedramcore_cas_allowed;
-wire [1:0] main_litedramcore_rdcmdphase;
-wire [1:0] main_litedramcore_wrcmdphase;
-reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_valid;
-reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire main_litedramcore_choose_cmd_cmd_payload_is_read;
-wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_cmd_request;
-reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
-wire main_litedramcore_choose_cmd_ce;
-reg  main_litedramcore_choose_req_want_reads = 1'd0;
-reg  main_litedramcore_choose_req_want_writes = 1'd0;
-reg  main_litedramcore_choose_req_want_cmds = 1'd0;
-reg  main_litedramcore_choose_req_want_activates = 1'd0;
-wire main_litedramcore_choose_req_cmd_valid;
-reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
-wire [13:0] main_litedramcore_choose_req_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_req_cmd_payload_is_cmd;
-wire main_litedramcore_choose_req_cmd_payload_is_read;
-wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_req_request;
-reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
-wire main_litedramcore_choose_req_ce;
-reg  [13:0] main_litedramcore_nop_a = 14'd0;
-reg  [2:0] main_litedramcore_nop_ba = 3'd0;
-reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg  main_litedramcore_steerer0 = 1'd1;
-reg  main_litedramcore_steerer1 = 1'd1;
-reg  main_litedramcore_steerer2 = 1'd1;
-reg  main_litedramcore_steerer3 = 1'd1;
-reg  main_litedramcore_steerer4 = 1'd1;
-reg  main_litedramcore_steerer5 = 1'd1;
-reg  main_litedramcore_steerer6 = 1'd1;
-reg  main_litedramcore_steerer7 = 1'd1;
-wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
-reg  main_litedramcore_trrdcon_count = 1'd0;
-wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] main_litedramcore_tfawcon_count;
-reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
-wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
-reg  main_litedramcore_tccdcon_count = 1'd0;
-wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
-wire main_litedramcore_read_available;
-wire main_litedramcore_write_available;
-reg  main_litedramcore_en0 = 1'd0;
-wire main_litedramcore_max_time0;
-reg  [4:0] main_litedramcore_time0 = 5'd0;
-reg  main_litedramcore_en1 = 1'd0;
-wire main_litedramcore_max_time1;
-reg  [3:0] main_litedramcore_time1 = 4'd0;
-wire main_litedramcore_go_to_refresh;
-reg  main_init_done_storage = 1'd0;
-reg  main_init_done_re = 1'd0;
-reg  main_init_error_storage = 1'd0;
-reg  main_init_error_re = 1'd0;
-wire [29:0] main_wb_bus_adr;
-wire [31:0] main_wb_bus_dat_w;
-wire [31:0] main_wb_bus_dat_r;
-wire [3:0] main_wb_bus_sel;
-wire main_wb_bus_cyc;
-wire main_wb_bus_stb;
-wire main_wb_bus_ack;
-wire main_wb_bus_we;
-wire [2:0] main_wb_bus_cti;
-wire [1:0] main_wb_bus_bte;
-wire main_wb_bus_err;
-wire main_user_enable;
-wire main_user_port_cmd_valid;
-wire main_user_port_cmd_ready;
-wire main_user_port_cmd_payload_we;
-wire [23:0] main_user_port_cmd_payload_addr;
-wire main_user_port_wdata_valid;
-wire main_user_port_wdata_ready;
-wire [127:0] main_user_port_wdata_payload_data;
-wire [15:0] main_user_port_wdata_payload_we;
-wire main_user_port_rdata_valid;
-wire main_user_port_rdata_ready;
-wire [127:0] main_user_port_rdata_payload_data;
-wire builder_reset0;
-wire builder_reset1;
-wire builder_reset2;
-wire builder_reset3;
-wire builder_reset4;
-wire builder_reset5;
-wire builder_reset6;
-wire builder_reset7;
-wire builder_pll_fb;
-reg  [1:0] builder_refresher_state = 2'd0;
-reg  [1:0] builder_refresher_next_state = 2'd0;
-reg  [3:0] builder_bankmachine0_state = 4'd0;
-reg  [3:0] builder_bankmachine0_next_state = 4'd0;
-reg  [3:0] builder_bankmachine1_state = 4'd0;
-reg  [3:0] builder_bankmachine1_next_state = 4'd0;
-reg  [3:0] builder_bankmachine2_state = 4'd0;
-reg  [3:0] builder_bankmachine2_next_state = 4'd0;
-reg  [3:0] builder_bankmachine3_state = 4'd0;
-reg  [3:0] builder_bankmachine3_next_state = 4'd0;
-reg  [3:0] builder_bankmachine4_state = 4'd0;
-reg  [3:0] builder_bankmachine4_next_state = 4'd0;
-reg  [3:0] builder_bankmachine5_state = 4'd0;
-reg  [3:0] builder_bankmachine5_next_state = 4'd0;
-reg  [3:0] builder_bankmachine6_state = 4'd0;
-reg  [3:0] builder_bankmachine6_next_state = 4'd0;
-reg  [3:0] builder_bankmachine7_state = 4'd0;
-reg  [3:0] builder_bankmachine7_next_state = 4'd0;
-reg  [3:0] builder_multiplexer_state = 4'd0;
-reg  [3:0] builder_multiplexer_next_state = 4'd0;
-wire builder_roundrobin0_request;
-wire builder_roundrobin0_grant;
-wire builder_roundrobin0_ce;
-wire builder_roundrobin1_request;
-wire builder_roundrobin1_grant;
-wire builder_roundrobin1_ce;
-wire builder_roundrobin2_request;
-wire builder_roundrobin2_grant;
-wire builder_roundrobin2_ce;
-wire builder_roundrobin3_request;
-wire builder_roundrobin3_grant;
-wire builder_roundrobin3_ce;
-wire builder_roundrobin4_request;
-wire builder_roundrobin4_grant;
-wire builder_roundrobin4_ce;
-wire builder_roundrobin5_request;
-wire builder_roundrobin5_grant;
-wire builder_roundrobin5_ce;
-wire builder_roundrobin6_request;
-wire builder_roundrobin6_grant;
-wire builder_roundrobin6_ce;
-wire builder_roundrobin7_request;
-wire builder_roundrobin7_grant;
-wire builder_roundrobin7_ce;
-reg  builder_locked0 = 1'd0;
-reg  builder_locked1 = 1'd0;
-reg  builder_locked2 = 1'd0;
-reg  builder_locked3 = 1'd0;
-reg  builder_locked4 = 1'd0;
-reg  builder_locked5 = 1'd0;
-reg  builder_locked6 = 1'd0;
-reg  builder_locked7 = 1'd0;
-reg  builder_new_master_wdata_ready0 = 1'd0;
-reg  builder_new_master_wdata_ready1 = 1'd0;
-reg  builder_new_master_rdata_valid0 = 1'd0;
-reg  builder_new_master_rdata_valid1 = 1'd0;
-reg  builder_new_master_rdata_valid2 = 1'd0;
-reg  builder_new_master_rdata_valid3 = 1'd0;
-reg  builder_new_master_rdata_valid4 = 1'd0;
-reg  builder_new_master_rdata_valid5 = 1'd0;
-reg  builder_new_master_rdata_valid6 = 1'd0;
-reg  builder_new_master_rdata_valid7 = 1'd0;
-reg  builder_new_master_rdata_valid8 = 1'd0;
-reg  [13:0] builder_litedramcore_adr = 14'd0;
-reg  builder_litedramcore_we = 1'd0;
-reg  [31:0] builder_litedramcore_dat_w = 32'd0;
-wire [31:0] builder_litedramcore_dat_r;
-wire [29:0] builder_litedramcore_wishbone_adr;
-wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] builder_litedramcore_wishbone_sel;
-wire builder_litedramcore_wishbone_cyc;
-wire builder_litedramcore_wishbone_stb;
-reg  builder_litedramcore_wishbone_ack = 1'd0;
-wire builder_litedramcore_wishbone_we;
-wire [2:0] builder_litedramcore_wishbone_cti;
-wire [1:0] builder_litedramcore_wishbone_bte;
-reg  builder_litedramcore_wishbone_err = 1'd0;
-wire [13:0] builder_interface0_bank_bus_adr;
-wire builder_interface0_bank_bus_we;
-wire [31:0] builder_interface0_bank_bus_dat_w;
-reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank0_init_done0_re = 1'd0;
-wire builder_csrbank0_init_done0_r;
-reg  builder_csrbank0_init_done0_we = 1'd0;
-wire builder_csrbank0_init_done0_w;
-reg  builder_csrbank0_init_error0_re = 1'd0;
-wire builder_csrbank0_init_error0_r;
-reg  builder_csrbank0_init_error0_we = 1'd0;
-wire builder_csrbank0_init_error0_w;
-wire builder_csrbank0_sel;
-wire [13:0] builder_interface1_bank_bus_adr;
-wire builder_interface1_bank_bus_we;
-wire [31:0] builder_interface1_bank_bus_dat_w;
-reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank1_rst0_re = 1'd0;
-wire builder_csrbank1_rst0_r;
-reg  builder_csrbank1_rst0_we = 1'd0;
-wire builder_csrbank1_rst0_w;
-reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg  builder_csrbank1_wlevel_en0_re = 1'd0;
-wire builder_csrbank1_wlevel_en0_r;
-reg  builder_csrbank1_wlevel_en0_we = 1'd0;
-wire builder_csrbank1_wlevel_en0_w;
-reg  builder_csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_r;
-reg  builder_csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_w;
-reg  builder_csrbank1_rdphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_r;
-reg  builder_csrbank1_rdphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_w;
-reg  builder_csrbank1_wrphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_r;
-reg  builder_csrbank1_wrphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_w;
-wire builder_csrbank1_sel;
-wire [13:0] builder_interface2_bank_bus_adr;
-wire builder_interface2_bank_bus_we;
-wire [31:0] builder_interface2_bank_bus_dat_w;
-reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_r;
-reg  builder_csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_w;
-reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi0_address0_r;
-reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi0_address0_w;
-reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
-reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
-reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi1_address0_r;
-reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi1_address0_w;
-reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
-reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
-reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi2_address0_r;
-reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi2_address0_w;
-reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
-reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
-reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi3_address0_r;
-reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi3_address0_w;
-reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
-reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
-wire builder_csrbank2_sel;
-wire [13:0] builder_csr_interconnect_adr;
-wire builder_csr_interconnect_we;
-wire [31:0] builder_csr_interconnect_dat_w;
-wire [31:0] builder_csr_interconnect_dat_r;
-reg  [1:0] builder_state = 2'd0;
-reg  [1:0] builder_next_state = 2'd0;
-reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
-reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg  builder_litedramcore_we_next_value2 = 1'd0;
-reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg  builder_rhs_array_muxed0 = 1'd0;
-reg  [13:0] builder_rhs_array_muxed1 = 14'd0;
-reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg  builder_rhs_array_muxed3 = 1'd0;
-reg  builder_rhs_array_muxed4 = 1'd0;
-reg  builder_rhs_array_muxed5 = 1'd0;
-reg  builder_t_array_muxed0 = 1'd0;
-reg  builder_t_array_muxed1 = 1'd0;
-reg  builder_t_array_muxed2 = 1'd0;
-reg  builder_rhs_array_muxed6 = 1'd0;
-reg  [13:0] builder_rhs_array_muxed7 = 14'd0;
-reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg  builder_rhs_array_muxed9 = 1'd0;
-reg  builder_rhs_array_muxed10 = 1'd0;
-reg  builder_rhs_array_muxed11 = 1'd0;
-reg  builder_t_array_muxed3 = 1'd0;
-reg  builder_t_array_muxed4 = 1'd0;
-reg  builder_t_array_muxed5 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed12 = 21'd0;
-reg  builder_rhs_array_muxed13 = 1'd0;
-reg  builder_rhs_array_muxed14 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed15 = 21'd0;
-reg  builder_rhs_array_muxed16 = 1'd0;
-reg  builder_rhs_array_muxed17 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed18 = 21'd0;
-reg  builder_rhs_array_muxed19 = 1'd0;
-reg  builder_rhs_array_muxed20 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed21 = 21'd0;
-reg  builder_rhs_array_muxed22 = 1'd0;
-reg  builder_rhs_array_muxed23 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed24 = 21'd0;
-reg  builder_rhs_array_muxed25 = 1'd0;
-reg  builder_rhs_array_muxed26 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed27 = 21'd0;
-reg  builder_rhs_array_muxed28 = 1'd0;
-reg  builder_rhs_array_muxed29 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed30 = 21'd0;
-reg  builder_rhs_array_muxed31 = 1'd0;
-reg  builder_rhs_array_muxed32 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed33 = 21'd0;
-reg  builder_rhs_array_muxed34 = 1'd0;
-reg  builder_rhs_array_muxed35 = 1'd0;
-reg  [2:0] builder_array_muxed0 = 3'd0;
-reg  [13:0] builder_array_muxed1 = 14'd0;
-reg  builder_array_muxed2 = 1'd0;
-reg  builder_array_muxed3 = 1'd0;
-reg  builder_array_muxed4 = 1'd0;
-reg  builder_array_muxed5 = 1'd0;
-reg  builder_array_muxed6 = 1'd0;
-reg  [2:0] builder_array_muxed7 = 3'd0;
-reg  [13:0] builder_array_muxed8 = 14'd0;
-reg  builder_array_muxed9 = 1'd0;
-reg  builder_array_muxed10 = 1'd0;
-reg  builder_array_muxed11 = 1'd0;
-reg  builder_array_muxed12 = 1'd0;
-reg  builder_array_muxed13 = 1'd0;
-reg  [2:0] builder_array_muxed14 = 3'd0;
-reg  [13:0] builder_array_muxed15 = 14'd0;
-reg  builder_array_muxed16 = 1'd0;
-reg  builder_array_muxed17 = 1'd0;
-reg  builder_array_muxed18 = 1'd0;
-reg  builder_array_muxed19 = 1'd0;
-reg  builder_array_muxed20 = 1'd0;
-reg  [2:0] builder_array_muxed21 = 3'd0;
-reg  [13:0] builder_array_muxed22 = 14'd0;
-reg  builder_array_muxed23 = 1'd0;
-reg  builder_array_muxed24 = 1'd0;
-reg  builder_array_muxed25 = 1'd0;
-reg  builder_array_muxed26 = 1'd0;
-reg  builder_array_muxed27 = 1'd0;
-wire builder_xilinxasyncresetsynchronizerimpl0;
-wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl1;
-wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2;
-wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2_expr;
-wire builder_xilinxasyncresetsynchronizerimpl3;
-wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire reset;
+reg  power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg  [3:0] reset_counter = 4'd15;
+reg  ic_reset = 1'd1;
+reg  a7ddrphy_rst_storage = 1'd0;
+reg  a7ddrphy_rst_re = 1'd0;
+reg  [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg  a7ddrphy_dly_sel_re = 1'd0;
+reg  [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  a7ddrphy_wlevel_en_storage = 1'd0;
+reg  a7ddrphy_wlevel_en_re = 1'd0;
+reg  a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg  a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg  a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg  a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg  a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg  a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg  a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg  a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg  a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg  a7ddrphy_wrphase_re = 1'd0;
+wire [13:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg  a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_dqspattern0 = 1'd0;
+reg  a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg  [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg  [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg  [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg  [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg  [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg  [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg  [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg  [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg  [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg  [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg  [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg  [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg  [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg  [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg  [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg  [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg  [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg  [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg  [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg  [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg  [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg  [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg  [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg  [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg  [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg  [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg  [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg  [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg  [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg  [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg  [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg  [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg  [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg  [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg  [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [13:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg  [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg  litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg  [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg  litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg  [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg  litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg  [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg  litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_master_p0_address = 14'd0;
+reg  [2:0] litedramcore_master_p0_bank = 3'd0;
+reg  litedramcore_master_p0_cas_n = 1'd1;
+reg  litedramcore_master_p0_cs_n = 1'd1;
+reg  litedramcore_master_p0_ras_n = 1'd1;
+reg  litedramcore_master_p0_we_n = 1'd1;
+reg  litedramcore_master_p0_cke = 1'd0;
+reg  litedramcore_master_p0_odt = 1'd0;
+reg  litedramcore_master_p0_reset_n = 1'd0;
+reg  litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg  litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg  [13:0] litedramcore_master_p1_address = 14'd0;
+reg  [2:0] litedramcore_master_p1_bank = 3'd0;
+reg  litedramcore_master_p1_cas_n = 1'd1;
+reg  litedramcore_master_p1_cs_n = 1'd1;
+reg  litedramcore_master_p1_ras_n = 1'd1;
+reg  litedramcore_master_p1_we_n = 1'd1;
+reg  litedramcore_master_p1_cke = 1'd0;
+reg  litedramcore_master_p1_odt = 1'd0;
+reg  litedramcore_master_p1_reset_n = 1'd0;
+reg  litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg  litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg  [13:0] litedramcore_master_p2_address = 14'd0;
+reg  [2:0] litedramcore_master_p2_bank = 3'd0;
+reg  litedramcore_master_p2_cas_n = 1'd1;
+reg  litedramcore_master_p2_cs_n = 1'd1;
+reg  litedramcore_master_p2_ras_n = 1'd1;
+reg  litedramcore_master_p2_we_n = 1'd1;
+reg  litedramcore_master_p2_cke = 1'd0;
+reg  litedramcore_master_p2_odt = 1'd0;
+reg  litedramcore_master_p2_reset_n = 1'd0;
+reg  litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg  litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg  [13:0] litedramcore_master_p3_address = 14'd0;
+reg  [2:0] litedramcore_master_p3_bank = 3'd0;
+reg  litedramcore_master_p3_cas_n = 1'd1;
+reg  litedramcore_master_p3_cs_n = 1'd1;
+reg  litedramcore_master_p3_ras_n = 1'd1;
+reg  litedramcore_master_p3_we_n = 1'd1;
+reg  litedramcore_master_p3_cke = 1'd0;
+reg  litedramcore_master_p3_odt = 1'd0;
+reg  litedramcore_master_p3_reset_n = 1'd0;
+reg  litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg  litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [13:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg  litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg  litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg  litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg  litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg  litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg  litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg  litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg  litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg  litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cke = 1'd0;
+reg  litedramcore_ext_dfi_p0_odt = 1'd0;
+reg  litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg  litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cke = 1'd0;
+reg  litedramcore_ext_dfi_p1_odt = 1'd0;
+reg  litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg  litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cke = 1'd0;
+reg  litedramcore_ext_dfi_p2_odt = 1'd0;
+reg  litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg  litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cke = 1'd0;
+reg  litedramcore_ext_dfi_p3_odt = 1'd0;
+reg  litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg  litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg  [3:0] litedramcore_storage = 4'd1;
+reg  litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  litedramcore_phaseinjector0_command_re = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg  litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
+reg  litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg  litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  litedramcore_phaseinjector1_command_re = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg  litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
+reg  litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg  litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  litedramcore_phaseinjector2_command_re = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg  litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
+reg  litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg  litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  litedramcore_phaseinjector3_command_re = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg  litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
+reg  litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg  litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [20:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [20:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [20:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [20:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [20:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [20:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [20:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [20:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg  [127:0] litedramcore_interface_wdata = 128'd0;
+reg  [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg  [13:0] litedramcore_dfi_p0_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg  litedramcore_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg  litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg  litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg  litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg  [13:0] litedramcore_dfi_p1_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg  litedramcore_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg  litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg  litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg  litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg  [13:0] litedramcore_dfi_p2_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg  litedramcore_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg  litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg  litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg  litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg  [13:0] litedramcore_dfi_p3_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg  litedramcore_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg  litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg  litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg  litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg  litedramcore_cmd_valid = 1'd0;
+reg  litedramcore_cmd_ready = 1'd0;
+reg  litedramcore_cmd_last = 1'd0;
+reg  [13:0] litedramcore_cmd_payload_a = 14'd0;
+reg  [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg  litedramcore_cmd_payload_cas = 1'd0;
+reg  litedramcore_cmd_payload_ras = 1'd0;
+reg  litedramcore_cmd_payload_we = 1'd0;
+reg  litedramcore_cmd_payload_is_read = 1'd0;
+reg  litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg  [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg  litedramcore_postponer_req_o = 1'd0;
+reg  litedramcore_postponer_count = 1'd0;
+reg  litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg  litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] litedramcore_sequencer_counter = 6'd0;
+reg  litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg  [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  litedramcore_zqcs_executer_start = 1'd0;
+reg  litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [20:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg  litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg  litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg  litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg  [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine0_row = 14'd0;
+reg  litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg  litedramcore_bankmachine0_row_open = 1'd0;
+reg  litedramcore_bankmachine0_row_close = 1'd0;
+reg  litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [20:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg  litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg  litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg  litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg  [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine1_row = 14'd0;
+reg  litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg  litedramcore_bankmachine1_row_open = 1'd0;
+reg  litedramcore_bankmachine1_row_close = 1'd0;
+reg  litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [20:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg  litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg  litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg  litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg  [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine2_row = 14'd0;
+reg  litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg  litedramcore_bankmachine2_row_open = 1'd0;
+reg  litedramcore_bankmachine2_row_close = 1'd0;
+reg  litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [20:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg  litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg  litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg  litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg  [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine3_row = 14'd0;
+reg  litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg  litedramcore_bankmachine3_row_open = 1'd0;
+reg  litedramcore_bankmachine3_row_close = 1'd0;
+reg  litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [20:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg  litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg  litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg  litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg  [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine4_row = 14'd0;
+reg  litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg  litedramcore_bankmachine4_row_open = 1'd0;
+reg  litedramcore_bankmachine4_row_close = 1'd0;
+reg  litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [20:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg  litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg  litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg  litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg  [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine5_row = 14'd0;
+reg  litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg  litedramcore_bankmachine5_row_open = 1'd0;
+reg  litedramcore_bankmachine5_row_close = 1'd0;
+reg  litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [20:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg  litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg  litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg  litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg  [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine6_row = 14'd0;
+reg  litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg  litedramcore_bankmachine6_row_open = 1'd0;
+reg  litedramcore_bankmachine6_row_close = 1'd0;
+reg  litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [20:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg  litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg  litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg  litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg  [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine7_row = 14'd0;
+reg  litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg  litedramcore_bankmachine7_row_open = 1'd0;
+reg  litedramcore_bankmachine7_row_close = 1'd0;
+reg  litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg  litedramcore_choose_cmd_want_reads = 1'd0;
+reg  litedramcore_choose_cmd_want_writes = 1'd0;
+reg  litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg  litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg  litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg  [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg  litedramcore_choose_req_want_reads = 1'd0;
+reg  litedramcore_choose_req_want_writes = 1'd0;
+reg  litedramcore_choose_req_want_cmds = 1'd0;
+reg  litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg  litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg  litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg  [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg  [13:0] litedramcore_nop_a = 14'd0;
+reg  [2:0] litedramcore_nop_ba = 3'd0;
+reg  [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg  litedramcore_steerer0 = 1'd1;
+reg  litedramcore_steerer1 = 1'd1;
+reg  litedramcore_steerer2 = 1'd1;
+reg  litedramcore_steerer3 = 1'd1;
+reg  litedramcore_steerer4 = 1'd1;
+reg  litedramcore_steerer5 = 1'd1;
+reg  litedramcore_steerer6 = 1'd1;
+reg  litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_trrdcon_ready = 1'd0;
+reg  litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg  [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tccdcon_ready = 1'd0;
+reg  litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg  litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg  [4:0] litedramcore_time0 = 5'd0;
+reg  litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg  [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg  init_done_storage = 1'd0;
+reg  init_done_re = 1'd0;
+reg  init_error_storage = 1'd0;
+reg  init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [23:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg  [13:0] litedramcore_adr = 14'd0;
+reg  litedramcore_we = 1'd0;
+reg  [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg  [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg  litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg  litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg  [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg  csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg  csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg  csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg  csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg  [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg  csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg  csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg  csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg  csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg  csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg  csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg  csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg  csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg  csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg  csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg  csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg  csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg  [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg  csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg  csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg  csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg  csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg  csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_r;
+reg  csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_w;
+reg  csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg  csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg  csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg  csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg  csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg  csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg  csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg  csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg  csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_r;
+reg  csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_w;
+reg  csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg  csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg  csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg  csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg  csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg  csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg  csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg  csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg  csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_r;
+reg  csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_w;
+reg  csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg  csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg  csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg  csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg  csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg  csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg  csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg  csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg  csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_r;
+reg  csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_w;
+reg  csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg  csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg  csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg  csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg  csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg  csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg  [1:0] litedramcore_refresher_state = 2'd0;
+reg  [1:0] litedramcore_refresher_next_state = 2'd0;
+reg  [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg  litedramcore_locked0 = 1'd0;
+reg  litedramcore_locked1 = 1'd0;
+reg  litedramcore_locked2 = 1'd0;
+reg  litedramcore_locked3 = 1'd0;
+reg  litedramcore_locked4 = 1'd0;
+reg  litedramcore_locked5 = 1'd0;
+reg  litedramcore_locked6 = 1'd0;
+reg  litedramcore_locked7 = 1'd0;
+reg  litedramcore_new_master_wdata_ready0 = 1'd0;
+reg  litedramcore_new_master_wdata_ready1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid0 = 1'd0;
+reg  litedramcore_new_master_rdata_valid1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid2 = 1'd0;
+reg  litedramcore_new_master_rdata_valid3 = 1'd0;
+reg  litedramcore_new_master_rdata_valid4 = 1'd0;
+reg  litedramcore_new_master_rdata_valid5 = 1'd0;
+reg  litedramcore_new_master_rdata_valid6 = 1'd0;
+reg  litedramcore_new_master_rdata_valid7 = 1'd0;
+reg  litedramcore_new_master_rdata_valid8 = 1'd0;
+reg  [1:0] litedramcore_state = 2'd0;
+reg  [1:0] litedramcore_next_state = 2'd0;
+reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg  litedramcore_adr_next_value_ce1 = 1'd0;
+reg  litedramcore_we_next_value2 = 1'd0;
+reg  litedramcore_we_next_value_ce2 = 1'd0;
+reg  rhs_array_muxed0 = 1'd0;
+reg  [13:0] rhs_array_muxed1 = 14'd0;
+reg  [2:0] rhs_array_muxed2 = 3'd0;
+reg  rhs_array_muxed3 = 1'd0;
+reg  rhs_array_muxed4 = 1'd0;
+reg  rhs_array_muxed5 = 1'd0;
+reg  t_array_muxed0 = 1'd0;
+reg  t_array_muxed1 = 1'd0;
+reg  t_array_muxed2 = 1'd0;
+reg  rhs_array_muxed6 = 1'd0;
+reg  [13:0] rhs_array_muxed7 = 14'd0;
+reg  [2:0] rhs_array_muxed8 = 3'd0;
+reg  rhs_array_muxed9 = 1'd0;
+reg  rhs_array_muxed10 = 1'd0;
+reg  rhs_array_muxed11 = 1'd0;
+reg  t_array_muxed3 = 1'd0;
+reg  t_array_muxed4 = 1'd0;
+reg  t_array_muxed5 = 1'd0;
+reg  [20:0] rhs_array_muxed12 = 21'd0;
+reg  rhs_array_muxed13 = 1'd0;
+reg  rhs_array_muxed14 = 1'd0;
+reg  [20:0] rhs_array_muxed15 = 21'd0;
+reg  rhs_array_muxed16 = 1'd0;
+reg  rhs_array_muxed17 = 1'd0;
+reg  [20:0] rhs_array_muxed18 = 21'd0;
+reg  rhs_array_muxed19 = 1'd0;
+reg  rhs_array_muxed20 = 1'd0;
+reg  [20:0] rhs_array_muxed21 = 21'd0;
+reg  rhs_array_muxed22 = 1'd0;
+reg  rhs_array_muxed23 = 1'd0;
+reg  [20:0] rhs_array_muxed24 = 21'd0;
+reg  rhs_array_muxed25 = 1'd0;
+reg  rhs_array_muxed26 = 1'd0;
+reg  [20:0] rhs_array_muxed27 = 21'd0;
+reg  rhs_array_muxed28 = 1'd0;
+reg  rhs_array_muxed29 = 1'd0;
+reg  [20:0] rhs_array_muxed30 = 21'd0;
+reg  rhs_array_muxed31 = 1'd0;
+reg  rhs_array_muxed32 = 1'd0;
+reg  [20:0] rhs_array_muxed33 = 21'd0;
+reg  rhs_array_muxed34 = 1'd0;
+reg  rhs_array_muxed35 = 1'd0;
+reg  [2:0] array_muxed0 = 3'd0;
+reg  [13:0] array_muxed1 = 14'd0;
+reg  array_muxed2 = 1'd0;
+reg  array_muxed3 = 1'd0;
+reg  array_muxed4 = 1'd0;
+reg  array_muxed5 = 1'd0;
+reg  array_muxed6 = 1'd0;
+reg  [2:0] array_muxed7 = 3'd0;
+reg  [13:0] array_muxed8 = 14'd0;
+reg  array_muxed9 = 1'd0;
+reg  array_muxed10 = 1'd0;
+reg  array_muxed11 = 1'd0;
+reg  array_muxed12 = 1'd0;
+reg  array_muxed13 = 1'd0;
+reg  [2:0] array_muxed14 = 3'd0;
+reg  [13:0] array_muxed15 = 14'd0;
+reg  array_muxed16 = 1'd0;
+reg  array_muxed17 = 1'd0;
+reg  array_muxed18 = 1'd0;
+reg  array_muxed19 = 1'd0;
+reg  array_muxed20 = 1'd0;
+reg  [2:0] array_muxed21 = 3'd0;
+reg  [13:0] array_muxed22 = 14'd0;
+reg  array_muxed23 = 1'd0;
+reg  array_muxed24 = 1'd0;
+reg  array_muxed25 = 1'd0;
+reg  array_muxed26 = 1'd0;
+reg  array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = main_init_done_storage;
-assign init_error = main_init_error_storage;
-assign main_wb_bus_adr = wb_ctrl_adr;
-assign main_wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = main_wb_bus_dat_r;
-assign main_wb_bus_sel = wb_ctrl_sel;
-assign main_wb_bus_cyc = wb_ctrl_cyc;
-assign main_wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = main_wb_bus_ack;
-assign main_wb_bus_we = wb_ctrl_we;
-assign main_wb_bus_cti = wb_ctrl_cti;
-assign main_wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = main_wb_bus_err;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_enable = 1'd1;
-assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
-assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
-assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
-assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
-assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
-assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
-assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = (rst | main_rst);
-assign pll_locked = main_locked;
-assign main_clkin = clk;
-assign iodelay_clk = main_clkout_buf0;
-assign sys_clk = main_clkout_buf1;
-assign sys4x_clk = main_clkout_buf2;
-assign sys4x_dqs_clk = main_clkout_buf3;
-assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
-assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-always @(*) begin
-	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
-	main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
-	main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
-	main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
-	main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
-	main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
-	main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
-	main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
-	main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
-	main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
-	main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
-	main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
-	main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
-	main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
-	main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
-	main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
-	main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
-	main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
-	main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
-	main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
-	main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
-	main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
-	main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
-	main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
-	main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
-	main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
-	main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
-	main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
-	main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
-	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
-	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
-	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
-	main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
-	main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
-	main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
-	main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
-	main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
-	main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
-	main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
-	main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
-	main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
-	main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
-	main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
-	main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
-	main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
-	main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
-	main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
-	main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
-	main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
-	main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
-	main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
-	main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
-	main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
-	main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
-	main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
-	main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
-	main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
-	main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
-	main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
-	main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
-	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
-	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
-	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
-	main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
-	main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
-	main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
-	main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
-	main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
-	main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
-	main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
-	main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
-	main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
-	main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
-	main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
-	main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
-	main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
-	main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
-	main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
-	main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
-	main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
-	main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
-	main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
-	main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
-	main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
-	main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
-	main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
-	main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
-	main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
-	main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
-	main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
-	main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
-	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
-	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
-	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
-	main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
-	main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
-	main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
-	main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
-	main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
-	main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
-	main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
-	main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
-	main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
-	main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
-	main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
-	main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
-	main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
-	main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
-	main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
-	main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
-	main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
-	main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
-	main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
-	main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
-	main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
-	main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
-	main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
-	main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
-	main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
-	main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
-	main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
-	main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
-	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
-	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
-	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-end
-assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-	main_a7ddrphy_dqs_oe <= 1'd0;
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqs_oe <= 1'd1;
-	end else begin
-		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
-	end
-end
-assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-always @(*) begin
-	main_a7ddrphy_dqspattern_o0 <= 8'd0;
-	main_a7ddrphy_dqspattern_o0 <= 7'd85;
-	if (main_a7ddrphy_dqspattern0) begin
-		main_a7ddrphy_dqspattern_o0 <= 5'd21;
-	end
-	if (main_a7ddrphy_dqspattern1) begin
-		main_a7ddrphy_dqspattern_o0 <= 7'd84;
-	end
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqspattern_o0 <= 1'd0;
-		if (main_a7ddrphy_wlevel_strobe_re) begin
-			main_a7ddrphy_dqspattern_o0 <= 1'd1;
-		end
-	end
-end
-always @(*) begin
-	main_a7ddrphy_bitslip00 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value0)
+assign user_enable = 1'd1;
+assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
+assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
+assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
+assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign reset = (rst | rst_1);
+assign pll_locked = locked;
+assign clkin = clk;
+assign iodelay_clk = clkout_buf0;
+assign sys_clk = clkout_buf1;
+assign sys4x_clk = clkout_buf2;
+assign sys4x_dqs_clk = clkout_buf3;
+assign ddram_ba = a7ddrphy_pads_ba;
+assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
+assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
+always @(*) begin
+	a7ddrphy_dfi_p0_rddata <= 32'd0;
+	a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+	a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+	a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+	a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+	a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+	a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+	a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+	a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+	a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+	a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+	a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+	a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+	a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+	a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+	a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+	a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+	a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+	a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+	a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+	a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+	a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+	a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+	a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+	a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+	a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+	a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+	a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+	a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+	a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+	a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+	a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+	a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+	a7ddrphy_dfi_p1_rddata <= 32'd0;
+	a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+	a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+	a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+	a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+	a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+	a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+	a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+	a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+	a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+	a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+	a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+	a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+	a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+	a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+	a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+	a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+	a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+	a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+	a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+	a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+	a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+	a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+	a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+	a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+	a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+	a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+	a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+	a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+	a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+	a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+	a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+	a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+	a7ddrphy_dfi_p2_rddata <= 32'd0;
+	a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+	a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+	a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+	a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+	a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+	a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+	a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+	a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+	a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+	a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+	a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+	a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+	a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+	a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+	a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+	a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+	a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+	a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+	a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+	a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+	a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+	a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+	a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+	a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+	a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+	a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+	a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+	a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+	a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+	a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+	a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+	a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+	a7ddrphy_dfi_p3_rddata <= 32'd0;
+	a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+	a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+	a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+	a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+	a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+	a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+	a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+	a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+	a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+	a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+	a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+	a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+	a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+	a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+	a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+	a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+	a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+	a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+	a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+	a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+	a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+	a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+	a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+	a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+	a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+	a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+	a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+	a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+	a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+	a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+	a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+	a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+end
+assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+	a7ddrphy_dqs_oe <= 1'd0;
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqs_oe <= 1'd1;
+	end else begin
+		a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+	end
+end
+assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+always @(*) begin
+	a7ddrphy_dqspattern_o0 <= 8'd0;
+	a7ddrphy_dqspattern_o0 <= 7'd85;
+	if (a7ddrphy_dqspattern0) begin
+		a7ddrphy_dqspattern_o0 <= 5'd21;
+	end
+	if (a7ddrphy_dqspattern1) begin
+		a7ddrphy_dqspattern_o0 <= 7'd84;
+	end
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqspattern_o0 <= 1'd0;
+		if (a7ddrphy_wlevel_strobe_re) begin
+			a7ddrphy_dqspattern_o0 <= 1'd1;
+		end
+	end
+end
+always @(*) begin
+	a7ddrphy_bitslip00 <= 8'd0;
+	case (a7ddrphy_bitslip0_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip10 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value0)
+	a7ddrphy_bitslip10 <= 8'd0;
+	case (a7ddrphy_bitslip1_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip01 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value1)
+	a7ddrphy_bitslip01 <= 8'd0;
+	case (a7ddrphy_bitslip0_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip11 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value1)
+	a7ddrphy_bitslip11 <= 8'd0;
+	case (a7ddrphy_bitslip1_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip02 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value2)
+	a7ddrphy_bitslip02 <= 8'd0;
+	case (a7ddrphy_bitslip0_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip04 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value3)
+	a7ddrphy_bitslip04 <= 8'd0;
+	case (a7ddrphy_bitslip0_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip12 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value2)
+	a7ddrphy_bitslip12 <= 8'd0;
+	case (a7ddrphy_bitslip1_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip14 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value3)
+	a7ddrphy_bitslip14 <= 8'd0;
+	case (a7ddrphy_bitslip1_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip20 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value0)
+	a7ddrphy_bitslip20 <= 8'd0;
+	case (a7ddrphy_bitslip2_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip22 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value1)
+	a7ddrphy_bitslip22 <= 8'd0;
+	case (a7ddrphy_bitslip2_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip30 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value0)
+	a7ddrphy_bitslip30 <= 8'd0;
+	case (a7ddrphy_bitslip3_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip32 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value1)
+	a7ddrphy_bitslip32 <= 8'd0;
+	case (a7ddrphy_bitslip3_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip40 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value0)
+	a7ddrphy_bitslip40 <= 8'd0;
+	case (a7ddrphy_bitslip4_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip42 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value1)
+	a7ddrphy_bitslip42 <= 8'd0;
+	case (a7ddrphy_bitslip4_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip50 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value0)
+	a7ddrphy_bitslip50 <= 8'd0;
+	case (a7ddrphy_bitslip5_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip52 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value1)
+	a7ddrphy_bitslip52 <= 8'd0;
+	case (a7ddrphy_bitslip5_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip60 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value0)
+	a7ddrphy_bitslip60 <= 8'd0;
+	case (a7ddrphy_bitslip6_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip62 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value1)
+	a7ddrphy_bitslip62 <= 8'd0;
+	case (a7ddrphy_bitslip6_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip70 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value0)
+	a7ddrphy_bitslip70 <= 8'd0;
+	case (a7ddrphy_bitslip7_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip72 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value1)
+	a7ddrphy_bitslip72 <= 8'd0;
+	case (a7ddrphy_bitslip7_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip80 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value0)
+	a7ddrphy_bitslip80 <= 8'd0;
+	case (a7ddrphy_bitslip8_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip82 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value1)
+	a7ddrphy_bitslip82 <= 8'd0;
+	case (a7ddrphy_bitslip8_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip90 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value0)
+	a7ddrphy_bitslip90 <= 8'd0;
+	case (a7ddrphy_bitslip9_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip92 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value1)
+	a7ddrphy_bitslip92 <= 8'd0;
+	case (a7ddrphy_bitslip9_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip100 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value0)
+	a7ddrphy_bitslip100 <= 8'd0;
+	case (a7ddrphy_bitslip10_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip102 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value1)
+	a7ddrphy_bitslip102 <= 8'd0;
+	case (a7ddrphy_bitslip10_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip110 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value0)
+	a7ddrphy_bitslip110 <= 8'd0;
+	case (a7ddrphy_bitslip11_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip112 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value1)
+	a7ddrphy_bitslip112 <= 8'd0;
+	case (a7ddrphy_bitslip11_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip120 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value0)
+	a7ddrphy_bitslip120 <= 8'd0;
+	case (a7ddrphy_bitslip12_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip122 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value1)
+	a7ddrphy_bitslip122 <= 8'd0;
+	case (a7ddrphy_bitslip12_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip130 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value0)
+	a7ddrphy_bitslip130 <= 8'd0;
+	case (a7ddrphy_bitslip13_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip132 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value1)
+	a7ddrphy_bitslip132 <= 8'd0;
+	case (a7ddrphy_bitslip13_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip140 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value0)
+	a7ddrphy_bitslip140 <= 8'd0;
+	case (a7ddrphy_bitslip14_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip142 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value1)
+	a7ddrphy_bitslip142 <= 8'd0;
+	case (a7ddrphy_bitslip14_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip150 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value0)
+	a7ddrphy_bitslip150 <= 8'd0;
+	case (a7ddrphy_bitslip15_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip152 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value1)
+	a7ddrphy_bitslip152 <= 8'd0;
+	case (a7ddrphy_bitslip15_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
-		end
-		1'd1: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
-		end
-		2'd2: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
-		end
-		2'd3: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
-		end
-		3'd4: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
-		end
-		3'd5: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
-		end
-		3'd6: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
-		end
-		3'd7: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
-		end
-	endcase
-end
-assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
-assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
-assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
-assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
-assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
-assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
-assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
-assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
-assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
-assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
-assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
-assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
-assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
-assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
-assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
-assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
-assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
-assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
-assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
-assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
-assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
-assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
-assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
-assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
-assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
-assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
-assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
-assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
-assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
-assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
-assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
-assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
-assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
-assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
-assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
-assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
-assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
-assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
-assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
-assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
-assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
-assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
-assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
-assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
-assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
-assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
-assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
-assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
-assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
-assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
-assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
-assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
-assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
-assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
-assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
-assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
-assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
-assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
-assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
-assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
-assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
-assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
-assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
-assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
-assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
-assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
-assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
-assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
-assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
-assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
-assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
-assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
-assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
-assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
-assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
-assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
-assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
-assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
-assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
-assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
-assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
-assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
-assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
-assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
-assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
-assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
-assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
-assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
-assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
-assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
-assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
-assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
-assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
-assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
-assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
-assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
-assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
-assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
-assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
-assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
-assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
-assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
-assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
-assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
-assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
-assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
-assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
-assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
-assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
-assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
-assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
-assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
-assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
-assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
-assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
-assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
-assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
-assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
-assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
-assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
-assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
-assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
-assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
-assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
-assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
-assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
-assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
-assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+		end
+		1'd1: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+		end
+		2'd2: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+		end
+		2'd3: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+		end
+		3'd4: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+		end
+		3'd5: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+		end
+		3'd6: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+		end
+		3'd7: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+		end
+	endcase
+end
+assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
+assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
+assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
+assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+	litedramcore_csr_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+	end
+end
 always @(*) begin
-	main_litedramcore_master_p3_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	litedramcore_csr_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
+		litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
+	litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
+		litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
+	litedramcore_csr_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
+		litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
+	litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
+		litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+	litedramcore_ext_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
+	litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
+	litedramcore_ext_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+		end else begin
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
+	litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	litedramcore_ext_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+		end else begin
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
+	litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
+	litedramcore_slave_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
+	litedramcore_slave_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
+	litedramcore_ext_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
+	litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_slave_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
+	litedramcore_slave_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_slave_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
+	litedramcore_slave_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
+	litedramcore_slave_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
+	litedramcore_slave_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
+	litedramcore_master_p0_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+		end else begin
+			litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+		end
 	end else begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
+		litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
+	litedramcore_master_p0_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+		end else begin
+			litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+		end
 	end else begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
+		litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+	litedramcore_master_p0_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+		end else begin
+			litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
+		litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
+	litedramcore_master_p0_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+		end else begin
+			litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
+		litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
+	litedramcore_master_p0_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+		end else begin
+			litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+		end
 	end else begin
+		litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
+	litedramcore_master_p0_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+		end else begin
+			litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
+		litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	litedramcore_master_p0_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+		end else begin
+			litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+		end
 	end else begin
+		litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
+	litedramcore_master_p0_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+		end else begin
+			litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+		end
 	end else begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
+		litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
+	litedramcore_master_p0_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+		end else begin
+			litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+		end
+	end else begin
+		litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+		end else begin
+			litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+		end
+	end else begin
+		litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+		end else begin
+			litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+		end
+	end else begin
+		litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+		end else begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+		end
+	end else begin
+		litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+		end else begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
+		litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
+	litedramcore_master_p0_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+		end else begin
+			litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
+		litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
+	litedramcore_master_p1_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+		end else begin
+			litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+		end
 	end else begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
+		litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
+	litedramcore_master_p1_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+		end else begin
+			litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
+		litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p1_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+		end else begin
+			litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
+		litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
+	litedramcore_master_p1_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+		end else begin
+			litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
+		litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p1_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+		end else begin
+			litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+		litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
+	litedramcore_master_p1_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+		end else begin
+			litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
+		litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
+	litedramcore_master_p1_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+		end else begin
+			litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+		end
 	end else begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
+		litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
+	litedramcore_master_p1_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+		end else begin
+			litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
+		litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
+	litedramcore_master_p1_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+		end else begin
+			litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
+		litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
+	litedramcore_master_p1_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+		end else begin
+			litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
+		litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+	litedramcore_master_p1_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+		end else begin
+			litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
+		litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
+	litedramcore_master_p1_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+		end else begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
+		litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
+	litedramcore_master_p1_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+		end else begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+		end
 	end else begin
+		litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
+	litedramcore_master_p1_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+		end else begin
+			litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
+		litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	litedramcore_master_p2_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+		end else begin
+			litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+		end
 	end else begin
+		litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
+	litedramcore_master_p2_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+		end else begin
+			litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+		end
 	end else begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
+		litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
+	litedramcore_master_p2_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+		end else begin
+			litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
+		litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
+	litedramcore_master_p2_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+		end else begin
+			litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
+		litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
+	litedramcore_master_p2_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+		end else begin
+			litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
+		litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+	litedramcore_master_p2_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+		end else begin
+			litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+		litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+		end else begin
+			litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+	litedramcore_master_p2_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+		end else begin
+			litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+		litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+		end else begin
+			litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
+	litedramcore_master_p2_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+		end else begin
+			litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
+		litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+		end else begin
+			litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
+		litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
+	litedramcore_master_p2_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+		end else begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+		litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+	litedramcore_master_p2_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+		end else begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+		litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
+	litedramcore_master_p2_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+		end else begin
+			litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
+		litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p3_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+		end else begin
+			litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+		litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
+	litedramcore_master_p3_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+		end else begin
+			litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+		end
 	end else begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
+		litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+	litedramcore_master_p3_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+		end else begin
+			litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
+		litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+	litedramcore_master_p3_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+		end else begin
+			litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
+		litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+	litedramcore_master_p3_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+		end else begin
+			litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+		end
 	end else begin
+		litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
+	litedramcore_master_p3_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+		end else begin
+			litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
+		litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	litedramcore_master_p3_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+		end else begin
+			litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+		end
 	end else begin
+		litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
+	litedramcore_master_p3_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+		end else begin
+			litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+		end
 	end else begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
+		litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
+	litedramcore_master_p3_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+		end else begin
+			litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
+		litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
+	litedramcore_master_p3_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+		end else begin
+			litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
+		litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
+	litedramcore_master_p3_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+		end else begin
+			litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
+		litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
+	litedramcore_master_p3_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+		end else begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
+		litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
+	litedramcore_master_p3_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+		end else begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
+		litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
+	litedramcore_master_p3_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+		end else begin
+			litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
+		litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
 	end
 end
-assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p2_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p3_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p0_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p1_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p2_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p3_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	litedramcore_csr_dfi_p0_we_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+	litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+	litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+	litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
-assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
-assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]);
-assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
-assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
-assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
+assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
+assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	litedramcore_csr_dfi_p1_we_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+	litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+	litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+	litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
-assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
-assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]);
-assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
-assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
-assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
+assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
+assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	litedramcore_csr_dfi_p2_we_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		litedramcore_csr_dfi_p2_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+	litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p2_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+	litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p2_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
-assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
-assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]);
-assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
-assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
-assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
+assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
+assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	litedramcore_csr_dfi_p3_we_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		litedramcore_csr_dfi_p3_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+	litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p3_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+	litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+	litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p3_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
-assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
-assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]);
-assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]);
-assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
-assign main_litedramcore_inti_p3_wrdata_mask = 1'd0;
-assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
-assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
-assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
-assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
-assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
-assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
-assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
-assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
-assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
-assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
-assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
-assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
-assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
-assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
-assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
-assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
-assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
-assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
-assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
-assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
-assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
-assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
-assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
-assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
-assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
-assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
-assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
-assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
-assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
-assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
-assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
-assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
-assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
-assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
-assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
-assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
-assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
-assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
-assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
-assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
-assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
-assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
-assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
-assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
-assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
-assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
-assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
-assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
-assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
-assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
-assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
-assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
-assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
-assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
-assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
-assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
-assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
-assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
-assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
-assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
-assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
-assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
-assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
-assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
-assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
-assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
-assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
-assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
-assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-always @(*) begin
-	builder_refresher_next_state <= 2'd0;
-	builder_refresher_next_state <= builder_refresher_state;
-	case (builder_refresher_state)
-		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				builder_refresher_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					builder_refresher_next_state <= 2'd3;
+assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
+assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
+assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+always @(*) begin
+	litedramcore_refresher_next_state <= 2'd0;
+	litedramcore_refresher_next_state <= litedramcore_refresher_state;
+	case (litedramcore_refresher_state)
+		1'd1: begin
+			if (litedramcore_cmd_ready) begin
+				litedramcore_refresher_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_refresher_next_state <= 2'd3;
 				end else begin
-					builder_refresher_next_state <= 1'd0;
+					litedramcore_refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				builder_refresher_next_state <= 1'd0;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
-				if (main_litedramcore_wants_refresh) begin
-					builder_refresher_next_state <= 1'd1;
+				if (litedramcore_wants_refresh) begin
+					litedramcore_refresher_next_state <= 1'd1;
 				end
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_zqcs_executer_start <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
-			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_last <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+				end else begin
+					litedramcore_cmd_last <= 1'd1;
+				end
+			end
 		end
 		2'd3: begin
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_last <= 1'd1;
+			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_sequencer_start0 <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_cmd_ready) begin
+				litedramcore_sequencer_start0 <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
-				end
-			end
 		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
-			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_valid <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
+			litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
 				end else begin
+					litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_valid <= 1'd0;
+			end
 		end
 		default: begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
-assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
-assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+	litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+		litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
-assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
-assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+	litedramcore_bankmachine0_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+	litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine0_next_state <= 4'd0;
-	builder_bankmachine0_next_state <= builder_bankmachine0_state;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_next_state <= 4'd0;
+	litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd7;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine0_refresh_req)) begin
-				builder_bankmachine0_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine0_refresh_req)) begin
+				litedramcore_bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine0_next_state <= 3'd6;
+			litedramcore_bankmachine0_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine0_next_state <= 2'd3;
+			litedramcore_bankmachine0_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine0_next_state <= 4'd8;
+			litedramcore_bankmachine0_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine0_next_state <= 1'd0;
+			litedramcore_bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-				builder_bankmachine0_next_state <= 3'd4;
+			if (litedramcore_bankmachine0_refresh_req) begin
+				litedramcore_bankmachine0_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
-								builder_bankmachine0_next_state <= 2'd2;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+								litedramcore_bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine0_next_state <= 1'd1;
+							litedramcore_bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine0_next_state <= 2'd3;
+						litedramcore_bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4333,18 +4752,82 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (litedramcore_bankmachine0_twtpcon_ready) begin
+				litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4358,12 +4841,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4374,15 +4857,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_open <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_open <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_open <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4400,18 +4883,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_close <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_close <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4426,8 +4909,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4445,12 +4928,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4461,18 +4944,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4490,11 +4973,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4512,13 +4995,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4531,15 +5014,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4557,22 +5040,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4587,8 +5070,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4606,14 +5089,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -4625,8 +5108,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4644,13 +5127,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4663,8 +5146,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4682,13 +5165,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -4700,38 +5183,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+		litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+always @(*) begin
+	litedramcore_bankmachine1_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine1_next_state <= 4'd0;
+	litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+	case (litedramcore_bankmachine1_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine1_refresh_req)) begin
+				litedramcore_bankmachine1_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+				litedramcore_bankmachine1_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+								litedramcore_bankmachine1_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4739,8 +5311,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4748,9 +5320,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -4761,149 +5330,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
-assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
-assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
-assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine1_next_state <= 4'd0;
-	builder_bankmachine1_next_state <= builder_bankmachine1_state;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				builder_bankmachine1_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine1_refresh_req)) begin
-				builder_bankmachine1_next_state <= 1'd0;
+			if (litedramcore_bankmachine1_twtpcon_ready) begin
+				litedramcore_bankmachine1_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-				builder_bankmachine1_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
-								builder_bankmachine1_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine1_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine1_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4917,12 +5400,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4933,15 +5416,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_open <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_open <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4959,18 +5442,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_close <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_close <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4985,8 +5468,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5004,12 +5487,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5020,18 +5503,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5049,11 +5532,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5071,13 +5554,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5090,15 +5573,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5116,22 +5599,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5146,8 +5629,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5165,14 +5648,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5184,8 +5667,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5203,13 +5686,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5222,8 +5705,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5241,13 +5724,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5259,38 +5742,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine1_state)
-		1'd1: begin
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+		litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+always @(*) begin
+	litedramcore_bankmachine2_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine2_next_state <= 4'd0;
+	litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine2_refresh_req)) begin
+				litedramcore_bankmachine2_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+				litedramcore_bankmachine2_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+								litedramcore_bankmachine2_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5298,8 +5870,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5307,9 +5879,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5320,149 +5889,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
-assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
-assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine2_next_state <= 4'd0;
-	builder_bankmachine2_next_state <= builder_bankmachine2_state;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				builder_bankmachine2_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine2_refresh_req)) begin
-				builder_bankmachine2_next_state <= 1'd0;
+			if (litedramcore_bankmachine2_twtpcon_ready) begin
+				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-				builder_bankmachine2_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
-								builder_bankmachine2_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine2_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine2_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5476,12 +5959,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5492,15 +5975,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_open <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_open <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_open <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5518,18 +6001,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_close <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_close <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5544,8 +6027,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5563,12 +6046,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5579,18 +6062,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5608,11 +6091,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5630,13 +6113,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5649,15 +6132,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5675,22 +6158,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5705,8 +6188,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5724,14 +6207,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5743,8 +6226,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5762,13 +6245,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5781,8 +6264,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5800,13 +6283,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5818,38 +6301,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+		litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+always @(*) begin
+	litedramcore_bankmachine3_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine3_next_state <= 4'd0;
+	litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+	case (litedramcore_bankmachine3_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine3_refresh_req)) begin
+				litedramcore_bankmachine3_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+				litedramcore_bankmachine3_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+								litedramcore_bankmachine3_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5857,8 +6429,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5866,9 +6438,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5879,149 +6448,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
-assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
-assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
-assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine3_next_state <= 4'd0;
-	builder_bankmachine3_next_state <= builder_bankmachine3_state;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				builder_bankmachine3_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine3_refresh_req)) begin
-				builder_bankmachine3_next_state <= 1'd0;
+			if (litedramcore_bankmachine3_twtpcon_ready) begin
+				litedramcore_bankmachine3_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-				builder_bankmachine3_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
-								builder_bankmachine3_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine3_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine3_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6035,12 +6518,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6051,15 +6534,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_open <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_open <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6077,18 +6560,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_close <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_close <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6103,8 +6586,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6122,12 +6605,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6138,18 +6621,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6167,11 +6650,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6189,13 +6672,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6208,15 +6691,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6234,22 +6717,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6264,8 +6747,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6283,14 +6766,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6302,8 +6785,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6321,13 +6804,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6340,8 +6823,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6359,13 +6842,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -6377,38 +6860,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+		litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+always @(*) begin
+	litedramcore_bankmachine4_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine4_next_state <= 4'd0;
+	litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine4_refresh_req)) begin
+				litedramcore_bankmachine4_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+				litedramcore_bankmachine4_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+								litedramcore_bankmachine4_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6416,8 +6988,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6425,9 +6997,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6438,149 +7007,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
-assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
-assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
-assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine4_next_state <= 4'd0;
-	builder_bankmachine4_next_state <= builder_bankmachine4_state;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				builder_bankmachine4_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine4_refresh_req)) begin
-				builder_bankmachine4_next_state <= 1'd0;
+			if (litedramcore_bankmachine4_twtpcon_ready) begin
+				litedramcore_bankmachine4_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine4_next_state <= 1'd0;
 		end
-		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-				builder_bankmachine4_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
-								builder_bankmachine4_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine4_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine4_next_state <= 2'd3;
-					end
-				end
-			end
+		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6594,12 +7077,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6610,15 +7093,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_open <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6636,18 +7119,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_close <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6662,8 +7145,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6681,12 +7164,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6697,18 +7180,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6726,11 +7209,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6748,13 +7231,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6767,15 +7250,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6793,22 +7276,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6823,8 +7306,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6842,14 +7325,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6861,8 +7344,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6880,13 +7363,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6899,8 +7382,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6918,13 +7401,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -6936,38 +7419,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+		litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+always @(*) begin
+	litedramcore_bankmachine5_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine5_next_state <= 4'd0;
+	litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+	case (litedramcore_bankmachine5_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine5_refresh_req)) begin
+				litedramcore_bankmachine5_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+				litedramcore_bankmachine5_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+								litedramcore_bankmachine5_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6975,8 +7547,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6984,9 +7556,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6997,149 +7566,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
-assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
-assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
-assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine5_next_state <= 4'd0;
-	builder_bankmachine5_next_state <= builder_bankmachine5_state;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				builder_bankmachine5_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-				builder_bankmachine5_next_state <= 1'd0;
+			if (litedramcore_bankmachine5_twtpcon_ready) begin
+				litedramcore_bankmachine5_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-				builder_bankmachine5_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-								builder_bankmachine5_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine5_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine5_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7153,12 +7636,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7169,15 +7652,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_open <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_open <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_open <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7195,18 +7678,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_close <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_close <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7221,8 +7704,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7240,12 +7723,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7256,18 +7739,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7285,11 +7768,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7307,13 +7790,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7326,15 +7809,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7352,22 +7835,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7382,8 +7865,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7401,14 +7884,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7420,8 +7903,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7439,13 +7922,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7458,8 +7941,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7477,13 +7960,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -7495,38 +7978,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+	litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+		litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+always @(*) begin
+	litedramcore_bankmachine6_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine6_next_state <= 4'd0;
+	litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+	case (litedramcore_bankmachine6_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine6_refresh_req)) begin
+				litedramcore_bankmachine6_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+				litedramcore_bankmachine6_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+								litedramcore_bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7534,8 +8106,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7543,9 +8115,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7556,149 +8125,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
-assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
-assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
-assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine6_next_state <= 4'd0;
-	builder_bankmachine6_next_state <= builder_bankmachine6_state;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				builder_bankmachine6_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine6_refresh_req)) begin
-				builder_bankmachine6_next_state <= 1'd0;
+			if (litedramcore_bankmachine6_twtpcon_ready) begin
+				litedramcore_bankmachine6_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-				builder_bankmachine6_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
-								builder_bankmachine6_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine6_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine6_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7712,12 +8195,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7728,15 +8211,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_open <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7754,18 +8237,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_close <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7780,8 +8263,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7799,12 +8282,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7815,18 +8298,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7844,11 +8327,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7866,13 +8349,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7885,15 +8368,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7911,22 +8394,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7941,8 +8424,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7960,14 +8443,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7979,8 +8462,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7998,13 +8481,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8017,8 +8500,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8036,13 +8519,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -8054,38 +8537,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine6_state)
-		1'd1: begin
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+	litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+		litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+always @(*) begin
+	litedramcore_bankmachine7_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine7_next_state <= 4'd0;
+	litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+	case (litedramcore_bankmachine7_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine7_refresh_req)) begin
+				litedramcore_bankmachine7_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+				litedramcore_bankmachine7_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+								litedramcore_bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8093,8 +8665,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8102,9 +8674,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8115,149 +8684,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
-assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
-assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
-assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine7_next_state <= 4'd0;
-	builder_bankmachine7_next_state <= builder_bankmachine7_state;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				builder_bankmachine7_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine7_refresh_req)) begin
-				builder_bankmachine7_next_state <= 1'd0;
+			if (litedramcore_bankmachine7_twtpcon_ready) begin
+				litedramcore_bankmachine7_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-				builder_bankmachine7_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
-								builder_bankmachine7_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine7_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine7_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8271,12 +8754,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8287,15 +8770,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_open <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_open <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_open <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8313,18 +8796,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_close <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_close <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8339,8 +8822,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8358,12 +8841,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8374,18 +8857,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8403,11 +8886,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -8425,13 +8908,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8444,15 +8927,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8470,45 +8953,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
+			litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8519,27 +8979,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8557,14 +9002,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8576,8 +9021,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8595,13 +9040,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8614,8 +9059,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8633,14 +9078,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -8651,288 +9096,266 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
+assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
 always @(*) begin
-	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
-assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
-assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
-assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
-assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
-assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
-assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
-assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
-assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
-assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
-assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
-assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-always @(*) begin
-	main_litedramcore_choose_cmd_valids <= 8'd0;
-	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids <= 8'd0;
+	litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
 end
-assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
-assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
-assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
-assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
-assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
-assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
-assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
+	litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
+	litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
+	litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	litedramcore_bankmachine0_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	litedramcore_bankmachine1_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	litedramcore_bankmachine2_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	litedramcore_bankmachine3_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	litedramcore_bankmachine4_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	litedramcore_bankmachine5_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	litedramcore_bankmachine6_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	litedramcore_bankmachine7_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
 end
-assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-	main_litedramcore_choose_req_valids <= 8'd0;
-	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids <= 8'd0;
+	litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
 end
-assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
-assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
-assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
-assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
-assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
-assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
-assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
+	litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
+	litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
+	litedramcore_choose_req_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
 	end
 end
-assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
-assign main_litedramcore_dfi_p0_reset_n = 1'd1;
-assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}};
-assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}};
-assign main_litedramcore_dfi_p1_reset_n = 1'd1;
-assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}};
-assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}};
-assign main_litedramcore_dfi_p2_reset_n = 1'd1;
-assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}};
-assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}};
-assign main_litedramcore_dfi_p3_reset_n = 1'd1;
-assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
-assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
-assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
 always @(*) begin
-	builder_multiplexer_next_state <= 4'd0;
-	builder_multiplexer_next_state <= builder_multiplexer_state;
-	case (builder_multiplexer_state)
+	litedramcore_multiplexer_next_state <= 4'd0;
+	litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (main_litedramcore_read_available) begin
-				if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
-					builder_multiplexer_next_state <= 2'd3;
+			if (litedramcore_read_available) begin
+				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+					litedramcore_multiplexer_next_state <= 2'd3;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
-			if (main_litedramcore_cmd_last) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_cmd_last) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_twtrcon_ready) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_twtrcon_ready) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			builder_multiplexer_next_state <= 3'd5;
+			litedramcore_multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			builder_multiplexer_next_state <= 3'd6;
+			litedramcore_multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_multiplexer_next_state <= 3'd7;
+			litedramcore_multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			builder_multiplexer_next_state <= 4'd8;
+			litedramcore_multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_multiplexer_next_state <= 4'd9;
+			litedramcore_multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			builder_multiplexer_next_state <= 4'd10;
+			litedramcore_multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			builder_multiplexer_next_state <= 1'd1;
+			litedramcore_multiplexer_next_state <= 1'd1;
 		end
 		default: begin
-			if (main_litedramcore_write_available) begin
-				if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
-					builder_multiplexer_next_state <= 3'd4;
+			if (litedramcore_write_available) begin
+				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+					litedramcore_multiplexer_next_state <= 3'd4;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel0 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 		2'd2: begin
+			litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -8951,26 +9374,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -8989,20 +9409,20 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel1 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -9023,17 +9443,26 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel2 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9055,17 +9484,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_want_activates <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -9086,15 +9522,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel3 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -9115,18 +9560,20 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en0 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -9147,19 +9594,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			litedramcore_en0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -9180,23 +9626,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel0 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_reads <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
 		end
 		2'd2: begin
-			main_litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -9215,23 +9657,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
+			litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_writes <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -9254,15 +9690,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
 			end
 		end
 		2'd2: begin
@@ -9284,27 +9718,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel2 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en1 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
+			litedramcore_en1 <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9325,1994 +9751,2011 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
 		end
 	endcase
 end
-assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
-assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12;
-assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13;
-assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14;
-assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
-assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15;
-assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16;
-assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17;
-assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
-assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18;
-assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19;
-assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20;
-assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
-assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21;
-assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22;
-assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23;
-assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
-assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24;
-assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25;
-assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26;
-assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
-assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27;
-assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28;
-assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29;
-assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
-assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30;
-assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31;
-assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32;
-assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
-assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33;
-assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34;
-assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
-assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
-assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
-assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
+assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
 always @(*) begin
-	main_litedramcore_interface_wdata <= 128'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata <= 128'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			litedramcore_interface_wdata <= user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 16'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata_we <= 16'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 end
-assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
-assign builder_roundrobin0_grant = 1'd0;
-assign builder_roundrobin1_grant = 1'd0;
-assign builder_roundrobin2_grant = 1'd0;
-assign builder_roundrobin3_grant = 1'd0;
-assign builder_roundrobin4_grant = 1'd0;
-assign builder_roundrobin5_grant = 1'd0;
-assign builder_roundrobin6_grant = 1'd0;
-assign builder_roundrobin7_grant = 1'd0;
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-	builder_next_state <= 2'd0;
-	builder_next_state <= builder_state;
-	case (builder_state)
+	litedramcore_next_state <= 2'd0;
+	litedramcore_next_state <= litedramcore_state;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_next_state <= 2'd2;
+			litedramcore_next_state <= 2'd2;
 		end
 		2'd2: begin
-			builder_next_state <= 1'd0;
+			litedramcore_next_state <= 1'd0;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_next_state <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 32'd0;
-	case (builder_state)
+	litedramcore_we_next_value2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
-	case (builder_state)
+	litedramcore_we_next_value_ce2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_ack <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value1 <= 14'd0;
-	case (builder_state)
+	litedramcore_wishbone_dat_r <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value2 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
-			end
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value_ce2 <= 1'd0;
-	case (builder_state)
+	litedramcore_adr_next_value1 <= 14'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value_ce2 <= 1'd1;
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value_ce2 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_dat_r <= 32'd0;
-	case (builder_state)
+	litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
 		end
 	endcase
 end
-assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
-assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
-assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r;
-assign builder_litedramcore_wishbone_sel = main_wb_bus_sel;
-assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc;
-assign builder_litedramcore_wishbone_stb = main_wb_bus_stb;
-assign main_wb_bus_ack = builder_litedramcore_wishbone_ack;
-assign builder_litedramcore_wishbone_we = main_wb_bus_we;
-assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
-assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
-assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
-assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_done0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_done0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_re <= interface0_bank_bus_we;
 	end
 end
-assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_error0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_error0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
-assign builder_csrbank0_init_done0_w = main_init_done_storage;
-assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
-assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rst0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rst0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+	csrbank1_dly_sel0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_dly_sel0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_half_sys8x_taps0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+	csrbank1_half_sys8x_taps0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wlevel_en0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+	csrbank1_wlevel_en0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wlevel_strobe_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wlevel_strobe_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rdphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rdphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wrphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_wrphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
-assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
-assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
+assign csrbank1_rst0_w = a7ddrphy_rst_storage;
+assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
+assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
+assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
+assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
+assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_control0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_control0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_sel = main_litedramcore_storage[0];
-assign main_litedramcore_cke = main_litedramcore_storage[1];
-assign main_litedramcore_odt = main_litedramcore_storage[2];
-assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
-assign builder_csr_interconnect_adr = builder_litedramcore_adr;
-assign builder_csr_interconnect_we = builder_litedramcore_we;
-assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
-assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r;
-assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-always @(*) begin
-	builder_rhs_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+assign litedramcore_sel = litedramcore_storage[0];
+assign litedramcore_cke = litedramcore_storage[1];
+assign litedramcore_odt = litedramcore_storage[2];
+assign litedramcore_reset_n = litedramcore_storage[3];
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
+assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
+assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
+assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
+assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
+assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
+assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
+assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
+assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
+assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
+assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
+assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
+assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
+assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
+assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
+assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
+assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
+assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
+assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
+assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
+assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
+assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
+assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
+assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
+assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
+assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
+assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
+assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
+assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
+assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
+assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
+assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
+assign csr_interconnect_adr = litedramcore_adr;
+assign csr_interconnect_we = litedramcore_we;
+assign csr_interconnect_dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = csr_interconnect_dat_r;
+assign interface0_bank_bus_adr = csr_interconnect_adr;
+assign interface1_bank_bus_adr = csr_interconnect_adr;
+assign interface2_bank_bus_adr = csr_interconnect_adr;
+assign interface0_bank_bus_we = csr_interconnect_we;
+assign interface1_bank_bus_we = csr_interconnect_we;
+assign interface2_bank_bus_we = csr_interconnect_we;
+assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
+assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+always @(*) begin
+	rhs_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed1 <= 14'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed1 <= 14'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed2 <= 3'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed2 <= 3'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed1 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed1 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed2 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed2 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed6 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed6 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed7 <= 14'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed7 <= 14'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed8 <= 3'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed8 <= 3'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed9 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed9 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed10 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed10 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed11 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed11 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed12 <= 21'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed12 <= 21'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed13 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed13 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed13 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed14 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed14 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed15 <= 21'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed15 <= 21'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed16 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed16 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed16 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed17 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed17 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed18 <= 21'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed18 <= 21'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed19 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed19 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed19 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed20 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed20 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed21 <= 21'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed21 <= 21'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed22 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed22 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed22 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed23 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed23 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed24 <= 21'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed24 <= 21'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed25 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed25 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed25 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed26 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed26 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed27 <= 21'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed27 <= 21'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed28 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed28 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed28 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed29 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed29 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed30 <= 21'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed30 <= 21'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed31 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed31 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed31 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed32 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed32 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed33 <= 21'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed33 <= 21'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed34 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed34 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed34 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed35 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed35 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed0 <= 3'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed0 <= 3'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed0 <= main_litedramcore_nop_ba[2:0];
+			array_muxed0 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed1 <= 14'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed1 <= 14'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed1 <= main_litedramcore_nop_a;
+			array_muxed1 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
+			array_muxed1 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed2 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed2 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed2 <= 1'd0;
+			array_muxed2 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed3 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed3 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed3 <= 1'd0;
+			array_muxed3 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed4 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed4 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed4 <= 1'd0;
+			array_muxed4 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed5 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed5 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed5 <= 1'd0;
+			array_muxed5 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed6 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed6 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed6 <= 1'd0;
+			array_muxed6 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed7 <= 3'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed7 <= 3'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed7 <= main_litedramcore_nop_ba[2:0];
+			array_muxed7 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed8 <= 14'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed8 <= 14'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed8 <= main_litedramcore_nop_a;
+			array_muxed8 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
+			array_muxed8 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed9 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed9 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed9 <= 1'd0;
+			array_muxed9 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed10 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed10 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed10 <= 1'd0;
+			array_muxed10 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed11 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed11 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed11 <= 1'd0;
+			array_muxed11 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed12 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed12 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed12 <= 1'd0;
+			array_muxed12 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed13 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed13 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed13 <= 1'd0;
+			array_muxed13 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed14 <= 3'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed14 <= 3'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed14 <= main_litedramcore_nop_ba[2:0];
+			array_muxed14 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed15 <= 14'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed15 <= 14'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed15 <= main_litedramcore_nop_a;
+			array_muxed15 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
+			array_muxed15 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed16 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed16 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed16 <= 1'd0;
+			array_muxed16 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed17 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed17 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed17 <= 1'd0;
+			array_muxed17 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed18 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed18 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed18 <= 1'd0;
+			array_muxed18 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed19 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed19 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed19 <= 1'd0;
+			array_muxed19 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed20 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed20 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed20 <= 1'd0;
+			array_muxed20 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed21 <= 3'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed21 <= 3'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed21 <= main_litedramcore_nop_ba[2:0];
+			array_muxed21 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed22 <= 14'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed22 <= 14'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed22 <= main_litedramcore_nop_a;
+			array_muxed22 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
+			array_muxed22 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed23 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed23 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed23 <= 1'd0;
+			array_muxed23 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed24 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed24 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed24 <= 1'd0;
+			array_muxed24 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed25 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed25 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed25 <= 1'd0;
+			array_muxed25 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed26 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed26 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed26 <= 1'd0;
+			array_muxed26 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed27 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed27 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed27 <= 1'd0;
+			array_muxed27 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
+assign xilinxasyncresetsynchronizerimpl0 = (~locked);
+assign xilinxasyncresetsynchronizerimpl1 = (~locked);
+assign xilinxasyncresetsynchronizerimpl2 = (~locked);
+assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 
 
 //------------------------------------------------------------------------------
@@ -11320,1044 +11763,1044 @@ assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-	if ((main_reset_counter != 1'd0)) begin
-		main_reset_counter <= (main_reset_counter - 1'd1);
+	if ((reset_counter != 1'd0)) begin
+		reset_counter <= (reset_counter - 1'd1);
 	end else begin
-		main_ic_reset <= 1'd0;
+		ic_reset <= 1'd0;
 	end
 	if (iodelay_rst) begin
-		main_reset_counter <= 4'd15;
-		main_ic_reset <= 1'd1;
+		reset_counter <= 4'd15;
+		ic_reset <= 1'd1;
 	end
 end
 
 always @(posedge sys_clk) begin
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-	main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+	a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
+	a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
+	a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
+	a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
+	a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
+	a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
+	a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
+	a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
+	a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
+	a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
+	a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
+	a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
+	a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
+	a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
+	a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
+	a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
+	a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
+	a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
+	a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
+	a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
+	a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
+	a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
+	a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
+	a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
+	a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
+	a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
+	a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
+	a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
+	a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
+	a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
+	a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
+	a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
+	a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
+	a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
+	a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
+	a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
-	main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
-	main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
-	main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
-	main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
-	main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
-	main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
-	main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
-	main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
-	main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
-	main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
-	main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
-	if (main_litedramcore_inti_p0_rddata_valid) begin
-		main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata;
+	a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+	a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+	a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+	a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+	a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+	a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+	a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+	a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+	a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+	a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+	a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+	a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+	if (litedramcore_csr_dfi_p0_rddata_valid) begin
+		litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
 	end
-	if (main_litedramcore_inti_p1_rddata_valid) begin
-		main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata;
+	if (litedramcore_csr_dfi_p1_rddata_valid) begin
+		litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
 	end
-	if (main_litedramcore_inti_p2_rddata_valid) begin
-		main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata;
+	if (litedramcore_csr_dfi_p2_rddata_valid) begin
+		litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
 	end
-	if (main_litedramcore_inti_p3_rddata_valid) begin
-		main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata;
-	end
-	if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
-		main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
+	if (litedramcore_csr_dfi_p3_rddata_valid) begin
+		litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+	end
+	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_timer_count1 <= 10'd781;
+		litedramcore_timer_count1 <= 10'd781;
 	end
-	main_litedramcore_postponer_req_o <= 1'd0;
-	if (main_litedramcore_postponer_req_i) begin
-		main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
-		if ((main_litedramcore_postponer_count == 1'd0)) begin
-			main_litedramcore_postponer_count <= 1'd0;
-			main_litedramcore_postponer_req_o <= 1'd1;
-		end
+	litedramcore_postponer_req_o <= 1'd0;
+	if (litedramcore_postponer_req_i) begin
+		litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+		if ((litedramcore_postponer_count == 1'd0)) begin
+			litedramcore_postponer_count <= 1'd0;
+			litedramcore_postponer_req_o <= 1'd1;
+		end
 	end
-	if (main_litedramcore_sequencer_start0) begin
-		main_litedramcore_sequencer_count <= 1'd0;
-	end else begin
-		if (main_litedramcore_sequencer_done1) begin
-			if ((main_litedramcore_sequencer_count != 1'd0)) begin
-				main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
-			end
-		end
-	end
-	main_litedramcore_cmd_payload_a <= 1'd0;
-	main_litedramcore_cmd_payload_ba <= 1'd0;
-	main_litedramcore_cmd_payload_cas <= 1'd0;
-	main_litedramcore_cmd_payload_ras <= 1'd0;
-	main_litedramcore_cmd_payload_we <= 1'd0;
-	main_litedramcore_sequencer_done1 <= 1'd0;
-	if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd1;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd35)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd35)) begin
-		main_litedramcore_sequencer_counter <= 1'd0;
-	end else begin
-		if ((main_litedramcore_sequencer_counter != 1'd0)) begin
-			main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1);
+	if (litedramcore_sequencer_start0) begin
+		litedramcore_sequencer_count <= 1'd0;
+	end else begin
+		if (litedramcore_sequencer_done1) begin
+			if ((litedramcore_sequencer_count != 1'd0)) begin
+				litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+			end
+		end
+	end
+	litedramcore_cmd_payload_a <= 1'd0;
+	litedramcore_cmd_payload_ba <= 1'd0;
+	litedramcore_cmd_payload_cas <= 1'd0;
+	litedramcore_cmd_payload_ras <= 1'd0;
+	litedramcore_cmd_payload_we <= 1'd0;
+	litedramcore_sequencer_done1 <= 1'd0;
+	if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd1;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd0;
+	end
+	if ((litedramcore_sequencer_counter == 6'd35)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 6'd35)) begin
+		litedramcore_sequencer_counter <= 1'd0;
+	end else begin
+		if ((litedramcore_sequencer_counter != 1'd0)) begin
+			litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_sequencer_start1) begin
-				main_litedramcore_sequencer_counter <= 1'd1;
+			if (litedramcore_sequencer_start1) begin
+				litedramcore_sequencer_counter <= 1'd1;
 			end
 		end
 	end
-	if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
-		main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
+	if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+		litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
 	end
-	main_litedramcore_zqcs_executer_done <= 1'd0;
-	if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	litedramcore_zqcs_executer_done <= 1'd0;
+	if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_zqcs_executer_done <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_zqcs_executer_done <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_zqcs_executer_counter <= 1'd0;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_zqcs_executer_counter <= 1'd0;
 	end else begin
-		if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin
-			main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1);
+		if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+			litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_zqcs_executer_start) begin
-				main_litedramcore_zqcs_executer_counter <= 1'd1;
+			if (litedramcore_zqcs_executer_start) begin
+				litedramcore_zqcs_executer_counter <= 1'd1;
 			end
 		end
 	end
-	builder_refresher_state <= builder_refresher_next_state;
-	if (main_litedramcore_bankmachine0_row_close) begin
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
+	litedramcore_refresher_state <= litedramcore_refresher_next_state;
+	if (litedramcore_bankmachine0_row_close) begin
+		litedramcore_bankmachine0_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine0_row_open) begin
-			main_litedramcore_bankmachine0_row_opened <= 1'd1;
-			main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine0_row_open) begin
+			litedramcore_bankmachine0_row_opened <= 1'd1;
+			litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+		litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+		litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine0_twtpcon_valid) begin
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine0_twtpcon_valid) begin
+		litedramcore_bankmachine0_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
-			main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+			litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trccon_valid) begin
-		main_litedramcore_bankmachine0_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine0_trccon_valid) begin
+		litedramcore_bankmachine0_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+			litedramcore_bankmachine0_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+			litedramcore_bankmachine0_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
-			main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trccon_ready)) begin
+			litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trascon_valid) begin
-		main_litedramcore_bankmachine0_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine0_trascon_valid) begin
+		litedramcore_bankmachine0_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+			litedramcore_bankmachine0_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+			litedramcore_bankmachine0_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
-			main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trascon_ready)) begin
+			litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine0_state <= builder_bankmachine0_next_state;
-	if (main_litedramcore_bankmachine1_row_close) begin
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
+	litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+	if (litedramcore_bankmachine1_row_close) begin
+		litedramcore_bankmachine1_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine1_row_open) begin
-			main_litedramcore_bankmachine1_row_opened <= 1'd1;
-			main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine1_row_open) begin
+			litedramcore_bankmachine1_row_opened <= 1'd1;
+			litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+		litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+		litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine1_twtpcon_valid) begin
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine1_twtpcon_valid) begin
+		litedramcore_bankmachine1_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
-			main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+			litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trccon_valid) begin
-		main_litedramcore_bankmachine1_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine1_trccon_valid) begin
+		litedramcore_bankmachine1_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+			litedramcore_bankmachine1_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+			litedramcore_bankmachine1_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
-			main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trccon_ready)) begin
+			litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trascon_valid) begin
-		main_litedramcore_bankmachine1_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine1_trascon_valid) begin
+		litedramcore_bankmachine1_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+			litedramcore_bankmachine1_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+			litedramcore_bankmachine1_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
-			main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trascon_ready)) begin
+			litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine1_state <= builder_bankmachine1_next_state;
-	if (main_litedramcore_bankmachine2_row_close) begin
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
+	litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+	if (litedramcore_bankmachine2_row_close) begin
+		litedramcore_bankmachine2_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine2_row_open) begin
-			main_litedramcore_bankmachine2_row_opened <= 1'd1;
-			main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine2_row_open) begin
+			litedramcore_bankmachine2_row_opened <= 1'd1;
+			litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+		litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+		litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine2_twtpcon_valid) begin
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine2_twtpcon_valid) begin
+		litedramcore_bankmachine2_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
-			main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+			litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trccon_valid) begin
-		main_litedramcore_bankmachine2_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine2_trccon_valid) begin
+		litedramcore_bankmachine2_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+			litedramcore_bankmachine2_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+			litedramcore_bankmachine2_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
-			main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trccon_ready)) begin
+			litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trascon_valid) begin
-		main_litedramcore_bankmachine2_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine2_trascon_valid) begin
+		litedramcore_bankmachine2_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+			litedramcore_bankmachine2_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+			litedramcore_bankmachine2_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
-			main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trascon_ready)) begin
+			litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine2_state <= builder_bankmachine2_next_state;
-	if (main_litedramcore_bankmachine3_row_close) begin
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
+	litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+	if (litedramcore_bankmachine3_row_close) begin
+		litedramcore_bankmachine3_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine3_row_open) begin
-			main_litedramcore_bankmachine3_row_opened <= 1'd1;
-			main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine3_row_open) begin
+			litedramcore_bankmachine3_row_opened <= 1'd1;
+			litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+		litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+		litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine3_twtpcon_valid) begin
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine3_twtpcon_valid) begin
+		litedramcore_bankmachine3_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
-			main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+			litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trccon_valid) begin
-		main_litedramcore_bankmachine3_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine3_trccon_valid) begin
+		litedramcore_bankmachine3_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+			litedramcore_bankmachine3_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+			litedramcore_bankmachine3_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
-			main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trccon_ready)) begin
+			litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trascon_valid) begin
-		main_litedramcore_bankmachine3_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine3_trascon_valid) begin
+		litedramcore_bankmachine3_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+			litedramcore_bankmachine3_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+			litedramcore_bankmachine3_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
-			main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trascon_ready)) begin
+			litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine3_state <= builder_bankmachine3_next_state;
-	if (main_litedramcore_bankmachine4_row_close) begin
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
+	litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+	if (litedramcore_bankmachine4_row_close) begin
+		litedramcore_bankmachine4_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine4_row_open) begin
-			main_litedramcore_bankmachine4_row_opened <= 1'd1;
-			main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine4_row_open) begin
+			litedramcore_bankmachine4_row_opened <= 1'd1;
+			litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+		litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+		litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine4_twtpcon_valid) begin
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine4_twtpcon_valid) begin
+		litedramcore_bankmachine4_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
-			main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+			litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trccon_valid) begin
-		main_litedramcore_bankmachine4_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine4_trccon_valid) begin
+		litedramcore_bankmachine4_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+			litedramcore_bankmachine4_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+			litedramcore_bankmachine4_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
-			main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trccon_ready)) begin
+			litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trascon_valid) begin
-		main_litedramcore_bankmachine4_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine4_trascon_valid) begin
+		litedramcore_bankmachine4_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+			litedramcore_bankmachine4_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+			litedramcore_bankmachine4_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
-			main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trascon_ready)) begin
+			litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine4_state <= builder_bankmachine4_next_state;
-	if (main_litedramcore_bankmachine5_row_close) begin
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
+	litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+	if (litedramcore_bankmachine5_row_close) begin
+		litedramcore_bankmachine5_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine5_row_open) begin
-			main_litedramcore_bankmachine5_row_opened <= 1'd1;
-			main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine5_row_open) begin
+			litedramcore_bankmachine5_row_opened <= 1'd1;
+			litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+		litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+		litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine5_twtpcon_valid) begin
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine5_twtpcon_valid) begin
+		litedramcore_bankmachine5_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
-			main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+			litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trccon_valid) begin
-		main_litedramcore_bankmachine5_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine5_trccon_valid) begin
+		litedramcore_bankmachine5_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+			litedramcore_bankmachine5_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+			litedramcore_bankmachine5_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
-			main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trccon_ready)) begin
+			litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trascon_valid) begin
-		main_litedramcore_bankmachine5_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine5_trascon_valid) begin
+		litedramcore_bankmachine5_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+			litedramcore_bankmachine5_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+			litedramcore_bankmachine5_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
-			main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trascon_ready)) begin
+			litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine5_state <= builder_bankmachine5_next_state;
-	if (main_litedramcore_bankmachine6_row_close) begin
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
+	litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+	if (litedramcore_bankmachine6_row_close) begin
+		litedramcore_bankmachine6_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine6_row_open) begin
-			main_litedramcore_bankmachine6_row_opened <= 1'd1;
-			main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine6_row_open) begin
+			litedramcore_bankmachine6_row_opened <= 1'd1;
+			litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+		litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+		litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine6_twtpcon_valid) begin
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine6_twtpcon_valid) begin
+		litedramcore_bankmachine6_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
-			main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+			litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trccon_valid) begin
-		main_litedramcore_bankmachine6_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine6_trccon_valid) begin
+		litedramcore_bankmachine6_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+			litedramcore_bankmachine6_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+			litedramcore_bankmachine6_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
-			main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trccon_ready)) begin
+			litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trascon_valid) begin
-		main_litedramcore_bankmachine6_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine6_trascon_valid) begin
+		litedramcore_bankmachine6_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+			litedramcore_bankmachine6_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+			litedramcore_bankmachine6_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
-			main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trascon_ready)) begin
+			litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine6_state <= builder_bankmachine6_next_state;
-	if (main_litedramcore_bankmachine7_row_close) begin
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
+	litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+	if (litedramcore_bankmachine7_row_close) begin
+		litedramcore_bankmachine7_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine7_row_open) begin
-			main_litedramcore_bankmachine7_row_opened <= 1'd1;
-			main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine7_row_open) begin
+			litedramcore_bankmachine7_row_opened <= 1'd1;
+			litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+		litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+		litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine7_twtpcon_valid) begin
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine7_twtpcon_valid) begin
+		litedramcore_bankmachine7_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
-			main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+			litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trccon_valid) begin
-		main_litedramcore_bankmachine7_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine7_trccon_valid) begin
+		litedramcore_bankmachine7_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+			litedramcore_bankmachine7_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+			litedramcore_bankmachine7_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
-			main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trccon_ready)) begin
+			litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trascon_valid) begin
-		main_litedramcore_bankmachine7_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine7_trascon_valid) begin
+		litedramcore_bankmachine7_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+			litedramcore_bankmachine7_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+			litedramcore_bankmachine7_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
-			main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trascon_ready)) begin
+			litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine7_state <= builder_bankmachine7_next_state;
-	if ((~main_litedramcore_en0)) begin
-		main_litedramcore_time0 <= 5'd31;
+	litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+	if ((~litedramcore_en0)) begin
+		litedramcore_time0 <= 5'd31;
 	end else begin
-		if ((~main_litedramcore_max_time0)) begin
-			main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
+		if ((~litedramcore_max_time0)) begin
+			litedramcore_time0 <= (litedramcore_time0 - 1'd1);
 		end
 	end
-	if ((~main_litedramcore_en1)) begin
-		main_litedramcore_time1 <= 4'd15;
+	if ((~litedramcore_en1)) begin
+		litedramcore_time1 <= 4'd15;
 	end else begin
-		if ((~main_litedramcore_max_time1)) begin
-			main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
+		if ((~litedramcore_max_time1)) begin
+			litedramcore_time1 <= (litedramcore_time1 - 1'd1);
 		end
 	end
-	if (main_litedramcore_choose_cmd_ce) begin
-		case (main_litedramcore_choose_cmd_grant)
+	if (litedramcore_choose_cmd_ce) begin
+		case (litedramcore_choose_cmd_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_cmd_request[1]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd1;
+				if (litedramcore_choose_cmd_request[1]) begin
+					litedramcore_choose_cmd_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[2]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd2;
+					if (litedramcore_choose_cmd_request[2]) begin
+						litedramcore_choose_cmd_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[3]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd3;
+						if (litedramcore_choose_cmd_request[3]) begin
+							litedramcore_choose_cmd_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[4]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd4;
+							if (litedramcore_choose_cmd_request[4]) begin
+								litedramcore_choose_cmd_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[5]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd5;
+								if (litedramcore_choose_cmd_request[5]) begin
+									litedramcore_choose_cmd_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[6]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd6;
+									if (litedramcore_choose_cmd_request[6]) begin
+										litedramcore_choose_cmd_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[7]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd7;
+										if (litedramcore_choose_cmd_request[7]) begin
+											litedramcore_choose_cmd_grant <= 3'd7;
 										end
 									end
 								end
@@ -12367,26 +12810,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_cmd_request[2]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd2;
+				if (litedramcore_choose_cmd_request[2]) begin
+					litedramcore_choose_cmd_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[3]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd3;
+					if (litedramcore_choose_cmd_request[3]) begin
+						litedramcore_choose_cmd_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[4]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd4;
+						if (litedramcore_choose_cmd_request[4]) begin
+							litedramcore_choose_cmd_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[5]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd5;
+							if (litedramcore_choose_cmd_request[5]) begin
+								litedramcore_choose_cmd_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[6]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd6;
+								if (litedramcore_choose_cmd_request[6]) begin
+									litedramcore_choose_cmd_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[7]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd7;
+									if (litedramcore_choose_cmd_request[7]) begin
+										litedramcore_choose_cmd_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[0]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd0;
+										if (litedramcore_choose_cmd_request[0]) begin
+											litedramcore_choose_cmd_grant <= 1'd0;
 										end
 									end
 								end
@@ -12396,26 +12839,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_cmd_request[3]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd3;
+				if (litedramcore_choose_cmd_request[3]) begin
+					litedramcore_choose_cmd_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[4]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd4;
+					if (litedramcore_choose_cmd_request[4]) begin
+						litedramcore_choose_cmd_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[5]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd5;
+						if (litedramcore_choose_cmd_request[5]) begin
+							litedramcore_choose_cmd_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[6]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd6;
+							if (litedramcore_choose_cmd_request[6]) begin
+								litedramcore_choose_cmd_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[7]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd7;
+								if (litedramcore_choose_cmd_request[7]) begin
+									litedramcore_choose_cmd_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[0]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd0;
+									if (litedramcore_choose_cmd_request[0]) begin
+										litedramcore_choose_cmd_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[1]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd1;
+										if (litedramcore_choose_cmd_request[1]) begin
+											litedramcore_choose_cmd_grant <= 1'd1;
 										end
 									end
 								end
@@ -12425,26 +12868,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_cmd_request[4]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd4;
+				if (litedramcore_choose_cmd_request[4]) begin
+					litedramcore_choose_cmd_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[5]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd5;
+					if (litedramcore_choose_cmd_request[5]) begin
+						litedramcore_choose_cmd_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[6]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd6;
+						if (litedramcore_choose_cmd_request[6]) begin
+							litedramcore_choose_cmd_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[7]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd7;
+							if (litedramcore_choose_cmd_request[7]) begin
+								litedramcore_choose_cmd_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[0]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd0;
+								if (litedramcore_choose_cmd_request[0]) begin
+									litedramcore_choose_cmd_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[1]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd1;
+									if (litedramcore_choose_cmd_request[1]) begin
+										litedramcore_choose_cmd_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[2]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd2;
+										if (litedramcore_choose_cmd_request[2]) begin
+											litedramcore_choose_cmd_grant <= 2'd2;
 										end
 									end
 								end
@@ -12454,26 +12897,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_cmd_request[5]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd5;
+				if (litedramcore_choose_cmd_request[5]) begin
+					litedramcore_choose_cmd_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[6]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd6;
+					if (litedramcore_choose_cmd_request[6]) begin
+						litedramcore_choose_cmd_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[7]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd7;
+						if (litedramcore_choose_cmd_request[7]) begin
+							litedramcore_choose_cmd_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[0]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd0;
+							if (litedramcore_choose_cmd_request[0]) begin
+								litedramcore_choose_cmd_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[1]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd1;
+								if (litedramcore_choose_cmd_request[1]) begin
+									litedramcore_choose_cmd_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[2]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd2;
+									if (litedramcore_choose_cmd_request[2]) begin
+										litedramcore_choose_cmd_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[3]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd3;
+										if (litedramcore_choose_cmd_request[3]) begin
+											litedramcore_choose_cmd_grant <= 2'd3;
 										end
 									end
 								end
@@ -12483,26 +12926,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_cmd_request[6]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd6;
+				if (litedramcore_choose_cmd_request[6]) begin
+					litedramcore_choose_cmd_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[7]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd7;
+					if (litedramcore_choose_cmd_request[7]) begin
+						litedramcore_choose_cmd_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[0]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd0;
+						if (litedramcore_choose_cmd_request[0]) begin
+							litedramcore_choose_cmd_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[1]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd1;
+							if (litedramcore_choose_cmd_request[1]) begin
+								litedramcore_choose_cmd_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[2]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd2;
+								if (litedramcore_choose_cmd_request[2]) begin
+									litedramcore_choose_cmd_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[3]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd3;
+									if (litedramcore_choose_cmd_request[3]) begin
+										litedramcore_choose_cmd_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[4]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd4;
+										if (litedramcore_choose_cmd_request[4]) begin
+											litedramcore_choose_cmd_grant <= 3'd4;
 										end
 									end
 								end
@@ -12512,26 +12955,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_cmd_request[7]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd7;
+				if (litedramcore_choose_cmd_request[7]) begin
+					litedramcore_choose_cmd_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[0]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd0;
+					if (litedramcore_choose_cmd_request[0]) begin
+						litedramcore_choose_cmd_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[1]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd1;
+						if (litedramcore_choose_cmd_request[1]) begin
+							litedramcore_choose_cmd_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[2]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd2;
+							if (litedramcore_choose_cmd_request[2]) begin
+								litedramcore_choose_cmd_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[3]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd3;
+								if (litedramcore_choose_cmd_request[3]) begin
+									litedramcore_choose_cmd_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[4]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd4;
+									if (litedramcore_choose_cmd_request[4]) begin
+										litedramcore_choose_cmd_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[5]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd5;
+										if (litedramcore_choose_cmd_request[5]) begin
+											litedramcore_choose_cmd_grant <= 3'd5;
 										end
 									end
 								end
@@ -12541,26 +12984,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_cmd_request[0]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd0;
+				if (litedramcore_choose_cmd_request[0]) begin
+					litedramcore_choose_cmd_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[1]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd1;
+					if (litedramcore_choose_cmd_request[1]) begin
+						litedramcore_choose_cmd_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[2]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd2;
+						if (litedramcore_choose_cmd_request[2]) begin
+							litedramcore_choose_cmd_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[3]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd3;
+							if (litedramcore_choose_cmd_request[3]) begin
+								litedramcore_choose_cmd_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[4]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd4;
+								if (litedramcore_choose_cmd_request[4]) begin
+									litedramcore_choose_cmd_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[5]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd5;
+									if (litedramcore_choose_cmd_request[5]) begin
+										litedramcore_choose_cmd_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[6]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd6;
+										if (litedramcore_choose_cmd_request[6]) begin
+											litedramcore_choose_cmd_grant <= 3'd6;
 										end
 									end
 								end
@@ -12571,29 +13014,29 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	if (main_litedramcore_choose_req_ce) begin
-		case (main_litedramcore_choose_req_grant)
+	if (litedramcore_choose_req_ce) begin
+		case (litedramcore_choose_req_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_req_request[1]) begin
-					main_litedramcore_choose_req_grant <= 1'd1;
+				if (litedramcore_choose_req_request[1]) begin
+					litedramcore_choose_req_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_req_request[2]) begin
-						main_litedramcore_choose_req_grant <= 2'd2;
+					if (litedramcore_choose_req_request[2]) begin
+						litedramcore_choose_req_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_req_request[3]) begin
-							main_litedramcore_choose_req_grant <= 2'd3;
+						if (litedramcore_choose_req_request[3]) begin
+							litedramcore_choose_req_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_req_request[4]) begin
-								main_litedramcore_choose_req_grant <= 3'd4;
+							if (litedramcore_choose_req_request[4]) begin
+								litedramcore_choose_req_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_req_request[5]) begin
-									main_litedramcore_choose_req_grant <= 3'd5;
+								if (litedramcore_choose_req_request[5]) begin
+									litedramcore_choose_req_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_req_request[6]) begin
-										main_litedramcore_choose_req_grant <= 3'd6;
+									if (litedramcore_choose_req_request[6]) begin
+										litedramcore_choose_req_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_req_request[7]) begin
-											main_litedramcore_choose_req_grant <= 3'd7;
+										if (litedramcore_choose_req_request[7]) begin
+											litedramcore_choose_req_grant <= 3'd7;
 										end
 									end
 								end
@@ -12603,26 +13046,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_req_request[2]) begin
-					main_litedramcore_choose_req_grant <= 2'd2;
+				if (litedramcore_choose_req_request[2]) begin
+					litedramcore_choose_req_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_req_request[3]) begin
-						main_litedramcore_choose_req_grant <= 2'd3;
+					if (litedramcore_choose_req_request[3]) begin
+						litedramcore_choose_req_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_req_request[4]) begin
-							main_litedramcore_choose_req_grant <= 3'd4;
+						if (litedramcore_choose_req_request[4]) begin
+							litedramcore_choose_req_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_req_request[5]) begin
-								main_litedramcore_choose_req_grant <= 3'd5;
+							if (litedramcore_choose_req_request[5]) begin
+								litedramcore_choose_req_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_req_request[6]) begin
-									main_litedramcore_choose_req_grant <= 3'd6;
+								if (litedramcore_choose_req_request[6]) begin
+									litedramcore_choose_req_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_req_request[7]) begin
-										main_litedramcore_choose_req_grant <= 3'd7;
+									if (litedramcore_choose_req_request[7]) begin
+										litedramcore_choose_req_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_req_request[0]) begin
-											main_litedramcore_choose_req_grant <= 1'd0;
+										if (litedramcore_choose_req_request[0]) begin
+											litedramcore_choose_req_grant <= 1'd0;
 										end
 									end
 								end
@@ -12632,26 +13075,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_req_request[3]) begin
-					main_litedramcore_choose_req_grant <= 2'd3;
+				if (litedramcore_choose_req_request[3]) begin
+					litedramcore_choose_req_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_req_request[4]) begin
-						main_litedramcore_choose_req_grant <= 3'd4;
+					if (litedramcore_choose_req_request[4]) begin
+						litedramcore_choose_req_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_req_request[5]) begin
-							main_litedramcore_choose_req_grant <= 3'd5;
+						if (litedramcore_choose_req_request[5]) begin
+							litedramcore_choose_req_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_req_request[6]) begin
-								main_litedramcore_choose_req_grant <= 3'd6;
+							if (litedramcore_choose_req_request[6]) begin
+								litedramcore_choose_req_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_req_request[7]) begin
-									main_litedramcore_choose_req_grant <= 3'd7;
+								if (litedramcore_choose_req_request[7]) begin
+									litedramcore_choose_req_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_req_request[0]) begin
-										main_litedramcore_choose_req_grant <= 1'd0;
+									if (litedramcore_choose_req_request[0]) begin
+										litedramcore_choose_req_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_req_request[1]) begin
-											main_litedramcore_choose_req_grant <= 1'd1;
+										if (litedramcore_choose_req_request[1]) begin
+											litedramcore_choose_req_grant <= 1'd1;
 										end
 									end
 								end
@@ -12661,26 +13104,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_req_request[4]) begin
-					main_litedramcore_choose_req_grant <= 3'd4;
+				if (litedramcore_choose_req_request[4]) begin
+					litedramcore_choose_req_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_req_request[5]) begin
-						main_litedramcore_choose_req_grant <= 3'd5;
+					if (litedramcore_choose_req_request[5]) begin
+						litedramcore_choose_req_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_req_request[6]) begin
-							main_litedramcore_choose_req_grant <= 3'd6;
+						if (litedramcore_choose_req_request[6]) begin
+							litedramcore_choose_req_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_req_request[7]) begin
-								main_litedramcore_choose_req_grant <= 3'd7;
+							if (litedramcore_choose_req_request[7]) begin
+								litedramcore_choose_req_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_req_request[0]) begin
-									main_litedramcore_choose_req_grant <= 1'd0;
+								if (litedramcore_choose_req_request[0]) begin
+									litedramcore_choose_req_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_req_request[1]) begin
-										main_litedramcore_choose_req_grant <= 1'd1;
+									if (litedramcore_choose_req_request[1]) begin
+										litedramcore_choose_req_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_req_request[2]) begin
-											main_litedramcore_choose_req_grant <= 2'd2;
+										if (litedramcore_choose_req_request[2]) begin
+											litedramcore_choose_req_grant <= 2'd2;
 										end
 									end
 								end
@@ -12690,26 +13133,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_req_request[5]) begin
-					main_litedramcore_choose_req_grant <= 3'd5;
+				if (litedramcore_choose_req_request[5]) begin
+					litedramcore_choose_req_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_req_request[6]) begin
-						main_litedramcore_choose_req_grant <= 3'd6;
+					if (litedramcore_choose_req_request[6]) begin
+						litedramcore_choose_req_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_req_request[7]) begin
-							main_litedramcore_choose_req_grant <= 3'd7;
+						if (litedramcore_choose_req_request[7]) begin
+							litedramcore_choose_req_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_req_request[0]) begin
-								main_litedramcore_choose_req_grant <= 1'd0;
+							if (litedramcore_choose_req_request[0]) begin
+								litedramcore_choose_req_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_req_request[1]) begin
-									main_litedramcore_choose_req_grant <= 1'd1;
+								if (litedramcore_choose_req_request[1]) begin
+									litedramcore_choose_req_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_req_request[2]) begin
-										main_litedramcore_choose_req_grant <= 2'd2;
+									if (litedramcore_choose_req_request[2]) begin
+										litedramcore_choose_req_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_req_request[3]) begin
-											main_litedramcore_choose_req_grant <= 2'd3;
+										if (litedramcore_choose_req_request[3]) begin
+											litedramcore_choose_req_grant <= 2'd3;
 										end
 									end
 								end
@@ -12719,26 +13162,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_req_request[6]) begin
-					main_litedramcore_choose_req_grant <= 3'd6;
+				if (litedramcore_choose_req_request[6]) begin
+					litedramcore_choose_req_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_req_request[7]) begin
-						main_litedramcore_choose_req_grant <= 3'd7;
+					if (litedramcore_choose_req_request[7]) begin
+						litedramcore_choose_req_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_req_request[0]) begin
-							main_litedramcore_choose_req_grant <= 1'd0;
+						if (litedramcore_choose_req_request[0]) begin
+							litedramcore_choose_req_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_req_request[1]) begin
-								main_litedramcore_choose_req_grant <= 1'd1;
+							if (litedramcore_choose_req_request[1]) begin
+								litedramcore_choose_req_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_req_request[2]) begin
-									main_litedramcore_choose_req_grant <= 2'd2;
+								if (litedramcore_choose_req_request[2]) begin
+									litedramcore_choose_req_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_req_request[3]) begin
-										main_litedramcore_choose_req_grant <= 2'd3;
+									if (litedramcore_choose_req_request[3]) begin
+										litedramcore_choose_req_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_req_request[4]) begin
-											main_litedramcore_choose_req_grant <= 3'd4;
+										if (litedramcore_choose_req_request[4]) begin
+											litedramcore_choose_req_grant <= 3'd4;
 										end
 									end
 								end
@@ -12748,26 +13191,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_req_request[7]) begin
-					main_litedramcore_choose_req_grant <= 3'd7;
+				if (litedramcore_choose_req_request[7]) begin
+					litedramcore_choose_req_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_req_request[0]) begin
-						main_litedramcore_choose_req_grant <= 1'd0;
+					if (litedramcore_choose_req_request[0]) begin
+						litedramcore_choose_req_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_req_request[1]) begin
-							main_litedramcore_choose_req_grant <= 1'd1;
+						if (litedramcore_choose_req_request[1]) begin
+							litedramcore_choose_req_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_req_request[2]) begin
-								main_litedramcore_choose_req_grant <= 2'd2;
+							if (litedramcore_choose_req_request[2]) begin
+								litedramcore_choose_req_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_req_request[3]) begin
-									main_litedramcore_choose_req_grant <= 2'd3;
+								if (litedramcore_choose_req_request[3]) begin
+									litedramcore_choose_req_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_req_request[4]) begin
-										main_litedramcore_choose_req_grant <= 3'd4;
+									if (litedramcore_choose_req_request[4]) begin
+										litedramcore_choose_req_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_req_request[5]) begin
-											main_litedramcore_choose_req_grant <= 3'd5;
+										if (litedramcore_choose_req_request[5]) begin
+											litedramcore_choose_req_grant <= 3'd5;
 										end
 									end
 								end
@@ -12777,26 +13220,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_req_request[0]) begin
-					main_litedramcore_choose_req_grant <= 1'd0;
+				if (litedramcore_choose_req_request[0]) begin
+					litedramcore_choose_req_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_req_request[1]) begin
-						main_litedramcore_choose_req_grant <= 1'd1;
+					if (litedramcore_choose_req_request[1]) begin
+						litedramcore_choose_req_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_req_request[2]) begin
-							main_litedramcore_choose_req_grant <= 2'd2;
+						if (litedramcore_choose_req_request[2]) begin
+							litedramcore_choose_req_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_req_request[3]) begin
-								main_litedramcore_choose_req_grant <= 2'd3;
+							if (litedramcore_choose_req_request[3]) begin
+								litedramcore_choose_req_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_req_request[4]) begin
-									main_litedramcore_choose_req_grant <= 3'd4;
+								if (litedramcore_choose_req_request[4]) begin
+									litedramcore_choose_req_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_req_request[5]) begin
-										main_litedramcore_choose_req_grant <= 3'd5;
+									if (litedramcore_choose_req_request[5]) begin
+										litedramcore_choose_req_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_req_request[6]) begin
-											main_litedramcore_choose_req_grant <= 3'd6;
+										if (litedramcore_choose_req_request[6]) begin
+											litedramcore_choose_req_grant <= 3'd6;
 										end
 									end
 								end
@@ -12807,644 +13250,644 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	main_litedramcore_dfi_p0_cs_n <= 1'd0;
-	main_litedramcore_dfi_p0_bank <= builder_array_muxed0;
-	main_litedramcore_dfi_p0_address <= builder_array_muxed1;
-	main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2);
-	main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3);
-	main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4);
-	main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5;
-	main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6;
-	main_litedramcore_dfi_p1_cs_n <= 1'd0;
-	main_litedramcore_dfi_p1_bank <= builder_array_muxed7;
-	main_litedramcore_dfi_p1_address <= builder_array_muxed8;
-	main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9);
-	main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10);
-	main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11);
-	main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12;
-	main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13;
-	main_litedramcore_dfi_p2_cs_n <= 1'd0;
-	main_litedramcore_dfi_p2_bank <= builder_array_muxed14;
-	main_litedramcore_dfi_p2_address <= builder_array_muxed15;
-	main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16);
-	main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17);
-	main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18);
-	main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19;
-	main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20;
-	main_litedramcore_dfi_p3_cs_n <= 1'd0;
-	main_litedramcore_dfi_p3_bank <= builder_array_muxed21;
-	main_litedramcore_dfi_p3_address <= builder_array_muxed22;
-	main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23);
-	main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24);
-	main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25);
-	main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26;
-	main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27;
-	if (main_litedramcore_trrdcon_valid) begin
-		main_litedramcore_trrdcon_count <= 1'd1;
+	litedramcore_dfi_p0_cs_n <= 1'd0;
+	litedramcore_dfi_p0_bank <= array_muxed0;
+	litedramcore_dfi_p0_address <= array_muxed1;
+	litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+	litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+	litedramcore_dfi_p0_we_n <= (~array_muxed4);
+	litedramcore_dfi_p0_rddata_en <= array_muxed5;
+	litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+	litedramcore_dfi_p1_cs_n <= 1'd0;
+	litedramcore_dfi_p1_bank <= array_muxed7;
+	litedramcore_dfi_p1_address <= array_muxed8;
+	litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+	litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+	litedramcore_dfi_p1_we_n <= (~array_muxed11);
+	litedramcore_dfi_p1_rddata_en <= array_muxed12;
+	litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+	litedramcore_dfi_p2_cs_n <= 1'd0;
+	litedramcore_dfi_p2_bank <= array_muxed14;
+	litedramcore_dfi_p2_address <= array_muxed15;
+	litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+	litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+	litedramcore_dfi_p2_we_n <= (~array_muxed18);
+	litedramcore_dfi_p2_rddata_en <= array_muxed19;
+	litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+	litedramcore_dfi_p3_cs_n <= 1'd0;
+	litedramcore_dfi_p3_bank <= array_muxed21;
+	litedramcore_dfi_p3_address <= array_muxed22;
+	litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+	litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+	litedramcore_dfi_p3_we_n <= (~array_muxed25);
+	litedramcore_dfi_p3_rddata_en <= array_muxed26;
+	litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+	if (litedramcore_trrdcon_valid) begin
+		litedramcore_trrdcon_count <= 1'd1;
 		if (1'd0) begin
-			main_litedramcore_trrdcon_ready <= 1'd1;
+			litedramcore_trrdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_trrdcon_ready <= 1'd0;
+			litedramcore_trrdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_trrdcon_ready)) begin
-			main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
-			if ((main_litedramcore_trrdcon_count == 1'd1)) begin
-				main_litedramcore_trrdcon_ready <= 1'd1;
+		if ((~litedramcore_trrdcon_ready)) begin
+			litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+			if ((litedramcore_trrdcon_count == 1'd1)) begin
+				litedramcore_trrdcon_ready <= 1'd1;
 			end
 		end
 	end
-	main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
-	if ((main_litedramcore_tfawcon_count < 3'd4)) begin
-		if ((main_litedramcore_tfawcon_count == 2'd3)) begin
-			main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
+	litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+	if ((litedramcore_tfawcon_count < 3'd4)) begin
+		if ((litedramcore_tfawcon_count == 2'd3)) begin
+			litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
 		end else begin
-			main_litedramcore_tfawcon_ready <= 1'd1;
+			litedramcore_tfawcon_ready <= 1'd1;
 		end
 	end
-	if (main_litedramcore_tccdcon_valid) begin
-		main_litedramcore_tccdcon_count <= 1'd0;
+	if (litedramcore_tccdcon_valid) begin
+		litedramcore_tccdcon_count <= 1'd0;
 		if (1'd1) begin
-			main_litedramcore_tccdcon_ready <= 1'd1;
+			litedramcore_tccdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_tccdcon_ready <= 1'd0;
+			litedramcore_tccdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_tccdcon_ready)) begin
-			main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
-			if ((main_litedramcore_tccdcon_count == 1'd1)) begin
-				main_litedramcore_tccdcon_ready <= 1'd1;
+		if ((~litedramcore_tccdcon_ready)) begin
+			litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+			if ((litedramcore_tccdcon_count == 1'd1)) begin
+				litedramcore_tccdcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_twtrcon_valid) begin
-		main_litedramcore_twtrcon_count <= 3'd4;
+	if (litedramcore_twtrcon_valid) begin
+		litedramcore_twtrcon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_twtrcon_ready <= 1'd1;
+			litedramcore_twtrcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_twtrcon_ready <= 1'd0;
+			litedramcore_twtrcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_twtrcon_ready)) begin
-			main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
-			if ((main_litedramcore_twtrcon_count == 1'd1)) begin
-				main_litedramcore_twtrcon_ready <= 1'd1;
+		if ((~litedramcore_twtrcon_ready)) begin
+			litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+			if ((litedramcore_twtrcon_count == 1'd1)) begin
+				litedramcore_twtrcon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_multiplexer_state <= builder_multiplexer_next_state;
-	builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
-	builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
-	builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
-	builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
-	builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
-	builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
-	builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
-	builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
-	builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
-	builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
-	builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
-	builder_state <= builder_next_state;
-	if (builder_litedramcore_dat_w_next_value_ce0) begin
-		builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0;
+	litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+	litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+	litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+	litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+	litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+	litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+	litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+	litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+	litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+	litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+	litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+	litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+	litedramcore_state <= litedramcore_next_state;
+	if (litedramcore_dat_w_next_value_ce0) begin
+		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
 	end
-	if (builder_litedramcore_adr_next_value_ce1) begin
-		builder_litedramcore_adr <= builder_litedramcore_adr_next_value1;
+	if (litedramcore_adr_next_value_ce1) begin
+		litedramcore_adr <= litedramcore_adr_next_value1;
 	end
-	if (builder_litedramcore_we_next_value_ce2) begin
-		builder_litedramcore_we <= builder_litedramcore_we_next_value2;
+	if (litedramcore_we_next_value_ce2) begin
+		litedramcore_we <= litedramcore_we_next_value2;
 	end
-	builder_interface0_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank0_sel) begin
-		case (builder_interface0_bank_bus_adr[8:0])
+	interface0_bank_bus_dat_r <= 1'd0;
+	if (csrbank0_sel) begin
+		case (interface0_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
 			end
 			1'd1: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank0_init_done0_re) begin
-		main_init_done_storage <= builder_csrbank0_init_done0_r;
+	if (csrbank0_init_done0_re) begin
+		init_done_storage <= csrbank0_init_done0_r;
 	end
-	main_init_done_re <= builder_csrbank0_init_done0_re;
-	if (builder_csrbank0_init_error0_re) begin
-		main_init_error_storage <= builder_csrbank0_init_error0_r;
+	init_done_re <= csrbank0_init_done0_re;
+	if (csrbank0_init_error0_re) begin
+		init_error_storage <= csrbank0_init_error0_r;
 	end
-	main_init_error_re <= builder_csrbank0_init_error0_re;
-	builder_interface1_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank1_sel) begin
-		case (builder_interface1_bank_bus_adr[8:0])
+	init_error_re <= csrbank0_init_error0_re;
+	interface1_bank_bus_dat_r <= 1'd0;
+	if (csrbank1_sel) begin
+		case (interface1_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rst0_w;
 			end
 			1'd1: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
 			end
 			2'd2: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
+				interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
 			end
 			2'd3: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
+				interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
 			end
 			3'd4: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
 			end
 			3'd5: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
 			end
 			3'd6: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
 			end
 			3'd7: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
 			end
 			4'd8: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
 			end
 			4'd9: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
 			end
 			4'd10: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
 			end
 			4'd11: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
 			end
 			4'd12: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank1_rst0_re) begin
-		main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
+	if (csrbank1_rst0_re) begin
+		a7ddrphy_rst_storage <= csrbank1_rst0_r;
 	end
-	main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
-	if (builder_csrbank1_half_sys8x_taps0_re) begin
-		main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+	a7ddrphy_rst_re <= csrbank1_rst0_re;
+	if (csrbank1_dly_sel0_re) begin
+		a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
 	end
-	main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
-	if (builder_csrbank1_wlevel_en0_re) begin
-		main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
+	a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+	if (csrbank1_half_sys8x_taps0_re) begin
+		a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
 	end
-	main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
-	if (builder_csrbank1_dly_sel0_re) begin
-		main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+	a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+	if (csrbank1_wlevel_en0_re) begin
+		a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
 	end
-	main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
-	if (builder_csrbank1_rdphase0_re) begin
-		main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+	a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+	if (csrbank1_rdphase0_re) begin
+		a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
 	end
-	main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
-	if (builder_csrbank1_wrphase0_re) begin
-		main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+	a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+	if (csrbank1_wrphase0_re) begin
+		a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
 	end
-	main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
-	builder_interface2_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank2_sel) begin
-		case (builder_interface2_bank_bus_adr[8:0])
+	a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+	interface2_bank_bus_dat_r <= 1'd0;
+	if (csrbank2_sel) begin
+		case (interface2_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
 			end
 			1'd1: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
 			end
 			2'd2: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
 			end
 			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
 			end
 			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
 			end
 			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
 			end
 			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
 			end
 			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
-	if (builder_csrbank2_dfii_control0_re) begin
-		main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+	if (csrbank2_dfii_control0_re) begin
+		litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
 	end
-	main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
-	if (builder_csrbank2_dfii_pi0_command0_re) begin
-		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
+	litedramcore_re <= csrbank2_dfii_control0_re;
+	if (csrbank2_dfii_pi0_command0_re) begin
+		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
 	end
-	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
+	litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+	if (csrbank2_dfii_pi0_address0_re) begin
+		litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
 	end
-	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
-	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+	litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+	if (csrbank2_dfii_pi0_baddress0_re) begin
+		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
 	end
-	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+	litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+	if (csrbank2_dfii_pi0_wrdata0_re) begin
+		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
-	if (builder_csrbank2_dfii_pi1_command0_re) begin
-		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
+	litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+	litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+	if (csrbank2_dfii_pi1_command0_re) begin
+		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
 	end
-	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
+	litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+	if (csrbank2_dfii_pi1_address0_re) begin
+		litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
 	end
-	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
-	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+	litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+	if (csrbank2_dfii_pi1_baddress0_re) begin
+		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
 	end
-	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+	litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+	if (csrbank2_dfii_pi1_wrdata0_re) begin
+		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
-	if (builder_csrbank2_dfii_pi2_command0_re) begin
-		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
+	litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+	litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+	if (csrbank2_dfii_pi2_command0_re) begin
+		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
 	end
-	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
+	litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+	if (csrbank2_dfii_pi2_address0_re) begin
+		litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
 	end
-	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
-	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+	litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+	if (csrbank2_dfii_pi2_baddress0_re) begin
+		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
 	end
-	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+	litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+	if (csrbank2_dfii_pi2_wrdata0_re) begin
+		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
-	if (builder_csrbank2_dfii_pi3_command0_re) begin
-		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
+	litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+	litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+	if (csrbank2_dfii_pi3_command0_re) begin
+		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
 	end
-	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
+	litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+	if (csrbank2_dfii_pi3_address0_re) begin
+		litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
 	end
-	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
-	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+	litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+	if (csrbank2_dfii_pi3_baddress0_re) begin
+		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
 	end
-	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+	litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+	if (csrbank2_dfii_pi3_wrdata0_re) begin
+		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
+	litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+	litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
-		main_a7ddrphy_rst_storage <= 1'd0;
-		main_a7ddrphy_rst_re <= 1'd0;
-		main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-		main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
-		main_a7ddrphy_wlevel_en_storage <= 1'd0;
-		main_a7ddrphy_wlevel_en_re <= 1'd0;
-		main_a7ddrphy_dly_sel_storage <= 2'd0;
-		main_a7ddrphy_dly_sel_re <= 1'd0;
-		main_a7ddrphy_rdphase_storage <= 2'd2;
-		main_a7ddrphy_rdphase_re <= 1'd0;
-		main_a7ddrphy_wrphase_storage <= 2'd3;
-		main_a7ddrphy_wrphase_re <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_dqspattern_o1 <= 8'd0;
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
-		main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-		main_litedramcore_storage <= 4'd1;
-		main_litedramcore_re <= 1'd0;
-		main_litedramcore_phaseinjector0_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector0_command_re <= 1'd0;
-		main_litedramcore_phaseinjector0_address_re <= 1'd0;
-		main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector1_command_re <= 1'd0;
-		main_litedramcore_phaseinjector1_address_re <= 1'd0;
-		main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector2_command_re <= 1'd0;
-		main_litedramcore_phaseinjector2_address_re <= 1'd0;
-		main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector3_command_re <= 1'd0;
-		main_litedramcore_phaseinjector3_address_re <= 1'd0;
-		main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
-		main_litedramcore_dfi_p0_address <= 14'd0;
-		main_litedramcore_dfi_p0_bank <= 3'd0;
-		main_litedramcore_dfi_p0_cas_n <= 1'd1;
-		main_litedramcore_dfi_p0_cs_n <= 1'd1;
-		main_litedramcore_dfi_p0_ras_n <= 1'd1;
-		main_litedramcore_dfi_p0_we_n <= 1'd1;
-		main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p0_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p1_address <= 14'd0;
-		main_litedramcore_dfi_p1_bank <= 3'd0;
-		main_litedramcore_dfi_p1_cas_n <= 1'd1;
-		main_litedramcore_dfi_p1_cs_n <= 1'd1;
-		main_litedramcore_dfi_p1_ras_n <= 1'd1;
-		main_litedramcore_dfi_p1_we_n <= 1'd1;
-		main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p1_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p2_address <= 14'd0;
-		main_litedramcore_dfi_p2_bank <= 3'd0;
-		main_litedramcore_dfi_p2_cas_n <= 1'd1;
-		main_litedramcore_dfi_p2_cs_n <= 1'd1;
-		main_litedramcore_dfi_p2_ras_n <= 1'd1;
-		main_litedramcore_dfi_p2_we_n <= 1'd1;
-		main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p2_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p3_address <= 14'd0;
-		main_litedramcore_dfi_p3_bank <= 3'd0;
-		main_litedramcore_dfi_p3_cas_n <= 1'd1;
-		main_litedramcore_dfi_p3_cs_n <= 1'd1;
-		main_litedramcore_dfi_p3_ras_n <= 1'd1;
-		main_litedramcore_dfi_p3_we_n <= 1'd1;
-		main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p3_rddata_en <= 1'd0;
-		main_litedramcore_cmd_payload_a <= 14'd0;
-		main_litedramcore_cmd_payload_ba <= 3'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_timer_count1 <= 10'd781;
-		main_litedramcore_postponer_req_o <= 1'd0;
-		main_litedramcore_postponer_count <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd0;
-		main_litedramcore_sequencer_counter <= 6'd0;
-		main_litedramcore_sequencer_count <= 1'd0;
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
-		main_litedramcore_zqcs_executer_done <= 1'd0;
-		main_litedramcore_zqcs_executer_counter <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine0_row <= 14'd0;
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine1_row <= 14'd0;
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine2_row <= 14'd0;
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine3_row <= 14'd0;
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine4_row <= 14'd0;
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine5_row <= 14'd0;
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine6_row <= 14'd0;
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine7_row <= 14'd0;
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trascon_count <= 3'd0;
-		main_litedramcore_choose_cmd_grant <= 3'd0;
-		main_litedramcore_choose_req_grant <= 3'd0;
-		main_litedramcore_trrdcon_ready <= 1'd0;
-		main_litedramcore_trrdcon_count <= 1'd0;
-		main_litedramcore_tfawcon_ready <= 1'd1;
-		main_litedramcore_tfawcon_window <= 5'd0;
-		main_litedramcore_tccdcon_ready <= 1'd0;
-		main_litedramcore_tccdcon_count <= 1'd0;
-		main_litedramcore_twtrcon_ready <= 1'd0;
-		main_litedramcore_twtrcon_count <= 3'd0;
-		main_litedramcore_time0 <= 5'd0;
-		main_litedramcore_time1 <= 4'd0;
-		main_init_done_storage <= 1'd0;
-		main_init_done_re <= 1'd0;
-		main_init_error_storage <= 1'd0;
-		main_init_error_re <= 1'd0;
-		builder_refresher_state <= 2'd0;
-		builder_bankmachine0_state <= 4'd0;
-		builder_bankmachine1_state <= 4'd0;
-		builder_bankmachine2_state <= 4'd0;
-		builder_bankmachine3_state <= 4'd0;
-		builder_bankmachine4_state <= 4'd0;
-		builder_bankmachine5_state <= 4'd0;
-		builder_bankmachine6_state <= 4'd0;
-		builder_bankmachine7_state <= 4'd0;
-		builder_multiplexer_state <= 4'd0;
-		builder_new_master_wdata_ready0 <= 1'd0;
-		builder_new_master_wdata_ready1 <= 1'd0;
-		builder_new_master_rdata_valid0 <= 1'd0;
-		builder_new_master_rdata_valid1 <= 1'd0;
-		builder_new_master_rdata_valid2 <= 1'd0;
-		builder_new_master_rdata_valid3 <= 1'd0;
-		builder_new_master_rdata_valid4 <= 1'd0;
-		builder_new_master_rdata_valid5 <= 1'd0;
-		builder_new_master_rdata_valid6 <= 1'd0;
-		builder_new_master_rdata_valid7 <= 1'd0;
-		builder_new_master_rdata_valid8 <= 1'd0;
-		builder_litedramcore_we <= 1'd0;
-		builder_state <= 2'd0;
+		a7ddrphy_rst_storage <= 1'd0;
+		a7ddrphy_rst_re <= 1'd0;
+		a7ddrphy_dly_sel_storage <= 2'd0;
+		a7ddrphy_dly_sel_re <= 1'd0;
+		a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+		a7ddrphy_half_sys8x_taps_re <= 1'd0;
+		a7ddrphy_wlevel_en_storage <= 1'd0;
+		a7ddrphy_wlevel_en_re <= 1'd0;
+		a7ddrphy_rdphase_storage <= 2'd2;
+		a7ddrphy_rdphase_re <= 1'd0;
+		a7ddrphy_wrphase_storage <= 2'd3;
+		a7ddrphy_wrphase_re <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_dqspattern_o1 <= 8'd0;
+		a7ddrphy_bitslip0_value0 <= 3'd7;
+		a7ddrphy_bitslip1_value0 <= 3'd7;
+		a7ddrphy_bitslip0_value1 <= 3'd7;
+		a7ddrphy_bitslip1_value1 <= 3'd7;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_bitslip0_value2 <= 3'd7;
+		a7ddrphy_bitslip0_value3 <= 3'd7;
+		a7ddrphy_bitslip1_value2 <= 3'd7;
+		a7ddrphy_bitslip1_value3 <= 3'd7;
+		a7ddrphy_bitslip2_value0 <= 3'd7;
+		a7ddrphy_bitslip2_value1 <= 3'd7;
+		a7ddrphy_bitslip3_value0 <= 3'd7;
+		a7ddrphy_bitslip3_value1 <= 3'd7;
+		a7ddrphy_bitslip4_value0 <= 3'd7;
+		a7ddrphy_bitslip4_value1 <= 3'd7;
+		a7ddrphy_bitslip5_value0 <= 3'd7;
+		a7ddrphy_bitslip5_value1 <= 3'd7;
+		a7ddrphy_bitslip6_value0 <= 3'd7;
+		a7ddrphy_bitslip6_value1 <= 3'd7;
+		a7ddrphy_bitslip7_value0 <= 3'd7;
+		a7ddrphy_bitslip7_value1 <= 3'd7;
+		a7ddrphy_bitslip8_value0 <= 3'd7;
+		a7ddrphy_bitslip8_value1 <= 3'd7;
+		a7ddrphy_bitslip9_value0 <= 3'd7;
+		a7ddrphy_bitslip9_value1 <= 3'd7;
+		a7ddrphy_bitslip10_value0 <= 3'd7;
+		a7ddrphy_bitslip10_value1 <= 3'd7;
+		a7ddrphy_bitslip11_value0 <= 3'd7;
+		a7ddrphy_bitslip11_value1 <= 3'd7;
+		a7ddrphy_bitslip12_value0 <= 3'd7;
+		a7ddrphy_bitslip12_value1 <= 3'd7;
+		a7ddrphy_bitslip13_value0 <= 3'd7;
+		a7ddrphy_bitslip13_value1 <= 3'd7;
+		a7ddrphy_bitslip14_value0 <= 3'd7;
+		a7ddrphy_bitslip14_value1 <= 3'd7;
+		a7ddrphy_bitslip15_value0 <= 3'd7;
+		a7ddrphy_bitslip15_value1 <= 3'd7;
+		a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+		litedramcore_storage <= 4'd1;
+		litedramcore_re <= 1'd0;
+		litedramcore_phaseinjector0_command_storage <= 6'd0;
+		litedramcore_phaseinjector0_command_re <= 1'd0;
+		litedramcore_phaseinjector0_address_re <= 1'd0;
+		litedramcore_phaseinjector0_baddress_re <= 1'd0;
+		litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector0_rddata_status <= 32'd0;
+		litedramcore_phaseinjector0_rddata_re <= 1'd0;
+		litedramcore_phaseinjector1_command_storage <= 6'd0;
+		litedramcore_phaseinjector1_command_re <= 1'd0;
+		litedramcore_phaseinjector1_address_re <= 1'd0;
+		litedramcore_phaseinjector1_baddress_re <= 1'd0;
+		litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector1_rddata_status <= 32'd0;
+		litedramcore_phaseinjector1_rddata_re <= 1'd0;
+		litedramcore_phaseinjector2_command_storage <= 6'd0;
+		litedramcore_phaseinjector2_command_re <= 1'd0;
+		litedramcore_phaseinjector2_address_re <= 1'd0;
+		litedramcore_phaseinjector2_baddress_re <= 1'd0;
+		litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector2_rddata_status <= 32'd0;
+		litedramcore_phaseinjector2_rddata_re <= 1'd0;
+		litedramcore_phaseinjector3_command_storage <= 6'd0;
+		litedramcore_phaseinjector3_command_re <= 1'd0;
+		litedramcore_phaseinjector3_address_re <= 1'd0;
+		litedramcore_phaseinjector3_baddress_re <= 1'd0;
+		litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector3_rddata_status <= 32'd0;
+		litedramcore_phaseinjector3_rddata_re <= 1'd0;
+		litedramcore_dfi_p0_address <= 14'd0;
+		litedramcore_dfi_p0_bank <= 3'd0;
+		litedramcore_dfi_p0_cas_n <= 1'd1;
+		litedramcore_dfi_p0_cs_n <= 1'd1;
+		litedramcore_dfi_p0_ras_n <= 1'd1;
+		litedramcore_dfi_p0_we_n <= 1'd1;
+		litedramcore_dfi_p0_wrdata_en <= 1'd0;
+		litedramcore_dfi_p0_rddata_en <= 1'd0;
+		litedramcore_dfi_p1_address <= 14'd0;
+		litedramcore_dfi_p1_bank <= 3'd0;
+		litedramcore_dfi_p1_cas_n <= 1'd1;
+		litedramcore_dfi_p1_cs_n <= 1'd1;
+		litedramcore_dfi_p1_ras_n <= 1'd1;
+		litedramcore_dfi_p1_we_n <= 1'd1;
+		litedramcore_dfi_p1_wrdata_en <= 1'd0;
+		litedramcore_dfi_p1_rddata_en <= 1'd0;
+		litedramcore_dfi_p2_address <= 14'd0;
+		litedramcore_dfi_p2_bank <= 3'd0;
+		litedramcore_dfi_p2_cas_n <= 1'd1;
+		litedramcore_dfi_p2_cs_n <= 1'd1;
+		litedramcore_dfi_p2_ras_n <= 1'd1;
+		litedramcore_dfi_p2_we_n <= 1'd1;
+		litedramcore_dfi_p2_wrdata_en <= 1'd0;
+		litedramcore_dfi_p2_rddata_en <= 1'd0;
+		litedramcore_dfi_p3_address <= 14'd0;
+		litedramcore_dfi_p3_bank <= 3'd0;
+		litedramcore_dfi_p3_cas_n <= 1'd1;
+		litedramcore_dfi_p3_cs_n <= 1'd1;
+		litedramcore_dfi_p3_ras_n <= 1'd1;
+		litedramcore_dfi_p3_we_n <= 1'd1;
+		litedramcore_dfi_p3_wrdata_en <= 1'd0;
+		litedramcore_dfi_p3_rddata_en <= 1'd0;
+		litedramcore_cmd_payload_a <= 14'd0;
+		litedramcore_cmd_payload_ba <= 3'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_timer_count1 <= 10'd781;
+		litedramcore_postponer_req_o <= 1'd0;
+		litedramcore_postponer_count <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd0;
+		litedramcore_sequencer_counter <= 6'd0;
+		litedramcore_sequencer_count <= 1'd0;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_executer_done <= 1'd0;
+		litedramcore_zqcs_executer_counter <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine0_row <= 14'd0;
+		litedramcore_bankmachine0_row_opened <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine0_trccon_ready <= 1'd0;
+		litedramcore_bankmachine0_trccon_count <= 3'd0;
+		litedramcore_bankmachine0_trascon_ready <= 1'd0;
+		litedramcore_bankmachine0_trascon_count <= 3'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine1_row <= 14'd0;
+		litedramcore_bankmachine1_row_opened <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine1_trccon_ready <= 1'd0;
+		litedramcore_bankmachine1_trccon_count <= 3'd0;
+		litedramcore_bankmachine1_trascon_ready <= 1'd0;
+		litedramcore_bankmachine1_trascon_count <= 3'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine2_row <= 14'd0;
+		litedramcore_bankmachine2_row_opened <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine2_trccon_ready <= 1'd0;
+		litedramcore_bankmachine2_trccon_count <= 3'd0;
+		litedramcore_bankmachine2_trascon_ready <= 1'd0;
+		litedramcore_bankmachine2_trascon_count <= 3'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine3_row <= 14'd0;
+		litedramcore_bankmachine3_row_opened <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine3_trccon_ready <= 1'd0;
+		litedramcore_bankmachine3_trccon_count <= 3'd0;
+		litedramcore_bankmachine3_trascon_ready <= 1'd0;
+		litedramcore_bankmachine3_trascon_count <= 3'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine4_row <= 14'd0;
+		litedramcore_bankmachine4_row_opened <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine4_trccon_ready <= 1'd0;
+		litedramcore_bankmachine4_trccon_count <= 3'd0;
+		litedramcore_bankmachine4_trascon_ready <= 1'd0;
+		litedramcore_bankmachine4_trascon_count <= 3'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine5_row <= 14'd0;
+		litedramcore_bankmachine5_row_opened <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine5_trccon_ready <= 1'd0;
+		litedramcore_bankmachine5_trccon_count <= 3'd0;
+		litedramcore_bankmachine5_trascon_ready <= 1'd0;
+		litedramcore_bankmachine5_trascon_count <= 3'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine6_row <= 14'd0;
+		litedramcore_bankmachine6_row_opened <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine6_trccon_ready <= 1'd0;
+		litedramcore_bankmachine6_trccon_count <= 3'd0;
+		litedramcore_bankmachine6_trascon_ready <= 1'd0;
+		litedramcore_bankmachine6_trascon_count <= 3'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine7_row <= 14'd0;
+		litedramcore_bankmachine7_row_opened <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine7_trccon_ready <= 1'd0;
+		litedramcore_bankmachine7_trccon_count <= 3'd0;
+		litedramcore_bankmachine7_trascon_ready <= 1'd0;
+		litedramcore_bankmachine7_trascon_count <= 3'd0;
+		litedramcore_choose_cmd_grant <= 3'd0;
+		litedramcore_choose_req_grant <= 3'd0;
+		litedramcore_trrdcon_ready <= 1'd0;
+		litedramcore_trrdcon_count <= 1'd0;
+		litedramcore_tfawcon_ready <= 1'd1;
+		litedramcore_tfawcon_window <= 5'd0;
+		litedramcore_tccdcon_ready <= 1'd0;
+		litedramcore_tccdcon_count <= 1'd0;
+		litedramcore_twtrcon_ready <= 1'd0;
+		litedramcore_twtrcon_count <= 3'd0;
+		litedramcore_time0 <= 5'd0;
+		litedramcore_time1 <= 4'd0;
+		init_done_storage <= 1'd0;
+		init_done_re <= 1'd0;
+		init_error_storage <= 1'd0;
+		init_error_re <= 1'd0;
+		litedramcore_we <= 1'd0;
+		litedramcore_refresher_state <= 2'd0;
+		litedramcore_bankmachine0_state <= 4'd0;
+		litedramcore_bankmachine1_state <= 4'd0;
+		litedramcore_bankmachine2_state <= 4'd0;
+		litedramcore_bankmachine3_state <= 4'd0;
+		litedramcore_bankmachine4_state <= 4'd0;
+		litedramcore_bankmachine5_state <= 4'd0;
+		litedramcore_bankmachine6_state <= 4'd0;
+		litedramcore_bankmachine7_state <= 4'd0;
+		litedramcore_multiplexer_state <= 4'd0;
+		litedramcore_new_master_wdata_ready0 <= 1'd0;
+		litedramcore_new_master_wdata_ready1 <= 1'd0;
+		litedramcore_new_master_rdata_valid0 <= 1'd0;
+		litedramcore_new_master_rdata_valid1 <= 1'd0;
+		litedramcore_new_master_rdata_valid2 <= 1'd0;
+		litedramcore_new_master_rdata_valid3 <= 1'd0;
+		litedramcore_new_master_rdata_valid4 <= 1'd0;
+		litedramcore_new_master_rdata_valid5 <= 1'd0;
+		litedramcore_new_master_rdata_valid6 <= 1'd0;
+		litedramcore_new_master_rdata_valid7 <= 1'd0;
+		litedramcore_new_master_rdata_valid8 <= 1'd0;
+		litedramcore_state <= 2'd0;
 	end
 end
 
@@ -13454,28 +13897,28 @@ end
 //------------------------------------------------------------------------------
 
 BUFG BUFG(
-	.I(main_clkout0),
-	.O(main_clkout_buf0)
+	.I(clkout0),
+	.O(clkout_buf0)
 );
 
 BUFG BUFG_1(
-	.I(main_clkout1),
-	.O(main_clkout_buf1)
+	.I(clkout1),
+	.O(clkout_buf1)
 );
 
 BUFG BUFG_2(
-	.I(main_clkout2),
-	.O(main_clkout_buf2)
+	.I(clkout2),
+	.O(clkout_buf2)
 );
 
 BUFG BUFG_3(
-	.I(main_clkout3),
-	.O(main_clkout_buf3)
+	.I(clkout3),
+	.O(clkout_buf3)
 );
 
 IDELAYCTRL IDELAYCTRL(
 	.REFCLK(iodelay_clk),
-	.RST(main_ic_reset)
+	.RST(ic_reset)
 );
 
 OSERDESE2 #(
@@ -13496,12 +13939,12 @@ OSERDESE2 #(
 	.D7(1'd0),
 	.D8(1'd1),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(main_a7ddrphy_sd_clk_se_nodelay)
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_sd_clk_se_nodelay)
 );
 
 OBUFDS OBUFDS(
-	.I(main_a7ddrphy_sd_clk_se_nodelay),
+	.I(a7ddrphy_sd_clk_se_nodelay),
 	.O(ddram_clk_p),
 	.OB(ddram_clk_n)
 );
@@ -13515,16 +13958,16 @@ OSERDESE2 #(
 ) OSERDESE2_1 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_reset_n),
-	.D2(main_a7ddrphy_dfi_p0_reset_n),
-	.D3(main_a7ddrphy_dfi_p1_reset_n),
-	.D4(main_a7ddrphy_dfi_p1_reset_n),
-	.D5(main_a7ddrphy_dfi_p2_reset_n),
-	.D6(main_a7ddrphy_dfi_p2_reset_n),
-	.D7(main_a7ddrphy_dfi_p3_reset_n),
-	.D8(main_a7ddrphy_dfi_p3_reset_n),
+	.D1(a7ddrphy_dfi_p0_reset_n),
+	.D2(a7ddrphy_dfi_p0_reset_n),
+	.D3(a7ddrphy_dfi_p1_reset_n),
+	.D4(a7ddrphy_dfi_p1_reset_n),
+	.D5(a7ddrphy_dfi_p2_reset_n),
+	.D6(a7ddrphy_dfi_p2_reset_n),
+	.D7(a7ddrphy_dfi_p3_reset_n),
+	.D8(a7ddrphy_dfi_p3_reset_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_reset_n)
 );
 
@@ -13537,16 +13980,16 @@ OSERDESE2 #(
 ) OSERDESE2_2 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cs_n),
-	.D2(main_a7ddrphy_dfi_p0_cs_n),
-	.D3(main_a7ddrphy_dfi_p1_cs_n),
-	.D4(main_a7ddrphy_dfi_p1_cs_n),
-	.D5(main_a7ddrphy_dfi_p2_cs_n),
-	.D6(main_a7ddrphy_dfi_p2_cs_n),
-	.D7(main_a7ddrphy_dfi_p3_cs_n),
-	.D8(main_a7ddrphy_dfi_p3_cs_n),
+	.D1(a7ddrphy_dfi_p0_cs_n),
+	.D2(a7ddrphy_dfi_p0_cs_n),
+	.D3(a7ddrphy_dfi_p1_cs_n),
+	.D4(a7ddrphy_dfi_p1_cs_n),
+	.D5(a7ddrphy_dfi_p2_cs_n),
+	.D6(a7ddrphy_dfi_p2_cs_n),
+	.D7(a7ddrphy_dfi_p3_cs_n),
+	.D8(a7ddrphy_dfi_p3_cs_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cs_n)
 );
 
@@ -13559,16 +14002,16 @@ OSERDESE2 #(
 ) OSERDESE2_3 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[0]),
-	.D2(main_a7ddrphy_dfi_p0_address[0]),
-	.D3(main_a7ddrphy_dfi_p1_address[0]),
-	.D4(main_a7ddrphy_dfi_p1_address[0]),
-	.D5(main_a7ddrphy_dfi_p2_address[0]),
-	.D6(main_a7ddrphy_dfi_p2_address[0]),
-	.D7(main_a7ddrphy_dfi_p3_address[0]),
-	.D8(main_a7ddrphy_dfi_p3_address[0]),
+	.D1(a7ddrphy_dfi_p0_address[0]),
+	.D2(a7ddrphy_dfi_p0_address[0]),
+	.D3(a7ddrphy_dfi_p1_address[0]),
+	.D4(a7ddrphy_dfi_p1_address[0]),
+	.D5(a7ddrphy_dfi_p2_address[0]),
+	.D6(a7ddrphy_dfi_p2_address[0]),
+	.D7(a7ddrphy_dfi_p3_address[0]),
+	.D8(a7ddrphy_dfi_p3_address[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[0])
 );
 
@@ -13581,16 +14024,16 @@ OSERDESE2 #(
 ) OSERDESE2_4 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[1]),
-	.D2(main_a7ddrphy_dfi_p0_address[1]),
-	.D3(main_a7ddrphy_dfi_p1_address[1]),
-	.D4(main_a7ddrphy_dfi_p1_address[1]),
-	.D5(main_a7ddrphy_dfi_p2_address[1]),
-	.D6(main_a7ddrphy_dfi_p2_address[1]),
-	.D7(main_a7ddrphy_dfi_p3_address[1]),
-	.D8(main_a7ddrphy_dfi_p3_address[1]),
+	.D1(a7ddrphy_dfi_p0_address[1]),
+	.D2(a7ddrphy_dfi_p0_address[1]),
+	.D3(a7ddrphy_dfi_p1_address[1]),
+	.D4(a7ddrphy_dfi_p1_address[1]),
+	.D5(a7ddrphy_dfi_p2_address[1]),
+	.D6(a7ddrphy_dfi_p2_address[1]),
+	.D7(a7ddrphy_dfi_p3_address[1]),
+	.D8(a7ddrphy_dfi_p3_address[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[1])
 );
 
@@ -13603,16 +14046,16 @@ OSERDESE2 #(
 ) OSERDESE2_5 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[2]),
-	.D2(main_a7ddrphy_dfi_p0_address[2]),
-	.D3(main_a7ddrphy_dfi_p1_address[2]),
-	.D4(main_a7ddrphy_dfi_p1_address[2]),
-	.D5(main_a7ddrphy_dfi_p2_address[2]),
-	.D6(main_a7ddrphy_dfi_p2_address[2]),
-	.D7(main_a7ddrphy_dfi_p3_address[2]),
-	.D8(main_a7ddrphy_dfi_p3_address[2]),
+	.D1(a7ddrphy_dfi_p0_address[2]),
+	.D2(a7ddrphy_dfi_p0_address[2]),
+	.D3(a7ddrphy_dfi_p1_address[2]),
+	.D4(a7ddrphy_dfi_p1_address[2]),
+	.D5(a7ddrphy_dfi_p2_address[2]),
+	.D6(a7ddrphy_dfi_p2_address[2]),
+	.D7(a7ddrphy_dfi_p3_address[2]),
+	.D8(a7ddrphy_dfi_p3_address[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[2])
 );
 
@@ -13625,16 +14068,16 @@ OSERDESE2 #(
 ) OSERDESE2_6 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[3]),
-	.D2(main_a7ddrphy_dfi_p0_address[3]),
-	.D3(main_a7ddrphy_dfi_p1_address[3]),
-	.D4(main_a7ddrphy_dfi_p1_address[3]),
-	.D5(main_a7ddrphy_dfi_p2_address[3]),
-	.D6(main_a7ddrphy_dfi_p2_address[3]),
-	.D7(main_a7ddrphy_dfi_p3_address[3]),
-	.D8(main_a7ddrphy_dfi_p3_address[3]),
+	.D1(a7ddrphy_dfi_p0_address[3]),
+	.D2(a7ddrphy_dfi_p0_address[3]),
+	.D3(a7ddrphy_dfi_p1_address[3]),
+	.D4(a7ddrphy_dfi_p1_address[3]),
+	.D5(a7ddrphy_dfi_p2_address[3]),
+	.D6(a7ddrphy_dfi_p2_address[3]),
+	.D7(a7ddrphy_dfi_p3_address[3]),
+	.D8(a7ddrphy_dfi_p3_address[3]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[3])
 );
 
@@ -13647,16 +14090,16 @@ OSERDESE2 #(
 ) OSERDESE2_7 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[4]),
-	.D2(main_a7ddrphy_dfi_p0_address[4]),
-	.D3(main_a7ddrphy_dfi_p1_address[4]),
-	.D4(main_a7ddrphy_dfi_p1_address[4]),
-	.D5(main_a7ddrphy_dfi_p2_address[4]),
-	.D6(main_a7ddrphy_dfi_p2_address[4]),
-	.D7(main_a7ddrphy_dfi_p3_address[4]),
-	.D8(main_a7ddrphy_dfi_p3_address[4]),
+	.D1(a7ddrphy_dfi_p0_address[4]),
+	.D2(a7ddrphy_dfi_p0_address[4]),
+	.D3(a7ddrphy_dfi_p1_address[4]),
+	.D4(a7ddrphy_dfi_p1_address[4]),
+	.D5(a7ddrphy_dfi_p2_address[4]),
+	.D6(a7ddrphy_dfi_p2_address[4]),
+	.D7(a7ddrphy_dfi_p3_address[4]),
+	.D8(a7ddrphy_dfi_p3_address[4]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[4])
 );
 
@@ -13669,16 +14112,16 @@ OSERDESE2 #(
 ) OSERDESE2_8 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[5]),
-	.D2(main_a7ddrphy_dfi_p0_address[5]),
-	.D3(main_a7ddrphy_dfi_p1_address[5]),
-	.D4(main_a7ddrphy_dfi_p1_address[5]),
-	.D5(main_a7ddrphy_dfi_p2_address[5]),
-	.D6(main_a7ddrphy_dfi_p2_address[5]),
-	.D7(main_a7ddrphy_dfi_p3_address[5]),
-	.D8(main_a7ddrphy_dfi_p3_address[5]),
+	.D1(a7ddrphy_dfi_p0_address[5]),
+	.D2(a7ddrphy_dfi_p0_address[5]),
+	.D3(a7ddrphy_dfi_p1_address[5]),
+	.D4(a7ddrphy_dfi_p1_address[5]),
+	.D5(a7ddrphy_dfi_p2_address[5]),
+	.D6(a7ddrphy_dfi_p2_address[5]),
+	.D7(a7ddrphy_dfi_p3_address[5]),
+	.D8(a7ddrphy_dfi_p3_address[5]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[5])
 );
 
@@ -13691,16 +14134,16 @@ OSERDESE2 #(
 ) OSERDESE2_9 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[6]),
-	.D2(main_a7ddrphy_dfi_p0_address[6]),
-	.D3(main_a7ddrphy_dfi_p1_address[6]),
-	.D4(main_a7ddrphy_dfi_p1_address[6]),
-	.D5(main_a7ddrphy_dfi_p2_address[6]),
-	.D6(main_a7ddrphy_dfi_p2_address[6]),
-	.D7(main_a7ddrphy_dfi_p3_address[6]),
-	.D8(main_a7ddrphy_dfi_p3_address[6]),
+	.D1(a7ddrphy_dfi_p0_address[6]),
+	.D2(a7ddrphy_dfi_p0_address[6]),
+	.D3(a7ddrphy_dfi_p1_address[6]),
+	.D4(a7ddrphy_dfi_p1_address[6]),
+	.D5(a7ddrphy_dfi_p2_address[6]),
+	.D6(a7ddrphy_dfi_p2_address[6]),
+	.D7(a7ddrphy_dfi_p3_address[6]),
+	.D8(a7ddrphy_dfi_p3_address[6]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[6])
 );
 
@@ -13713,16 +14156,16 @@ OSERDESE2 #(
 ) OSERDESE2_10 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[7]),
-	.D2(main_a7ddrphy_dfi_p0_address[7]),
-	.D3(main_a7ddrphy_dfi_p1_address[7]),
-	.D4(main_a7ddrphy_dfi_p1_address[7]),
-	.D5(main_a7ddrphy_dfi_p2_address[7]),
-	.D6(main_a7ddrphy_dfi_p2_address[7]),
-	.D7(main_a7ddrphy_dfi_p3_address[7]),
-	.D8(main_a7ddrphy_dfi_p3_address[7]),
+	.D1(a7ddrphy_dfi_p0_address[7]),
+	.D2(a7ddrphy_dfi_p0_address[7]),
+	.D3(a7ddrphy_dfi_p1_address[7]),
+	.D4(a7ddrphy_dfi_p1_address[7]),
+	.D5(a7ddrphy_dfi_p2_address[7]),
+	.D6(a7ddrphy_dfi_p2_address[7]),
+	.D7(a7ddrphy_dfi_p3_address[7]),
+	.D8(a7ddrphy_dfi_p3_address[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[7])
 );
 
@@ -13735,16 +14178,16 @@ OSERDESE2 #(
 ) OSERDESE2_11 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[8]),
-	.D2(main_a7ddrphy_dfi_p0_address[8]),
-	.D3(main_a7ddrphy_dfi_p1_address[8]),
-	.D4(main_a7ddrphy_dfi_p1_address[8]),
-	.D5(main_a7ddrphy_dfi_p2_address[8]),
-	.D6(main_a7ddrphy_dfi_p2_address[8]),
-	.D7(main_a7ddrphy_dfi_p3_address[8]),
-	.D8(main_a7ddrphy_dfi_p3_address[8]),
+	.D1(a7ddrphy_dfi_p0_address[8]),
+	.D2(a7ddrphy_dfi_p0_address[8]),
+	.D3(a7ddrphy_dfi_p1_address[8]),
+	.D4(a7ddrphy_dfi_p1_address[8]),
+	.D5(a7ddrphy_dfi_p2_address[8]),
+	.D6(a7ddrphy_dfi_p2_address[8]),
+	.D7(a7ddrphy_dfi_p3_address[8]),
+	.D8(a7ddrphy_dfi_p3_address[8]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[8])
 );
 
@@ -13757,16 +14200,16 @@ OSERDESE2 #(
 ) OSERDESE2_12 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[9]),
-	.D2(main_a7ddrphy_dfi_p0_address[9]),
-	.D3(main_a7ddrphy_dfi_p1_address[9]),
-	.D4(main_a7ddrphy_dfi_p1_address[9]),
-	.D5(main_a7ddrphy_dfi_p2_address[9]),
-	.D6(main_a7ddrphy_dfi_p2_address[9]),
-	.D7(main_a7ddrphy_dfi_p3_address[9]),
-	.D8(main_a7ddrphy_dfi_p3_address[9]),
+	.D1(a7ddrphy_dfi_p0_address[9]),
+	.D2(a7ddrphy_dfi_p0_address[9]),
+	.D3(a7ddrphy_dfi_p1_address[9]),
+	.D4(a7ddrphy_dfi_p1_address[9]),
+	.D5(a7ddrphy_dfi_p2_address[9]),
+	.D6(a7ddrphy_dfi_p2_address[9]),
+	.D7(a7ddrphy_dfi_p3_address[9]),
+	.D8(a7ddrphy_dfi_p3_address[9]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[9])
 );
 
@@ -13779,16 +14222,16 @@ OSERDESE2 #(
 ) OSERDESE2_13 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[10]),
-	.D2(main_a7ddrphy_dfi_p0_address[10]),
-	.D3(main_a7ddrphy_dfi_p1_address[10]),
-	.D4(main_a7ddrphy_dfi_p1_address[10]),
-	.D5(main_a7ddrphy_dfi_p2_address[10]),
-	.D6(main_a7ddrphy_dfi_p2_address[10]),
-	.D7(main_a7ddrphy_dfi_p3_address[10]),
-	.D8(main_a7ddrphy_dfi_p3_address[10]),
+	.D1(a7ddrphy_dfi_p0_address[10]),
+	.D2(a7ddrphy_dfi_p0_address[10]),
+	.D3(a7ddrphy_dfi_p1_address[10]),
+	.D4(a7ddrphy_dfi_p1_address[10]),
+	.D5(a7ddrphy_dfi_p2_address[10]),
+	.D6(a7ddrphy_dfi_p2_address[10]),
+	.D7(a7ddrphy_dfi_p3_address[10]),
+	.D8(a7ddrphy_dfi_p3_address[10]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[10])
 );
 
@@ -13801,16 +14244,16 @@ OSERDESE2 #(
 ) OSERDESE2_14 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[11]),
-	.D2(main_a7ddrphy_dfi_p0_address[11]),
-	.D3(main_a7ddrphy_dfi_p1_address[11]),
-	.D4(main_a7ddrphy_dfi_p1_address[11]),
-	.D5(main_a7ddrphy_dfi_p2_address[11]),
-	.D6(main_a7ddrphy_dfi_p2_address[11]),
-	.D7(main_a7ddrphy_dfi_p3_address[11]),
-	.D8(main_a7ddrphy_dfi_p3_address[11]),
+	.D1(a7ddrphy_dfi_p0_address[11]),
+	.D2(a7ddrphy_dfi_p0_address[11]),
+	.D3(a7ddrphy_dfi_p1_address[11]),
+	.D4(a7ddrphy_dfi_p1_address[11]),
+	.D5(a7ddrphy_dfi_p2_address[11]),
+	.D6(a7ddrphy_dfi_p2_address[11]),
+	.D7(a7ddrphy_dfi_p3_address[11]),
+	.D8(a7ddrphy_dfi_p3_address[11]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[11])
 );
 
@@ -13823,16 +14266,16 @@ OSERDESE2 #(
 ) OSERDESE2_15 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[12]),
-	.D2(main_a7ddrphy_dfi_p0_address[12]),
-	.D3(main_a7ddrphy_dfi_p1_address[12]),
-	.D4(main_a7ddrphy_dfi_p1_address[12]),
-	.D5(main_a7ddrphy_dfi_p2_address[12]),
-	.D6(main_a7ddrphy_dfi_p2_address[12]),
-	.D7(main_a7ddrphy_dfi_p3_address[12]),
-	.D8(main_a7ddrphy_dfi_p3_address[12]),
+	.D1(a7ddrphy_dfi_p0_address[12]),
+	.D2(a7ddrphy_dfi_p0_address[12]),
+	.D3(a7ddrphy_dfi_p1_address[12]),
+	.D4(a7ddrphy_dfi_p1_address[12]),
+	.D5(a7ddrphy_dfi_p2_address[12]),
+	.D6(a7ddrphy_dfi_p2_address[12]),
+	.D7(a7ddrphy_dfi_p3_address[12]),
+	.D8(a7ddrphy_dfi_p3_address[12]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[12])
 );
 
@@ -13845,16 +14288,16 @@ OSERDESE2 #(
 ) OSERDESE2_16 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[13]),
-	.D2(main_a7ddrphy_dfi_p0_address[13]),
-	.D3(main_a7ddrphy_dfi_p1_address[13]),
-	.D4(main_a7ddrphy_dfi_p1_address[13]),
-	.D5(main_a7ddrphy_dfi_p2_address[13]),
-	.D6(main_a7ddrphy_dfi_p2_address[13]),
-	.D7(main_a7ddrphy_dfi_p3_address[13]),
-	.D8(main_a7ddrphy_dfi_p3_address[13]),
+	.D1(a7ddrphy_dfi_p0_address[13]),
+	.D2(a7ddrphy_dfi_p0_address[13]),
+	.D3(a7ddrphy_dfi_p1_address[13]),
+	.D4(a7ddrphy_dfi_p1_address[13]),
+	.D5(a7ddrphy_dfi_p2_address[13]),
+	.D6(a7ddrphy_dfi_p2_address[13]),
+	.D7(a7ddrphy_dfi_p3_address[13]),
+	.D8(a7ddrphy_dfi_p3_address[13]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[13])
 );
 
@@ -13867,17 +14310,17 @@ OSERDESE2 #(
 ) OSERDESE2_17 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[0]),
-	.D2(main_a7ddrphy_dfi_p0_bank[0]),
-	.D3(main_a7ddrphy_dfi_p1_bank[0]),
-	.D4(main_a7ddrphy_dfi_p1_bank[0]),
-	.D5(main_a7ddrphy_dfi_p2_bank[0]),
-	.D6(main_a7ddrphy_dfi_p2_bank[0]),
-	.D7(main_a7ddrphy_dfi_p3_bank[0]),
-	.D8(main_a7ddrphy_dfi_p3_bank[0]),
+	.D1(a7ddrphy_dfi_p0_bank[0]),
+	.D2(a7ddrphy_dfi_p0_bank[0]),
+	.D3(a7ddrphy_dfi_p1_bank[0]),
+	.D4(a7ddrphy_dfi_p1_bank[0]),
+	.D5(a7ddrphy_dfi_p2_bank[0]),
+	.D6(a7ddrphy_dfi_p2_bank[0]),
+	.D7(a7ddrphy_dfi_p3_bank[0]),
+	.D8(a7ddrphy_dfi_p3_bank[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[0])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[0])
 );
 
 OSERDESE2 #(
@@ -13889,17 +14332,17 @@ OSERDESE2 #(
 ) OSERDESE2_18 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[1]),
-	.D2(main_a7ddrphy_dfi_p0_bank[1]),
-	.D3(main_a7ddrphy_dfi_p1_bank[1]),
-	.D4(main_a7ddrphy_dfi_p1_bank[1]),
-	.D5(main_a7ddrphy_dfi_p2_bank[1]),
-	.D6(main_a7ddrphy_dfi_p2_bank[1]),
-	.D7(main_a7ddrphy_dfi_p3_bank[1]),
-	.D8(main_a7ddrphy_dfi_p3_bank[1]),
+	.D1(a7ddrphy_dfi_p0_bank[1]),
+	.D2(a7ddrphy_dfi_p0_bank[1]),
+	.D3(a7ddrphy_dfi_p1_bank[1]),
+	.D4(a7ddrphy_dfi_p1_bank[1]),
+	.D5(a7ddrphy_dfi_p2_bank[1]),
+	.D6(a7ddrphy_dfi_p2_bank[1]),
+	.D7(a7ddrphy_dfi_p3_bank[1]),
+	.D8(a7ddrphy_dfi_p3_bank[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[1])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[1])
 );
 
 OSERDESE2 #(
@@ -13911,17 +14354,17 @@ OSERDESE2 #(
 ) OSERDESE2_19 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[2]),
-	.D2(main_a7ddrphy_dfi_p0_bank[2]),
-	.D3(main_a7ddrphy_dfi_p1_bank[2]),
-	.D4(main_a7ddrphy_dfi_p1_bank[2]),
-	.D5(main_a7ddrphy_dfi_p2_bank[2]),
-	.D6(main_a7ddrphy_dfi_p2_bank[2]),
-	.D7(main_a7ddrphy_dfi_p3_bank[2]),
-	.D8(main_a7ddrphy_dfi_p3_bank[2]),
+	.D1(a7ddrphy_dfi_p0_bank[2]),
+	.D2(a7ddrphy_dfi_p0_bank[2]),
+	.D3(a7ddrphy_dfi_p1_bank[2]),
+	.D4(a7ddrphy_dfi_p1_bank[2]),
+	.D5(a7ddrphy_dfi_p2_bank[2]),
+	.D6(a7ddrphy_dfi_p2_bank[2]),
+	.D7(a7ddrphy_dfi_p3_bank[2]),
+	.D8(a7ddrphy_dfi_p3_bank[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[2])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[2])
 );
 
 OSERDESE2 #(
@@ -13933,16 +14376,16 @@ OSERDESE2 #(
 ) OSERDESE2_20 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_ras_n),
-	.D2(main_a7ddrphy_dfi_p0_ras_n),
-	.D3(main_a7ddrphy_dfi_p1_ras_n),
-	.D4(main_a7ddrphy_dfi_p1_ras_n),
-	.D5(main_a7ddrphy_dfi_p2_ras_n),
-	.D6(main_a7ddrphy_dfi_p2_ras_n),
-	.D7(main_a7ddrphy_dfi_p3_ras_n),
-	.D8(main_a7ddrphy_dfi_p3_ras_n),
+	.D1(a7ddrphy_dfi_p0_ras_n),
+	.D2(a7ddrphy_dfi_p0_ras_n),
+	.D3(a7ddrphy_dfi_p1_ras_n),
+	.D4(a7ddrphy_dfi_p1_ras_n),
+	.D5(a7ddrphy_dfi_p2_ras_n),
+	.D6(a7ddrphy_dfi_p2_ras_n),
+	.D7(a7ddrphy_dfi_p3_ras_n),
+	.D8(a7ddrphy_dfi_p3_ras_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_ras_n)
 );
 
@@ -13955,16 +14398,16 @@ OSERDESE2 #(
 ) OSERDESE2_21 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cas_n),
-	.D2(main_a7ddrphy_dfi_p0_cas_n),
-	.D3(main_a7ddrphy_dfi_p1_cas_n),
-	.D4(main_a7ddrphy_dfi_p1_cas_n),
-	.D5(main_a7ddrphy_dfi_p2_cas_n),
-	.D6(main_a7ddrphy_dfi_p2_cas_n),
-	.D7(main_a7ddrphy_dfi_p3_cas_n),
-	.D8(main_a7ddrphy_dfi_p3_cas_n),
+	.D1(a7ddrphy_dfi_p0_cas_n),
+	.D2(a7ddrphy_dfi_p0_cas_n),
+	.D3(a7ddrphy_dfi_p1_cas_n),
+	.D4(a7ddrphy_dfi_p1_cas_n),
+	.D5(a7ddrphy_dfi_p2_cas_n),
+	.D6(a7ddrphy_dfi_p2_cas_n),
+	.D7(a7ddrphy_dfi_p3_cas_n),
+	.D8(a7ddrphy_dfi_p3_cas_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cas_n)
 );
 
@@ -13977,16 +14420,16 @@ OSERDESE2 #(
 ) OSERDESE2_22 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_we_n),
-	.D2(main_a7ddrphy_dfi_p0_we_n),
-	.D3(main_a7ddrphy_dfi_p1_we_n),
-	.D4(main_a7ddrphy_dfi_p1_we_n),
-	.D5(main_a7ddrphy_dfi_p2_we_n),
-	.D6(main_a7ddrphy_dfi_p2_we_n),
-	.D7(main_a7ddrphy_dfi_p3_we_n),
-	.D8(main_a7ddrphy_dfi_p3_we_n),
+	.D1(a7ddrphy_dfi_p0_we_n),
+	.D2(a7ddrphy_dfi_p0_we_n),
+	.D3(a7ddrphy_dfi_p1_we_n),
+	.D4(a7ddrphy_dfi_p1_we_n),
+	.D5(a7ddrphy_dfi_p2_we_n),
+	.D6(a7ddrphy_dfi_p2_we_n),
+	.D7(a7ddrphy_dfi_p3_we_n),
+	.D8(a7ddrphy_dfi_p3_we_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_we_n)
 );
 
@@ -13999,16 +14442,16 @@ OSERDESE2 #(
 ) OSERDESE2_23 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cke),
-	.D2(main_a7ddrphy_dfi_p0_cke),
-	.D3(main_a7ddrphy_dfi_p1_cke),
-	.D4(main_a7ddrphy_dfi_p1_cke),
-	.D5(main_a7ddrphy_dfi_p2_cke),
-	.D6(main_a7ddrphy_dfi_p2_cke),
-	.D7(main_a7ddrphy_dfi_p3_cke),
-	.D8(main_a7ddrphy_dfi_p3_cke),
+	.D1(a7ddrphy_dfi_p0_cke),
+	.D2(a7ddrphy_dfi_p0_cke),
+	.D3(a7ddrphy_dfi_p1_cke),
+	.D4(a7ddrphy_dfi_p1_cke),
+	.D5(a7ddrphy_dfi_p2_cke),
+	.D6(a7ddrphy_dfi_p2_cke),
+	.D7(a7ddrphy_dfi_p3_cke),
+	.D8(a7ddrphy_dfi_p3_cke),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cke)
 );
 
@@ -14021,16 +14464,16 @@ OSERDESE2 #(
 ) OSERDESE2_24 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_odt),
-	.D2(main_a7ddrphy_dfi_p0_odt),
-	.D3(main_a7ddrphy_dfi_p1_odt),
-	.D4(main_a7ddrphy_dfi_p1_odt),
-	.D5(main_a7ddrphy_dfi_p2_odt),
-	.D6(main_a7ddrphy_dfi_p2_odt),
-	.D7(main_a7ddrphy_dfi_p3_odt),
-	.D8(main_a7ddrphy_dfi_p3_odt),
+	.D1(a7ddrphy_dfi_p0_odt),
+	.D2(a7ddrphy_dfi_p0_odt),
+	.D3(a7ddrphy_dfi_p1_odt),
+	.D4(a7ddrphy_dfi_p1_odt),
+	.D5(a7ddrphy_dfi_p2_odt),
+	.D6(a7ddrphy_dfi_p2_odt),
+	.D7(a7ddrphy_dfi_p3_odt),
+	.D8(a7ddrphy_dfi_p3_odt),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_odt)
 );
 
@@ -14043,26 +14486,26 @@ OSERDESE2 #(
 ) OSERDESE2_25 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip00[0]),
-	.D2(main_a7ddrphy_bitslip00[1]),
-	.D3(main_a7ddrphy_bitslip00[2]),
-	.D4(main_a7ddrphy_bitslip00[3]),
-	.D5(main_a7ddrphy_bitslip00[4]),
-	.D6(main_a7ddrphy_bitslip00[5]),
-	.D7(main_a7ddrphy_bitslip00[6]),
-	.D8(main_a7ddrphy_bitslip00[7]),
+	.D1(a7ddrphy_bitslip00[0]),
+	.D2(a7ddrphy_bitslip00[1]),
+	.D3(a7ddrphy_bitslip00[2]),
+	.D4(a7ddrphy_bitslip00[3]),
+	.D5(a7ddrphy_bitslip00[4]),
+	.D6(a7ddrphy_bitslip00[5]),
+	.D7(a7ddrphy_bitslip00[6]),
+	.D8(a7ddrphy_bitslip00[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy0),
-	.OQ(main_a7ddrphy_dqs_o_no_delay0),
-	.TQ(main_a7ddrphy_dqs_t0)
+	.OFB(a7ddrphy0),
+	.OQ(a7ddrphy_dqs_o_no_delay0),
+	.TQ(a7ddrphy_dqs_t0)
 );
 
 IOBUFDS IOBUFDS(
-	.I(main_a7ddrphy_dqs_o_no_delay0),
-	.T(main_a7ddrphy_dqs_t0),
+	.I(a7ddrphy_dqs_o_no_delay0),
+	.T(a7ddrphy_dqs_t0),
 	.IO(ddram_dqs_p[0]),
 	.IOB(ddram_dqs_n[0])
 );
@@ -14076,26 +14519,26 @@ OSERDESE2 #(
 ) OSERDESE2_26 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip10[0]),
-	.D2(main_a7ddrphy_bitslip10[1]),
-	.D3(main_a7ddrphy_bitslip10[2]),
-	.D4(main_a7ddrphy_bitslip10[3]),
-	.D5(main_a7ddrphy_bitslip10[4]),
-	.D6(main_a7ddrphy_bitslip10[5]),
-	.D7(main_a7ddrphy_bitslip10[6]),
-	.D8(main_a7ddrphy_bitslip10[7]),
+	.D1(a7ddrphy_bitslip10[0]),
+	.D2(a7ddrphy_bitslip10[1]),
+	.D3(a7ddrphy_bitslip10[2]),
+	.D4(a7ddrphy_bitslip10[3]),
+	.D5(a7ddrphy_bitslip10[4]),
+	.D6(a7ddrphy_bitslip10[5]),
+	.D7(a7ddrphy_bitslip10[6]),
+	.D8(a7ddrphy_bitslip10[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy1),
-	.OQ(main_a7ddrphy_dqs_o_no_delay1),
-	.TQ(main_a7ddrphy_dqs_t1)
+	.OFB(a7ddrphy1),
+	.OQ(a7ddrphy_dqs_o_no_delay1),
+	.TQ(a7ddrphy_dqs_t1)
 );
 
 IOBUFDS IOBUFDS_1(
-	.I(main_a7ddrphy_dqs_o_no_delay1),
-	.T(main_a7ddrphy_dqs_t1),
+	.I(a7ddrphy_dqs_o_no_delay1),
+	.T(a7ddrphy_dqs_t1),
 	.IO(ddram_dqs_p[1]),
 	.IOB(ddram_dqs_n[1])
 );
@@ -14109,16 +14552,16 @@ OSERDESE2 #(
 ) OSERDESE2_27 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip01[0]),
-	.D2(main_a7ddrphy_bitslip01[1]),
-	.D3(main_a7ddrphy_bitslip01[2]),
-	.D4(main_a7ddrphy_bitslip01[3]),
-	.D5(main_a7ddrphy_bitslip01[4]),
-	.D6(main_a7ddrphy_bitslip01[5]),
-	.D7(main_a7ddrphy_bitslip01[6]),
-	.D8(main_a7ddrphy_bitslip01[7]),
+	.D1(a7ddrphy_bitslip01[0]),
+	.D2(a7ddrphy_bitslip01[1]),
+	.D3(a7ddrphy_bitslip01[2]),
+	.D4(a7ddrphy_bitslip01[3]),
+	.D5(a7ddrphy_bitslip01[4]),
+	.D6(a7ddrphy_bitslip01[5]),
+	.D7(a7ddrphy_bitslip01[6]),
+	.D8(a7ddrphy_bitslip01[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[0])
 );
 
@@ -14131,16 +14574,16 @@ OSERDESE2 #(
 ) OSERDESE2_28 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip11[0]),
-	.D2(main_a7ddrphy_bitslip11[1]),
-	.D3(main_a7ddrphy_bitslip11[2]),
-	.D4(main_a7ddrphy_bitslip11[3]),
-	.D5(main_a7ddrphy_bitslip11[4]),
-	.D6(main_a7ddrphy_bitslip11[5]),
-	.D7(main_a7ddrphy_bitslip11[6]),
-	.D8(main_a7ddrphy_bitslip11[7]),
+	.D1(a7ddrphy_bitslip11[0]),
+	.D2(a7ddrphy_bitslip11[1]),
+	.D3(a7ddrphy_bitslip11[2]),
+	.D4(a7ddrphy_bitslip11[3]),
+	.D5(a7ddrphy_bitslip11[4]),
+	.D6(a7ddrphy_bitslip11[5]),
+	.D7(a7ddrphy_bitslip11[6]),
+	.D8(a7ddrphy_bitslip11[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[1])
 );
 
@@ -14153,20 +14596,20 @@ OSERDESE2 #(
 ) OSERDESE2_29 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip02[0]),
-	.D2(main_a7ddrphy_bitslip02[1]),
-	.D3(main_a7ddrphy_bitslip02[2]),
-	.D4(main_a7ddrphy_bitslip02[3]),
-	.D5(main_a7ddrphy_bitslip02[4]),
-	.D6(main_a7ddrphy_bitslip02[5]),
-	.D7(main_a7ddrphy_bitslip02[6]),
-	.D8(main_a7ddrphy_bitslip02[7]),
+	.D1(a7ddrphy_bitslip02[0]),
+	.D2(a7ddrphy_bitslip02[1]),
+	.D3(a7ddrphy_bitslip02[2]),
+	.D4(a7ddrphy_bitslip02[3]),
+	.D5(a7ddrphy_bitslip02[4]),
+	.D6(a7ddrphy_bitslip02[5]),
+	.D7(a7ddrphy_bitslip02[6]),
+	.D8(a7ddrphy_bitslip02[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay0),
-	.TQ(main_a7ddrphy_dq_t0)
+	.OQ(a7ddrphy_dq_o_nodelay0),
+	.TQ(a7ddrphy_dq_t0)
 );
 
 ISERDESE2 #(
@@ -14182,16 +14625,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip03[7]),
-	.Q2(main_a7ddrphy_bitslip03[6]),
-	.Q3(main_a7ddrphy_bitslip03[5]),
-	.Q4(main_a7ddrphy_bitslip03[4]),
-	.Q5(main_a7ddrphy_bitslip03[3]),
-	.Q6(main_a7ddrphy_bitslip03[2]),
-	.Q7(main_a7ddrphy_bitslip03[1]),
-	.Q8(main_a7ddrphy_bitslip03[0])
+	.DDLY(a7ddrphy_dq_i_delayed0),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip03[7]),
+	.Q2(a7ddrphy_bitslip03[6]),
+	.Q3(a7ddrphy_bitslip03[5]),
+	.Q4(a7ddrphy_bitslip03[4]),
+	.Q5(a7ddrphy_bitslip03[3]),
+	.Q6(a7ddrphy_bitslip03[2]),
+	.Q7(a7ddrphy_bitslip03[1]),
+	.Q8(a7ddrphy_bitslip03[0])
 );
 
 IDELAYE2 #(
@@ -14205,19 +14648,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay0),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay0),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed0)
+	.DATAOUT(a7ddrphy_dq_i_delayed0)
 );
 
 IOBUF IOBUF(
-	.I(main_a7ddrphy_dq_o_nodelay0),
-	.T(main_a7ddrphy_dq_t0),
+	.I(a7ddrphy_dq_o_nodelay0),
+	.T(a7ddrphy_dq_t0),
 	.IO(ddram_dq[0]),
-	.O(main_a7ddrphy_dq_i_nodelay0)
+	.O(a7ddrphy_dq_i_nodelay0)
 );
 
 OSERDESE2 #(
@@ -14229,20 +14672,20 @@ OSERDESE2 #(
 ) OSERDESE2_30 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip12[0]),
-	.D2(main_a7ddrphy_bitslip12[1]),
-	.D3(main_a7ddrphy_bitslip12[2]),
-	.D4(main_a7ddrphy_bitslip12[3]),
-	.D5(main_a7ddrphy_bitslip12[4]),
-	.D6(main_a7ddrphy_bitslip12[5]),
-	.D7(main_a7ddrphy_bitslip12[6]),
-	.D8(main_a7ddrphy_bitslip12[7]),
+	.D1(a7ddrphy_bitslip12[0]),
+	.D2(a7ddrphy_bitslip12[1]),
+	.D3(a7ddrphy_bitslip12[2]),
+	.D4(a7ddrphy_bitslip12[3]),
+	.D5(a7ddrphy_bitslip12[4]),
+	.D6(a7ddrphy_bitslip12[5]),
+	.D7(a7ddrphy_bitslip12[6]),
+	.D8(a7ddrphy_bitslip12[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay1),
-	.TQ(main_a7ddrphy_dq_t1)
+	.OQ(a7ddrphy_dq_o_nodelay1),
+	.TQ(a7ddrphy_dq_t1)
 );
 
 ISERDESE2 #(
@@ -14258,16 +14701,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip13[7]),
-	.Q2(main_a7ddrphy_bitslip13[6]),
-	.Q3(main_a7ddrphy_bitslip13[5]),
-	.Q4(main_a7ddrphy_bitslip13[4]),
-	.Q5(main_a7ddrphy_bitslip13[3]),
-	.Q6(main_a7ddrphy_bitslip13[2]),
-	.Q7(main_a7ddrphy_bitslip13[1]),
-	.Q8(main_a7ddrphy_bitslip13[0])
+	.DDLY(a7ddrphy_dq_i_delayed1),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip13[7]),
+	.Q2(a7ddrphy_bitslip13[6]),
+	.Q3(a7ddrphy_bitslip13[5]),
+	.Q4(a7ddrphy_bitslip13[4]),
+	.Q5(a7ddrphy_bitslip13[3]),
+	.Q6(a7ddrphy_bitslip13[2]),
+	.Q7(a7ddrphy_bitslip13[1]),
+	.Q8(a7ddrphy_bitslip13[0])
 );
 
 IDELAYE2 #(
@@ -14281,19 +14724,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_1 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay1),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay1),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed1)
+	.DATAOUT(a7ddrphy_dq_i_delayed1)
 );
 
 IOBUF IOBUF_1(
-	.I(main_a7ddrphy_dq_o_nodelay1),
-	.T(main_a7ddrphy_dq_t1),
+	.I(a7ddrphy_dq_o_nodelay1),
+	.T(a7ddrphy_dq_t1),
 	.IO(ddram_dq[1]),
-	.O(main_a7ddrphy_dq_i_nodelay1)
+	.O(a7ddrphy_dq_i_nodelay1)
 );
 
 OSERDESE2 #(
@@ -14305,20 +14748,20 @@ OSERDESE2 #(
 ) OSERDESE2_31 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip20[0]),
-	.D2(main_a7ddrphy_bitslip20[1]),
-	.D3(main_a7ddrphy_bitslip20[2]),
-	.D4(main_a7ddrphy_bitslip20[3]),
-	.D5(main_a7ddrphy_bitslip20[4]),
-	.D6(main_a7ddrphy_bitslip20[5]),
-	.D7(main_a7ddrphy_bitslip20[6]),
-	.D8(main_a7ddrphy_bitslip20[7]),
+	.D1(a7ddrphy_bitslip20[0]),
+	.D2(a7ddrphy_bitslip20[1]),
+	.D3(a7ddrphy_bitslip20[2]),
+	.D4(a7ddrphy_bitslip20[3]),
+	.D5(a7ddrphy_bitslip20[4]),
+	.D6(a7ddrphy_bitslip20[5]),
+	.D7(a7ddrphy_bitslip20[6]),
+	.D8(a7ddrphy_bitslip20[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay2),
-	.TQ(main_a7ddrphy_dq_t2)
+	.OQ(a7ddrphy_dq_o_nodelay2),
+	.TQ(a7ddrphy_dq_t2)
 );
 
 ISERDESE2 #(
@@ -14334,16 +14777,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip21[7]),
-	.Q2(main_a7ddrphy_bitslip21[6]),
-	.Q3(main_a7ddrphy_bitslip21[5]),
-	.Q4(main_a7ddrphy_bitslip21[4]),
-	.Q5(main_a7ddrphy_bitslip21[3]),
-	.Q6(main_a7ddrphy_bitslip21[2]),
-	.Q7(main_a7ddrphy_bitslip21[1]),
-	.Q8(main_a7ddrphy_bitslip21[0])
+	.DDLY(a7ddrphy_dq_i_delayed2),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip21[7]),
+	.Q2(a7ddrphy_bitslip21[6]),
+	.Q3(a7ddrphy_bitslip21[5]),
+	.Q4(a7ddrphy_bitslip21[4]),
+	.Q5(a7ddrphy_bitslip21[3]),
+	.Q6(a7ddrphy_bitslip21[2]),
+	.Q7(a7ddrphy_bitslip21[1]),
+	.Q8(a7ddrphy_bitslip21[0])
 );
 
 IDELAYE2 #(
@@ -14357,19 +14800,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay2),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay2),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed2)
+	.DATAOUT(a7ddrphy_dq_i_delayed2)
 );
 
 IOBUF IOBUF_2(
-	.I(main_a7ddrphy_dq_o_nodelay2),
-	.T(main_a7ddrphy_dq_t2),
+	.I(a7ddrphy_dq_o_nodelay2),
+	.T(a7ddrphy_dq_t2),
 	.IO(ddram_dq[2]),
-	.O(main_a7ddrphy_dq_i_nodelay2)
+	.O(a7ddrphy_dq_i_nodelay2)
 );
 
 OSERDESE2 #(
@@ -14381,20 +14824,20 @@ OSERDESE2 #(
 ) OSERDESE2_32 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip30[0]),
-	.D2(main_a7ddrphy_bitslip30[1]),
-	.D3(main_a7ddrphy_bitslip30[2]),
-	.D4(main_a7ddrphy_bitslip30[3]),
-	.D5(main_a7ddrphy_bitslip30[4]),
-	.D6(main_a7ddrphy_bitslip30[5]),
-	.D7(main_a7ddrphy_bitslip30[6]),
-	.D8(main_a7ddrphy_bitslip30[7]),
+	.D1(a7ddrphy_bitslip30[0]),
+	.D2(a7ddrphy_bitslip30[1]),
+	.D3(a7ddrphy_bitslip30[2]),
+	.D4(a7ddrphy_bitslip30[3]),
+	.D5(a7ddrphy_bitslip30[4]),
+	.D6(a7ddrphy_bitslip30[5]),
+	.D7(a7ddrphy_bitslip30[6]),
+	.D8(a7ddrphy_bitslip30[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay3),
-	.TQ(main_a7ddrphy_dq_t3)
+	.OQ(a7ddrphy_dq_o_nodelay3),
+	.TQ(a7ddrphy_dq_t3)
 );
 
 ISERDESE2 #(
@@ -14410,16 +14853,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip31[7]),
-	.Q2(main_a7ddrphy_bitslip31[6]),
-	.Q3(main_a7ddrphy_bitslip31[5]),
-	.Q4(main_a7ddrphy_bitslip31[4]),
-	.Q5(main_a7ddrphy_bitslip31[3]),
-	.Q6(main_a7ddrphy_bitslip31[2]),
-	.Q7(main_a7ddrphy_bitslip31[1]),
-	.Q8(main_a7ddrphy_bitslip31[0])
+	.DDLY(a7ddrphy_dq_i_delayed3),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip31[7]),
+	.Q2(a7ddrphy_bitslip31[6]),
+	.Q3(a7ddrphy_bitslip31[5]),
+	.Q4(a7ddrphy_bitslip31[4]),
+	.Q5(a7ddrphy_bitslip31[3]),
+	.Q6(a7ddrphy_bitslip31[2]),
+	.Q7(a7ddrphy_bitslip31[1]),
+	.Q8(a7ddrphy_bitslip31[0])
 );
 
 IDELAYE2 #(
@@ -14433,19 +14876,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_3 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay3),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay3),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed3)
+	.DATAOUT(a7ddrphy_dq_i_delayed3)
 );
 
 IOBUF IOBUF_3(
-	.I(main_a7ddrphy_dq_o_nodelay3),
-	.T(main_a7ddrphy_dq_t3),
+	.I(a7ddrphy_dq_o_nodelay3),
+	.T(a7ddrphy_dq_t3),
 	.IO(ddram_dq[3]),
-	.O(main_a7ddrphy_dq_i_nodelay3)
+	.O(a7ddrphy_dq_i_nodelay3)
 );
 
 OSERDESE2 #(
@@ -14457,20 +14900,20 @@ OSERDESE2 #(
 ) OSERDESE2_33 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip40[0]),
-	.D2(main_a7ddrphy_bitslip40[1]),
-	.D3(main_a7ddrphy_bitslip40[2]),
-	.D4(main_a7ddrphy_bitslip40[3]),
-	.D5(main_a7ddrphy_bitslip40[4]),
-	.D6(main_a7ddrphy_bitslip40[5]),
-	.D7(main_a7ddrphy_bitslip40[6]),
-	.D8(main_a7ddrphy_bitslip40[7]),
+	.D1(a7ddrphy_bitslip40[0]),
+	.D2(a7ddrphy_bitslip40[1]),
+	.D3(a7ddrphy_bitslip40[2]),
+	.D4(a7ddrphy_bitslip40[3]),
+	.D5(a7ddrphy_bitslip40[4]),
+	.D6(a7ddrphy_bitslip40[5]),
+	.D7(a7ddrphy_bitslip40[6]),
+	.D8(a7ddrphy_bitslip40[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay4),
-	.TQ(main_a7ddrphy_dq_t4)
+	.OQ(a7ddrphy_dq_o_nodelay4),
+	.TQ(a7ddrphy_dq_t4)
 );
 
 ISERDESE2 #(
@@ -14486,16 +14929,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip41[7]),
-	.Q2(main_a7ddrphy_bitslip41[6]),
-	.Q3(main_a7ddrphy_bitslip41[5]),
-	.Q4(main_a7ddrphy_bitslip41[4]),
-	.Q5(main_a7ddrphy_bitslip41[3]),
-	.Q6(main_a7ddrphy_bitslip41[2]),
-	.Q7(main_a7ddrphy_bitslip41[1]),
-	.Q8(main_a7ddrphy_bitslip41[0])
+	.DDLY(a7ddrphy_dq_i_delayed4),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip41[7]),
+	.Q2(a7ddrphy_bitslip41[6]),
+	.Q3(a7ddrphy_bitslip41[5]),
+	.Q4(a7ddrphy_bitslip41[4]),
+	.Q5(a7ddrphy_bitslip41[3]),
+	.Q6(a7ddrphy_bitslip41[2]),
+	.Q7(a7ddrphy_bitslip41[1]),
+	.Q8(a7ddrphy_bitslip41[0])
 );
 
 IDELAYE2 #(
@@ -14509,19 +14952,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_4 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay4),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay4),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed4)
+	.DATAOUT(a7ddrphy_dq_i_delayed4)
 );
 
 IOBUF IOBUF_4(
-	.I(main_a7ddrphy_dq_o_nodelay4),
-	.T(main_a7ddrphy_dq_t4),
+	.I(a7ddrphy_dq_o_nodelay4),
+	.T(a7ddrphy_dq_t4),
 	.IO(ddram_dq[4]),
-	.O(main_a7ddrphy_dq_i_nodelay4)
+	.O(a7ddrphy_dq_i_nodelay4)
 );
 
 OSERDESE2 #(
@@ -14533,20 +14976,20 @@ OSERDESE2 #(
 ) OSERDESE2_34 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip50[0]),
-	.D2(main_a7ddrphy_bitslip50[1]),
-	.D3(main_a7ddrphy_bitslip50[2]),
-	.D4(main_a7ddrphy_bitslip50[3]),
-	.D5(main_a7ddrphy_bitslip50[4]),
-	.D6(main_a7ddrphy_bitslip50[5]),
-	.D7(main_a7ddrphy_bitslip50[6]),
-	.D8(main_a7ddrphy_bitslip50[7]),
+	.D1(a7ddrphy_bitslip50[0]),
+	.D2(a7ddrphy_bitslip50[1]),
+	.D3(a7ddrphy_bitslip50[2]),
+	.D4(a7ddrphy_bitslip50[3]),
+	.D5(a7ddrphy_bitslip50[4]),
+	.D6(a7ddrphy_bitslip50[5]),
+	.D7(a7ddrphy_bitslip50[6]),
+	.D8(a7ddrphy_bitslip50[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay5),
-	.TQ(main_a7ddrphy_dq_t5)
+	.OQ(a7ddrphy_dq_o_nodelay5),
+	.TQ(a7ddrphy_dq_t5)
 );
 
 ISERDESE2 #(
@@ -14562,16 +15005,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip51[7]),
-	.Q2(main_a7ddrphy_bitslip51[6]),
-	.Q3(main_a7ddrphy_bitslip51[5]),
-	.Q4(main_a7ddrphy_bitslip51[4]),
-	.Q5(main_a7ddrphy_bitslip51[3]),
-	.Q6(main_a7ddrphy_bitslip51[2]),
-	.Q7(main_a7ddrphy_bitslip51[1]),
-	.Q8(main_a7ddrphy_bitslip51[0])
+	.DDLY(a7ddrphy_dq_i_delayed5),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip51[7]),
+	.Q2(a7ddrphy_bitslip51[6]),
+	.Q3(a7ddrphy_bitslip51[5]),
+	.Q4(a7ddrphy_bitslip51[4]),
+	.Q5(a7ddrphy_bitslip51[3]),
+	.Q6(a7ddrphy_bitslip51[2]),
+	.Q7(a7ddrphy_bitslip51[1]),
+	.Q8(a7ddrphy_bitslip51[0])
 );
 
 IDELAYE2 #(
@@ -14585,19 +15028,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_5 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay5),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay5),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed5)
+	.DATAOUT(a7ddrphy_dq_i_delayed5)
 );
 
 IOBUF IOBUF_5(
-	.I(main_a7ddrphy_dq_o_nodelay5),
-	.T(main_a7ddrphy_dq_t5),
+	.I(a7ddrphy_dq_o_nodelay5),
+	.T(a7ddrphy_dq_t5),
 	.IO(ddram_dq[5]),
-	.O(main_a7ddrphy_dq_i_nodelay5)
+	.O(a7ddrphy_dq_i_nodelay5)
 );
 
 OSERDESE2 #(
@@ -14609,20 +15052,20 @@ OSERDESE2 #(
 ) OSERDESE2_35 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip60[0]),
-	.D2(main_a7ddrphy_bitslip60[1]),
-	.D3(main_a7ddrphy_bitslip60[2]),
-	.D4(main_a7ddrphy_bitslip60[3]),
-	.D5(main_a7ddrphy_bitslip60[4]),
-	.D6(main_a7ddrphy_bitslip60[5]),
-	.D7(main_a7ddrphy_bitslip60[6]),
-	.D8(main_a7ddrphy_bitslip60[7]),
+	.D1(a7ddrphy_bitslip60[0]),
+	.D2(a7ddrphy_bitslip60[1]),
+	.D3(a7ddrphy_bitslip60[2]),
+	.D4(a7ddrphy_bitslip60[3]),
+	.D5(a7ddrphy_bitslip60[4]),
+	.D6(a7ddrphy_bitslip60[5]),
+	.D7(a7ddrphy_bitslip60[6]),
+	.D8(a7ddrphy_bitslip60[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay6),
-	.TQ(main_a7ddrphy_dq_t6)
+	.OQ(a7ddrphy_dq_o_nodelay6),
+	.TQ(a7ddrphy_dq_t6)
 );
 
 ISERDESE2 #(
@@ -14638,16 +15081,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip61[7]),
-	.Q2(main_a7ddrphy_bitslip61[6]),
-	.Q3(main_a7ddrphy_bitslip61[5]),
-	.Q4(main_a7ddrphy_bitslip61[4]),
-	.Q5(main_a7ddrphy_bitslip61[3]),
-	.Q6(main_a7ddrphy_bitslip61[2]),
-	.Q7(main_a7ddrphy_bitslip61[1]),
-	.Q8(main_a7ddrphy_bitslip61[0])
+	.DDLY(a7ddrphy_dq_i_delayed6),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip61[7]),
+	.Q2(a7ddrphy_bitslip61[6]),
+	.Q3(a7ddrphy_bitslip61[5]),
+	.Q4(a7ddrphy_bitslip61[4]),
+	.Q5(a7ddrphy_bitslip61[3]),
+	.Q6(a7ddrphy_bitslip61[2]),
+	.Q7(a7ddrphy_bitslip61[1]),
+	.Q8(a7ddrphy_bitslip61[0])
 );
 
 IDELAYE2 #(
@@ -14661,19 +15104,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_6 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay6),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay6),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed6)
+	.DATAOUT(a7ddrphy_dq_i_delayed6)
 );
 
 IOBUF IOBUF_6(
-	.I(main_a7ddrphy_dq_o_nodelay6),
-	.T(main_a7ddrphy_dq_t6),
+	.I(a7ddrphy_dq_o_nodelay6),
+	.T(a7ddrphy_dq_t6),
 	.IO(ddram_dq[6]),
-	.O(main_a7ddrphy_dq_i_nodelay6)
+	.O(a7ddrphy_dq_i_nodelay6)
 );
 
 OSERDESE2 #(
@@ -14685,20 +15128,20 @@ OSERDESE2 #(
 ) OSERDESE2_36 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip70[0]),
-	.D2(main_a7ddrphy_bitslip70[1]),
-	.D3(main_a7ddrphy_bitslip70[2]),
-	.D4(main_a7ddrphy_bitslip70[3]),
-	.D5(main_a7ddrphy_bitslip70[4]),
-	.D6(main_a7ddrphy_bitslip70[5]),
-	.D7(main_a7ddrphy_bitslip70[6]),
-	.D8(main_a7ddrphy_bitslip70[7]),
+	.D1(a7ddrphy_bitslip70[0]),
+	.D2(a7ddrphy_bitslip70[1]),
+	.D3(a7ddrphy_bitslip70[2]),
+	.D4(a7ddrphy_bitslip70[3]),
+	.D5(a7ddrphy_bitslip70[4]),
+	.D6(a7ddrphy_bitslip70[5]),
+	.D7(a7ddrphy_bitslip70[6]),
+	.D8(a7ddrphy_bitslip70[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay7),
-	.TQ(main_a7ddrphy_dq_t7)
+	.OQ(a7ddrphy_dq_o_nodelay7),
+	.TQ(a7ddrphy_dq_t7)
 );
 
 ISERDESE2 #(
@@ -14714,16 +15157,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip71[7]),
-	.Q2(main_a7ddrphy_bitslip71[6]),
-	.Q3(main_a7ddrphy_bitslip71[5]),
-	.Q4(main_a7ddrphy_bitslip71[4]),
-	.Q5(main_a7ddrphy_bitslip71[3]),
-	.Q6(main_a7ddrphy_bitslip71[2]),
-	.Q7(main_a7ddrphy_bitslip71[1]),
-	.Q8(main_a7ddrphy_bitslip71[0])
+	.DDLY(a7ddrphy_dq_i_delayed7),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip71[7]),
+	.Q2(a7ddrphy_bitslip71[6]),
+	.Q3(a7ddrphy_bitslip71[5]),
+	.Q4(a7ddrphy_bitslip71[4]),
+	.Q5(a7ddrphy_bitslip71[3]),
+	.Q6(a7ddrphy_bitslip71[2]),
+	.Q7(a7ddrphy_bitslip71[1]),
+	.Q8(a7ddrphy_bitslip71[0])
 );
 
 IDELAYE2 #(
@@ -14737,19 +15180,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_7 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay7),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay7),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed7)
+	.DATAOUT(a7ddrphy_dq_i_delayed7)
 );
 
 IOBUF IOBUF_7(
-	.I(main_a7ddrphy_dq_o_nodelay7),
-	.T(main_a7ddrphy_dq_t7),
+	.I(a7ddrphy_dq_o_nodelay7),
+	.T(a7ddrphy_dq_t7),
 	.IO(ddram_dq[7]),
-	.O(main_a7ddrphy_dq_i_nodelay7)
+	.O(a7ddrphy_dq_i_nodelay7)
 );
 
 OSERDESE2 #(
@@ -14761,20 +15204,20 @@ OSERDESE2 #(
 ) OSERDESE2_37 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip80[0]),
-	.D2(main_a7ddrphy_bitslip80[1]),
-	.D3(main_a7ddrphy_bitslip80[2]),
-	.D4(main_a7ddrphy_bitslip80[3]),
-	.D5(main_a7ddrphy_bitslip80[4]),
-	.D6(main_a7ddrphy_bitslip80[5]),
-	.D7(main_a7ddrphy_bitslip80[6]),
-	.D8(main_a7ddrphy_bitslip80[7]),
+	.D1(a7ddrphy_bitslip80[0]),
+	.D2(a7ddrphy_bitslip80[1]),
+	.D3(a7ddrphy_bitslip80[2]),
+	.D4(a7ddrphy_bitslip80[3]),
+	.D5(a7ddrphy_bitslip80[4]),
+	.D6(a7ddrphy_bitslip80[5]),
+	.D7(a7ddrphy_bitslip80[6]),
+	.D8(a7ddrphy_bitslip80[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay8),
-	.TQ(main_a7ddrphy_dq_t8)
+	.OQ(a7ddrphy_dq_o_nodelay8),
+	.TQ(a7ddrphy_dq_t8)
 );
 
 ISERDESE2 #(
@@ -14790,16 +15233,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip81[7]),
-	.Q2(main_a7ddrphy_bitslip81[6]),
-	.Q3(main_a7ddrphy_bitslip81[5]),
-	.Q4(main_a7ddrphy_bitslip81[4]),
-	.Q5(main_a7ddrphy_bitslip81[3]),
-	.Q6(main_a7ddrphy_bitslip81[2]),
-	.Q7(main_a7ddrphy_bitslip81[1]),
-	.Q8(main_a7ddrphy_bitslip81[0])
+	.DDLY(a7ddrphy_dq_i_delayed8),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip81[7]),
+	.Q2(a7ddrphy_bitslip81[6]),
+	.Q3(a7ddrphy_bitslip81[5]),
+	.Q4(a7ddrphy_bitslip81[4]),
+	.Q5(a7ddrphy_bitslip81[3]),
+	.Q6(a7ddrphy_bitslip81[2]),
+	.Q7(a7ddrphy_bitslip81[1]),
+	.Q8(a7ddrphy_bitslip81[0])
 );
 
 IDELAYE2 #(
@@ -14813,19 +15256,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_8 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay8),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay8),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed8)
+	.DATAOUT(a7ddrphy_dq_i_delayed8)
 );
 
 IOBUF IOBUF_8(
-	.I(main_a7ddrphy_dq_o_nodelay8),
-	.T(main_a7ddrphy_dq_t8),
+	.I(a7ddrphy_dq_o_nodelay8),
+	.T(a7ddrphy_dq_t8),
 	.IO(ddram_dq[8]),
-	.O(main_a7ddrphy_dq_i_nodelay8)
+	.O(a7ddrphy_dq_i_nodelay8)
 );
 
 OSERDESE2 #(
@@ -14837,20 +15280,20 @@ OSERDESE2 #(
 ) OSERDESE2_38 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip90[0]),
-	.D2(main_a7ddrphy_bitslip90[1]),
-	.D3(main_a7ddrphy_bitslip90[2]),
-	.D4(main_a7ddrphy_bitslip90[3]),
-	.D5(main_a7ddrphy_bitslip90[4]),
-	.D6(main_a7ddrphy_bitslip90[5]),
-	.D7(main_a7ddrphy_bitslip90[6]),
-	.D8(main_a7ddrphy_bitslip90[7]),
+	.D1(a7ddrphy_bitslip90[0]),
+	.D2(a7ddrphy_bitslip90[1]),
+	.D3(a7ddrphy_bitslip90[2]),
+	.D4(a7ddrphy_bitslip90[3]),
+	.D5(a7ddrphy_bitslip90[4]),
+	.D6(a7ddrphy_bitslip90[5]),
+	.D7(a7ddrphy_bitslip90[6]),
+	.D8(a7ddrphy_bitslip90[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay9),
-	.TQ(main_a7ddrphy_dq_t9)
+	.OQ(a7ddrphy_dq_o_nodelay9),
+	.TQ(a7ddrphy_dq_t9)
 );
 
 ISERDESE2 #(
@@ -14866,16 +15309,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip91[7]),
-	.Q2(main_a7ddrphy_bitslip91[6]),
-	.Q3(main_a7ddrphy_bitslip91[5]),
-	.Q4(main_a7ddrphy_bitslip91[4]),
-	.Q5(main_a7ddrphy_bitslip91[3]),
-	.Q6(main_a7ddrphy_bitslip91[2]),
-	.Q7(main_a7ddrphy_bitslip91[1]),
-	.Q8(main_a7ddrphy_bitslip91[0])
+	.DDLY(a7ddrphy_dq_i_delayed9),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip91[7]),
+	.Q2(a7ddrphy_bitslip91[6]),
+	.Q3(a7ddrphy_bitslip91[5]),
+	.Q4(a7ddrphy_bitslip91[4]),
+	.Q5(a7ddrphy_bitslip91[3]),
+	.Q6(a7ddrphy_bitslip91[2]),
+	.Q7(a7ddrphy_bitslip91[1]),
+	.Q8(a7ddrphy_bitslip91[0])
 );
 
 IDELAYE2 #(
@@ -14889,19 +15332,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_9 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay9),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay9),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed9)
+	.DATAOUT(a7ddrphy_dq_i_delayed9)
 );
 
 IOBUF IOBUF_9(
-	.I(main_a7ddrphy_dq_o_nodelay9),
-	.T(main_a7ddrphy_dq_t9),
+	.I(a7ddrphy_dq_o_nodelay9),
+	.T(a7ddrphy_dq_t9),
 	.IO(ddram_dq[9]),
-	.O(main_a7ddrphy_dq_i_nodelay9)
+	.O(a7ddrphy_dq_i_nodelay9)
 );
 
 OSERDESE2 #(
@@ -14913,20 +15356,20 @@ OSERDESE2 #(
 ) OSERDESE2_39 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip100[0]),
-	.D2(main_a7ddrphy_bitslip100[1]),
-	.D3(main_a7ddrphy_bitslip100[2]),
-	.D4(main_a7ddrphy_bitslip100[3]),
-	.D5(main_a7ddrphy_bitslip100[4]),
-	.D6(main_a7ddrphy_bitslip100[5]),
-	.D7(main_a7ddrphy_bitslip100[6]),
-	.D8(main_a7ddrphy_bitslip100[7]),
+	.D1(a7ddrphy_bitslip100[0]),
+	.D2(a7ddrphy_bitslip100[1]),
+	.D3(a7ddrphy_bitslip100[2]),
+	.D4(a7ddrphy_bitslip100[3]),
+	.D5(a7ddrphy_bitslip100[4]),
+	.D6(a7ddrphy_bitslip100[5]),
+	.D7(a7ddrphy_bitslip100[6]),
+	.D8(a7ddrphy_bitslip100[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay10),
-	.TQ(main_a7ddrphy_dq_t10)
+	.OQ(a7ddrphy_dq_o_nodelay10),
+	.TQ(a7ddrphy_dq_t10)
 );
 
 ISERDESE2 #(
@@ -14942,16 +15385,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip101[7]),
-	.Q2(main_a7ddrphy_bitslip101[6]),
-	.Q3(main_a7ddrphy_bitslip101[5]),
-	.Q4(main_a7ddrphy_bitslip101[4]),
-	.Q5(main_a7ddrphy_bitslip101[3]),
-	.Q6(main_a7ddrphy_bitslip101[2]),
-	.Q7(main_a7ddrphy_bitslip101[1]),
-	.Q8(main_a7ddrphy_bitslip101[0])
+	.DDLY(a7ddrphy_dq_i_delayed10),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip101[7]),
+	.Q2(a7ddrphy_bitslip101[6]),
+	.Q3(a7ddrphy_bitslip101[5]),
+	.Q4(a7ddrphy_bitslip101[4]),
+	.Q5(a7ddrphy_bitslip101[3]),
+	.Q6(a7ddrphy_bitslip101[2]),
+	.Q7(a7ddrphy_bitslip101[1]),
+	.Q8(a7ddrphy_bitslip101[0])
 );
 
 IDELAYE2 #(
@@ -14965,19 +15408,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_10 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay10),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay10),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed10)
+	.DATAOUT(a7ddrphy_dq_i_delayed10)
 );
 
 IOBUF IOBUF_10(
-	.I(main_a7ddrphy_dq_o_nodelay10),
-	.T(main_a7ddrphy_dq_t10),
+	.I(a7ddrphy_dq_o_nodelay10),
+	.T(a7ddrphy_dq_t10),
 	.IO(ddram_dq[10]),
-	.O(main_a7ddrphy_dq_i_nodelay10)
+	.O(a7ddrphy_dq_i_nodelay10)
 );
 
 OSERDESE2 #(
@@ -14989,20 +15432,20 @@ OSERDESE2 #(
 ) OSERDESE2_40 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip110[0]),
-	.D2(main_a7ddrphy_bitslip110[1]),
-	.D3(main_a7ddrphy_bitslip110[2]),
-	.D4(main_a7ddrphy_bitslip110[3]),
-	.D5(main_a7ddrphy_bitslip110[4]),
-	.D6(main_a7ddrphy_bitslip110[5]),
-	.D7(main_a7ddrphy_bitslip110[6]),
-	.D8(main_a7ddrphy_bitslip110[7]),
+	.D1(a7ddrphy_bitslip110[0]),
+	.D2(a7ddrphy_bitslip110[1]),
+	.D3(a7ddrphy_bitslip110[2]),
+	.D4(a7ddrphy_bitslip110[3]),
+	.D5(a7ddrphy_bitslip110[4]),
+	.D6(a7ddrphy_bitslip110[5]),
+	.D7(a7ddrphy_bitslip110[6]),
+	.D8(a7ddrphy_bitslip110[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay11),
-	.TQ(main_a7ddrphy_dq_t11)
+	.OQ(a7ddrphy_dq_o_nodelay11),
+	.TQ(a7ddrphy_dq_t11)
 );
 
 ISERDESE2 #(
@@ -15018,16 +15461,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip111[7]),
-	.Q2(main_a7ddrphy_bitslip111[6]),
-	.Q3(main_a7ddrphy_bitslip111[5]),
-	.Q4(main_a7ddrphy_bitslip111[4]),
-	.Q5(main_a7ddrphy_bitslip111[3]),
-	.Q6(main_a7ddrphy_bitslip111[2]),
-	.Q7(main_a7ddrphy_bitslip111[1]),
-	.Q8(main_a7ddrphy_bitslip111[0])
+	.DDLY(a7ddrphy_dq_i_delayed11),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip111[7]),
+	.Q2(a7ddrphy_bitslip111[6]),
+	.Q3(a7ddrphy_bitslip111[5]),
+	.Q4(a7ddrphy_bitslip111[4]),
+	.Q5(a7ddrphy_bitslip111[3]),
+	.Q6(a7ddrphy_bitslip111[2]),
+	.Q7(a7ddrphy_bitslip111[1]),
+	.Q8(a7ddrphy_bitslip111[0])
 );
 
 IDELAYE2 #(
@@ -15041,19 +15484,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_11 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay11),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay11),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed11)
+	.DATAOUT(a7ddrphy_dq_i_delayed11)
 );
 
 IOBUF IOBUF_11(
-	.I(main_a7ddrphy_dq_o_nodelay11),
-	.T(main_a7ddrphy_dq_t11),
+	.I(a7ddrphy_dq_o_nodelay11),
+	.T(a7ddrphy_dq_t11),
 	.IO(ddram_dq[11]),
-	.O(main_a7ddrphy_dq_i_nodelay11)
+	.O(a7ddrphy_dq_i_nodelay11)
 );
 
 OSERDESE2 #(
@@ -15065,20 +15508,20 @@ OSERDESE2 #(
 ) OSERDESE2_41 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip120[0]),
-	.D2(main_a7ddrphy_bitslip120[1]),
-	.D3(main_a7ddrphy_bitslip120[2]),
-	.D4(main_a7ddrphy_bitslip120[3]),
-	.D5(main_a7ddrphy_bitslip120[4]),
-	.D6(main_a7ddrphy_bitslip120[5]),
-	.D7(main_a7ddrphy_bitslip120[6]),
-	.D8(main_a7ddrphy_bitslip120[7]),
+	.D1(a7ddrphy_bitslip120[0]),
+	.D2(a7ddrphy_bitslip120[1]),
+	.D3(a7ddrphy_bitslip120[2]),
+	.D4(a7ddrphy_bitslip120[3]),
+	.D5(a7ddrphy_bitslip120[4]),
+	.D6(a7ddrphy_bitslip120[5]),
+	.D7(a7ddrphy_bitslip120[6]),
+	.D8(a7ddrphy_bitslip120[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay12),
-	.TQ(main_a7ddrphy_dq_t12)
+	.OQ(a7ddrphy_dq_o_nodelay12),
+	.TQ(a7ddrphy_dq_t12)
 );
 
 ISERDESE2 #(
@@ -15094,16 +15537,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip121[7]),
-	.Q2(main_a7ddrphy_bitslip121[6]),
-	.Q3(main_a7ddrphy_bitslip121[5]),
-	.Q4(main_a7ddrphy_bitslip121[4]),
-	.Q5(main_a7ddrphy_bitslip121[3]),
-	.Q6(main_a7ddrphy_bitslip121[2]),
-	.Q7(main_a7ddrphy_bitslip121[1]),
-	.Q8(main_a7ddrphy_bitslip121[0])
+	.DDLY(a7ddrphy_dq_i_delayed12),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip121[7]),
+	.Q2(a7ddrphy_bitslip121[6]),
+	.Q3(a7ddrphy_bitslip121[5]),
+	.Q4(a7ddrphy_bitslip121[4]),
+	.Q5(a7ddrphy_bitslip121[3]),
+	.Q6(a7ddrphy_bitslip121[2]),
+	.Q7(a7ddrphy_bitslip121[1]),
+	.Q8(a7ddrphy_bitslip121[0])
 );
 
 IDELAYE2 #(
@@ -15117,19 +15560,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_12 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay12),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay12),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed12)
+	.DATAOUT(a7ddrphy_dq_i_delayed12)
 );
 
 IOBUF IOBUF_12(
-	.I(main_a7ddrphy_dq_o_nodelay12),
-	.T(main_a7ddrphy_dq_t12),
+	.I(a7ddrphy_dq_o_nodelay12),
+	.T(a7ddrphy_dq_t12),
 	.IO(ddram_dq[12]),
-	.O(main_a7ddrphy_dq_i_nodelay12)
+	.O(a7ddrphy_dq_i_nodelay12)
 );
 
 OSERDESE2 #(
@@ -15141,20 +15584,20 @@ OSERDESE2 #(
 ) OSERDESE2_42 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip130[0]),
-	.D2(main_a7ddrphy_bitslip130[1]),
-	.D3(main_a7ddrphy_bitslip130[2]),
-	.D4(main_a7ddrphy_bitslip130[3]),
-	.D5(main_a7ddrphy_bitslip130[4]),
-	.D6(main_a7ddrphy_bitslip130[5]),
-	.D7(main_a7ddrphy_bitslip130[6]),
-	.D8(main_a7ddrphy_bitslip130[7]),
+	.D1(a7ddrphy_bitslip130[0]),
+	.D2(a7ddrphy_bitslip130[1]),
+	.D3(a7ddrphy_bitslip130[2]),
+	.D4(a7ddrphy_bitslip130[3]),
+	.D5(a7ddrphy_bitslip130[4]),
+	.D6(a7ddrphy_bitslip130[5]),
+	.D7(a7ddrphy_bitslip130[6]),
+	.D8(a7ddrphy_bitslip130[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay13),
-	.TQ(main_a7ddrphy_dq_t13)
+	.OQ(a7ddrphy_dq_o_nodelay13),
+	.TQ(a7ddrphy_dq_t13)
 );
 
 ISERDESE2 #(
@@ -15170,16 +15613,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip131[7]),
-	.Q2(main_a7ddrphy_bitslip131[6]),
-	.Q3(main_a7ddrphy_bitslip131[5]),
-	.Q4(main_a7ddrphy_bitslip131[4]),
-	.Q5(main_a7ddrphy_bitslip131[3]),
-	.Q6(main_a7ddrphy_bitslip131[2]),
-	.Q7(main_a7ddrphy_bitslip131[1]),
-	.Q8(main_a7ddrphy_bitslip131[0])
+	.DDLY(a7ddrphy_dq_i_delayed13),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip131[7]),
+	.Q2(a7ddrphy_bitslip131[6]),
+	.Q3(a7ddrphy_bitslip131[5]),
+	.Q4(a7ddrphy_bitslip131[4]),
+	.Q5(a7ddrphy_bitslip131[3]),
+	.Q6(a7ddrphy_bitslip131[2]),
+	.Q7(a7ddrphy_bitslip131[1]),
+	.Q8(a7ddrphy_bitslip131[0])
 );
 
 IDELAYE2 #(
@@ -15193,19 +15636,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_13 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay13),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay13),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed13)
+	.DATAOUT(a7ddrphy_dq_i_delayed13)
 );
 
 IOBUF IOBUF_13(
-	.I(main_a7ddrphy_dq_o_nodelay13),
-	.T(main_a7ddrphy_dq_t13),
+	.I(a7ddrphy_dq_o_nodelay13),
+	.T(a7ddrphy_dq_t13),
 	.IO(ddram_dq[13]),
-	.O(main_a7ddrphy_dq_i_nodelay13)
+	.O(a7ddrphy_dq_i_nodelay13)
 );
 
 OSERDESE2 #(
@@ -15217,20 +15660,20 @@ OSERDESE2 #(
 ) OSERDESE2_43 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip140[0]),
-	.D2(main_a7ddrphy_bitslip140[1]),
-	.D3(main_a7ddrphy_bitslip140[2]),
-	.D4(main_a7ddrphy_bitslip140[3]),
-	.D5(main_a7ddrphy_bitslip140[4]),
-	.D6(main_a7ddrphy_bitslip140[5]),
-	.D7(main_a7ddrphy_bitslip140[6]),
-	.D8(main_a7ddrphy_bitslip140[7]),
+	.D1(a7ddrphy_bitslip140[0]),
+	.D2(a7ddrphy_bitslip140[1]),
+	.D3(a7ddrphy_bitslip140[2]),
+	.D4(a7ddrphy_bitslip140[3]),
+	.D5(a7ddrphy_bitslip140[4]),
+	.D6(a7ddrphy_bitslip140[5]),
+	.D7(a7ddrphy_bitslip140[6]),
+	.D8(a7ddrphy_bitslip140[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay14),
-	.TQ(main_a7ddrphy_dq_t14)
+	.OQ(a7ddrphy_dq_o_nodelay14),
+	.TQ(a7ddrphy_dq_t14)
 );
 
 ISERDESE2 #(
@@ -15246,16 +15689,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip141[7]),
-	.Q2(main_a7ddrphy_bitslip141[6]),
-	.Q3(main_a7ddrphy_bitslip141[5]),
-	.Q4(main_a7ddrphy_bitslip141[4]),
-	.Q5(main_a7ddrphy_bitslip141[3]),
-	.Q6(main_a7ddrphy_bitslip141[2]),
-	.Q7(main_a7ddrphy_bitslip141[1]),
-	.Q8(main_a7ddrphy_bitslip141[0])
+	.DDLY(a7ddrphy_dq_i_delayed14),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip141[7]),
+	.Q2(a7ddrphy_bitslip141[6]),
+	.Q3(a7ddrphy_bitslip141[5]),
+	.Q4(a7ddrphy_bitslip141[4]),
+	.Q5(a7ddrphy_bitslip141[3]),
+	.Q6(a7ddrphy_bitslip141[2]),
+	.Q7(a7ddrphy_bitslip141[1]),
+	.Q8(a7ddrphy_bitslip141[0])
 );
 
 IDELAYE2 #(
@@ -15269,19 +15712,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_14 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay14),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay14),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed14)
+	.DATAOUT(a7ddrphy_dq_i_delayed14)
 );
 
 IOBUF IOBUF_14(
-	.I(main_a7ddrphy_dq_o_nodelay14),
-	.T(main_a7ddrphy_dq_t14),
+	.I(a7ddrphy_dq_o_nodelay14),
+	.T(a7ddrphy_dq_t14),
 	.IO(ddram_dq[14]),
-	.O(main_a7ddrphy_dq_i_nodelay14)
+	.O(a7ddrphy_dq_i_nodelay14)
 );
 
 OSERDESE2 #(
@@ -15293,20 +15736,20 @@ OSERDESE2 #(
 ) OSERDESE2_44 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip150[0]),
-	.D2(main_a7ddrphy_bitslip150[1]),
-	.D3(main_a7ddrphy_bitslip150[2]),
-	.D4(main_a7ddrphy_bitslip150[3]),
-	.D5(main_a7ddrphy_bitslip150[4]),
-	.D6(main_a7ddrphy_bitslip150[5]),
-	.D7(main_a7ddrphy_bitslip150[6]),
-	.D8(main_a7ddrphy_bitslip150[7]),
+	.D1(a7ddrphy_bitslip150[0]),
+	.D2(a7ddrphy_bitslip150[1]),
+	.D3(a7ddrphy_bitslip150[2]),
+	.D4(a7ddrphy_bitslip150[3]),
+	.D5(a7ddrphy_bitslip150[4]),
+	.D6(a7ddrphy_bitslip150[5]),
+	.D7(a7ddrphy_bitslip150[6]),
+	.D8(a7ddrphy_bitslip150[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay15),
-	.TQ(main_a7ddrphy_dq_t15)
+	.OQ(a7ddrphy_dq_o_nodelay15),
+	.TQ(a7ddrphy_dq_t15)
 );
 
 ISERDESE2 #(
@@ -15322,16 +15765,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip151[7]),
-	.Q2(main_a7ddrphy_bitslip151[6]),
-	.Q3(main_a7ddrphy_bitslip151[5]),
-	.Q4(main_a7ddrphy_bitslip151[4]),
-	.Q5(main_a7ddrphy_bitslip151[3]),
-	.Q6(main_a7ddrphy_bitslip151[2]),
-	.Q7(main_a7ddrphy_bitslip151[1]),
-	.Q8(main_a7ddrphy_bitslip151[0])
+	.DDLY(a7ddrphy_dq_i_delayed15),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip151[7]),
+	.Q2(a7ddrphy_bitslip151[6]),
+	.Q3(a7ddrphy_bitslip151[5]),
+	.Q4(a7ddrphy_bitslip151[4]),
+	.Q5(a7ddrphy_bitslip151[3]),
+	.Q6(a7ddrphy_bitslip151[2]),
+	.Q7(a7ddrphy_bitslip151[1]),
+	.Q8(a7ddrphy_bitslip151[0])
 );
 
 IDELAYE2 #(
@@ -15345,19 +15788,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_15 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay15),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay15),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed15)
+	.DATAOUT(a7ddrphy_dq_i_delayed15)
 );
 
 IOBUF IOBUF_15(
-	.I(main_a7ddrphy_dq_o_nodelay15),
-	.T(main_a7ddrphy_dq_t15),
+	.I(a7ddrphy_dq_o_nodelay15),
+	.T(a7ddrphy_dq_t15),
 	.IO(ddram_dq[15]),
-	.O(main_a7ddrphy_dq_i_nodelay15)
+	.O(a7ddrphy_dq_i_nodelay15)
 );
 
 //------------------------------------------------------------------------------
@@ -15368,14 +15811,14 @@ IOBUF IOBUF_15(
 reg [23:0] storage[0:15];
 reg [23:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
-		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+		storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+	storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15386,14 +15829,14 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_1[0:15];
 reg [23:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
-		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+		storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15404,14 +15847,14 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_2[0:15];
 reg [23:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
-		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+		storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15422,14 +15865,14 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_3[0:15];
 reg [23:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
-		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+		storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15440,14 +15883,14 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_4[0:15];
 reg [23:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
-		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+		storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15458,14 +15901,14 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_5[0:15];
 reg [23:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
-		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+		storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15476,14 +15919,14 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_6[0:15];
 reg [23:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
-		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+		storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15494,62 +15937,78 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_7[0:15];
 reg [23:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
-		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+		storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
 
-FD FD(
-	.C(main_clkin),
-	.D(main_reset),
-	.Q(builder_reset0)
+FDCE FDCE(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(reset),
+	.Q(litedramcore_reset0)
 );
 
-FD FD_1(
-	.C(main_clkin),
-	.D(builder_reset0),
-	.Q(builder_reset1)
+FDCE FDCE_1(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset0),
+	.Q(litedramcore_reset1)
 );
 
-FD FD_2(
-	.C(main_clkin),
-	.D(builder_reset1),
-	.Q(builder_reset2)
+FDCE FDCE_2(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset1),
+	.Q(litedramcore_reset2)
 );
 
-FD FD_3(
-	.C(main_clkin),
-	.D(builder_reset2),
-	.Q(builder_reset3)
+FDCE FDCE_3(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset2),
+	.Q(litedramcore_reset3)
 );
 
-FD FD_4(
-	.C(main_clkin),
-	.D(builder_reset3),
-	.Q(builder_reset4)
+FDCE FDCE_4(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset3),
+	.Q(litedramcore_reset4)
 );
 
-FD FD_5(
-	.C(main_clkin),
-	.D(builder_reset4),
-	.Q(builder_reset5)
+FDCE FDCE_5(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset4),
+	.Q(litedramcore_reset5)
 );
 
-FD FD_6(
-	.C(main_clkin),
-	.D(builder_reset5),
-	.Q(builder_reset6)
+FDCE FDCE_6(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset5),
+	.Q(litedramcore_reset6)
 );
 
-FD FD_7(
-	.C(main_clkin),
-	.D(builder_reset6),
-	.Q(builder_reset7)
+FDCE FDCE_7(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset6),
+	.Q(litedramcore_reset7)
 );
 
 PLLE2_ADV #(
@@ -15567,16 +16026,16 @@ PLLE2_ADV #(
 	.REF_JITTER1(0.01),
 	.STARTUP_WAIT("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(builder_pll_fb),
-	.CLKIN1(main_clkin),
-	.PWRDWN(main_power_down),
-	.RST(builder_reset7),
-	.CLKFBOUT(builder_pll_fb),
-	.CLKOUT0(main_clkout0),
-	.CLKOUT1(main_clkout1),
-	.CLKOUT2(main_clkout2),
-	.CLKOUT3(main_clkout3),
-	.LOCKED(main_locked)
+	.CLKFBIN(litedramcore_pll_fb),
+	.CLKIN1(clkin),
+	.PWRDWN(power_down),
+	.RST(litedramcore_reset7),
+	.CLKFBOUT(litedramcore_pll_fb),
+	.CLKOUT0(clkout0),
+	.CLKOUT1(clkout1),
+	.CLKOUT2(clkout2),
+	.CLKOUT3(clkout3),
+	.LOCKED(locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15585,8 +16044,8 @@ PLLE2_ADV #(
 	.C(iodelay_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
-	.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl0),
+	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15594,8 +16053,8 @@ PLLE2_ADV #(
 ) FDPE_1 (
 	.C(iodelay_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
+	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl0),
 	.Q(iodelay_rst)
 );
 
@@ -15605,8 +16064,8 @@ PLLE2_ADV #(
 	.C(sys_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
-	.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl1),
+	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15614,8 +16073,8 @@ PLLE2_ADV #(
 ) FDPE_3 (
 	.C(sys_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
+	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl1),
 	.Q(sys_rst)
 );
 
@@ -15625,8 +16084,8 @@ PLLE2_ADV #(
 	.C(sys4x_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15634,9 +16093,9 @@ PLLE2_ADV #(
 ) FDPE_5 (
 	.C(sys4x_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_expr)
+	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15645,8 +16104,8 @@ PLLE2_ADV #(
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15654,13 +16113,13 @@ PLLE2_ADV #(
 ) FDPE_7 (
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_expr)
+	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-01-14 08:32:09.
+//  Auto-Generated by LiteX on 2022-08-04 21:06:55.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init
index 49b28a5..1ede481 100644
--- a/litedram/generated/genesys2/litedram_core.init
+++ b/litedram/generated/genesys2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10e0658cff00
+618c10d8658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -519,213 +519,215 @@ a64b5a7d14004a39
 0000000000000000
 3c4c000100000000
 7c0802a63842bcc4
-fbe1fff8fbc1fff0
-f821ff51f8010010
-f88100d83bc10020
+f8010010fbe1fff8
+f88100d8f821ff51
 38800080f8a100e0
 f8c100e87c651b78
-38c100d87fc3f378
+38c100d838610020
 f90100f8f8e100f0
 f9410108f9210100
-6000000048002f19
-7fc3f3787c7f1b78
-600000004800293d
+6000000048002f15
+386100207c7f1b78
+600000004800292d
 7fe3fb78382100b0
-0000000048003594
-0000028001000000
+000000004800361c
+0000018001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842bc203c4c0001
-7d8000267c0802a6
-91810008480034d1
-48002939f821fed1
+3842bc283c4c0001
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+9161000848003555
+48002929f821fed1
 3c62ffff60000000
-4bffff3938637950
+4bffff41386379d0
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
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-3c62ffff4bffff15
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 73e900017fe0feea
 3c62ffff41820010
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-4e00000073e90002
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+4d80000073e90002
 3c62ffff41820010
-4bfffed1386379b0
-4d80000073e90004
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+4e00000073e90004
 3c62ffff41820010
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+4bfffec138637a38
 4d00000073e90008
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-4bfffea1386379c0
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 4182001073e90010
-386379d03c62ffff
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+38637a503c62ffff
+73ff01004bfffe95
 3c62ffff41820010
-4bfffe79386379e0
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+4bfffe8138637a60
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+3c80c00041920028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe41386379f0
-3c80c0004192004c
+4bfffe4938637a70
+3c80c000418e004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637a08
+4bfffe2138637a88
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637a207884b282
-3d20c0004bfffdf5
+38637aa07884b282
+3d20c0004bfffdfd
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637a387c892392
-418a025c4bfffdc5
-639c00383f80c000
-7c0004ac7b9c0020
-3d40c0007f80e6ea
+38637ab87c892392
+418a02604bfffdcd
+63de00383fc0c000
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+3d40c0007fc0f6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
 7c0004ac7d20ffaa
-7c0004ac7fc0feaa
 7c0004ac7fa0feaa
-4bfffd1d7fe0feaa
+7c0004ac7f80feaa
+4bfffd257fe0feaa
 57e6063e3c62ffff
-57c4063e57a5063e
-57f8063e38637a58
-7fc9eb784bfffd45
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-5529063e57da063e
+57a4063e5785063e
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 418201682c090000
-7fdef8387fdee838
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-408201302c1d0020
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 57ff063e3bffffe8
 41810120281f0001
 392000353fe0c000
 7bff002063ff6000
 7d20ffaa7c0004ac
-3b4000023fc0c000
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 7d20ffaa7c0004ac
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 3c62ffff40820090
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 7c0004ac39200006
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 7c0004ac39200001
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+3c82ffff4bffff54
+38847b783c62ffff
+4bfffae938637b88
+60000000480019b9
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+4bfffad138637ba8
+38a000403c9ef000
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-6000000048002649
+60000000480025cd
 3d400002e9210070
 614a464c3c62ffff
-794a83e438637b50
+794a83e438637bc0
 614a457f79290600
 408200247c295000
 2c09000189210075
 a121008240820010
-418200802c090015
-38637b703c62ffff
-892100774bfffae5
+418200442c090015
+38637be03c62ffff
+892100774bfffa6d
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637bd088810070
+38637c4088810070
 89210075f9210060
-3c62ffff4bfffab5
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-60a5a00060846000
-3c60400078840020
-60000000480025a1
-38637c203c62ffff
-4bfffafd4bfffa7d
-ebe100904bffff08
-3ba000003f02ffff
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-a12100a87ffafa14
+4bfffee04bfffa3d
+3f22ffffe9210090
+3b397bf83ba00000
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 418000347c1d4840
 3c62ffff80810088
-4bfffa4138637bb0
-e86100884bfffac1
-4182ff802c23ffff
-8181000838210130
-48002fec7d838120
-38a000383c9ff000
-7f23cb7878840020
-6000000048002521
+4bfffa0938637c20
+e86100884bfffa81
+4182fea02c23ffff
+8161000838210130
+480030307d638120
+38a000383c9ef000
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 2c090001812100b0
 eb6100d040820048
-ebc100b8eb8100c0
-7f03c3787ba40020
+ebe100b8eb8100c0
+7f23cb787ba40020
 7b6500207f86e378
-4bfff9d93fdef000
-7b6500207c9af214
+4bfff9a13ffff000
+7b6500207c9fd214
 7f83e37878840020
-60000000480024d9
-7fff4a14a12100a6
+600000004800249d
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 4bffff583bbd0001
-4082fde02c1a0020
-4082fdd82c1900ba
-4082fdd02c180018
-38637aa83c62ffff
-4bfffd8c4bfff98d
 0300000000000000
 3d20c80000000880
 7929002061291004
@@ -735,7 +737,7 @@ ebc100b8eb8100c0
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-3842b5f83c4c0001
+3842b5e83c4c0001
 4182006828030002
 4182003028030003
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 0000000000000000
diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v
index 9a2c35e..14b291e 100644
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-01-14 08:32:12
+// LiteX sha1 : 6932fc51
+// Date       : 2022-08-04 21:06:58
 //------------------------------------------------------------------------------
 
 
@@ -69,5750 +69,6169 @@ module litedram_core (
 // Signals
 //------------------------------------------------------------------------------
 
-reg  main_rst = 1'd0;
+reg  rst_1 = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
 wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
-wire main_reset;
-reg  main_power_down = 1'd0;
-wire main_locked;
-wire main_clkin;
-wire main_clkout0;
-wire main_clkout_buf0;
-wire main_clkout1;
-wire main_clkout_buf1;
-wire main_clkout2;
-wire main_clkout_buf2;
-wire main_clkout3;
-wire main_clkout_buf3;
-reg  [3:0] main_reset_counter = 4'd15;
-reg  main_ic_reset = 1'd1;
-reg  main_k7ddrphy_rst_storage = 1'd0;
-reg  main_k7ddrphy_rst_re = 1'd0;
-reg  [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg  main_k7ddrphy_half_sys8x_taps_re = 1'd0;
-reg  main_k7ddrphy_wlevel_en_storage = 1'd0;
-reg  main_k7ddrphy_wlevel_en_re = 1'd0;
-reg  main_k7ddrphy_wlevel_strobe_re = 1'd0;
-wire main_k7ddrphy_wlevel_strobe_r;
-reg  main_k7ddrphy_wlevel_strobe_we = 1'd0;
-reg  main_k7ddrphy_wlevel_strobe_w = 1'd0;
-reg  main_k7ddrphy_cdly_rst_re = 1'd0;
-wire main_k7ddrphy_cdly_rst_r;
-reg  main_k7ddrphy_cdly_rst_we = 1'd0;
-reg  main_k7ddrphy_cdly_rst_w = 1'd0;
-reg  main_k7ddrphy_cdly_inc_re = 1'd0;
-wire main_k7ddrphy_cdly_inc_r;
-reg  main_k7ddrphy_cdly_inc_we = 1'd0;
-reg  main_k7ddrphy_cdly_inc_w = 1'd0;
-reg  [3:0] main_k7ddrphy_dly_sel_storage = 4'd0;
-reg  main_k7ddrphy_dly_sel_re = 1'd0;
-reg  main_k7ddrphy_rdly_dq_rst_re = 1'd0;
-wire main_k7ddrphy_rdly_dq_rst_r;
-reg  main_k7ddrphy_rdly_dq_rst_we = 1'd0;
-reg  main_k7ddrphy_rdly_dq_rst_w = 1'd0;
-reg  main_k7ddrphy_rdly_dq_inc_re = 1'd0;
-wire main_k7ddrphy_rdly_dq_inc_r;
-reg  main_k7ddrphy_rdly_dq_inc_we = 1'd0;
-reg  main_k7ddrphy_rdly_dq_inc_w = 1'd0;
-reg  main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire main_k7ddrphy_rdly_dq_bitslip_rst_r;
-reg  main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg  main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg  main_k7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire main_k7ddrphy_rdly_dq_bitslip_r;
-reg  main_k7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg  main_k7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg  main_k7ddrphy_wdly_dq_rst_re = 1'd0;
-wire main_k7ddrphy_wdly_dq_rst_r;
-reg  main_k7ddrphy_wdly_dq_rst_we = 1'd0;
-reg  main_k7ddrphy_wdly_dq_rst_w = 1'd0;
-reg  main_k7ddrphy_wdly_dq_inc_re = 1'd0;
-wire main_k7ddrphy_wdly_dq_inc_r;
-reg  main_k7ddrphy_wdly_dq_inc_we = 1'd0;
-reg  main_k7ddrphy_wdly_dq_inc_w = 1'd0;
-reg  main_k7ddrphy_wdly_dqs_rst_re = 1'd0;
-wire main_k7ddrphy_wdly_dqs_rst_r;
-reg  main_k7ddrphy_wdly_dqs_rst_we = 1'd0;
-reg  main_k7ddrphy_wdly_dqs_rst_w = 1'd0;
-reg  main_k7ddrphy_wdly_dqs_inc_re = 1'd0;
-wire main_k7ddrphy_wdly_dqs_inc_r;
-reg  main_k7ddrphy_wdly_dqs_inc_we = 1'd0;
-reg  main_k7ddrphy_wdly_dqs_inc_w = 1'd0;
-reg  main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire main_k7ddrphy_wdly_dq_bitslip_rst_r;
-reg  main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg  main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg  main_k7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire main_k7ddrphy_wdly_dq_bitslip_r;
-reg  main_k7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg  main_k7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg  [1:0] main_k7ddrphy_rdphase_storage = 2'd1;
-reg  main_k7ddrphy_rdphase_re = 1'd0;
-reg  [1:0] main_k7ddrphy_wrphase_storage = 2'd2;
-reg  main_k7ddrphy_wrphase_re = 1'd0;
-wire [14:0] main_k7ddrphy_dfi_p0_address;
-wire [2:0] main_k7ddrphy_dfi_p0_bank;
-wire main_k7ddrphy_dfi_p0_cas_n;
-wire main_k7ddrphy_dfi_p0_cs_n;
-wire main_k7ddrphy_dfi_p0_ras_n;
-wire main_k7ddrphy_dfi_p0_we_n;
-wire main_k7ddrphy_dfi_p0_cke;
-wire main_k7ddrphy_dfi_p0_odt;
-wire main_k7ddrphy_dfi_p0_reset_n;
-wire main_k7ddrphy_dfi_p0_act_n;
-wire [63:0] main_k7ddrphy_dfi_p0_wrdata;
-wire main_k7ddrphy_dfi_p0_wrdata_en;
-wire [7:0] main_k7ddrphy_dfi_p0_wrdata_mask;
-wire main_k7ddrphy_dfi_p0_rddata_en;
-reg  [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0;
-wire main_k7ddrphy_dfi_p0_rddata_valid;
-wire [14:0] main_k7ddrphy_dfi_p1_address;
-wire [2:0] main_k7ddrphy_dfi_p1_bank;
-wire main_k7ddrphy_dfi_p1_cas_n;
-wire main_k7ddrphy_dfi_p1_cs_n;
-wire main_k7ddrphy_dfi_p1_ras_n;
-wire main_k7ddrphy_dfi_p1_we_n;
-wire main_k7ddrphy_dfi_p1_cke;
-wire main_k7ddrphy_dfi_p1_odt;
-wire main_k7ddrphy_dfi_p1_reset_n;
-wire main_k7ddrphy_dfi_p1_act_n;
-wire [63:0] main_k7ddrphy_dfi_p1_wrdata;
-wire main_k7ddrphy_dfi_p1_wrdata_en;
-wire [7:0] main_k7ddrphy_dfi_p1_wrdata_mask;
-wire main_k7ddrphy_dfi_p1_rddata_en;
-reg  [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0;
-wire main_k7ddrphy_dfi_p1_rddata_valid;
-wire [14:0] main_k7ddrphy_dfi_p2_address;
-wire [2:0] main_k7ddrphy_dfi_p2_bank;
-wire main_k7ddrphy_dfi_p2_cas_n;
-wire main_k7ddrphy_dfi_p2_cs_n;
-wire main_k7ddrphy_dfi_p2_ras_n;
-wire main_k7ddrphy_dfi_p2_we_n;
-wire main_k7ddrphy_dfi_p2_cke;
-wire main_k7ddrphy_dfi_p2_odt;
-wire main_k7ddrphy_dfi_p2_reset_n;
-wire main_k7ddrphy_dfi_p2_act_n;
-wire [63:0] main_k7ddrphy_dfi_p2_wrdata;
-wire main_k7ddrphy_dfi_p2_wrdata_en;
-wire [7:0] main_k7ddrphy_dfi_p2_wrdata_mask;
-wire main_k7ddrphy_dfi_p2_rddata_en;
-reg  [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0;
-wire main_k7ddrphy_dfi_p2_rddata_valid;
-wire [14:0] main_k7ddrphy_dfi_p3_address;
-wire [2:0] main_k7ddrphy_dfi_p3_bank;
-wire main_k7ddrphy_dfi_p3_cas_n;
-wire main_k7ddrphy_dfi_p3_cs_n;
-wire main_k7ddrphy_dfi_p3_ras_n;
-wire main_k7ddrphy_dfi_p3_we_n;
-wire main_k7ddrphy_dfi_p3_cke;
-wire main_k7ddrphy_dfi_p3_odt;
-wire main_k7ddrphy_dfi_p3_reset_n;
-wire main_k7ddrphy_dfi_p3_act_n;
-wire [63:0] main_k7ddrphy_dfi_p3_wrdata;
-wire main_k7ddrphy_dfi_p3_wrdata_en;
-wire [7:0] main_k7ddrphy_dfi_p3_wrdata_mask;
-wire main_k7ddrphy_dfi_p3_rddata_en;
-reg  [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0;
-wire main_k7ddrphy_dfi_p3_rddata_valid;
-wire main_k7ddrphy_sd_clk_se_nodelay;
-wire main_k7ddrphy_sd_clk_se_delayed;
-wire main_k7ddrphy_oq0;
-wire main_k7ddrphy_oq1;
-wire main_k7ddrphy_oq2;
-wire main_k7ddrphy_oq3;
-wire main_k7ddrphy_oq4;
-wire main_k7ddrphy_oq5;
-wire main_k7ddrphy_oq6;
-wire main_k7ddrphy_oq7;
-wire main_k7ddrphy_oq8;
-wire main_k7ddrphy_oq9;
-wire main_k7ddrphy_oq10;
-wire main_k7ddrphy_oq11;
-wire main_k7ddrphy_oq12;
-wire main_k7ddrphy_oq13;
-wire main_k7ddrphy_oq14;
-wire main_k7ddrphy_oq15;
-wire main_k7ddrphy_oq16;
-wire main_k7ddrphy_oq17;
-wire main_k7ddrphy_oq18;
-wire main_k7ddrphy_oq19;
-wire main_k7ddrphy_oq20;
-wire main_k7ddrphy_oq21;
-wire main_k7ddrphy_oq22;
-wire main_k7ddrphy_oq23;
-wire main_k7ddrphy_oq24;
-reg  main_k7ddrphy_dqs_oe = 1'd0;
-wire main_k7ddrphy_dqs_preamble;
-wire main_k7ddrphy_dqs_postamble;
-wire main_k7ddrphy_dqs_oe_delay_tappeddelayline;
-reg  main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg  main_k7ddrphy_dqspattern0 = 1'd0;
-reg  main_k7ddrphy_dqspattern1 = 1'd0;
-reg  [7:0] main_k7ddrphy_dqspattern_o = 8'd0;
-wire main_k7ddrphy_dqs_o_no_delay0;
-wire main_k7ddrphy_dqs_o_delayed0;
-wire main_k7ddrphy_dqs_t0;
-reg  [7:0] main_k7ddrphy_bitslip00 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0;
-wire main_k7ddrphy0;
-wire main_k7ddrphy_dqs_o_no_delay1;
-wire main_k7ddrphy_dqs_o_delayed1;
-wire main_k7ddrphy_dqs_t1;
-reg  [7:0] main_k7ddrphy_bitslip10 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0;
-wire main_k7ddrphy1;
-wire main_k7ddrphy_dqs_o_no_delay2;
-wire main_k7ddrphy_dqs_o_delayed2;
-wire main_k7ddrphy_dqs_t2;
-reg  [7:0] main_k7ddrphy_bitslip20 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0;
-wire main_k7ddrphy2;
-wire main_k7ddrphy_dqs_o_no_delay3;
-wire main_k7ddrphy_dqs_o_delayed3;
-wire main_k7ddrphy_dqs_t3;
-reg  [7:0] main_k7ddrphy_bitslip30 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0;
-wire main_k7ddrphy3;
-wire main_k7ddrphy_dm_o_nodelay0;
-reg  [7:0] main_k7ddrphy_bitslip01 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0;
-wire main_k7ddrphy_dm_o_nodelay1;
-reg  [7:0] main_k7ddrphy_bitslip11 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0;
-wire main_k7ddrphy_dm_o_nodelay2;
-reg  [7:0] main_k7ddrphy_bitslip21 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0;
-wire main_k7ddrphy_dm_o_nodelay3;
-reg  [7:0] main_k7ddrphy_bitslip31 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0;
-wire main_k7ddrphy_dq_oe;
-wire main_k7ddrphy_dq_oe_delay_tappeddelayline;
-reg  main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire main_k7ddrphy_dq_o_nodelay0;
-wire main_k7ddrphy_dq_o_delayed0;
-wire main_k7ddrphy_dq_i_nodelay0;
-wire main_k7ddrphy_dq_i_delayed0;
-wire main_k7ddrphy_dq_t0;
-reg  [7:0] main_k7ddrphy_bitslip02 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip03;
-reg  [7:0] main_k7ddrphy_bitslip04 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay1;
-wire main_k7ddrphy_dq_o_delayed1;
-wire main_k7ddrphy_dq_i_nodelay1;
-wire main_k7ddrphy_dq_i_delayed1;
-wire main_k7ddrphy_dq_t1;
-reg  [7:0] main_k7ddrphy_bitslip12 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip13;
-reg  [7:0] main_k7ddrphy_bitslip14 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay2;
-wire main_k7ddrphy_dq_o_delayed2;
-wire main_k7ddrphy_dq_i_nodelay2;
-wire main_k7ddrphy_dq_i_delayed2;
-wire main_k7ddrphy_dq_t2;
-reg  [7:0] main_k7ddrphy_bitslip22 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip23;
-reg  [7:0] main_k7ddrphy_bitslip24 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay3;
-wire main_k7ddrphy_dq_o_delayed3;
-wire main_k7ddrphy_dq_i_nodelay3;
-wire main_k7ddrphy_dq_i_delayed3;
-wire main_k7ddrphy_dq_t3;
-reg  [7:0] main_k7ddrphy_bitslip32 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip33;
-reg  [7:0] main_k7ddrphy_bitslip34 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay4;
-wire main_k7ddrphy_dq_o_delayed4;
-wire main_k7ddrphy_dq_i_nodelay4;
-wire main_k7ddrphy_dq_i_delayed4;
-wire main_k7ddrphy_dq_t4;
-reg  [7:0] main_k7ddrphy_bitslip40 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip41;
-reg  [7:0] main_k7ddrphy_bitslip42 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay5;
-wire main_k7ddrphy_dq_o_delayed5;
-wire main_k7ddrphy_dq_i_nodelay5;
-wire main_k7ddrphy_dq_i_delayed5;
-wire main_k7ddrphy_dq_t5;
-reg  [7:0] main_k7ddrphy_bitslip50 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip51;
-reg  [7:0] main_k7ddrphy_bitslip52 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay6;
-wire main_k7ddrphy_dq_o_delayed6;
-wire main_k7ddrphy_dq_i_nodelay6;
-wire main_k7ddrphy_dq_i_delayed6;
-wire main_k7ddrphy_dq_t6;
-reg  [7:0] main_k7ddrphy_bitslip60 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip61;
-reg  [7:0] main_k7ddrphy_bitslip62 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay7;
-wire main_k7ddrphy_dq_o_delayed7;
-wire main_k7ddrphy_dq_i_nodelay7;
-wire main_k7ddrphy_dq_i_delayed7;
-wire main_k7ddrphy_dq_t7;
-reg  [7:0] main_k7ddrphy_bitslip70 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip71;
-reg  [7:0] main_k7ddrphy_bitslip72 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay8;
-wire main_k7ddrphy_dq_o_delayed8;
-wire main_k7ddrphy_dq_i_nodelay8;
-wire main_k7ddrphy_dq_i_delayed8;
-wire main_k7ddrphy_dq_t8;
-reg  [7:0] main_k7ddrphy_bitslip80 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip81;
-reg  [7:0] main_k7ddrphy_bitslip82 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay9;
-wire main_k7ddrphy_dq_o_delayed9;
-wire main_k7ddrphy_dq_i_nodelay9;
-wire main_k7ddrphy_dq_i_delayed9;
-wire main_k7ddrphy_dq_t9;
-reg  [7:0] main_k7ddrphy_bitslip90 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip91;
-reg  [7:0] main_k7ddrphy_bitslip92 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay10;
-wire main_k7ddrphy_dq_o_delayed10;
-wire main_k7ddrphy_dq_i_nodelay10;
-wire main_k7ddrphy_dq_i_delayed10;
-wire main_k7ddrphy_dq_t10;
-reg  [7:0] main_k7ddrphy_bitslip100 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip101;
-reg  [7:0] main_k7ddrphy_bitslip102 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay11;
-wire main_k7ddrphy_dq_o_delayed11;
-wire main_k7ddrphy_dq_i_nodelay11;
-wire main_k7ddrphy_dq_i_delayed11;
-wire main_k7ddrphy_dq_t11;
-reg  [7:0] main_k7ddrphy_bitslip110 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip111;
-reg  [7:0] main_k7ddrphy_bitslip112 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay12;
-wire main_k7ddrphy_dq_o_delayed12;
-wire main_k7ddrphy_dq_i_nodelay12;
-wire main_k7ddrphy_dq_i_delayed12;
-wire main_k7ddrphy_dq_t12;
-reg  [7:0] main_k7ddrphy_bitslip120 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip121;
-reg  [7:0] main_k7ddrphy_bitslip122 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay13;
-wire main_k7ddrphy_dq_o_delayed13;
-wire main_k7ddrphy_dq_i_nodelay13;
-wire main_k7ddrphy_dq_i_delayed13;
-wire main_k7ddrphy_dq_t13;
-reg  [7:0] main_k7ddrphy_bitslip130 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip131;
-reg  [7:0] main_k7ddrphy_bitslip132 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay14;
-wire main_k7ddrphy_dq_o_delayed14;
-wire main_k7ddrphy_dq_i_nodelay14;
-wire main_k7ddrphy_dq_i_delayed14;
-wire main_k7ddrphy_dq_t14;
-reg  [7:0] main_k7ddrphy_bitslip140 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip141;
-reg  [7:0] main_k7ddrphy_bitslip142 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay15;
-wire main_k7ddrphy_dq_o_delayed15;
-wire main_k7ddrphy_dq_i_nodelay15;
-wire main_k7ddrphy_dq_i_delayed15;
-wire main_k7ddrphy_dq_t15;
-reg  [7:0] main_k7ddrphy_bitslip150 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip151;
-reg  [7:0] main_k7ddrphy_bitslip152 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay16;
-wire main_k7ddrphy_dq_o_delayed16;
-wire main_k7ddrphy_dq_i_nodelay16;
-wire main_k7ddrphy_dq_i_delayed16;
-wire main_k7ddrphy_dq_t16;
-reg  [7:0] main_k7ddrphy_bitslip160 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip161;
-reg  [7:0] main_k7ddrphy_bitslip162 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay17;
-wire main_k7ddrphy_dq_o_delayed17;
-wire main_k7ddrphy_dq_i_nodelay17;
-wire main_k7ddrphy_dq_i_delayed17;
-wire main_k7ddrphy_dq_t17;
-reg  [7:0] main_k7ddrphy_bitslip170 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip171;
-reg  [7:0] main_k7ddrphy_bitslip172 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay18;
-wire main_k7ddrphy_dq_o_delayed18;
-wire main_k7ddrphy_dq_i_nodelay18;
-wire main_k7ddrphy_dq_i_delayed18;
-wire main_k7ddrphy_dq_t18;
-reg  [7:0] main_k7ddrphy_bitslip180 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip181;
-reg  [7:0] main_k7ddrphy_bitslip182 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay19;
-wire main_k7ddrphy_dq_o_delayed19;
-wire main_k7ddrphy_dq_i_nodelay19;
-wire main_k7ddrphy_dq_i_delayed19;
-wire main_k7ddrphy_dq_t19;
-reg  [7:0] main_k7ddrphy_bitslip190 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip191;
-reg  [7:0] main_k7ddrphy_bitslip192 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay20;
-wire main_k7ddrphy_dq_o_delayed20;
-wire main_k7ddrphy_dq_i_nodelay20;
-wire main_k7ddrphy_dq_i_delayed20;
-wire main_k7ddrphy_dq_t20;
-reg  [7:0] main_k7ddrphy_bitslip200 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip201;
-reg  [7:0] main_k7ddrphy_bitslip202 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay21;
-wire main_k7ddrphy_dq_o_delayed21;
-wire main_k7ddrphy_dq_i_nodelay21;
-wire main_k7ddrphy_dq_i_delayed21;
-wire main_k7ddrphy_dq_t21;
-reg  [7:0] main_k7ddrphy_bitslip210 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip211;
-reg  [7:0] main_k7ddrphy_bitslip212 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay22;
-wire main_k7ddrphy_dq_o_delayed22;
-wire main_k7ddrphy_dq_i_nodelay22;
-wire main_k7ddrphy_dq_i_delayed22;
-wire main_k7ddrphy_dq_t22;
-reg  [7:0] main_k7ddrphy_bitslip220 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip221;
-reg  [7:0] main_k7ddrphy_bitslip222 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay23;
-wire main_k7ddrphy_dq_o_delayed23;
-wire main_k7ddrphy_dq_i_nodelay23;
-wire main_k7ddrphy_dq_i_delayed23;
-wire main_k7ddrphy_dq_t23;
-reg  [7:0] main_k7ddrphy_bitslip230 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip231;
-reg  [7:0] main_k7ddrphy_bitslip232 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay24;
-wire main_k7ddrphy_dq_o_delayed24;
-wire main_k7ddrphy_dq_i_nodelay24;
-wire main_k7ddrphy_dq_i_delayed24;
-wire main_k7ddrphy_dq_t24;
-reg  [7:0] main_k7ddrphy_bitslip240 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip241;
-reg  [7:0] main_k7ddrphy_bitslip242 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay25;
-wire main_k7ddrphy_dq_o_delayed25;
-wire main_k7ddrphy_dq_i_nodelay25;
-wire main_k7ddrphy_dq_i_delayed25;
-wire main_k7ddrphy_dq_t25;
-reg  [7:0] main_k7ddrphy_bitslip250 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip251;
-reg  [7:0] main_k7ddrphy_bitslip252 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay26;
-wire main_k7ddrphy_dq_o_delayed26;
-wire main_k7ddrphy_dq_i_nodelay26;
-wire main_k7ddrphy_dq_i_delayed26;
-wire main_k7ddrphy_dq_t26;
-reg  [7:0] main_k7ddrphy_bitslip260 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip261;
-reg  [7:0] main_k7ddrphy_bitslip262 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay27;
-wire main_k7ddrphy_dq_o_delayed27;
-wire main_k7ddrphy_dq_i_nodelay27;
-wire main_k7ddrphy_dq_i_delayed27;
-wire main_k7ddrphy_dq_t27;
-reg  [7:0] main_k7ddrphy_bitslip270 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip271;
-reg  [7:0] main_k7ddrphy_bitslip272 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay28;
-wire main_k7ddrphy_dq_o_delayed28;
-wire main_k7ddrphy_dq_i_nodelay28;
-wire main_k7ddrphy_dq_i_delayed28;
-wire main_k7ddrphy_dq_t28;
-reg  [7:0] main_k7ddrphy_bitslip280 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip281;
-reg  [7:0] main_k7ddrphy_bitslip282 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay29;
-wire main_k7ddrphy_dq_o_delayed29;
-wire main_k7ddrphy_dq_i_nodelay29;
-wire main_k7ddrphy_dq_i_delayed29;
-wire main_k7ddrphy_dq_t29;
-reg  [7:0] main_k7ddrphy_bitslip290 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip291;
-reg  [7:0] main_k7ddrphy_bitslip292 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay30;
-wire main_k7ddrphy_dq_o_delayed30;
-wire main_k7ddrphy_dq_i_nodelay30;
-wire main_k7ddrphy_dq_i_delayed30;
-wire main_k7ddrphy_dq_t30;
-reg  [7:0] main_k7ddrphy_bitslip300 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip301;
-reg  [7:0] main_k7ddrphy_bitslip302 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0;
-wire main_k7ddrphy_dq_o_nodelay31;
-wire main_k7ddrphy_dq_o_delayed31;
-wire main_k7ddrphy_dq_i_nodelay31;
-wire main_k7ddrphy_dq_i_delayed31;
-wire main_k7ddrphy_dq_t31;
-reg  [7:0] main_k7ddrphy_bitslip310 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0;
-wire [7:0] main_k7ddrphy_bitslip311;
-reg  [7:0] main_k7ddrphy_bitslip312 = 8'd0;
-reg  [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7;
-reg  [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg  main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg  main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg  main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg  main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [14:0] main_litedramcore_inti_p0_address;
-wire [2:0] main_litedramcore_inti_p0_bank;
-reg  main_litedramcore_inti_p0_cas_n = 1'd1;
-reg  main_litedramcore_inti_p0_cs_n = 1'd1;
-reg  main_litedramcore_inti_p0_ras_n = 1'd1;
-reg  main_litedramcore_inti_p0_we_n = 1'd1;
-wire main_litedramcore_inti_p0_cke;
-wire main_litedramcore_inti_p0_odt;
-wire main_litedramcore_inti_p0_reset_n;
-reg  main_litedramcore_inti_p0_act_n = 1'd1;
-wire [63:0] main_litedramcore_inti_p0_wrdata;
-wire main_litedramcore_inti_p0_wrdata_en;
-wire [7:0] main_litedramcore_inti_p0_wrdata_mask;
-wire main_litedramcore_inti_p0_rddata_en;
-reg  [63:0] main_litedramcore_inti_p0_rddata = 64'd0;
-reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_inti_p1_address;
-wire [2:0] main_litedramcore_inti_p1_bank;
-reg  main_litedramcore_inti_p1_cas_n = 1'd1;
-reg  main_litedramcore_inti_p1_cs_n = 1'd1;
-reg  main_litedramcore_inti_p1_ras_n = 1'd1;
-reg  main_litedramcore_inti_p1_we_n = 1'd1;
-wire main_litedramcore_inti_p1_cke;
-wire main_litedramcore_inti_p1_odt;
-wire main_litedramcore_inti_p1_reset_n;
-reg  main_litedramcore_inti_p1_act_n = 1'd1;
-wire [63:0] main_litedramcore_inti_p1_wrdata;
-wire main_litedramcore_inti_p1_wrdata_en;
-wire [7:0] main_litedramcore_inti_p1_wrdata_mask;
-wire main_litedramcore_inti_p1_rddata_en;
-reg  [63:0] main_litedramcore_inti_p1_rddata = 64'd0;
-reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_inti_p2_address;
-wire [2:0] main_litedramcore_inti_p2_bank;
-reg  main_litedramcore_inti_p2_cas_n = 1'd1;
-reg  main_litedramcore_inti_p2_cs_n = 1'd1;
-reg  main_litedramcore_inti_p2_ras_n = 1'd1;
-reg  main_litedramcore_inti_p2_we_n = 1'd1;
-wire main_litedramcore_inti_p2_cke;
-wire main_litedramcore_inti_p2_odt;
-wire main_litedramcore_inti_p2_reset_n;
-reg  main_litedramcore_inti_p2_act_n = 1'd1;
-wire [63:0] main_litedramcore_inti_p2_wrdata;
-wire main_litedramcore_inti_p2_wrdata_en;
-wire [7:0] main_litedramcore_inti_p2_wrdata_mask;
-wire main_litedramcore_inti_p2_rddata_en;
-reg  [63:0] main_litedramcore_inti_p2_rddata = 64'd0;
-reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_inti_p3_address;
-wire [2:0] main_litedramcore_inti_p3_bank;
-reg  main_litedramcore_inti_p3_cas_n = 1'd1;
-reg  main_litedramcore_inti_p3_cs_n = 1'd1;
-reg  main_litedramcore_inti_p3_ras_n = 1'd1;
-reg  main_litedramcore_inti_p3_we_n = 1'd1;
-wire main_litedramcore_inti_p3_cke;
-wire main_litedramcore_inti_p3_odt;
-wire main_litedramcore_inti_p3_reset_n;
-reg  main_litedramcore_inti_p3_act_n = 1'd1;
-wire [63:0] main_litedramcore_inti_p3_wrdata;
-wire main_litedramcore_inti_p3_wrdata_en;
-wire [7:0] main_litedramcore_inti_p3_wrdata_mask;
-wire main_litedramcore_inti_p3_rddata_en;
-reg  [63:0] main_litedramcore_inti_p3_rddata = 64'd0;
-reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p0_address;
-wire [2:0] main_litedramcore_slave_p0_bank;
-wire main_litedramcore_slave_p0_cas_n;
-wire main_litedramcore_slave_p0_cs_n;
-wire main_litedramcore_slave_p0_ras_n;
-wire main_litedramcore_slave_p0_we_n;
-wire main_litedramcore_slave_p0_cke;
-wire main_litedramcore_slave_p0_odt;
-wire main_litedramcore_slave_p0_reset_n;
-wire main_litedramcore_slave_p0_act_n;
-wire [63:0] main_litedramcore_slave_p0_wrdata;
-wire main_litedramcore_slave_p0_wrdata_en;
-wire [7:0] main_litedramcore_slave_p0_wrdata_mask;
-wire main_litedramcore_slave_p0_rddata_en;
-reg  [63:0] main_litedramcore_slave_p0_rddata = 64'd0;
-reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p1_address;
-wire [2:0] main_litedramcore_slave_p1_bank;
-wire main_litedramcore_slave_p1_cas_n;
-wire main_litedramcore_slave_p1_cs_n;
-wire main_litedramcore_slave_p1_ras_n;
-wire main_litedramcore_slave_p1_we_n;
-wire main_litedramcore_slave_p1_cke;
-wire main_litedramcore_slave_p1_odt;
-wire main_litedramcore_slave_p1_reset_n;
-wire main_litedramcore_slave_p1_act_n;
-wire [63:0] main_litedramcore_slave_p1_wrdata;
-wire main_litedramcore_slave_p1_wrdata_en;
-wire [7:0] main_litedramcore_slave_p1_wrdata_mask;
-wire main_litedramcore_slave_p1_rddata_en;
-reg  [63:0] main_litedramcore_slave_p1_rddata = 64'd0;
-reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p2_address;
-wire [2:0] main_litedramcore_slave_p2_bank;
-wire main_litedramcore_slave_p2_cas_n;
-wire main_litedramcore_slave_p2_cs_n;
-wire main_litedramcore_slave_p2_ras_n;
-wire main_litedramcore_slave_p2_we_n;
-wire main_litedramcore_slave_p2_cke;
-wire main_litedramcore_slave_p2_odt;
-wire main_litedramcore_slave_p2_reset_n;
-wire main_litedramcore_slave_p2_act_n;
-wire [63:0] main_litedramcore_slave_p2_wrdata;
-wire main_litedramcore_slave_p2_wrdata_en;
-wire [7:0] main_litedramcore_slave_p2_wrdata_mask;
-wire main_litedramcore_slave_p2_rddata_en;
-reg  [63:0] main_litedramcore_slave_p2_rddata = 64'd0;
-reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p3_address;
-wire [2:0] main_litedramcore_slave_p3_bank;
-wire main_litedramcore_slave_p3_cas_n;
-wire main_litedramcore_slave_p3_cs_n;
-wire main_litedramcore_slave_p3_ras_n;
-wire main_litedramcore_slave_p3_we_n;
-wire main_litedramcore_slave_p3_cke;
-wire main_litedramcore_slave_p3_odt;
-wire main_litedramcore_slave_p3_reset_n;
-wire main_litedramcore_slave_p3_act_n;
-wire [63:0] main_litedramcore_slave_p3_wrdata;
-wire main_litedramcore_slave_p3_wrdata_en;
-wire [7:0] main_litedramcore_slave_p3_wrdata_mask;
-wire main_litedramcore_slave_p3_rddata_en;
-reg  [63:0] main_litedramcore_slave_p3_rddata = 64'd0;
-reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg  [14:0] main_litedramcore_master_p0_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg  main_litedramcore_master_p0_cas_n = 1'd1;
-reg  main_litedramcore_master_p0_cs_n = 1'd1;
-reg  main_litedramcore_master_p0_ras_n = 1'd1;
-reg  main_litedramcore_master_p0_we_n = 1'd1;
-reg  main_litedramcore_master_p0_cke = 1'd0;
-reg  main_litedramcore_master_p0_odt = 1'd0;
-reg  main_litedramcore_master_p0_reset_n = 1'd0;
-reg  main_litedramcore_master_p0_act_n = 1'd1;
-reg  [63:0] main_litedramcore_master_p0_wrdata = 64'd0;
-reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg  [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0;
-reg  main_litedramcore_master_p0_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_master_p0_rddata;
-wire main_litedramcore_master_p0_rddata_valid;
-reg  [14:0] main_litedramcore_master_p1_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg  main_litedramcore_master_p1_cas_n = 1'd1;
-reg  main_litedramcore_master_p1_cs_n = 1'd1;
-reg  main_litedramcore_master_p1_ras_n = 1'd1;
-reg  main_litedramcore_master_p1_we_n = 1'd1;
-reg  main_litedramcore_master_p1_cke = 1'd0;
-reg  main_litedramcore_master_p1_odt = 1'd0;
-reg  main_litedramcore_master_p1_reset_n = 1'd0;
-reg  main_litedramcore_master_p1_act_n = 1'd1;
-reg  [63:0] main_litedramcore_master_p1_wrdata = 64'd0;
-reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg  [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0;
-reg  main_litedramcore_master_p1_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_master_p1_rddata;
-wire main_litedramcore_master_p1_rddata_valid;
-reg  [14:0] main_litedramcore_master_p2_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg  main_litedramcore_master_p2_cas_n = 1'd1;
-reg  main_litedramcore_master_p2_cs_n = 1'd1;
-reg  main_litedramcore_master_p2_ras_n = 1'd1;
-reg  main_litedramcore_master_p2_we_n = 1'd1;
-reg  main_litedramcore_master_p2_cke = 1'd0;
-reg  main_litedramcore_master_p2_odt = 1'd0;
-reg  main_litedramcore_master_p2_reset_n = 1'd0;
-reg  main_litedramcore_master_p2_act_n = 1'd1;
-reg  [63:0] main_litedramcore_master_p2_wrdata = 64'd0;
-reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg  [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0;
-reg  main_litedramcore_master_p2_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_master_p2_rddata;
-wire main_litedramcore_master_p2_rddata_valid;
-reg  [14:0] main_litedramcore_master_p3_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg  main_litedramcore_master_p3_cas_n = 1'd1;
-reg  main_litedramcore_master_p3_cs_n = 1'd1;
-reg  main_litedramcore_master_p3_ras_n = 1'd1;
-reg  main_litedramcore_master_p3_we_n = 1'd1;
-reg  main_litedramcore_master_p3_cke = 1'd0;
-reg  main_litedramcore_master_p3_odt = 1'd0;
-reg  main_litedramcore_master_p3_reset_n = 1'd0;
-reg  main_litedramcore_master_p3_act_n = 1'd1;
-reg  [63:0] main_litedramcore_master_p3_wrdata = 64'd0;
-reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg  [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0;
-reg  main_litedramcore_master_p3_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_master_p3_rddata;
-wire main_litedramcore_master_p3_rddata_valid;
-wire main_litedramcore_sel;
-wire main_litedramcore_cke;
-wire main_litedramcore_odt;
-wire main_litedramcore_reset_n;
-reg  [3:0] main_litedramcore_storage = 4'd1;
-reg  main_litedramcore_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector0_command_issue_r;
-reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0;
-reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0;
-wire main_litedramcore_phaseinjector0_rddata_we;
-reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector1_command_issue_r;
-reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0;
-reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0;
-wire main_litedramcore_phaseinjector1_rddata_we;
-reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector2_command_issue_r;
-reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0;
-reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0;
-wire main_litedramcore_phaseinjector2_rddata_we;
-reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector3_command_issue_r;
-reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0;
-reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg  [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0;
-wire main_litedramcore_phaseinjector3_rddata_we;
-reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire main_litedramcore_interface_bank0_valid;
-wire main_litedramcore_interface_bank0_ready;
-wire main_litedramcore_interface_bank0_we;
-wire [21:0] main_litedramcore_interface_bank0_addr;
-wire main_litedramcore_interface_bank0_lock;
-wire main_litedramcore_interface_bank0_wdata_ready;
-wire main_litedramcore_interface_bank0_rdata_valid;
-wire main_litedramcore_interface_bank1_valid;
-wire main_litedramcore_interface_bank1_ready;
-wire main_litedramcore_interface_bank1_we;
-wire [21:0] main_litedramcore_interface_bank1_addr;
-wire main_litedramcore_interface_bank1_lock;
-wire main_litedramcore_interface_bank1_wdata_ready;
-wire main_litedramcore_interface_bank1_rdata_valid;
-wire main_litedramcore_interface_bank2_valid;
-wire main_litedramcore_interface_bank2_ready;
-wire main_litedramcore_interface_bank2_we;
-wire [21:0] main_litedramcore_interface_bank2_addr;
-wire main_litedramcore_interface_bank2_lock;
-wire main_litedramcore_interface_bank2_wdata_ready;
-wire main_litedramcore_interface_bank2_rdata_valid;
-wire main_litedramcore_interface_bank3_valid;
-wire main_litedramcore_interface_bank3_ready;
-wire main_litedramcore_interface_bank3_we;
-wire [21:0] main_litedramcore_interface_bank3_addr;
-wire main_litedramcore_interface_bank3_lock;
-wire main_litedramcore_interface_bank3_wdata_ready;
-wire main_litedramcore_interface_bank3_rdata_valid;
-wire main_litedramcore_interface_bank4_valid;
-wire main_litedramcore_interface_bank4_ready;
-wire main_litedramcore_interface_bank4_we;
-wire [21:0] main_litedramcore_interface_bank4_addr;
-wire main_litedramcore_interface_bank4_lock;
-wire main_litedramcore_interface_bank4_wdata_ready;
-wire main_litedramcore_interface_bank4_rdata_valid;
-wire main_litedramcore_interface_bank5_valid;
-wire main_litedramcore_interface_bank5_ready;
-wire main_litedramcore_interface_bank5_we;
-wire [21:0] main_litedramcore_interface_bank5_addr;
-wire main_litedramcore_interface_bank5_lock;
-wire main_litedramcore_interface_bank5_wdata_ready;
-wire main_litedramcore_interface_bank5_rdata_valid;
-wire main_litedramcore_interface_bank6_valid;
-wire main_litedramcore_interface_bank6_ready;
-wire main_litedramcore_interface_bank6_we;
-wire [21:0] main_litedramcore_interface_bank6_addr;
-wire main_litedramcore_interface_bank6_lock;
-wire main_litedramcore_interface_bank6_wdata_ready;
-wire main_litedramcore_interface_bank6_rdata_valid;
-wire main_litedramcore_interface_bank7_valid;
-wire main_litedramcore_interface_bank7_ready;
-wire main_litedramcore_interface_bank7_we;
-wire [21:0] main_litedramcore_interface_bank7_addr;
-wire main_litedramcore_interface_bank7_lock;
-wire main_litedramcore_interface_bank7_wdata_ready;
-wire main_litedramcore_interface_bank7_rdata_valid;
-reg  [255:0] main_litedramcore_interface_wdata = 256'd0;
-reg  [31:0] main_litedramcore_interface_wdata_we = 32'd0;
-wire [255:0] main_litedramcore_interface_rdata;
-reg  [14:0] main_litedramcore_dfi_p0_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p0_we_n = 1'd1;
-wire main_litedramcore_dfi_p0_cke;
-wire main_litedramcore_dfi_p0_odt;
-wire main_litedramcore_dfi_p0_reset_n;
-reg  main_litedramcore_dfi_p0_act_n = 1'd1;
-wire [63:0] main_litedramcore_dfi_p0_wrdata;
-reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [7:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_dfi_p0_rddata;
-wire main_litedramcore_dfi_p0_rddata_valid;
-reg  [14:0] main_litedramcore_dfi_p1_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p1_we_n = 1'd1;
-wire main_litedramcore_dfi_p1_cke;
-wire main_litedramcore_dfi_p1_odt;
-wire main_litedramcore_dfi_p1_reset_n;
-reg  main_litedramcore_dfi_p1_act_n = 1'd1;
-wire [63:0] main_litedramcore_dfi_p1_wrdata;
-reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [7:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_dfi_p1_rddata;
-wire main_litedramcore_dfi_p1_rddata_valid;
-reg  [14:0] main_litedramcore_dfi_p2_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p2_we_n = 1'd1;
-wire main_litedramcore_dfi_p2_cke;
-wire main_litedramcore_dfi_p2_odt;
-wire main_litedramcore_dfi_p2_reset_n;
-reg  main_litedramcore_dfi_p2_act_n = 1'd1;
-wire [63:0] main_litedramcore_dfi_p2_wrdata;
-reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [7:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_dfi_p2_rddata;
-wire main_litedramcore_dfi_p2_rddata_valid;
-reg  [14:0] main_litedramcore_dfi_p3_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p3_we_n = 1'd1;
-wire main_litedramcore_dfi_p3_cke;
-wire main_litedramcore_dfi_p3_odt;
-wire main_litedramcore_dfi_p3_reset_n;
-reg  main_litedramcore_dfi_p3_act_n = 1'd1;
-wire [63:0] main_litedramcore_dfi_p3_wrdata;
-reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [7:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [63:0] main_litedramcore_dfi_p3_rddata;
-wire main_litedramcore_dfi_p3_rddata_valid;
-reg  main_litedramcore_cmd_valid = 1'd0;
-reg  main_litedramcore_cmd_ready = 1'd0;
-reg  main_litedramcore_cmd_last = 1'd0;
-reg  [14:0] main_litedramcore_cmd_payload_a = 15'd0;
-reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg  main_litedramcore_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_cmd_payload_we = 1'd0;
-reg  main_litedramcore_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_cmd_payload_is_write = 1'd0;
-wire main_litedramcore_wants_refresh;
-wire main_litedramcore_wants_zqcs;
-wire main_litedramcore_timer_wait;
-wire main_litedramcore_timer_done0;
-wire [9:0] main_litedramcore_timer_count0;
-wire main_litedramcore_timer_done1;
-reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
-wire main_litedramcore_postponer_req_i;
-reg  main_litedramcore_postponer_req_o = 1'd0;
-reg  main_litedramcore_postponer_count = 1'd0;
-reg  main_litedramcore_sequencer_start0 = 1'd0;
-wire main_litedramcore_sequencer_done0;
-wire main_litedramcore_sequencer_start1;
-reg  main_litedramcore_sequencer_done1 = 1'd0;
-reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg  main_litedramcore_sequencer_count = 1'd0;
-wire main_litedramcore_zqcs_timer_wait;
-wire main_litedramcore_zqcs_timer_done0;
-wire [26:0] main_litedramcore_zqcs_timer_count0;
-wire main_litedramcore_zqcs_timer_done1;
-reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg  main_litedramcore_zqcs_executer_start = 1'd0;
-reg  main_litedramcore_zqcs_executer_done = 1'd0;
-reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
-wire main_litedramcore_bankmachine0_req_valid;
-wire main_litedramcore_bankmachine0_req_ready;
-wire main_litedramcore_bankmachine0_req_we;
-wire [21:0] main_litedramcore_bankmachine0_req_addr;
-wire main_litedramcore_bankmachine0_req_lock;
-reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine0_refresh_req;
-reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine0_row = 15'd0;
-reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
-wire main_litedramcore_bankmachine0_row_hit;
-reg  main_litedramcore_bankmachine0_row_open = 1'd0;
-reg  main_litedramcore_bankmachine0_row_close = 1'd0;
-reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine1_req_valid;
-wire main_litedramcore_bankmachine1_req_ready;
-wire main_litedramcore_bankmachine1_req_we;
-wire [21:0] main_litedramcore_bankmachine1_req_addr;
-wire main_litedramcore_bankmachine1_req_lock;
-reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine1_refresh_req;
-reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine1_row = 15'd0;
-reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
-wire main_litedramcore_bankmachine1_row_hit;
-reg  main_litedramcore_bankmachine1_row_open = 1'd0;
-reg  main_litedramcore_bankmachine1_row_close = 1'd0;
-reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine2_req_valid;
-wire main_litedramcore_bankmachine2_req_ready;
-wire main_litedramcore_bankmachine2_req_we;
-wire [21:0] main_litedramcore_bankmachine2_req_addr;
-wire main_litedramcore_bankmachine2_req_lock;
-reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine2_refresh_req;
-reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine2_row = 15'd0;
-reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
-wire main_litedramcore_bankmachine2_row_hit;
-reg  main_litedramcore_bankmachine2_row_open = 1'd0;
-reg  main_litedramcore_bankmachine2_row_close = 1'd0;
-reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine3_req_valid;
-wire main_litedramcore_bankmachine3_req_ready;
-wire main_litedramcore_bankmachine3_req_we;
-wire [21:0] main_litedramcore_bankmachine3_req_addr;
-wire main_litedramcore_bankmachine3_req_lock;
-reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine3_refresh_req;
-reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine3_row = 15'd0;
-reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
-wire main_litedramcore_bankmachine3_row_hit;
-reg  main_litedramcore_bankmachine3_row_open = 1'd0;
-reg  main_litedramcore_bankmachine3_row_close = 1'd0;
-reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine4_req_valid;
-wire main_litedramcore_bankmachine4_req_ready;
-wire main_litedramcore_bankmachine4_req_we;
-wire [21:0] main_litedramcore_bankmachine4_req_addr;
-wire main_litedramcore_bankmachine4_req_lock;
-reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine4_refresh_req;
-reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine4_row = 15'd0;
-reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
-wire main_litedramcore_bankmachine4_row_hit;
-reg  main_litedramcore_bankmachine4_row_open = 1'd0;
-reg  main_litedramcore_bankmachine4_row_close = 1'd0;
-reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine5_req_valid;
-wire main_litedramcore_bankmachine5_req_ready;
-wire main_litedramcore_bankmachine5_req_we;
-wire [21:0] main_litedramcore_bankmachine5_req_addr;
-wire main_litedramcore_bankmachine5_req_lock;
-reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine5_refresh_req;
-reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine5_row = 15'd0;
-reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
-wire main_litedramcore_bankmachine5_row_hit;
-reg  main_litedramcore_bankmachine5_row_open = 1'd0;
-reg  main_litedramcore_bankmachine5_row_close = 1'd0;
-reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine6_req_valid;
-wire main_litedramcore_bankmachine6_req_ready;
-wire main_litedramcore_bankmachine6_req_we;
-wire [21:0] main_litedramcore_bankmachine6_req_addr;
-wire main_litedramcore_bankmachine6_req_lock;
-reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine6_refresh_req;
-reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine6_row = 15'd0;
-reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
-wire main_litedramcore_bankmachine6_row_hit;
-reg  main_litedramcore_bankmachine6_row_open = 1'd0;
-reg  main_litedramcore_bankmachine6_row_close = 1'd0;
-reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine7_req_valid;
-wire main_litedramcore_bankmachine7_req_ready;
-wire main_litedramcore_bankmachine7_req_we;
-wire [21:0] main_litedramcore_bankmachine7_req_addr;
-wire main_litedramcore_bankmachine7_req_lock;
-reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine7_refresh_req;
-reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine7_row = 15'd0;
-reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
-wire main_litedramcore_bankmachine7_row_hit;
-reg  main_litedramcore_bankmachine7_row_open = 1'd0;
-reg  main_litedramcore_bankmachine7_row_close = 1'd0;
-reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
-wire main_litedramcore_ras_allowed;
-wire main_litedramcore_cas_allowed;
-wire [1:0] main_litedramcore_rdcmdphase;
-wire [1:0] main_litedramcore_wrcmdphase;
-reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_valid;
-reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire main_litedramcore_choose_cmd_cmd_payload_is_read;
-wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_cmd_request;
-reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
-wire main_litedramcore_choose_cmd_ce;
-reg  main_litedramcore_choose_req_want_reads = 1'd0;
-reg  main_litedramcore_choose_req_want_writes = 1'd0;
-reg  main_litedramcore_choose_req_want_cmds = 1'd0;
-reg  main_litedramcore_choose_req_want_activates = 1'd0;
-wire main_litedramcore_choose_req_cmd_valid;
-reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
-wire [14:0] main_litedramcore_choose_req_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_req_cmd_payload_is_cmd;
-wire main_litedramcore_choose_req_cmd_payload_is_read;
-wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_req_request;
-reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
-wire main_litedramcore_choose_req_ce;
-reg  [14:0] main_litedramcore_nop_a = 15'd0;
-reg  [2:0] main_litedramcore_nop_ba = 3'd0;
-reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg  main_litedramcore_steerer0 = 1'd1;
-reg  main_litedramcore_steerer1 = 1'd1;
-reg  main_litedramcore_steerer2 = 1'd1;
-reg  main_litedramcore_steerer3 = 1'd1;
-reg  main_litedramcore_steerer4 = 1'd1;
-reg  main_litedramcore_steerer5 = 1'd1;
-reg  main_litedramcore_steerer6 = 1'd1;
-reg  main_litedramcore_steerer7 = 1'd1;
-wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
-reg  main_litedramcore_trrdcon_count = 1'd0;
-wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] main_litedramcore_tfawcon_count;
-reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
-wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
-reg  main_litedramcore_tccdcon_count = 1'd0;
-wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
-wire main_litedramcore_read_available;
-wire main_litedramcore_write_available;
-reg  main_litedramcore_en0 = 1'd0;
-wire main_litedramcore_max_time0;
-reg  [4:0] main_litedramcore_time0 = 5'd0;
-reg  main_litedramcore_en1 = 1'd0;
-wire main_litedramcore_max_time1;
-reg  [3:0] main_litedramcore_time1 = 4'd0;
-wire main_litedramcore_go_to_refresh;
-reg  main_init_done_storage = 1'd0;
-reg  main_init_done_re = 1'd0;
-reg  main_init_error_storage = 1'd0;
-reg  main_init_error_re = 1'd0;
-wire [29:0] main_wb_bus_adr;
-wire [31:0] main_wb_bus_dat_w;
-wire [31:0] main_wb_bus_dat_r;
-wire [3:0] main_wb_bus_sel;
-wire main_wb_bus_cyc;
-wire main_wb_bus_stb;
-wire main_wb_bus_ack;
-wire main_wb_bus_we;
-wire [2:0] main_wb_bus_cti;
-wire [1:0] main_wb_bus_bte;
-wire main_wb_bus_err;
-wire main_user_enable;
-wire main_user_port_cmd_valid;
-wire main_user_port_cmd_ready;
-wire main_user_port_cmd_payload_we;
-wire [24:0] main_user_port_cmd_payload_addr;
-wire main_user_port_wdata_valid;
-wire main_user_port_wdata_ready;
-wire [255:0] main_user_port_wdata_payload_data;
-wire [31:0] main_user_port_wdata_payload_we;
-wire main_user_port_rdata_valid;
-wire main_user_port_rdata_ready;
-wire [255:0] main_user_port_rdata_payload_data;
-wire builder_reset0;
-wire builder_reset1;
-wire builder_reset2;
-wire builder_reset3;
-wire builder_reset4;
-wire builder_reset5;
-wire builder_reset6;
-wire builder_reset7;
-wire builder_pll_fb;
-reg  [1:0] builder_refresher_state = 2'd0;
-reg  [1:0] builder_refresher_next_state = 2'd0;
-reg  [3:0] builder_bankmachine0_state = 4'd0;
-reg  [3:0] builder_bankmachine0_next_state = 4'd0;
-reg  [3:0] builder_bankmachine1_state = 4'd0;
-reg  [3:0] builder_bankmachine1_next_state = 4'd0;
-reg  [3:0] builder_bankmachine2_state = 4'd0;
-reg  [3:0] builder_bankmachine2_next_state = 4'd0;
-reg  [3:0] builder_bankmachine3_state = 4'd0;
-reg  [3:0] builder_bankmachine3_next_state = 4'd0;
-reg  [3:0] builder_bankmachine4_state = 4'd0;
-reg  [3:0] builder_bankmachine4_next_state = 4'd0;
-reg  [3:0] builder_bankmachine5_state = 4'd0;
-reg  [3:0] builder_bankmachine5_next_state = 4'd0;
-reg  [3:0] builder_bankmachine6_state = 4'd0;
-reg  [3:0] builder_bankmachine6_next_state = 4'd0;
-reg  [3:0] builder_bankmachine7_state = 4'd0;
-reg  [3:0] builder_bankmachine7_next_state = 4'd0;
-reg  [3:0] builder_multiplexer_state = 4'd0;
-reg  [3:0] builder_multiplexer_next_state = 4'd0;
-wire builder_roundrobin0_request;
-wire builder_roundrobin0_grant;
-wire builder_roundrobin0_ce;
-wire builder_roundrobin1_request;
-wire builder_roundrobin1_grant;
-wire builder_roundrobin1_ce;
-wire builder_roundrobin2_request;
-wire builder_roundrobin2_grant;
-wire builder_roundrobin2_ce;
-wire builder_roundrobin3_request;
-wire builder_roundrobin3_grant;
-wire builder_roundrobin3_ce;
-wire builder_roundrobin4_request;
-wire builder_roundrobin4_grant;
-wire builder_roundrobin4_ce;
-wire builder_roundrobin5_request;
-wire builder_roundrobin5_grant;
-wire builder_roundrobin5_ce;
-wire builder_roundrobin6_request;
-wire builder_roundrobin6_grant;
-wire builder_roundrobin6_ce;
-wire builder_roundrobin7_request;
-wire builder_roundrobin7_grant;
-wire builder_roundrobin7_ce;
-reg  builder_locked0 = 1'd0;
-reg  builder_locked1 = 1'd0;
-reg  builder_locked2 = 1'd0;
-reg  builder_locked3 = 1'd0;
-reg  builder_locked4 = 1'd0;
-reg  builder_locked5 = 1'd0;
-reg  builder_locked6 = 1'd0;
-reg  builder_locked7 = 1'd0;
-reg  builder_new_master_wdata_ready0 = 1'd0;
-reg  builder_new_master_wdata_ready1 = 1'd0;
-reg  builder_new_master_rdata_valid0 = 1'd0;
-reg  builder_new_master_rdata_valid1 = 1'd0;
-reg  builder_new_master_rdata_valid2 = 1'd0;
-reg  builder_new_master_rdata_valid3 = 1'd0;
-reg  builder_new_master_rdata_valid4 = 1'd0;
-reg  builder_new_master_rdata_valid5 = 1'd0;
-reg  builder_new_master_rdata_valid6 = 1'd0;
-reg  builder_new_master_rdata_valid7 = 1'd0;
-reg  builder_new_master_rdata_valid8 = 1'd0;
-reg  [13:0] builder_litedramcore_adr = 14'd0;
-reg  builder_litedramcore_we = 1'd0;
-reg  [31:0] builder_litedramcore_dat_w = 32'd0;
-wire [31:0] builder_litedramcore_dat_r;
-wire [29:0] builder_litedramcore_wishbone_adr;
-wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] builder_litedramcore_wishbone_sel;
-wire builder_litedramcore_wishbone_cyc;
-wire builder_litedramcore_wishbone_stb;
-reg  builder_litedramcore_wishbone_ack = 1'd0;
-wire builder_litedramcore_wishbone_we;
-wire [2:0] builder_litedramcore_wishbone_cti;
-wire [1:0] builder_litedramcore_wishbone_bte;
-reg  builder_litedramcore_wishbone_err = 1'd0;
-wire [13:0] builder_interface0_bank_bus_adr;
-wire builder_interface0_bank_bus_we;
-wire [31:0] builder_interface0_bank_bus_dat_w;
-reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank0_init_done0_re = 1'd0;
-wire builder_csrbank0_init_done0_r;
-reg  builder_csrbank0_init_done0_we = 1'd0;
-wire builder_csrbank0_init_done0_w;
-reg  builder_csrbank0_init_error0_re = 1'd0;
-wire builder_csrbank0_init_error0_r;
-reg  builder_csrbank0_init_error0_we = 1'd0;
-wire builder_csrbank0_init_error0_w;
-wire builder_csrbank0_sel;
-wire [13:0] builder_interface1_bank_bus_adr;
-wire builder_interface1_bank_bus_we;
-wire [31:0] builder_interface1_bank_bus_dat_w;
-reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank1_rst0_re = 1'd0;
-wire builder_csrbank1_rst0_r;
-reg  builder_csrbank1_rst0_we = 1'd0;
-wire builder_csrbank1_rst0_w;
-reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg  builder_csrbank1_wlevel_en0_re = 1'd0;
-wire builder_csrbank1_wlevel_en0_r;
-reg  builder_csrbank1_wlevel_en0_we = 1'd0;
-wire builder_csrbank1_wlevel_en0_w;
-reg  builder_csrbank1_dly_sel0_re = 1'd0;
-wire [3:0] builder_csrbank1_dly_sel0_r;
-reg  builder_csrbank1_dly_sel0_we = 1'd0;
-wire [3:0] builder_csrbank1_dly_sel0_w;
-reg  builder_csrbank1_rdphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_r;
-reg  builder_csrbank1_rdphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_w;
-reg  builder_csrbank1_wrphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_r;
-reg  builder_csrbank1_wrphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_w;
-wire builder_csrbank1_sel;
-wire [13:0] builder_interface2_bank_bus_adr;
-wire builder_interface2_bank_bus_we;
-wire [31:0] builder_interface2_bank_bus_dat_w;
-reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_r;
-reg  builder_csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_w;
-reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi0_address0_r;
-reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi0_address0_w;
-reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg  builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_r;
-reg  builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_w;
-reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg  builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata1_r;
-reg  builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata1_w;
-reg  builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata0_r;
-reg  builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata0_w;
-reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi1_address0_r;
-reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi1_address0_w;
-reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg  builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_r;
-reg  builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_w;
-reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg  builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata1_r;
-reg  builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata1_w;
-reg  builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata0_r;
-reg  builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata0_w;
-reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi2_address0_r;
-reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi2_address0_w;
-reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg  builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_r;
-reg  builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_w;
-reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg  builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata1_r;
-reg  builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata1_w;
-reg  builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata0_r;
-reg  builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata0_w;
-reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi3_address0_r;
-reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi3_address0_w;
-reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg  builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_r;
-reg  builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_w;
-reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg  builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata1_r;
-reg  builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata1_w;
-reg  builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata0_r;
-reg  builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata0_w;
-wire builder_csrbank2_sel;
-wire [13:0] builder_csr_interconnect_adr;
-wire builder_csr_interconnect_we;
-wire [31:0] builder_csr_interconnect_dat_w;
-wire [31:0] builder_csr_interconnect_dat_r;
-reg  [1:0] builder_state = 2'd0;
-reg  [1:0] builder_next_state = 2'd0;
-reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
-reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg  builder_litedramcore_we_next_value2 = 1'd0;
-reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg  builder_rhs_array_muxed0 = 1'd0;
-reg  [14:0] builder_rhs_array_muxed1 = 15'd0;
-reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg  builder_rhs_array_muxed3 = 1'd0;
-reg  builder_rhs_array_muxed4 = 1'd0;
-reg  builder_rhs_array_muxed5 = 1'd0;
-reg  builder_t_array_muxed0 = 1'd0;
-reg  builder_t_array_muxed1 = 1'd0;
-reg  builder_t_array_muxed2 = 1'd0;
-reg  builder_rhs_array_muxed6 = 1'd0;
-reg  [14:0] builder_rhs_array_muxed7 = 15'd0;
-reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg  builder_rhs_array_muxed9 = 1'd0;
-reg  builder_rhs_array_muxed10 = 1'd0;
-reg  builder_rhs_array_muxed11 = 1'd0;
-reg  builder_t_array_muxed3 = 1'd0;
-reg  builder_t_array_muxed4 = 1'd0;
-reg  builder_t_array_muxed5 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed12 = 22'd0;
-reg  builder_rhs_array_muxed13 = 1'd0;
-reg  builder_rhs_array_muxed14 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed15 = 22'd0;
-reg  builder_rhs_array_muxed16 = 1'd0;
-reg  builder_rhs_array_muxed17 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed18 = 22'd0;
-reg  builder_rhs_array_muxed19 = 1'd0;
-reg  builder_rhs_array_muxed20 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed21 = 22'd0;
-reg  builder_rhs_array_muxed22 = 1'd0;
-reg  builder_rhs_array_muxed23 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed24 = 22'd0;
-reg  builder_rhs_array_muxed25 = 1'd0;
-reg  builder_rhs_array_muxed26 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed27 = 22'd0;
-reg  builder_rhs_array_muxed28 = 1'd0;
-reg  builder_rhs_array_muxed29 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed30 = 22'd0;
-reg  builder_rhs_array_muxed31 = 1'd0;
-reg  builder_rhs_array_muxed32 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed33 = 22'd0;
-reg  builder_rhs_array_muxed34 = 1'd0;
-reg  builder_rhs_array_muxed35 = 1'd0;
-reg  [2:0] builder_array_muxed0 = 3'd0;
-reg  [14:0] builder_array_muxed1 = 15'd0;
-reg  builder_array_muxed2 = 1'd0;
-reg  builder_array_muxed3 = 1'd0;
-reg  builder_array_muxed4 = 1'd0;
-reg  builder_array_muxed5 = 1'd0;
-reg  builder_array_muxed6 = 1'd0;
-reg  [2:0] builder_array_muxed7 = 3'd0;
-reg  [14:0] builder_array_muxed8 = 15'd0;
-reg  builder_array_muxed9 = 1'd0;
-reg  builder_array_muxed10 = 1'd0;
-reg  builder_array_muxed11 = 1'd0;
-reg  builder_array_muxed12 = 1'd0;
-reg  builder_array_muxed13 = 1'd0;
-reg  [2:0] builder_array_muxed14 = 3'd0;
-reg  [14:0] builder_array_muxed15 = 15'd0;
-reg  builder_array_muxed16 = 1'd0;
-reg  builder_array_muxed17 = 1'd0;
-reg  builder_array_muxed18 = 1'd0;
-reg  builder_array_muxed19 = 1'd0;
-reg  builder_array_muxed20 = 1'd0;
-reg  [2:0] builder_array_muxed21 = 3'd0;
-reg  [14:0] builder_array_muxed22 = 15'd0;
-reg  builder_array_muxed23 = 1'd0;
-reg  builder_array_muxed24 = 1'd0;
-reg  builder_array_muxed25 = 1'd0;
-reg  builder_array_muxed26 = 1'd0;
-reg  builder_array_muxed27 = 1'd0;
-wire builder_xilinxasyncresetsynchronizerimpl0;
-wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl1;
-wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2;
-wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2_expr;
-wire builder_xilinxasyncresetsynchronizerimpl3;
-wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire reset;
+reg  power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg  [3:0] reset_counter = 4'd15;
+reg  ic_reset = 1'd1;
+reg  k7ddrphy_rst_storage = 1'd0;
+reg  k7ddrphy_rst_re = 1'd0;
+reg  [3:0] k7ddrphy_dly_sel_storage = 4'd0;
+reg  k7ddrphy_dly_sel_re = 1'd0;
+reg  [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  k7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  k7ddrphy_wlevel_en_storage = 1'd0;
+reg  k7ddrphy_wlevel_en_re = 1'd0;
+reg  k7ddrphy_wlevel_strobe_re = 1'd0;
+wire k7ddrphy_wlevel_strobe_r;
+reg  k7ddrphy_wlevel_strobe_we = 1'd0;
+reg  k7ddrphy_wlevel_strobe_w = 1'd0;
+reg  k7ddrphy_cdly_rst_re = 1'd0;
+wire k7ddrphy_cdly_rst_r;
+reg  k7ddrphy_cdly_rst_we = 1'd0;
+reg  k7ddrphy_cdly_rst_w = 1'd0;
+reg  k7ddrphy_cdly_inc_re = 1'd0;
+wire k7ddrphy_cdly_inc_r;
+reg  k7ddrphy_cdly_inc_we = 1'd0;
+reg  k7ddrphy_cdly_inc_w = 1'd0;
+reg  k7ddrphy_rdly_dq_rst_re = 1'd0;
+wire k7ddrphy_rdly_dq_rst_r;
+reg  k7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  k7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  k7ddrphy_rdly_dq_inc_re = 1'd0;
+wire k7ddrphy_rdly_dq_inc_r;
+reg  k7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  k7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire k7ddrphy_rdly_dq_bitslip_rst_r;
+reg  k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  k7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire k7ddrphy_rdly_dq_bitslip_r;
+reg  k7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  k7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  k7ddrphy_wdly_dq_rst_re = 1'd0;
+wire k7ddrphy_wdly_dq_rst_r;
+reg  k7ddrphy_wdly_dq_rst_we = 1'd0;
+reg  k7ddrphy_wdly_dq_rst_w = 1'd0;
+reg  k7ddrphy_wdly_dq_inc_re = 1'd0;
+wire k7ddrphy_wdly_dq_inc_r;
+reg  k7ddrphy_wdly_dq_inc_we = 1'd0;
+reg  k7ddrphy_wdly_dq_inc_w = 1'd0;
+reg  k7ddrphy_wdly_dqs_rst_re = 1'd0;
+wire k7ddrphy_wdly_dqs_rst_r;
+reg  k7ddrphy_wdly_dqs_rst_we = 1'd0;
+reg  k7ddrphy_wdly_dqs_rst_w = 1'd0;
+reg  k7ddrphy_wdly_dqs_inc_re = 1'd0;
+wire k7ddrphy_wdly_dqs_inc_r;
+reg  k7ddrphy_wdly_dqs_inc_we = 1'd0;
+reg  k7ddrphy_wdly_dqs_inc_w = 1'd0;
+reg  k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire k7ddrphy_wdly_dq_bitslip_rst_r;
+reg  k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  k7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire k7ddrphy_wdly_dq_bitslip_r;
+reg  k7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  k7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] k7ddrphy_rdphase_storage = 2'd1;
+reg  k7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] k7ddrphy_wrphase_storage = 2'd2;
+reg  k7ddrphy_wrphase_re = 1'd0;
+wire [14:0] k7ddrphy_dfi_p0_address;
+wire [2:0] k7ddrphy_dfi_p0_bank;
+wire k7ddrphy_dfi_p0_cas_n;
+wire k7ddrphy_dfi_p0_cs_n;
+wire k7ddrphy_dfi_p0_ras_n;
+wire k7ddrphy_dfi_p0_we_n;
+wire k7ddrphy_dfi_p0_cke;
+wire k7ddrphy_dfi_p0_odt;
+wire k7ddrphy_dfi_p0_reset_n;
+wire k7ddrphy_dfi_p0_act_n;
+wire [63:0] k7ddrphy_dfi_p0_wrdata;
+wire k7ddrphy_dfi_p0_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p0_wrdata_mask;
+wire k7ddrphy_dfi_p0_rddata_en;
+reg  [63:0] k7ddrphy_dfi_p0_rddata = 64'd0;
+wire k7ddrphy_dfi_p0_rddata_valid;
+wire [14:0] k7ddrphy_dfi_p1_address;
+wire [2:0] k7ddrphy_dfi_p1_bank;
+wire k7ddrphy_dfi_p1_cas_n;
+wire k7ddrphy_dfi_p1_cs_n;
+wire k7ddrphy_dfi_p1_ras_n;
+wire k7ddrphy_dfi_p1_we_n;
+wire k7ddrphy_dfi_p1_cke;
+wire k7ddrphy_dfi_p1_odt;
+wire k7ddrphy_dfi_p1_reset_n;
+wire k7ddrphy_dfi_p1_act_n;
+wire [63:0] k7ddrphy_dfi_p1_wrdata;
+wire k7ddrphy_dfi_p1_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p1_wrdata_mask;
+wire k7ddrphy_dfi_p1_rddata_en;
+reg  [63:0] k7ddrphy_dfi_p1_rddata = 64'd0;
+wire k7ddrphy_dfi_p1_rddata_valid;
+wire [14:0] k7ddrphy_dfi_p2_address;
+wire [2:0] k7ddrphy_dfi_p2_bank;
+wire k7ddrphy_dfi_p2_cas_n;
+wire k7ddrphy_dfi_p2_cs_n;
+wire k7ddrphy_dfi_p2_ras_n;
+wire k7ddrphy_dfi_p2_we_n;
+wire k7ddrphy_dfi_p2_cke;
+wire k7ddrphy_dfi_p2_odt;
+wire k7ddrphy_dfi_p2_reset_n;
+wire k7ddrphy_dfi_p2_act_n;
+wire [63:0] k7ddrphy_dfi_p2_wrdata;
+wire k7ddrphy_dfi_p2_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p2_wrdata_mask;
+wire k7ddrphy_dfi_p2_rddata_en;
+reg  [63:0] k7ddrphy_dfi_p2_rddata = 64'd0;
+wire k7ddrphy_dfi_p2_rddata_valid;
+wire [14:0] k7ddrphy_dfi_p3_address;
+wire [2:0] k7ddrphy_dfi_p3_bank;
+wire k7ddrphy_dfi_p3_cas_n;
+wire k7ddrphy_dfi_p3_cs_n;
+wire k7ddrphy_dfi_p3_ras_n;
+wire k7ddrphy_dfi_p3_we_n;
+wire k7ddrphy_dfi_p3_cke;
+wire k7ddrphy_dfi_p3_odt;
+wire k7ddrphy_dfi_p3_reset_n;
+wire k7ddrphy_dfi_p3_act_n;
+wire [63:0] k7ddrphy_dfi_p3_wrdata;
+wire k7ddrphy_dfi_p3_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p3_wrdata_mask;
+wire k7ddrphy_dfi_p3_rddata_en;
+reg  [63:0] k7ddrphy_dfi_p3_rddata = 64'd0;
+wire k7ddrphy_dfi_p3_rddata_valid;
+wire k7ddrphy_sd_clk_se_nodelay;
+wire k7ddrphy_sd_clk_se_delayed;
+wire [2:0] k7ddrphy_pads_ba;
+wire k7ddrphy_oq0;
+wire k7ddrphy_oq1;
+wire k7ddrphy_oq2;
+wire k7ddrphy_oq3;
+wire k7ddrphy_oq4;
+wire k7ddrphy_oq5;
+wire k7ddrphy_oq6;
+wire k7ddrphy_oq7;
+wire k7ddrphy_oq8;
+wire k7ddrphy_oq9;
+wire k7ddrphy_oq10;
+wire k7ddrphy_oq11;
+wire k7ddrphy_oq12;
+wire k7ddrphy_oq13;
+wire k7ddrphy_oq14;
+wire k7ddrphy_oq15;
+wire k7ddrphy_oq16;
+wire k7ddrphy_oq17;
+wire k7ddrphy_oq18;
+wire k7ddrphy_oq19;
+wire k7ddrphy_oq20;
+wire k7ddrphy_oq21;
+wire k7ddrphy_oq22;
+wire k7ddrphy_oq23;
+wire k7ddrphy_oq24;
+reg  k7ddrphy_dqs_oe = 1'd0;
+wire k7ddrphy_dqs_preamble;
+wire k7ddrphy_dqs_postamble;
+wire k7ddrphy_dqs_oe_delay_tappeddelayline;
+reg  k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  k7ddrphy_dqspattern0 = 1'd0;
+reg  k7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] k7ddrphy_dqspattern_o = 8'd0;
+wire k7ddrphy_dqs_o_no_delay0;
+wire k7ddrphy_dqs_o_delayed0;
+wire k7ddrphy_dqs_t0;
+reg  [7:0] k7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip0_r0 = 16'd0;
+wire k7ddrphy0;
+wire k7ddrphy_dqs_o_no_delay1;
+wire k7ddrphy_dqs_o_delayed1;
+wire k7ddrphy_dqs_t1;
+reg  [7:0] k7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip1_r0 = 16'd0;
+wire k7ddrphy1;
+wire k7ddrphy_dqs_o_no_delay2;
+wire k7ddrphy_dqs_o_delayed2;
+wire k7ddrphy_dqs_t2;
+reg  [7:0] k7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip2_r0 = 16'd0;
+wire k7ddrphy2;
+wire k7ddrphy_dqs_o_no_delay3;
+wire k7ddrphy_dqs_o_delayed3;
+wire k7ddrphy_dqs_t3;
+reg  [7:0] k7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip3_r0 = 16'd0;
+wire k7ddrphy3;
+wire k7ddrphy_dm_o_nodelay0;
+reg  [7:0] k7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip0_r1 = 16'd0;
+wire k7ddrphy_dm_o_nodelay1;
+reg  [7:0] k7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip1_r1 = 16'd0;
+wire k7ddrphy_dm_o_nodelay2;
+reg  [7:0] k7ddrphy_bitslip21 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip2_r1 = 16'd0;
+wire k7ddrphy_dm_o_nodelay3;
+reg  [7:0] k7ddrphy_bitslip31 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip3_r1 = 16'd0;
+wire k7ddrphy_dq_oe;
+wire k7ddrphy_dq_oe_delay_tappeddelayline;
+reg  k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire k7ddrphy_dq_o_nodelay0;
+wire k7ddrphy_dq_o_delayed0;
+wire k7ddrphy_dq_i_nodelay0;
+wire k7ddrphy_dq_i_delayed0;
+wire k7ddrphy_dq_t0;
+reg  [7:0] k7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip03;
+reg  [7:0] k7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip0_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay1;
+wire k7ddrphy_dq_o_delayed1;
+wire k7ddrphy_dq_i_nodelay1;
+wire k7ddrphy_dq_i_delayed1;
+wire k7ddrphy_dq_t1;
+reg  [7:0] k7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip13;
+reg  [7:0] k7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip1_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay2;
+wire k7ddrphy_dq_o_delayed2;
+wire k7ddrphy_dq_i_nodelay2;
+wire k7ddrphy_dq_i_delayed2;
+wire k7ddrphy_dq_t2;
+reg  [7:0] k7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip2_value2 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip2_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip23;
+reg  [7:0] k7ddrphy_bitslip24 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip2_value3 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip2_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay3;
+wire k7ddrphy_dq_o_delayed3;
+wire k7ddrphy_dq_i_nodelay3;
+wire k7ddrphy_dq_i_delayed3;
+wire k7ddrphy_dq_t3;
+reg  [7:0] k7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip3_value2 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip3_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip33;
+reg  [7:0] k7ddrphy_bitslip34 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip3_value3 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip3_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay4;
+wire k7ddrphy_dq_o_delayed4;
+wire k7ddrphy_dq_i_nodelay4;
+wire k7ddrphy_dq_i_delayed4;
+wire k7ddrphy_dq_t4;
+reg  [7:0] k7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip41;
+reg  [7:0] k7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip4_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay5;
+wire k7ddrphy_dq_o_delayed5;
+wire k7ddrphy_dq_i_nodelay5;
+wire k7ddrphy_dq_i_delayed5;
+wire k7ddrphy_dq_t5;
+reg  [7:0] k7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip51;
+reg  [7:0] k7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip5_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay6;
+wire k7ddrphy_dq_o_delayed6;
+wire k7ddrphy_dq_i_nodelay6;
+wire k7ddrphy_dq_i_delayed6;
+wire k7ddrphy_dq_t6;
+reg  [7:0] k7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip61;
+reg  [7:0] k7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip6_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay7;
+wire k7ddrphy_dq_o_delayed7;
+wire k7ddrphy_dq_i_nodelay7;
+wire k7ddrphy_dq_i_delayed7;
+wire k7ddrphy_dq_t7;
+reg  [7:0] k7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip71;
+reg  [7:0] k7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip7_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay8;
+wire k7ddrphy_dq_o_delayed8;
+wire k7ddrphy_dq_i_nodelay8;
+wire k7ddrphy_dq_i_delayed8;
+wire k7ddrphy_dq_t8;
+reg  [7:0] k7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip81;
+reg  [7:0] k7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip8_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay9;
+wire k7ddrphy_dq_o_delayed9;
+wire k7ddrphy_dq_i_nodelay9;
+wire k7ddrphy_dq_i_delayed9;
+wire k7ddrphy_dq_t9;
+reg  [7:0] k7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip91;
+reg  [7:0] k7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip9_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay10;
+wire k7ddrphy_dq_o_delayed10;
+wire k7ddrphy_dq_i_nodelay10;
+wire k7ddrphy_dq_i_delayed10;
+wire k7ddrphy_dq_t10;
+reg  [7:0] k7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip101;
+reg  [7:0] k7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip10_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay11;
+wire k7ddrphy_dq_o_delayed11;
+wire k7ddrphy_dq_i_nodelay11;
+wire k7ddrphy_dq_i_delayed11;
+wire k7ddrphy_dq_t11;
+reg  [7:0] k7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip111;
+reg  [7:0] k7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip11_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay12;
+wire k7ddrphy_dq_o_delayed12;
+wire k7ddrphy_dq_i_nodelay12;
+wire k7ddrphy_dq_i_delayed12;
+wire k7ddrphy_dq_t12;
+reg  [7:0] k7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip121;
+reg  [7:0] k7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip12_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay13;
+wire k7ddrphy_dq_o_delayed13;
+wire k7ddrphy_dq_i_nodelay13;
+wire k7ddrphy_dq_i_delayed13;
+wire k7ddrphy_dq_t13;
+reg  [7:0] k7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip131;
+reg  [7:0] k7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip13_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay14;
+wire k7ddrphy_dq_o_delayed14;
+wire k7ddrphy_dq_i_nodelay14;
+wire k7ddrphy_dq_i_delayed14;
+wire k7ddrphy_dq_t14;
+reg  [7:0] k7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip141;
+reg  [7:0] k7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip14_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay15;
+wire k7ddrphy_dq_o_delayed15;
+wire k7ddrphy_dq_i_nodelay15;
+wire k7ddrphy_dq_i_delayed15;
+wire k7ddrphy_dq_t15;
+reg  [7:0] k7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip151;
+reg  [7:0] k7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip15_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay16;
+wire k7ddrphy_dq_o_delayed16;
+wire k7ddrphy_dq_i_nodelay16;
+wire k7ddrphy_dq_i_delayed16;
+wire k7ddrphy_dq_t16;
+reg  [7:0] k7ddrphy_bitslip160 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip16_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip16_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip161;
+reg  [7:0] k7ddrphy_bitslip162 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip16_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip16_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay17;
+wire k7ddrphy_dq_o_delayed17;
+wire k7ddrphy_dq_i_nodelay17;
+wire k7ddrphy_dq_i_delayed17;
+wire k7ddrphy_dq_t17;
+reg  [7:0] k7ddrphy_bitslip170 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip17_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip17_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip171;
+reg  [7:0] k7ddrphy_bitslip172 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip17_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip17_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay18;
+wire k7ddrphy_dq_o_delayed18;
+wire k7ddrphy_dq_i_nodelay18;
+wire k7ddrphy_dq_i_delayed18;
+wire k7ddrphy_dq_t18;
+reg  [7:0] k7ddrphy_bitslip180 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip18_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip18_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip181;
+reg  [7:0] k7ddrphy_bitslip182 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip18_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip18_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay19;
+wire k7ddrphy_dq_o_delayed19;
+wire k7ddrphy_dq_i_nodelay19;
+wire k7ddrphy_dq_i_delayed19;
+wire k7ddrphy_dq_t19;
+reg  [7:0] k7ddrphy_bitslip190 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip19_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip19_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip191;
+reg  [7:0] k7ddrphy_bitslip192 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip19_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip19_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay20;
+wire k7ddrphy_dq_o_delayed20;
+wire k7ddrphy_dq_i_nodelay20;
+wire k7ddrphy_dq_i_delayed20;
+wire k7ddrphy_dq_t20;
+reg  [7:0] k7ddrphy_bitslip200 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip20_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip20_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip201;
+reg  [7:0] k7ddrphy_bitslip202 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip20_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip20_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay21;
+wire k7ddrphy_dq_o_delayed21;
+wire k7ddrphy_dq_i_nodelay21;
+wire k7ddrphy_dq_i_delayed21;
+wire k7ddrphy_dq_t21;
+reg  [7:0] k7ddrphy_bitslip210 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip21_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip21_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip211;
+reg  [7:0] k7ddrphy_bitslip212 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip21_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip21_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay22;
+wire k7ddrphy_dq_o_delayed22;
+wire k7ddrphy_dq_i_nodelay22;
+wire k7ddrphy_dq_i_delayed22;
+wire k7ddrphy_dq_t22;
+reg  [7:0] k7ddrphy_bitslip220 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip22_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip22_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip221;
+reg  [7:0] k7ddrphy_bitslip222 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip22_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip22_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay23;
+wire k7ddrphy_dq_o_delayed23;
+wire k7ddrphy_dq_i_nodelay23;
+wire k7ddrphy_dq_i_delayed23;
+wire k7ddrphy_dq_t23;
+reg  [7:0] k7ddrphy_bitslip230 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip23_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip23_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip231;
+reg  [7:0] k7ddrphy_bitslip232 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip23_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip23_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay24;
+wire k7ddrphy_dq_o_delayed24;
+wire k7ddrphy_dq_i_nodelay24;
+wire k7ddrphy_dq_i_delayed24;
+wire k7ddrphy_dq_t24;
+reg  [7:0] k7ddrphy_bitslip240 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip24_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip24_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip241;
+reg  [7:0] k7ddrphy_bitslip242 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip24_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip24_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay25;
+wire k7ddrphy_dq_o_delayed25;
+wire k7ddrphy_dq_i_nodelay25;
+wire k7ddrphy_dq_i_delayed25;
+wire k7ddrphy_dq_t25;
+reg  [7:0] k7ddrphy_bitslip250 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip25_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip25_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip251;
+reg  [7:0] k7ddrphy_bitslip252 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip25_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip25_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay26;
+wire k7ddrphy_dq_o_delayed26;
+wire k7ddrphy_dq_i_nodelay26;
+wire k7ddrphy_dq_i_delayed26;
+wire k7ddrphy_dq_t26;
+reg  [7:0] k7ddrphy_bitslip260 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip26_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip26_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip261;
+reg  [7:0] k7ddrphy_bitslip262 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip26_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip26_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay27;
+wire k7ddrphy_dq_o_delayed27;
+wire k7ddrphy_dq_i_nodelay27;
+wire k7ddrphy_dq_i_delayed27;
+wire k7ddrphy_dq_t27;
+reg  [7:0] k7ddrphy_bitslip270 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip27_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip27_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip271;
+reg  [7:0] k7ddrphy_bitslip272 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip27_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip27_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay28;
+wire k7ddrphy_dq_o_delayed28;
+wire k7ddrphy_dq_i_nodelay28;
+wire k7ddrphy_dq_i_delayed28;
+wire k7ddrphy_dq_t28;
+reg  [7:0] k7ddrphy_bitslip280 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip28_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip28_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip281;
+reg  [7:0] k7ddrphy_bitslip282 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip28_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip28_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay29;
+wire k7ddrphy_dq_o_delayed29;
+wire k7ddrphy_dq_i_nodelay29;
+wire k7ddrphy_dq_i_delayed29;
+wire k7ddrphy_dq_t29;
+reg  [7:0] k7ddrphy_bitslip290 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip29_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip29_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip291;
+reg  [7:0] k7ddrphy_bitslip292 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip29_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip29_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay30;
+wire k7ddrphy_dq_o_delayed30;
+wire k7ddrphy_dq_i_nodelay30;
+wire k7ddrphy_dq_i_delayed30;
+wire k7ddrphy_dq_t30;
+reg  [7:0] k7ddrphy_bitslip300 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip30_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip30_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip301;
+reg  [7:0] k7ddrphy_bitslip302 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip30_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip30_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay31;
+wire k7ddrphy_dq_o_delayed31;
+wire k7ddrphy_dq_i_nodelay31;
+wire k7ddrphy_dq_i_delayed31;
+wire k7ddrphy_dq_t31;
+reg  [7:0] k7ddrphy_bitslip310 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip31_value0 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip31_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip311;
+reg  [7:0] k7ddrphy_bitslip312 = 8'd0;
+reg  [2:0] k7ddrphy_bitslip31_value1 = 3'd7;
+reg  [15:0] k7ddrphy_bitslip31_r1 = 16'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [14:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [63:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [7:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg  [63:0] litedramcore_slave_p0_rddata = 64'd0;
+reg  litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [63:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [7:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg  [63:0] litedramcore_slave_p1_rddata = 64'd0;
+reg  litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [63:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [7:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg  [63:0] litedramcore_slave_p2_rddata = 64'd0;
+reg  litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [63:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [7:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg  [63:0] litedramcore_slave_p3_rddata = 64'd0;
+reg  litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_master_p0_address = 15'd0;
+reg  [2:0] litedramcore_master_p0_bank = 3'd0;
+reg  litedramcore_master_p0_cas_n = 1'd1;
+reg  litedramcore_master_p0_cs_n = 1'd1;
+reg  litedramcore_master_p0_ras_n = 1'd1;
+reg  litedramcore_master_p0_we_n = 1'd1;
+reg  litedramcore_master_p0_cke = 1'd0;
+reg  litedramcore_master_p0_odt = 1'd0;
+reg  litedramcore_master_p0_reset_n = 1'd0;
+reg  litedramcore_master_p0_act_n = 1'd1;
+reg  [63:0] litedramcore_master_p0_wrdata = 64'd0;
+reg  litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
+reg  litedramcore_master_p0_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg  [14:0] litedramcore_master_p1_address = 15'd0;
+reg  [2:0] litedramcore_master_p1_bank = 3'd0;
+reg  litedramcore_master_p1_cas_n = 1'd1;
+reg  litedramcore_master_p1_cs_n = 1'd1;
+reg  litedramcore_master_p1_ras_n = 1'd1;
+reg  litedramcore_master_p1_we_n = 1'd1;
+reg  litedramcore_master_p1_cke = 1'd0;
+reg  litedramcore_master_p1_odt = 1'd0;
+reg  litedramcore_master_p1_reset_n = 1'd0;
+reg  litedramcore_master_p1_act_n = 1'd1;
+reg  [63:0] litedramcore_master_p1_wrdata = 64'd0;
+reg  litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
+reg  litedramcore_master_p1_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg  [14:0] litedramcore_master_p2_address = 15'd0;
+reg  [2:0] litedramcore_master_p2_bank = 3'd0;
+reg  litedramcore_master_p2_cas_n = 1'd1;
+reg  litedramcore_master_p2_cs_n = 1'd1;
+reg  litedramcore_master_p2_ras_n = 1'd1;
+reg  litedramcore_master_p2_we_n = 1'd1;
+reg  litedramcore_master_p2_cke = 1'd0;
+reg  litedramcore_master_p2_odt = 1'd0;
+reg  litedramcore_master_p2_reset_n = 1'd0;
+reg  litedramcore_master_p2_act_n = 1'd1;
+reg  [63:0] litedramcore_master_p2_wrdata = 64'd0;
+reg  litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_master_p2_wrdata_mask = 8'd0;
+reg  litedramcore_master_p2_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg  [14:0] litedramcore_master_p3_address = 15'd0;
+reg  [2:0] litedramcore_master_p3_bank = 3'd0;
+reg  litedramcore_master_p3_cas_n = 1'd1;
+reg  litedramcore_master_p3_cs_n = 1'd1;
+reg  litedramcore_master_p3_ras_n = 1'd1;
+reg  litedramcore_master_p3_we_n = 1'd1;
+reg  litedramcore_master_p3_cke = 1'd0;
+reg  litedramcore_master_p3_odt = 1'd0;
+reg  litedramcore_master_p3_reset_n = 1'd0;
+reg  litedramcore_master_p3_act_n = 1'd1;
+reg  [63:0] litedramcore_master_p3_wrdata = 64'd0;
+reg  litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_master_p3_wrdata_mask = 8'd0;
+reg  litedramcore_master_p3_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [14:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg  litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg  litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg  [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
+reg  litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg  litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg  litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg  [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
+reg  litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg  litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg  litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg  [63:0] litedramcore_csr_dfi_p2_rddata = 64'd0;
+reg  litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg  litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg  litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg  [63:0] litedramcore_csr_dfi_p3_rddata = 64'd0;
+reg  litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg  litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cke = 1'd0;
+reg  litedramcore_ext_dfi_p0_odt = 1'd0;
+reg  litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg  [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
+reg  litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
+reg  litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg  [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
+reg  litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg  litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cke = 1'd0;
+reg  litedramcore_ext_dfi_p1_odt = 1'd0;
+reg  litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg  [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
+reg  litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
+reg  litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg  [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
+reg  litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg  litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cke = 1'd0;
+reg  litedramcore_ext_dfi_p2_odt = 1'd0;
+reg  litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg  [63:0] litedramcore_ext_dfi_p2_wrdata = 64'd0;
+reg  litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_ext_dfi_p2_wrdata_mask = 8'd0;
+reg  litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg  [63:0] litedramcore_ext_dfi_p2_rddata = 64'd0;
+reg  litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg  litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cke = 1'd0;
+reg  litedramcore_ext_dfi_p3_odt = 1'd0;
+reg  litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg  [63:0] litedramcore_ext_dfi_p3_wrdata = 64'd0;
+reg  litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_ext_dfi_p3_wrdata_mask = 8'd0;
+reg  litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg  [63:0] litedramcore_ext_dfi_p3_rddata = 64'd0;
+reg  litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg  litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg  [3:0] litedramcore_storage = 4'd1;
+reg  litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  litedramcore_phaseinjector0_command_re = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg  litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg  litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
+reg  litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg  litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  litedramcore_phaseinjector1_command_re = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg  litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg  litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
+reg  litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg  litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  litedramcore_phaseinjector2_command_re = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg  litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
+reg  litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector2_wrdata_storage = 64'd0;
+reg  litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector2_rddata_status = 64'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg  litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  litedramcore_phaseinjector3_command_re = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg  litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
+reg  litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector3_wrdata_storage = 64'd0;
+reg  litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [63:0] litedramcore_phaseinjector3_rddata_status = 64'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg  litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [21:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [21:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [21:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [21:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [21:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [21:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [21:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [21:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg  [255:0] litedramcore_interface_wdata = 256'd0;
+reg  [31:0] litedramcore_interface_wdata_we = 32'd0;
+wire [255:0] litedramcore_interface_rdata;
+reg  [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg  litedramcore_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg  litedramcore_dfi_p0_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p0_wrdata;
+reg  litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p0_wrdata_mask;
+reg  litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg  [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg  litedramcore_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg  litedramcore_dfi_p1_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p1_wrdata;
+reg  litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p1_wrdata_mask;
+reg  litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg  [14:0] litedramcore_dfi_p2_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg  litedramcore_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg  litedramcore_dfi_p2_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p2_wrdata;
+reg  litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p2_wrdata_mask;
+reg  litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg  [14:0] litedramcore_dfi_p3_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg  litedramcore_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg  litedramcore_dfi_p3_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p3_wrdata;
+reg  litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p3_wrdata_mask;
+reg  litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg  litedramcore_cmd_valid = 1'd0;
+reg  litedramcore_cmd_ready = 1'd0;
+reg  litedramcore_cmd_last = 1'd0;
+reg  [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg  [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg  litedramcore_cmd_payload_cas = 1'd0;
+reg  litedramcore_cmd_payload_ras = 1'd0;
+reg  litedramcore_cmd_payload_we = 1'd0;
+reg  litedramcore_cmd_payload_is_read = 1'd0;
+reg  litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg  [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg  litedramcore_postponer_req_o = 1'd0;
+reg  litedramcore_postponer_count = 1'd0;
+reg  litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg  litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] litedramcore_sequencer_counter = 6'd0;
+reg  litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg  [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  litedramcore_zqcs_executer_start = 1'd0;
+reg  litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [21:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg  litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg  litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg  litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg  [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine0_row = 15'd0;
+reg  litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg  litedramcore_bankmachine0_row_open = 1'd0;
+reg  litedramcore_bankmachine0_row_close = 1'd0;
+reg  litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [21:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg  litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg  litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg  litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg  [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine1_row = 15'd0;
+reg  litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg  litedramcore_bankmachine1_row_open = 1'd0;
+reg  litedramcore_bankmachine1_row_close = 1'd0;
+reg  litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [21:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg  litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg  litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg  litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg  [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine2_row = 15'd0;
+reg  litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg  litedramcore_bankmachine2_row_open = 1'd0;
+reg  litedramcore_bankmachine2_row_close = 1'd0;
+reg  litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [21:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg  litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg  litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg  litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg  [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine3_row = 15'd0;
+reg  litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg  litedramcore_bankmachine3_row_open = 1'd0;
+reg  litedramcore_bankmachine3_row_close = 1'd0;
+reg  litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [21:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg  litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg  litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg  litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg  [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine4_row = 15'd0;
+reg  litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg  litedramcore_bankmachine4_row_open = 1'd0;
+reg  litedramcore_bankmachine4_row_close = 1'd0;
+reg  litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [21:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg  litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg  litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg  litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg  [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine5_row = 15'd0;
+reg  litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg  litedramcore_bankmachine5_row_open = 1'd0;
+reg  litedramcore_bankmachine5_row_close = 1'd0;
+reg  litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [21:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg  litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg  litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg  litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg  [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine6_row = 15'd0;
+reg  litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg  litedramcore_bankmachine6_row_open = 1'd0;
+reg  litedramcore_bankmachine6_row_close = 1'd0;
+reg  litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [21:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg  litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg  litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg  litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg  [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine7_row = 15'd0;
+reg  litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg  litedramcore_bankmachine7_row_open = 1'd0;
+reg  litedramcore_bankmachine7_row_close = 1'd0;
+reg  litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg  litedramcore_choose_cmd_want_reads = 1'd0;
+reg  litedramcore_choose_cmd_want_writes = 1'd0;
+reg  litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg  litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg  litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg  [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg  litedramcore_choose_req_want_reads = 1'd0;
+reg  litedramcore_choose_req_want_writes = 1'd0;
+reg  litedramcore_choose_req_want_cmds = 1'd0;
+reg  litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg  litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg  litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg  [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg  [14:0] litedramcore_nop_a = 15'd0;
+reg  [2:0] litedramcore_nop_ba = 3'd0;
+reg  [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg  litedramcore_steerer0 = 1'd1;
+reg  litedramcore_steerer1 = 1'd1;
+reg  litedramcore_steerer2 = 1'd1;
+reg  litedramcore_steerer3 = 1'd1;
+reg  litedramcore_steerer4 = 1'd1;
+reg  litedramcore_steerer5 = 1'd1;
+reg  litedramcore_steerer6 = 1'd1;
+reg  litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_trrdcon_ready = 1'd0;
+reg  litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg  [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tccdcon_ready = 1'd0;
+reg  litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg  litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg  [4:0] litedramcore_time0 = 5'd0;
+reg  litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg  [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg  init_done_storage = 1'd0;
+reg  init_done_re = 1'd0;
+reg  init_error_storage = 1'd0;
+reg  init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [24:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [255:0] user_port_wdata_payload_data;
+wire [31:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [255:0] user_port_rdata_payload_data;
+reg  [13:0] litedramcore_adr = 14'd0;
+reg  litedramcore_we = 1'd0;
+reg  [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg  [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg  litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg  litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg  [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg  csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg  csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg  csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg  csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg  [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg  csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg  csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg  csrbank1_dly_sel0_re = 1'd0;
+wire [3:0] csrbank1_dly_sel0_r;
+reg  csrbank1_dly_sel0_we = 1'd0;
+wire [3:0] csrbank1_dly_sel0_w;
+reg  csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg  csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg  csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg  csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg  csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg  csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg  csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg  csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg  [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg  csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg  csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg  csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg  csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg  csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_r;
+reg  csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_w;
+reg  csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg  csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg  csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_r;
+reg  csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_w;
+reg  csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg  csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg  csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_r;
+reg  csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_w;
+reg  csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_r;
+reg  csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_w;
+reg  csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg  csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg  csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_r;
+reg  csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_w;
+reg  csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg  csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg  csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_r;
+reg  csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_w;
+reg  csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg  csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg  csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_r;
+reg  csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_w;
+reg  csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_r;
+reg  csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_w;
+reg  csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg  csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg  csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_r;
+reg  csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_w;
+reg  csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg  csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg  csrbank2_dfii_pi2_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata1_r;
+reg  csrbank2_dfii_pi2_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata1_w;
+reg  csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg  csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg  csrbank2_dfii_pi2_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata1_r;
+reg  csrbank2_dfii_pi2_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata1_w;
+reg  csrbank2_dfii_pi2_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata0_r;
+reg  csrbank2_dfii_pi2_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata0_w;
+reg  csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg  csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg  csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_r;
+reg  csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_w;
+reg  csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg  csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg  csrbank2_dfii_pi3_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata1_r;
+reg  csrbank2_dfii_pi3_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata1_w;
+reg  csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg  csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg  csrbank2_dfii_pi3_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata1_r;
+reg  csrbank2_dfii_pi3_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata1_w;
+reg  csrbank2_dfii_pi3_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata0_r;
+reg  csrbank2_dfii_pi3_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata0_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg  [1:0] litedramcore_refresher_state = 2'd0;
+reg  [1:0] litedramcore_refresher_next_state = 2'd0;
+reg  [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg  litedramcore_locked0 = 1'd0;
+reg  litedramcore_locked1 = 1'd0;
+reg  litedramcore_locked2 = 1'd0;
+reg  litedramcore_locked3 = 1'd0;
+reg  litedramcore_locked4 = 1'd0;
+reg  litedramcore_locked5 = 1'd0;
+reg  litedramcore_locked6 = 1'd0;
+reg  litedramcore_locked7 = 1'd0;
+reg  litedramcore_new_master_wdata_ready0 = 1'd0;
+reg  litedramcore_new_master_wdata_ready1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid0 = 1'd0;
+reg  litedramcore_new_master_rdata_valid1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid2 = 1'd0;
+reg  litedramcore_new_master_rdata_valid3 = 1'd0;
+reg  litedramcore_new_master_rdata_valid4 = 1'd0;
+reg  litedramcore_new_master_rdata_valid5 = 1'd0;
+reg  litedramcore_new_master_rdata_valid6 = 1'd0;
+reg  litedramcore_new_master_rdata_valid7 = 1'd0;
+reg  litedramcore_new_master_rdata_valid8 = 1'd0;
+reg  [1:0] litedramcore_state = 2'd0;
+reg  [1:0] litedramcore_next_state = 2'd0;
+reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg  litedramcore_adr_next_value_ce1 = 1'd0;
+reg  litedramcore_we_next_value2 = 1'd0;
+reg  litedramcore_we_next_value_ce2 = 1'd0;
+reg  rhs_array_muxed0 = 1'd0;
+reg  [14:0] rhs_array_muxed1 = 15'd0;
+reg  [2:0] rhs_array_muxed2 = 3'd0;
+reg  rhs_array_muxed3 = 1'd0;
+reg  rhs_array_muxed4 = 1'd0;
+reg  rhs_array_muxed5 = 1'd0;
+reg  t_array_muxed0 = 1'd0;
+reg  t_array_muxed1 = 1'd0;
+reg  t_array_muxed2 = 1'd0;
+reg  rhs_array_muxed6 = 1'd0;
+reg  [14:0] rhs_array_muxed7 = 15'd0;
+reg  [2:0] rhs_array_muxed8 = 3'd0;
+reg  rhs_array_muxed9 = 1'd0;
+reg  rhs_array_muxed10 = 1'd0;
+reg  rhs_array_muxed11 = 1'd0;
+reg  t_array_muxed3 = 1'd0;
+reg  t_array_muxed4 = 1'd0;
+reg  t_array_muxed5 = 1'd0;
+reg  [21:0] rhs_array_muxed12 = 22'd0;
+reg  rhs_array_muxed13 = 1'd0;
+reg  rhs_array_muxed14 = 1'd0;
+reg  [21:0] rhs_array_muxed15 = 22'd0;
+reg  rhs_array_muxed16 = 1'd0;
+reg  rhs_array_muxed17 = 1'd0;
+reg  [21:0] rhs_array_muxed18 = 22'd0;
+reg  rhs_array_muxed19 = 1'd0;
+reg  rhs_array_muxed20 = 1'd0;
+reg  [21:0] rhs_array_muxed21 = 22'd0;
+reg  rhs_array_muxed22 = 1'd0;
+reg  rhs_array_muxed23 = 1'd0;
+reg  [21:0] rhs_array_muxed24 = 22'd0;
+reg  rhs_array_muxed25 = 1'd0;
+reg  rhs_array_muxed26 = 1'd0;
+reg  [21:0] rhs_array_muxed27 = 22'd0;
+reg  rhs_array_muxed28 = 1'd0;
+reg  rhs_array_muxed29 = 1'd0;
+reg  [21:0] rhs_array_muxed30 = 22'd0;
+reg  rhs_array_muxed31 = 1'd0;
+reg  rhs_array_muxed32 = 1'd0;
+reg  [21:0] rhs_array_muxed33 = 22'd0;
+reg  rhs_array_muxed34 = 1'd0;
+reg  rhs_array_muxed35 = 1'd0;
+reg  [2:0] array_muxed0 = 3'd0;
+reg  [14:0] array_muxed1 = 15'd0;
+reg  array_muxed2 = 1'd0;
+reg  array_muxed3 = 1'd0;
+reg  array_muxed4 = 1'd0;
+reg  array_muxed5 = 1'd0;
+reg  array_muxed6 = 1'd0;
+reg  [2:0] array_muxed7 = 3'd0;
+reg  [14:0] array_muxed8 = 15'd0;
+reg  array_muxed9 = 1'd0;
+reg  array_muxed10 = 1'd0;
+reg  array_muxed11 = 1'd0;
+reg  array_muxed12 = 1'd0;
+reg  array_muxed13 = 1'd0;
+reg  [2:0] array_muxed14 = 3'd0;
+reg  [14:0] array_muxed15 = 15'd0;
+reg  array_muxed16 = 1'd0;
+reg  array_muxed17 = 1'd0;
+reg  array_muxed18 = 1'd0;
+reg  array_muxed19 = 1'd0;
+reg  array_muxed20 = 1'd0;
+reg  [2:0] array_muxed21 = 3'd0;
+reg  [14:0] array_muxed22 = 15'd0;
+reg  array_muxed23 = 1'd0;
+reg  array_muxed24 = 1'd0;
+reg  array_muxed25 = 1'd0;
+reg  array_muxed26 = 1'd0;
+reg  array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = main_init_done_storage;
-assign init_error = main_init_error_storage;
-assign main_wb_bus_adr = wb_ctrl_adr;
-assign main_wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = main_wb_bus_dat_r;
-assign main_wb_bus_sel = wb_ctrl_sel;
-assign main_wb_bus_cyc = wb_ctrl_cyc;
-assign main_wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = main_wb_bus_ack;
-assign main_wb_bus_we = wb_ctrl_we;
-assign main_wb_bus_cti = wb_ctrl_cti;
-assign main_wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = main_wb_bus_err;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_enable = 1'd1;
-assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
-assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
-assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
-assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
-assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
-assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
-assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = (rst | main_rst);
-assign pll_locked = main_locked;
-assign main_clkin = clk;
-assign iodelay_clk = main_clkout_buf0;
-assign sys_clk = main_clkout_buf1;
-assign sys4x_clk = main_clkout_buf2;
-assign sys4x_dqs_clk = main_clkout_buf3;
-assign main_k7ddrphy_dqs_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dqs_oe) | main_k7ddrphy_dqs_postamble);
-assign main_k7ddrphy_dq_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dq_oe) | main_k7ddrphy_dqs_postamble);
-always @(*) begin
-	main_k7ddrphy_dfi_p0_rddata <= 64'd0;
-	main_k7ddrphy_dfi_p0_rddata[0] <= main_k7ddrphy_bitslip04[0];
-	main_k7ddrphy_dfi_p0_rddata[32] <= main_k7ddrphy_bitslip04[1];
-	main_k7ddrphy_dfi_p0_rddata[1] <= main_k7ddrphy_bitslip14[0];
-	main_k7ddrphy_dfi_p0_rddata[33] <= main_k7ddrphy_bitslip14[1];
-	main_k7ddrphy_dfi_p0_rddata[2] <= main_k7ddrphy_bitslip24[0];
-	main_k7ddrphy_dfi_p0_rddata[34] <= main_k7ddrphy_bitslip24[1];
-	main_k7ddrphy_dfi_p0_rddata[3] <= main_k7ddrphy_bitslip34[0];
-	main_k7ddrphy_dfi_p0_rddata[35] <= main_k7ddrphy_bitslip34[1];
-	main_k7ddrphy_dfi_p0_rddata[4] <= main_k7ddrphy_bitslip42[0];
-	main_k7ddrphy_dfi_p0_rddata[36] <= main_k7ddrphy_bitslip42[1];
-	main_k7ddrphy_dfi_p0_rddata[5] <= main_k7ddrphy_bitslip52[0];
-	main_k7ddrphy_dfi_p0_rddata[37] <= main_k7ddrphy_bitslip52[1];
-	main_k7ddrphy_dfi_p0_rddata[6] <= main_k7ddrphy_bitslip62[0];
-	main_k7ddrphy_dfi_p0_rddata[38] <= main_k7ddrphy_bitslip62[1];
-	main_k7ddrphy_dfi_p0_rddata[7] <= main_k7ddrphy_bitslip72[0];
-	main_k7ddrphy_dfi_p0_rddata[39] <= main_k7ddrphy_bitslip72[1];
-	main_k7ddrphy_dfi_p0_rddata[8] <= main_k7ddrphy_bitslip82[0];
-	main_k7ddrphy_dfi_p0_rddata[40] <= main_k7ddrphy_bitslip82[1];
-	main_k7ddrphy_dfi_p0_rddata[9] <= main_k7ddrphy_bitslip92[0];
-	main_k7ddrphy_dfi_p0_rddata[41] <= main_k7ddrphy_bitslip92[1];
-	main_k7ddrphy_dfi_p0_rddata[10] <= main_k7ddrphy_bitslip102[0];
-	main_k7ddrphy_dfi_p0_rddata[42] <= main_k7ddrphy_bitslip102[1];
-	main_k7ddrphy_dfi_p0_rddata[11] <= main_k7ddrphy_bitslip112[0];
-	main_k7ddrphy_dfi_p0_rddata[43] <= main_k7ddrphy_bitslip112[1];
-	main_k7ddrphy_dfi_p0_rddata[12] <= main_k7ddrphy_bitslip122[0];
-	main_k7ddrphy_dfi_p0_rddata[44] <= main_k7ddrphy_bitslip122[1];
-	main_k7ddrphy_dfi_p0_rddata[13] <= main_k7ddrphy_bitslip132[0];
-	main_k7ddrphy_dfi_p0_rddata[45] <= main_k7ddrphy_bitslip132[1];
-	main_k7ddrphy_dfi_p0_rddata[14] <= main_k7ddrphy_bitslip142[0];
-	main_k7ddrphy_dfi_p0_rddata[46] <= main_k7ddrphy_bitslip142[1];
-	main_k7ddrphy_dfi_p0_rddata[15] <= main_k7ddrphy_bitslip152[0];
-	main_k7ddrphy_dfi_p0_rddata[47] <= main_k7ddrphy_bitslip152[1];
-	main_k7ddrphy_dfi_p0_rddata[16] <= main_k7ddrphy_bitslip162[0];
-	main_k7ddrphy_dfi_p0_rddata[48] <= main_k7ddrphy_bitslip162[1];
-	main_k7ddrphy_dfi_p0_rddata[17] <= main_k7ddrphy_bitslip172[0];
-	main_k7ddrphy_dfi_p0_rddata[49] <= main_k7ddrphy_bitslip172[1];
-	main_k7ddrphy_dfi_p0_rddata[18] <= main_k7ddrphy_bitslip182[0];
-	main_k7ddrphy_dfi_p0_rddata[50] <= main_k7ddrphy_bitslip182[1];
-	main_k7ddrphy_dfi_p0_rddata[19] <= main_k7ddrphy_bitslip192[0];
-	main_k7ddrphy_dfi_p0_rddata[51] <= main_k7ddrphy_bitslip192[1];
-	main_k7ddrphy_dfi_p0_rddata[20] <= main_k7ddrphy_bitslip202[0];
-	main_k7ddrphy_dfi_p0_rddata[52] <= main_k7ddrphy_bitslip202[1];
-	main_k7ddrphy_dfi_p0_rddata[21] <= main_k7ddrphy_bitslip212[0];
-	main_k7ddrphy_dfi_p0_rddata[53] <= main_k7ddrphy_bitslip212[1];
-	main_k7ddrphy_dfi_p0_rddata[22] <= main_k7ddrphy_bitslip222[0];
-	main_k7ddrphy_dfi_p0_rddata[54] <= main_k7ddrphy_bitslip222[1];
-	main_k7ddrphy_dfi_p0_rddata[23] <= main_k7ddrphy_bitslip232[0];
-	main_k7ddrphy_dfi_p0_rddata[55] <= main_k7ddrphy_bitslip232[1];
-	main_k7ddrphy_dfi_p0_rddata[24] <= main_k7ddrphy_bitslip242[0];
-	main_k7ddrphy_dfi_p0_rddata[56] <= main_k7ddrphy_bitslip242[1];
-	main_k7ddrphy_dfi_p0_rddata[25] <= main_k7ddrphy_bitslip252[0];
-	main_k7ddrphy_dfi_p0_rddata[57] <= main_k7ddrphy_bitslip252[1];
-	main_k7ddrphy_dfi_p0_rddata[26] <= main_k7ddrphy_bitslip262[0];
-	main_k7ddrphy_dfi_p0_rddata[58] <= main_k7ddrphy_bitslip262[1];
-	main_k7ddrphy_dfi_p0_rddata[27] <= main_k7ddrphy_bitslip272[0];
-	main_k7ddrphy_dfi_p0_rddata[59] <= main_k7ddrphy_bitslip272[1];
-	main_k7ddrphy_dfi_p0_rddata[28] <= main_k7ddrphy_bitslip282[0];
-	main_k7ddrphy_dfi_p0_rddata[60] <= main_k7ddrphy_bitslip282[1];
-	main_k7ddrphy_dfi_p0_rddata[29] <= main_k7ddrphy_bitslip292[0];
-	main_k7ddrphy_dfi_p0_rddata[61] <= main_k7ddrphy_bitslip292[1];
-	main_k7ddrphy_dfi_p0_rddata[30] <= main_k7ddrphy_bitslip302[0];
-	main_k7ddrphy_dfi_p0_rddata[62] <= main_k7ddrphy_bitslip302[1];
-	main_k7ddrphy_dfi_p0_rddata[31] <= main_k7ddrphy_bitslip312[0];
-	main_k7ddrphy_dfi_p0_rddata[63] <= main_k7ddrphy_bitslip312[1];
-end
-always @(*) begin
-	main_k7ddrphy_dfi_p1_rddata <= 64'd0;
-	main_k7ddrphy_dfi_p1_rddata[0] <= main_k7ddrphy_bitslip04[2];
-	main_k7ddrphy_dfi_p1_rddata[32] <= main_k7ddrphy_bitslip04[3];
-	main_k7ddrphy_dfi_p1_rddata[1] <= main_k7ddrphy_bitslip14[2];
-	main_k7ddrphy_dfi_p1_rddata[33] <= main_k7ddrphy_bitslip14[3];
-	main_k7ddrphy_dfi_p1_rddata[2] <= main_k7ddrphy_bitslip24[2];
-	main_k7ddrphy_dfi_p1_rddata[34] <= main_k7ddrphy_bitslip24[3];
-	main_k7ddrphy_dfi_p1_rddata[3] <= main_k7ddrphy_bitslip34[2];
-	main_k7ddrphy_dfi_p1_rddata[35] <= main_k7ddrphy_bitslip34[3];
-	main_k7ddrphy_dfi_p1_rddata[4] <= main_k7ddrphy_bitslip42[2];
-	main_k7ddrphy_dfi_p1_rddata[36] <= main_k7ddrphy_bitslip42[3];
-	main_k7ddrphy_dfi_p1_rddata[5] <= main_k7ddrphy_bitslip52[2];
-	main_k7ddrphy_dfi_p1_rddata[37] <= main_k7ddrphy_bitslip52[3];
-	main_k7ddrphy_dfi_p1_rddata[6] <= main_k7ddrphy_bitslip62[2];
-	main_k7ddrphy_dfi_p1_rddata[38] <= main_k7ddrphy_bitslip62[3];
-	main_k7ddrphy_dfi_p1_rddata[7] <= main_k7ddrphy_bitslip72[2];
-	main_k7ddrphy_dfi_p1_rddata[39] <= main_k7ddrphy_bitslip72[3];
-	main_k7ddrphy_dfi_p1_rddata[8] <= main_k7ddrphy_bitslip82[2];
-	main_k7ddrphy_dfi_p1_rddata[40] <= main_k7ddrphy_bitslip82[3];
-	main_k7ddrphy_dfi_p1_rddata[9] <= main_k7ddrphy_bitslip92[2];
-	main_k7ddrphy_dfi_p1_rddata[41] <= main_k7ddrphy_bitslip92[3];
-	main_k7ddrphy_dfi_p1_rddata[10] <= main_k7ddrphy_bitslip102[2];
-	main_k7ddrphy_dfi_p1_rddata[42] <= main_k7ddrphy_bitslip102[3];
-	main_k7ddrphy_dfi_p1_rddata[11] <= main_k7ddrphy_bitslip112[2];
-	main_k7ddrphy_dfi_p1_rddata[43] <= main_k7ddrphy_bitslip112[3];
-	main_k7ddrphy_dfi_p1_rddata[12] <= main_k7ddrphy_bitslip122[2];
-	main_k7ddrphy_dfi_p1_rddata[44] <= main_k7ddrphy_bitslip122[3];
-	main_k7ddrphy_dfi_p1_rddata[13] <= main_k7ddrphy_bitslip132[2];
-	main_k7ddrphy_dfi_p1_rddata[45] <= main_k7ddrphy_bitslip132[3];
-	main_k7ddrphy_dfi_p1_rddata[14] <= main_k7ddrphy_bitslip142[2];
-	main_k7ddrphy_dfi_p1_rddata[46] <= main_k7ddrphy_bitslip142[3];
-	main_k7ddrphy_dfi_p1_rddata[15] <= main_k7ddrphy_bitslip152[2];
-	main_k7ddrphy_dfi_p1_rddata[47] <= main_k7ddrphy_bitslip152[3];
-	main_k7ddrphy_dfi_p1_rddata[16] <= main_k7ddrphy_bitslip162[2];
-	main_k7ddrphy_dfi_p1_rddata[48] <= main_k7ddrphy_bitslip162[3];
-	main_k7ddrphy_dfi_p1_rddata[17] <= main_k7ddrphy_bitslip172[2];
-	main_k7ddrphy_dfi_p1_rddata[49] <= main_k7ddrphy_bitslip172[3];
-	main_k7ddrphy_dfi_p1_rddata[18] <= main_k7ddrphy_bitslip182[2];
-	main_k7ddrphy_dfi_p1_rddata[50] <= main_k7ddrphy_bitslip182[3];
-	main_k7ddrphy_dfi_p1_rddata[19] <= main_k7ddrphy_bitslip192[2];
-	main_k7ddrphy_dfi_p1_rddata[51] <= main_k7ddrphy_bitslip192[3];
-	main_k7ddrphy_dfi_p1_rddata[20] <= main_k7ddrphy_bitslip202[2];
-	main_k7ddrphy_dfi_p1_rddata[52] <= main_k7ddrphy_bitslip202[3];
-	main_k7ddrphy_dfi_p1_rddata[21] <= main_k7ddrphy_bitslip212[2];
-	main_k7ddrphy_dfi_p1_rddata[53] <= main_k7ddrphy_bitslip212[3];
-	main_k7ddrphy_dfi_p1_rddata[22] <= main_k7ddrphy_bitslip222[2];
-	main_k7ddrphy_dfi_p1_rddata[54] <= main_k7ddrphy_bitslip222[3];
-	main_k7ddrphy_dfi_p1_rddata[23] <= main_k7ddrphy_bitslip232[2];
-	main_k7ddrphy_dfi_p1_rddata[55] <= main_k7ddrphy_bitslip232[3];
-	main_k7ddrphy_dfi_p1_rddata[24] <= main_k7ddrphy_bitslip242[2];
-	main_k7ddrphy_dfi_p1_rddata[56] <= main_k7ddrphy_bitslip242[3];
-	main_k7ddrphy_dfi_p1_rddata[25] <= main_k7ddrphy_bitslip252[2];
-	main_k7ddrphy_dfi_p1_rddata[57] <= main_k7ddrphy_bitslip252[3];
-	main_k7ddrphy_dfi_p1_rddata[26] <= main_k7ddrphy_bitslip262[2];
-	main_k7ddrphy_dfi_p1_rddata[58] <= main_k7ddrphy_bitslip262[3];
-	main_k7ddrphy_dfi_p1_rddata[27] <= main_k7ddrphy_bitslip272[2];
-	main_k7ddrphy_dfi_p1_rddata[59] <= main_k7ddrphy_bitslip272[3];
-	main_k7ddrphy_dfi_p1_rddata[28] <= main_k7ddrphy_bitslip282[2];
-	main_k7ddrphy_dfi_p1_rddata[60] <= main_k7ddrphy_bitslip282[3];
-	main_k7ddrphy_dfi_p1_rddata[29] <= main_k7ddrphy_bitslip292[2];
-	main_k7ddrphy_dfi_p1_rddata[61] <= main_k7ddrphy_bitslip292[3];
-	main_k7ddrphy_dfi_p1_rddata[30] <= main_k7ddrphy_bitslip302[2];
-	main_k7ddrphy_dfi_p1_rddata[62] <= main_k7ddrphy_bitslip302[3];
-	main_k7ddrphy_dfi_p1_rddata[31] <= main_k7ddrphy_bitslip312[2];
-	main_k7ddrphy_dfi_p1_rddata[63] <= main_k7ddrphy_bitslip312[3];
-end
-always @(*) begin
-	main_k7ddrphy_dfi_p2_rddata <= 64'd0;
-	main_k7ddrphy_dfi_p2_rddata[0] <= main_k7ddrphy_bitslip04[4];
-	main_k7ddrphy_dfi_p2_rddata[32] <= main_k7ddrphy_bitslip04[5];
-	main_k7ddrphy_dfi_p2_rddata[1] <= main_k7ddrphy_bitslip14[4];
-	main_k7ddrphy_dfi_p2_rddata[33] <= main_k7ddrphy_bitslip14[5];
-	main_k7ddrphy_dfi_p2_rddata[2] <= main_k7ddrphy_bitslip24[4];
-	main_k7ddrphy_dfi_p2_rddata[34] <= main_k7ddrphy_bitslip24[5];
-	main_k7ddrphy_dfi_p2_rddata[3] <= main_k7ddrphy_bitslip34[4];
-	main_k7ddrphy_dfi_p2_rddata[35] <= main_k7ddrphy_bitslip34[5];
-	main_k7ddrphy_dfi_p2_rddata[4] <= main_k7ddrphy_bitslip42[4];
-	main_k7ddrphy_dfi_p2_rddata[36] <= main_k7ddrphy_bitslip42[5];
-	main_k7ddrphy_dfi_p2_rddata[5] <= main_k7ddrphy_bitslip52[4];
-	main_k7ddrphy_dfi_p2_rddata[37] <= main_k7ddrphy_bitslip52[5];
-	main_k7ddrphy_dfi_p2_rddata[6] <= main_k7ddrphy_bitslip62[4];
-	main_k7ddrphy_dfi_p2_rddata[38] <= main_k7ddrphy_bitslip62[5];
-	main_k7ddrphy_dfi_p2_rddata[7] <= main_k7ddrphy_bitslip72[4];
-	main_k7ddrphy_dfi_p2_rddata[39] <= main_k7ddrphy_bitslip72[5];
-	main_k7ddrphy_dfi_p2_rddata[8] <= main_k7ddrphy_bitslip82[4];
-	main_k7ddrphy_dfi_p2_rddata[40] <= main_k7ddrphy_bitslip82[5];
-	main_k7ddrphy_dfi_p2_rddata[9] <= main_k7ddrphy_bitslip92[4];
-	main_k7ddrphy_dfi_p2_rddata[41] <= main_k7ddrphy_bitslip92[5];
-	main_k7ddrphy_dfi_p2_rddata[10] <= main_k7ddrphy_bitslip102[4];
-	main_k7ddrphy_dfi_p2_rddata[42] <= main_k7ddrphy_bitslip102[5];
-	main_k7ddrphy_dfi_p2_rddata[11] <= main_k7ddrphy_bitslip112[4];
-	main_k7ddrphy_dfi_p2_rddata[43] <= main_k7ddrphy_bitslip112[5];
-	main_k7ddrphy_dfi_p2_rddata[12] <= main_k7ddrphy_bitslip122[4];
-	main_k7ddrphy_dfi_p2_rddata[44] <= main_k7ddrphy_bitslip122[5];
-	main_k7ddrphy_dfi_p2_rddata[13] <= main_k7ddrphy_bitslip132[4];
-	main_k7ddrphy_dfi_p2_rddata[45] <= main_k7ddrphy_bitslip132[5];
-	main_k7ddrphy_dfi_p2_rddata[14] <= main_k7ddrphy_bitslip142[4];
-	main_k7ddrphy_dfi_p2_rddata[46] <= main_k7ddrphy_bitslip142[5];
-	main_k7ddrphy_dfi_p2_rddata[15] <= main_k7ddrphy_bitslip152[4];
-	main_k7ddrphy_dfi_p2_rddata[47] <= main_k7ddrphy_bitslip152[5];
-	main_k7ddrphy_dfi_p2_rddata[16] <= main_k7ddrphy_bitslip162[4];
-	main_k7ddrphy_dfi_p2_rddata[48] <= main_k7ddrphy_bitslip162[5];
-	main_k7ddrphy_dfi_p2_rddata[17] <= main_k7ddrphy_bitslip172[4];
-	main_k7ddrphy_dfi_p2_rddata[49] <= main_k7ddrphy_bitslip172[5];
-	main_k7ddrphy_dfi_p2_rddata[18] <= main_k7ddrphy_bitslip182[4];
-	main_k7ddrphy_dfi_p2_rddata[50] <= main_k7ddrphy_bitslip182[5];
-	main_k7ddrphy_dfi_p2_rddata[19] <= main_k7ddrphy_bitslip192[4];
-	main_k7ddrphy_dfi_p2_rddata[51] <= main_k7ddrphy_bitslip192[5];
-	main_k7ddrphy_dfi_p2_rddata[20] <= main_k7ddrphy_bitslip202[4];
-	main_k7ddrphy_dfi_p2_rddata[52] <= main_k7ddrphy_bitslip202[5];
-	main_k7ddrphy_dfi_p2_rddata[21] <= main_k7ddrphy_bitslip212[4];
-	main_k7ddrphy_dfi_p2_rddata[53] <= main_k7ddrphy_bitslip212[5];
-	main_k7ddrphy_dfi_p2_rddata[22] <= main_k7ddrphy_bitslip222[4];
-	main_k7ddrphy_dfi_p2_rddata[54] <= main_k7ddrphy_bitslip222[5];
-	main_k7ddrphy_dfi_p2_rddata[23] <= main_k7ddrphy_bitslip232[4];
-	main_k7ddrphy_dfi_p2_rddata[55] <= main_k7ddrphy_bitslip232[5];
-	main_k7ddrphy_dfi_p2_rddata[24] <= main_k7ddrphy_bitslip242[4];
-	main_k7ddrphy_dfi_p2_rddata[56] <= main_k7ddrphy_bitslip242[5];
-	main_k7ddrphy_dfi_p2_rddata[25] <= main_k7ddrphy_bitslip252[4];
-	main_k7ddrphy_dfi_p2_rddata[57] <= main_k7ddrphy_bitslip252[5];
-	main_k7ddrphy_dfi_p2_rddata[26] <= main_k7ddrphy_bitslip262[4];
-	main_k7ddrphy_dfi_p2_rddata[58] <= main_k7ddrphy_bitslip262[5];
-	main_k7ddrphy_dfi_p2_rddata[27] <= main_k7ddrphy_bitslip272[4];
-	main_k7ddrphy_dfi_p2_rddata[59] <= main_k7ddrphy_bitslip272[5];
-	main_k7ddrphy_dfi_p2_rddata[28] <= main_k7ddrphy_bitslip282[4];
-	main_k7ddrphy_dfi_p2_rddata[60] <= main_k7ddrphy_bitslip282[5];
-	main_k7ddrphy_dfi_p2_rddata[29] <= main_k7ddrphy_bitslip292[4];
-	main_k7ddrphy_dfi_p2_rddata[61] <= main_k7ddrphy_bitslip292[5];
-	main_k7ddrphy_dfi_p2_rddata[30] <= main_k7ddrphy_bitslip302[4];
-	main_k7ddrphy_dfi_p2_rddata[62] <= main_k7ddrphy_bitslip302[5];
-	main_k7ddrphy_dfi_p2_rddata[31] <= main_k7ddrphy_bitslip312[4];
-	main_k7ddrphy_dfi_p2_rddata[63] <= main_k7ddrphy_bitslip312[5];
-end
-always @(*) begin
-	main_k7ddrphy_dfi_p3_rddata <= 64'd0;
-	main_k7ddrphy_dfi_p3_rddata[0] <= main_k7ddrphy_bitslip04[6];
-	main_k7ddrphy_dfi_p3_rddata[32] <= main_k7ddrphy_bitslip04[7];
-	main_k7ddrphy_dfi_p3_rddata[1] <= main_k7ddrphy_bitslip14[6];
-	main_k7ddrphy_dfi_p3_rddata[33] <= main_k7ddrphy_bitslip14[7];
-	main_k7ddrphy_dfi_p3_rddata[2] <= main_k7ddrphy_bitslip24[6];
-	main_k7ddrphy_dfi_p3_rddata[34] <= main_k7ddrphy_bitslip24[7];
-	main_k7ddrphy_dfi_p3_rddata[3] <= main_k7ddrphy_bitslip34[6];
-	main_k7ddrphy_dfi_p3_rddata[35] <= main_k7ddrphy_bitslip34[7];
-	main_k7ddrphy_dfi_p3_rddata[4] <= main_k7ddrphy_bitslip42[6];
-	main_k7ddrphy_dfi_p3_rddata[36] <= main_k7ddrphy_bitslip42[7];
-	main_k7ddrphy_dfi_p3_rddata[5] <= main_k7ddrphy_bitslip52[6];
-	main_k7ddrphy_dfi_p3_rddata[37] <= main_k7ddrphy_bitslip52[7];
-	main_k7ddrphy_dfi_p3_rddata[6] <= main_k7ddrphy_bitslip62[6];
-	main_k7ddrphy_dfi_p3_rddata[38] <= main_k7ddrphy_bitslip62[7];
-	main_k7ddrphy_dfi_p3_rddata[7] <= main_k7ddrphy_bitslip72[6];
-	main_k7ddrphy_dfi_p3_rddata[39] <= main_k7ddrphy_bitslip72[7];
-	main_k7ddrphy_dfi_p3_rddata[8] <= main_k7ddrphy_bitslip82[6];
-	main_k7ddrphy_dfi_p3_rddata[40] <= main_k7ddrphy_bitslip82[7];
-	main_k7ddrphy_dfi_p3_rddata[9] <= main_k7ddrphy_bitslip92[6];
-	main_k7ddrphy_dfi_p3_rddata[41] <= main_k7ddrphy_bitslip92[7];
-	main_k7ddrphy_dfi_p3_rddata[10] <= main_k7ddrphy_bitslip102[6];
-	main_k7ddrphy_dfi_p3_rddata[42] <= main_k7ddrphy_bitslip102[7];
-	main_k7ddrphy_dfi_p3_rddata[11] <= main_k7ddrphy_bitslip112[6];
-	main_k7ddrphy_dfi_p3_rddata[43] <= main_k7ddrphy_bitslip112[7];
-	main_k7ddrphy_dfi_p3_rddata[12] <= main_k7ddrphy_bitslip122[6];
-	main_k7ddrphy_dfi_p3_rddata[44] <= main_k7ddrphy_bitslip122[7];
-	main_k7ddrphy_dfi_p3_rddata[13] <= main_k7ddrphy_bitslip132[6];
-	main_k7ddrphy_dfi_p3_rddata[45] <= main_k7ddrphy_bitslip132[7];
-	main_k7ddrphy_dfi_p3_rddata[14] <= main_k7ddrphy_bitslip142[6];
-	main_k7ddrphy_dfi_p3_rddata[46] <= main_k7ddrphy_bitslip142[7];
-	main_k7ddrphy_dfi_p3_rddata[15] <= main_k7ddrphy_bitslip152[6];
-	main_k7ddrphy_dfi_p3_rddata[47] <= main_k7ddrphy_bitslip152[7];
-	main_k7ddrphy_dfi_p3_rddata[16] <= main_k7ddrphy_bitslip162[6];
-	main_k7ddrphy_dfi_p3_rddata[48] <= main_k7ddrphy_bitslip162[7];
-	main_k7ddrphy_dfi_p3_rddata[17] <= main_k7ddrphy_bitslip172[6];
-	main_k7ddrphy_dfi_p3_rddata[49] <= main_k7ddrphy_bitslip172[7];
-	main_k7ddrphy_dfi_p3_rddata[18] <= main_k7ddrphy_bitslip182[6];
-	main_k7ddrphy_dfi_p3_rddata[50] <= main_k7ddrphy_bitslip182[7];
-	main_k7ddrphy_dfi_p3_rddata[19] <= main_k7ddrphy_bitslip192[6];
-	main_k7ddrphy_dfi_p3_rddata[51] <= main_k7ddrphy_bitslip192[7];
-	main_k7ddrphy_dfi_p3_rddata[20] <= main_k7ddrphy_bitslip202[6];
-	main_k7ddrphy_dfi_p3_rddata[52] <= main_k7ddrphy_bitslip202[7];
-	main_k7ddrphy_dfi_p3_rddata[21] <= main_k7ddrphy_bitslip212[6];
-	main_k7ddrphy_dfi_p3_rddata[53] <= main_k7ddrphy_bitslip212[7];
-	main_k7ddrphy_dfi_p3_rddata[22] <= main_k7ddrphy_bitslip222[6];
-	main_k7ddrphy_dfi_p3_rddata[54] <= main_k7ddrphy_bitslip222[7];
-	main_k7ddrphy_dfi_p3_rddata[23] <= main_k7ddrphy_bitslip232[6];
-	main_k7ddrphy_dfi_p3_rddata[55] <= main_k7ddrphy_bitslip232[7];
-	main_k7ddrphy_dfi_p3_rddata[24] <= main_k7ddrphy_bitslip242[6];
-	main_k7ddrphy_dfi_p3_rddata[56] <= main_k7ddrphy_bitslip242[7];
-	main_k7ddrphy_dfi_p3_rddata[25] <= main_k7ddrphy_bitslip252[6];
-	main_k7ddrphy_dfi_p3_rddata[57] <= main_k7ddrphy_bitslip252[7];
-	main_k7ddrphy_dfi_p3_rddata[26] <= main_k7ddrphy_bitslip262[6];
-	main_k7ddrphy_dfi_p3_rddata[58] <= main_k7ddrphy_bitslip262[7];
-	main_k7ddrphy_dfi_p3_rddata[27] <= main_k7ddrphy_bitslip272[6];
-	main_k7ddrphy_dfi_p3_rddata[59] <= main_k7ddrphy_bitslip272[7];
-	main_k7ddrphy_dfi_p3_rddata[28] <= main_k7ddrphy_bitslip282[6];
-	main_k7ddrphy_dfi_p3_rddata[60] <= main_k7ddrphy_bitslip282[7];
-	main_k7ddrphy_dfi_p3_rddata[29] <= main_k7ddrphy_bitslip292[6];
-	main_k7ddrphy_dfi_p3_rddata[61] <= main_k7ddrphy_bitslip292[7];
-	main_k7ddrphy_dfi_p3_rddata[30] <= main_k7ddrphy_bitslip302[6];
-	main_k7ddrphy_dfi_p3_rddata[62] <= main_k7ddrphy_bitslip302[7];
-	main_k7ddrphy_dfi_p3_rddata[31] <= main_k7ddrphy_bitslip312[6];
-	main_k7ddrphy_dfi_p3_rddata[63] <= main_k7ddrphy_bitslip312[7];
-end
-assign main_k7ddrphy_dfi_p0_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
-assign main_k7ddrphy_dfi_p1_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
-assign main_k7ddrphy_dfi_p2_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
-assign main_k7ddrphy_dfi_p3_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
-assign main_k7ddrphy_dq_oe = main_k7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-	main_k7ddrphy_dqs_oe <= 1'd0;
-	if (main_k7ddrphy_wlevel_en_storage) begin
-		main_k7ddrphy_dqs_oe <= 1'd1;
+assign user_enable = 1'd1;
+assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
+assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
+assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
+assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign reset = (rst | rst_1);
+assign pll_locked = locked;
+assign clkin = clk;
+assign iodelay_clk = clkout_buf0;
+assign sys_clk = clkout_buf1;
+assign sys4x_clk = clkout_buf2;
+assign sys4x_dqs_clk = clkout_buf3;
+assign ddram_ba = k7ddrphy_pads_ba;
+assign k7ddrphy_dqs_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dqs_oe) | k7ddrphy_dqs_postamble);
+assign k7ddrphy_dq_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dq_oe) | k7ddrphy_dqs_postamble);
+always @(*) begin
+	k7ddrphy_dfi_p0_rddata <= 64'd0;
+	k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0];
+	k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1];
+	k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0];
+	k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1];
+	k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0];
+	k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1];
+	k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0];
+	k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1];
+	k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0];
+	k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1];
+	k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0];
+	k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1];
+	k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0];
+	k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1];
+	k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0];
+	k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1];
+	k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0];
+	k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1];
+	k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0];
+	k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1];
+	k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0];
+	k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1];
+	k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0];
+	k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1];
+	k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0];
+	k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1];
+	k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0];
+	k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1];
+	k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0];
+	k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1];
+	k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0];
+	k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1];
+	k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0];
+	k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1];
+	k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0];
+	k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1];
+	k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0];
+	k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1];
+	k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0];
+	k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1];
+	k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0];
+	k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1];
+	k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0];
+	k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1];
+	k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0];
+	k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1];
+	k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0];
+	k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1];
+	k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0];
+	k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1];
+	k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0];
+	k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1];
+	k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0];
+	k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1];
+	k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0];
+	k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1];
+	k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0];
+	k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1];
+	k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0];
+	k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1];
+	k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0];
+	k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1];
+	k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0];
+	k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1];
+end
+always @(*) begin
+	k7ddrphy_dfi_p1_rddata <= 64'd0;
+	k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2];
+	k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3];
+	k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2];
+	k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3];
+	k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2];
+	k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3];
+	k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2];
+	k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3];
+	k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2];
+	k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3];
+	k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2];
+	k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3];
+	k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2];
+	k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3];
+	k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2];
+	k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3];
+	k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2];
+	k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3];
+	k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2];
+	k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3];
+	k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2];
+	k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3];
+	k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2];
+	k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3];
+	k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2];
+	k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3];
+	k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2];
+	k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3];
+	k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2];
+	k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3];
+	k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2];
+	k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3];
+	k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2];
+	k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3];
+	k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2];
+	k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3];
+	k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2];
+	k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3];
+	k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2];
+	k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3];
+	k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2];
+	k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3];
+	k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2];
+	k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3];
+	k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2];
+	k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3];
+	k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2];
+	k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3];
+	k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2];
+	k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3];
+	k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2];
+	k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3];
+	k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2];
+	k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3];
+	k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2];
+	k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3];
+	k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2];
+	k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3];
+	k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2];
+	k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3];
+	k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2];
+	k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3];
+	k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2];
+	k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3];
+end
+always @(*) begin
+	k7ddrphy_dfi_p2_rddata <= 64'd0;
+	k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4];
+	k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5];
+	k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4];
+	k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5];
+	k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4];
+	k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5];
+	k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4];
+	k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5];
+	k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4];
+	k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5];
+	k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4];
+	k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5];
+	k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4];
+	k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5];
+	k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4];
+	k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5];
+	k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4];
+	k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5];
+	k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4];
+	k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5];
+	k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4];
+	k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5];
+	k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4];
+	k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5];
+	k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4];
+	k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5];
+	k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4];
+	k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5];
+	k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4];
+	k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5];
+	k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4];
+	k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5];
+	k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4];
+	k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5];
+	k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4];
+	k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5];
+	k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4];
+	k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5];
+	k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4];
+	k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5];
+	k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4];
+	k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5];
+	k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4];
+	k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5];
+	k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4];
+	k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5];
+	k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4];
+	k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5];
+	k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4];
+	k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5];
+	k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4];
+	k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5];
+	k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4];
+	k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5];
+	k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4];
+	k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5];
+	k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4];
+	k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5];
+	k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4];
+	k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5];
+	k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4];
+	k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5];
+	k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4];
+	k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5];
+end
+always @(*) begin
+	k7ddrphy_dfi_p3_rddata <= 64'd0;
+	k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6];
+	k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7];
+	k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6];
+	k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7];
+	k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6];
+	k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7];
+	k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6];
+	k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7];
+	k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6];
+	k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7];
+	k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6];
+	k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7];
+	k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6];
+	k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7];
+	k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6];
+	k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7];
+	k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6];
+	k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7];
+	k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6];
+	k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7];
+	k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6];
+	k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7];
+	k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6];
+	k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7];
+	k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6];
+	k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7];
+	k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6];
+	k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7];
+	k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6];
+	k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7];
+	k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6];
+	k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7];
+	k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6];
+	k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7];
+	k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6];
+	k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7];
+	k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6];
+	k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7];
+	k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6];
+	k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7];
+	k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6];
+	k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7];
+	k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6];
+	k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7];
+	k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6];
+	k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7];
+	k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6];
+	k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7];
+	k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6];
+	k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7];
+	k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6];
+	k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7];
+	k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6];
+	k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7];
+	k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6];
+	k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7];
+	k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6];
+	k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7];
+	k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6];
+	k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7];
+	k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6];
+	k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7];
+	k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6];
+	k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7];
+end
+assign k7ddrphy_dfi_p0_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
+assign k7ddrphy_dfi_p1_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
+assign k7ddrphy_dfi_p2_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
+assign k7ddrphy_dfi_p3_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
+assign k7ddrphy_dq_oe = k7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+	k7ddrphy_dqs_oe <= 1'd0;
+	if (k7ddrphy_wlevel_en_storage) begin
+		k7ddrphy_dqs_oe <= 1'd1;
 	end else begin
-		main_k7ddrphy_dqs_oe <= main_k7ddrphy_dq_oe;
+		k7ddrphy_dqs_oe <= k7ddrphy_dq_oe;
 	end
 end
-assign main_k7ddrphy_dqs_preamble = (main_k7ddrphy_wrdata_en_tappeddelayline0 & (~main_k7ddrphy_wrdata_en_tappeddelayline1));
-assign main_k7ddrphy_dqs_postamble = (main_k7ddrphy_wrdata_en_tappeddelayline2 & (~main_k7ddrphy_wrdata_en_tappeddelayline1));
+assign k7ddrphy_dqs_preamble = (k7ddrphy_wrdata_en_tappeddelayline0 & (~k7ddrphy_wrdata_en_tappeddelayline1));
+assign k7ddrphy_dqs_postamble = (k7ddrphy_wrdata_en_tappeddelayline2 & (~k7ddrphy_wrdata_en_tappeddelayline1));
 always @(*) begin
-	main_k7ddrphy_dqspattern_o <= 8'd0;
-	main_k7ddrphy_dqspattern_o <= 7'd85;
-	if (main_k7ddrphy_dqspattern0) begin
-		main_k7ddrphy_dqspattern_o <= 5'd21;
+	k7ddrphy_dqspattern_o <= 8'd0;
+	k7ddrphy_dqspattern_o <= 7'd85;
+	if (k7ddrphy_dqspattern0) begin
+		k7ddrphy_dqspattern_o <= 5'd21;
 	end
-	if (main_k7ddrphy_dqspattern1) begin
-		main_k7ddrphy_dqspattern_o <= 7'd84;
+	if (k7ddrphy_dqspattern1) begin
+		k7ddrphy_dqspattern_o <= 7'd84;
 	end
-	if (main_k7ddrphy_wlevel_en_storage) begin
-		main_k7ddrphy_dqspattern_o <= 1'd0;
-		if (main_k7ddrphy_wlevel_strobe_re) begin
-			main_k7ddrphy_dqspattern_o <= 1'd1;
+	if (k7ddrphy_wlevel_en_storage) begin
+		k7ddrphy_dqspattern_o <= 1'd0;
+		if (k7ddrphy_wlevel_strobe_re) begin
+			k7ddrphy_dqspattern_o <= 1'd1;
 		end
 	end
 end
 always @(*) begin
-	main_k7ddrphy_bitslip00 <= 8'd0;
-	case (main_k7ddrphy_bitslip0_value0)
+	k7ddrphy_bitslip00 <= 8'd0;
+	case (k7ddrphy_bitslip0_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[8:1];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[9:2];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[10:3];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[11:4];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[12:5];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[13:6];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[14:7];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[15:8];
+			k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip10 <= 8'd0;
-	case (main_k7ddrphy_bitslip1_value0)
+	k7ddrphy_bitslip10 <= 8'd0;
+	case (k7ddrphy_bitslip1_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[8:1];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[9:2];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[10:3];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[11:4];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[12:5];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[13:6];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[14:7];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[15:8];
+			k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip20 <= 8'd0;
-	case (main_k7ddrphy_bitslip2_value0)
+	k7ddrphy_bitslip20 <= 8'd0;
+	case (k7ddrphy_bitslip2_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[8:1];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[9:2];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[10:3];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[11:4];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[12:5];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[13:6];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[14:7];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[15:8];
+			k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip30 <= 8'd0;
-	case (main_k7ddrphy_bitslip3_value0)
+	k7ddrphy_bitslip30 <= 8'd0;
+	case (k7ddrphy_bitslip3_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[8:1];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[9:2];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[10:3];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[11:4];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[12:5];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[13:6];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[14:7];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[15:8];
+			k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip01 <= 8'd0;
-	case (main_k7ddrphy_bitslip0_value1)
+	k7ddrphy_bitslip01 <= 8'd0;
+	case (k7ddrphy_bitslip0_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[8:1];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[9:2];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[10:3];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[11:4];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[12:5];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[13:6];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[14:7];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[15:8];
+			k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip11 <= 8'd0;
-	case (main_k7ddrphy_bitslip1_value1)
+	k7ddrphy_bitslip11 <= 8'd0;
+	case (k7ddrphy_bitslip1_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[8:1];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[9:2];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[10:3];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[11:4];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[12:5];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[13:6];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[14:7];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[15:8];
+			k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip21 <= 8'd0;
-	case (main_k7ddrphy_bitslip2_value1)
+	k7ddrphy_bitslip21 <= 8'd0;
+	case (k7ddrphy_bitslip2_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[8:1];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[9:2];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[10:3];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[11:4];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[12:5];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[13:6];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[14:7];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[15:8];
+			k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip31 <= 8'd0;
-	case (main_k7ddrphy_bitslip3_value1)
+	k7ddrphy_bitslip31 <= 8'd0;
+	case (k7ddrphy_bitslip3_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[8:1];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[9:2];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[10:3];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[11:4];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[12:5];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[13:6];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[14:7];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[15:8];
+			k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip02 <= 8'd0;
-	case (main_k7ddrphy_bitslip0_value2)
+	k7ddrphy_bitslip02 <= 8'd0;
+	case (k7ddrphy_bitslip0_value2)
 		1'd0: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[8:1];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[9:2];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[10:3];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[11:4];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[12:5];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[13:6];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[14:7];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[15:8];
+			k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip04 <= 8'd0;
-	case (main_k7ddrphy_bitslip0_value3)
+	k7ddrphy_bitslip04 <= 8'd0;
+	case (k7ddrphy_bitslip0_value3)
 		1'd0: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[8:1];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[9:2];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[10:3];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[11:4];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[12:5];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[13:6];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[14:7];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[15:8];
+			k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip12 <= 8'd0;
-	case (main_k7ddrphy_bitslip1_value2)
+	k7ddrphy_bitslip12 <= 8'd0;
+	case (k7ddrphy_bitslip1_value2)
 		1'd0: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[8:1];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[9:2];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[10:3];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[11:4];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[12:5];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[13:6];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[14:7];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[15:8];
+			k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip14 <= 8'd0;
-	case (main_k7ddrphy_bitslip1_value3)
+	k7ddrphy_bitslip14 <= 8'd0;
+	case (k7ddrphy_bitslip1_value3)
 		1'd0: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[8:1];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[9:2];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[10:3];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[11:4];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[12:5];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[13:6];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[14:7];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[15:8];
+			k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip22 <= 8'd0;
-	case (main_k7ddrphy_bitslip2_value2)
+	k7ddrphy_bitslip22 <= 8'd0;
+	case (k7ddrphy_bitslip2_value2)
 		1'd0: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[8:1];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[9:2];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[10:3];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[11:4];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[12:5];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[13:6];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[14:7];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[15:8];
+			k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip24 <= 8'd0;
-	case (main_k7ddrphy_bitslip2_value3)
+	k7ddrphy_bitslip24 <= 8'd0;
+	case (k7ddrphy_bitslip2_value3)
 		1'd0: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[8:1];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[9:2];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[10:3];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[11:4];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[12:5];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[13:6];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[14:7];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[15:8];
+			k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip32 <= 8'd0;
-	case (main_k7ddrphy_bitslip3_value2)
+	k7ddrphy_bitslip32 <= 8'd0;
+	case (k7ddrphy_bitslip3_value2)
 		1'd0: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[8:1];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[9:2];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[10:3];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[11:4];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[12:5];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[13:6];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[14:7];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[15:8];
+			k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip34 <= 8'd0;
-	case (main_k7ddrphy_bitslip3_value3)
+	k7ddrphy_bitslip34 <= 8'd0;
+	case (k7ddrphy_bitslip3_value3)
 		1'd0: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[8:1];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[9:2];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[10:3];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[11:4];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[12:5];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[13:6];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[14:7];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[15:8];
+			k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip40 <= 8'd0;
-	case (main_k7ddrphy_bitslip4_value0)
+	k7ddrphy_bitslip40 <= 8'd0;
+	case (k7ddrphy_bitslip4_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[8:1];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[9:2];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[10:3];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[11:4];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[12:5];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[13:6];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[14:7];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[15:8];
+			k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip42 <= 8'd0;
-	case (main_k7ddrphy_bitslip4_value1)
+	k7ddrphy_bitslip42 <= 8'd0;
+	case (k7ddrphy_bitslip4_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[8:1];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[9:2];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[10:3];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[11:4];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[12:5];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[13:6];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[14:7];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[15:8];
+			k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip50 <= 8'd0;
-	case (main_k7ddrphy_bitslip5_value0)
+	k7ddrphy_bitslip50 <= 8'd0;
+	case (k7ddrphy_bitslip5_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[8:1];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[9:2];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[10:3];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[11:4];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[12:5];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[13:6];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[14:7];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[15:8];
+			k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip52 <= 8'd0;
-	case (main_k7ddrphy_bitslip5_value1)
+	k7ddrphy_bitslip52 <= 8'd0;
+	case (k7ddrphy_bitslip5_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[8:1];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[9:2];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[10:3];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[11:4];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[12:5];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[13:6];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[14:7];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[15:8];
+			k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip60 <= 8'd0;
-	case (main_k7ddrphy_bitslip6_value0)
+	k7ddrphy_bitslip60 <= 8'd0;
+	case (k7ddrphy_bitslip6_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[8:1];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[9:2];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[10:3];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[11:4];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[12:5];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[13:6];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[14:7];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[15:8];
+			k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip62 <= 8'd0;
-	case (main_k7ddrphy_bitslip6_value1)
+	k7ddrphy_bitslip62 <= 8'd0;
+	case (k7ddrphy_bitslip6_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[8:1];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[9:2];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[10:3];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[11:4];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[12:5];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[13:6];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[14:7];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[15:8];
+			k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip70 <= 8'd0;
-	case (main_k7ddrphy_bitslip7_value0)
+	k7ddrphy_bitslip70 <= 8'd0;
+	case (k7ddrphy_bitslip7_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[8:1];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[9:2];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[10:3];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[11:4];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[12:5];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[13:6];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[14:7];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[15:8];
+			k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip72 <= 8'd0;
-	case (main_k7ddrphy_bitslip7_value1)
+	k7ddrphy_bitslip72 <= 8'd0;
+	case (k7ddrphy_bitslip7_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[8:1];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[9:2];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[10:3];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[11:4];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[12:5];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[13:6];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[14:7];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[15:8];
+			k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip80 <= 8'd0;
-	case (main_k7ddrphy_bitslip8_value0)
+	k7ddrphy_bitslip80 <= 8'd0;
+	case (k7ddrphy_bitslip8_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[8:1];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[9:2];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[10:3];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[11:4];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[12:5];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[13:6];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[14:7];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[15:8];
+			k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip82 <= 8'd0;
-	case (main_k7ddrphy_bitslip8_value1)
+	k7ddrphy_bitslip82 <= 8'd0;
+	case (k7ddrphy_bitslip8_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[8:1];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[9:2];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[10:3];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[11:4];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[12:5];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[13:6];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[14:7];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[15:8];
+			k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip90 <= 8'd0;
-	case (main_k7ddrphy_bitslip9_value0)
+	k7ddrphy_bitslip90 <= 8'd0;
+	case (k7ddrphy_bitslip9_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[8:1];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[9:2];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[10:3];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[11:4];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[12:5];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[13:6];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[14:7];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[15:8];
+			k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip92 <= 8'd0;
-	case (main_k7ddrphy_bitslip9_value1)
+	k7ddrphy_bitslip92 <= 8'd0;
+	case (k7ddrphy_bitslip9_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[8:1];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[9:2];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[10:3];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[11:4];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[12:5];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[13:6];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[14:7];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[15:8];
+			k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip100 <= 8'd0;
-	case (main_k7ddrphy_bitslip10_value0)
+	k7ddrphy_bitslip100 <= 8'd0;
+	case (k7ddrphy_bitslip10_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[8:1];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[9:2];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[10:3];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[11:4];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[12:5];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[13:6];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[14:7];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[15:8];
+			k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip102 <= 8'd0;
-	case (main_k7ddrphy_bitslip10_value1)
+	k7ddrphy_bitslip102 <= 8'd0;
+	case (k7ddrphy_bitslip10_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[8:1];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[9:2];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[10:3];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[11:4];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[12:5];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[13:6];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[14:7];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[15:8];
+			k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip110 <= 8'd0;
-	case (main_k7ddrphy_bitslip11_value0)
+	k7ddrphy_bitslip110 <= 8'd0;
+	case (k7ddrphy_bitslip11_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[8:1];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[9:2];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[10:3];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[11:4];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[12:5];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[13:6];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[14:7];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[15:8];
+			k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip112 <= 8'd0;
-	case (main_k7ddrphy_bitslip11_value1)
+	k7ddrphy_bitslip112 <= 8'd0;
+	case (k7ddrphy_bitslip11_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[8:1];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[9:2];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[10:3];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[11:4];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[12:5];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[13:6];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[14:7];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[15:8];
+			k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip120 <= 8'd0;
-	case (main_k7ddrphy_bitslip12_value0)
+	k7ddrphy_bitslip120 <= 8'd0;
+	case (k7ddrphy_bitslip12_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[8:1];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[9:2];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[10:3];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[11:4];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[12:5];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[13:6];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[14:7];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[15:8];
+			k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip122 <= 8'd0;
-	case (main_k7ddrphy_bitslip12_value1)
+	k7ddrphy_bitslip122 <= 8'd0;
+	case (k7ddrphy_bitslip12_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[8:1];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[9:2];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[10:3];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[11:4];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[12:5];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[13:6];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[14:7];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[15:8];
+			k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip130 <= 8'd0;
-	case (main_k7ddrphy_bitslip13_value0)
+	k7ddrphy_bitslip130 <= 8'd0;
+	case (k7ddrphy_bitslip13_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[8:1];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[9:2];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[10:3];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[11:4];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[12:5];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[13:6];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[14:7];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[15:8];
+			k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip132 <= 8'd0;
-	case (main_k7ddrphy_bitslip13_value1)
+	k7ddrphy_bitslip132 <= 8'd0;
+	case (k7ddrphy_bitslip13_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[8:1];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[9:2];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[10:3];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[11:4];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[12:5];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[13:6];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[14:7];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[15:8];
+			k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip140 <= 8'd0;
-	case (main_k7ddrphy_bitslip14_value0)
+	k7ddrphy_bitslip140 <= 8'd0;
+	case (k7ddrphy_bitslip14_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[8:1];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[9:2];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[10:3];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[11:4];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[12:5];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[13:6];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[14:7];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[15:8];
+			k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip142 <= 8'd0;
-	case (main_k7ddrphy_bitslip14_value1)
+	k7ddrphy_bitslip142 <= 8'd0;
+	case (k7ddrphy_bitslip14_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[8:1];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[9:2];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[10:3];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[11:4];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[12:5];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[13:6];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[14:7];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[15:8];
+			k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip150 <= 8'd0;
-	case (main_k7ddrphy_bitslip15_value0)
+	k7ddrphy_bitslip150 <= 8'd0;
+	case (k7ddrphy_bitslip15_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[8:1];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[9:2];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[10:3];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[11:4];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[12:5];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[13:6];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[14:7];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[15:8];
+			k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip152 <= 8'd0;
-	case (main_k7ddrphy_bitslip15_value1)
+	k7ddrphy_bitslip152 <= 8'd0;
+	case (k7ddrphy_bitslip15_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[8:1];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[9:2];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[10:3];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[11:4];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[12:5];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[13:6];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[14:7];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[15:8];
+			k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip160 <= 8'd0;
-	case (main_k7ddrphy_bitslip16_value0)
+	k7ddrphy_bitslip160 <= 8'd0;
+	case (k7ddrphy_bitslip16_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[8:1];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[9:2];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[10:3];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[11:4];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[12:5];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[13:6];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[14:7];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[15:8];
+			k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip162 <= 8'd0;
-	case (main_k7ddrphy_bitslip16_value1)
+	k7ddrphy_bitslip162 <= 8'd0;
+	case (k7ddrphy_bitslip16_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[8:1];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[9:2];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[10:3];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[11:4];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[12:5];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[13:6];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[14:7];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[15:8];
+			k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip170 <= 8'd0;
-	case (main_k7ddrphy_bitslip17_value0)
+	k7ddrphy_bitslip170 <= 8'd0;
+	case (k7ddrphy_bitslip17_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[8:1];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[9:2];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[10:3];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[11:4];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[12:5];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[13:6];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[14:7];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[15:8];
+			k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip172 <= 8'd0;
-	case (main_k7ddrphy_bitslip17_value1)
+	k7ddrphy_bitslip172 <= 8'd0;
+	case (k7ddrphy_bitslip17_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[8:1];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[9:2];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[10:3];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[11:4];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[12:5];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[13:6];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[14:7];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[15:8];
+			k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip180 <= 8'd0;
-	case (main_k7ddrphy_bitslip18_value0)
+	k7ddrphy_bitslip180 <= 8'd0;
+	case (k7ddrphy_bitslip18_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[8:1];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[9:2];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[10:3];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[11:4];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[12:5];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[13:6];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[14:7];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[15:8];
+			k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip182 <= 8'd0;
-	case (main_k7ddrphy_bitslip18_value1)
+	k7ddrphy_bitslip182 <= 8'd0;
+	case (k7ddrphy_bitslip18_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[8:1];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[9:2];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[10:3];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[11:4];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[12:5];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[13:6];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[14:7];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[15:8];
+			k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip190 <= 8'd0;
-	case (main_k7ddrphy_bitslip19_value0)
+	k7ddrphy_bitslip190 <= 8'd0;
+	case (k7ddrphy_bitslip19_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[8:1];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[9:2];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[10:3];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[11:4];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[12:5];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[13:6];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[14:7];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[15:8];
+			k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip192 <= 8'd0;
-	case (main_k7ddrphy_bitslip19_value1)
+	k7ddrphy_bitslip192 <= 8'd0;
+	case (k7ddrphy_bitslip19_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[8:1];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[9:2];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[10:3];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[11:4];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[12:5];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[13:6];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[14:7];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[15:8];
+			k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip200 <= 8'd0;
-	case (main_k7ddrphy_bitslip20_value0)
+	k7ddrphy_bitslip200 <= 8'd0;
+	case (k7ddrphy_bitslip20_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[8:1];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[9:2];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[10:3];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[11:4];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[12:5];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[13:6];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[14:7];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[15:8];
+			k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip202 <= 8'd0;
-	case (main_k7ddrphy_bitslip20_value1)
+	k7ddrphy_bitslip202 <= 8'd0;
+	case (k7ddrphy_bitslip20_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[8:1];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[9:2];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[10:3];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[11:4];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[12:5];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[13:6];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[14:7];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[15:8];
+			k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip210 <= 8'd0;
-	case (main_k7ddrphy_bitslip21_value0)
+	k7ddrphy_bitslip210 <= 8'd0;
+	case (k7ddrphy_bitslip21_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[8:1];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[9:2];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[10:3];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[11:4];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[12:5];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[13:6];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[14:7];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[15:8];
+			k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip212 <= 8'd0;
-	case (main_k7ddrphy_bitslip21_value1)
+	k7ddrphy_bitslip212 <= 8'd0;
+	case (k7ddrphy_bitslip21_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[8:1];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[9:2];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[10:3];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[11:4];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[12:5];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[13:6];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[14:7];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[15:8];
+			k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip220 <= 8'd0;
-	case (main_k7ddrphy_bitslip22_value0)
+	k7ddrphy_bitslip220 <= 8'd0;
+	case (k7ddrphy_bitslip22_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[8:1];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[9:2];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[10:3];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[11:4];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[12:5];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[13:6];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[14:7];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[15:8];
+			k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip222 <= 8'd0;
-	case (main_k7ddrphy_bitslip22_value1)
+	k7ddrphy_bitslip222 <= 8'd0;
+	case (k7ddrphy_bitslip22_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[8:1];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[9:2];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[10:3];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[11:4];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[12:5];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[13:6];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[14:7];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[15:8];
+			k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip230 <= 8'd0;
-	case (main_k7ddrphy_bitslip23_value0)
+	k7ddrphy_bitslip230 <= 8'd0;
+	case (k7ddrphy_bitslip23_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[8:1];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[9:2];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[10:3];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[11:4];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[12:5];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[13:6];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[14:7];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[15:8];
+			k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip232 <= 8'd0;
-	case (main_k7ddrphy_bitslip23_value1)
+	k7ddrphy_bitslip232 <= 8'd0;
+	case (k7ddrphy_bitslip23_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[8:1];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[9:2];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[10:3];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[11:4];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[12:5];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[13:6];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[14:7];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[15:8];
+			k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip240 <= 8'd0;
-	case (main_k7ddrphy_bitslip24_value0)
+	k7ddrphy_bitslip240 <= 8'd0;
+	case (k7ddrphy_bitslip24_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[8:1];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[9:2];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[10:3];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[11:4];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[12:5];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[13:6];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[14:7];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[15:8];
+			k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip242 <= 8'd0;
-	case (main_k7ddrphy_bitslip24_value1)
+	k7ddrphy_bitslip242 <= 8'd0;
+	case (k7ddrphy_bitslip24_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[8:1];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[9:2];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[10:3];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[11:4];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[12:5];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[13:6];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[14:7];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[15:8];
+			k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip250 <= 8'd0;
-	case (main_k7ddrphy_bitslip25_value0)
+	k7ddrphy_bitslip250 <= 8'd0;
+	case (k7ddrphy_bitslip25_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[8:1];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[9:2];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[10:3];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[11:4];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[12:5];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[13:6];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[14:7];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[15:8];
+			k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip252 <= 8'd0;
-	case (main_k7ddrphy_bitslip25_value1)
+	k7ddrphy_bitslip252 <= 8'd0;
+	case (k7ddrphy_bitslip25_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[8:1];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[9:2];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[10:3];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[11:4];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[12:5];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[13:6];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[14:7];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[15:8];
+			k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip260 <= 8'd0;
-	case (main_k7ddrphy_bitslip26_value0)
+	k7ddrphy_bitslip260 <= 8'd0;
+	case (k7ddrphy_bitslip26_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[8:1];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[9:2];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[10:3];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[11:4];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[12:5];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[13:6];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[14:7];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[15:8];
+			k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip262 <= 8'd0;
-	case (main_k7ddrphy_bitslip26_value1)
+	k7ddrphy_bitslip262 <= 8'd0;
+	case (k7ddrphy_bitslip26_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[8:1];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[9:2];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[10:3];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[11:4];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[12:5];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[13:6];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[14:7];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[15:8];
+			k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip270 <= 8'd0;
-	case (main_k7ddrphy_bitslip27_value0)
+	k7ddrphy_bitslip270 <= 8'd0;
+	case (k7ddrphy_bitslip27_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[8:1];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[9:2];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[10:3];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[11:4];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[12:5];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[13:6];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[14:7];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[15:8];
+			k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip272 <= 8'd0;
-	case (main_k7ddrphy_bitslip27_value1)
+	k7ddrphy_bitslip272 <= 8'd0;
+	case (k7ddrphy_bitslip27_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[8:1];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[9:2];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[10:3];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[11:4];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[12:5];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[13:6];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[14:7];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[15:8];
+			k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip280 <= 8'd0;
-	case (main_k7ddrphy_bitslip28_value0)
+	k7ddrphy_bitslip280 <= 8'd0;
+	case (k7ddrphy_bitslip28_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[8:1];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[9:2];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[10:3];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[11:4];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[12:5];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[13:6];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[14:7];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[15:8];
+			k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip282 <= 8'd0;
-	case (main_k7ddrphy_bitslip28_value1)
+	k7ddrphy_bitslip282 <= 8'd0;
+	case (k7ddrphy_bitslip28_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[8:1];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[9:2];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[10:3];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[11:4];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[12:5];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[13:6];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[14:7];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[15:8];
+			k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip290 <= 8'd0;
-	case (main_k7ddrphy_bitslip29_value0)
+	k7ddrphy_bitslip290 <= 8'd0;
+	case (k7ddrphy_bitslip29_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[8:1];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[9:2];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[10:3];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[11:4];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[12:5];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[13:6];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[14:7];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[15:8];
+			k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip292 <= 8'd0;
-	case (main_k7ddrphy_bitslip29_value1)
+	k7ddrphy_bitslip292 <= 8'd0;
+	case (k7ddrphy_bitslip29_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[8:1];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[9:2];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[10:3];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[11:4];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[12:5];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[13:6];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[14:7];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[15:8];
+			k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip300 <= 8'd0;
-	case (main_k7ddrphy_bitslip30_value0)
+	k7ddrphy_bitslip300 <= 8'd0;
+	case (k7ddrphy_bitslip30_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[8:1];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[9:2];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[10:3];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[11:4];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[12:5];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[13:6];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[14:7];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[15:8];
+			k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip302 <= 8'd0;
-	case (main_k7ddrphy_bitslip30_value1)
+	k7ddrphy_bitslip302 <= 8'd0;
+	case (k7ddrphy_bitslip30_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[8:1];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[9:2];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[10:3];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[11:4];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[12:5];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[13:6];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[14:7];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[15:8];
+			k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip310 <= 8'd0;
-	case (main_k7ddrphy_bitslip31_value0)
+	k7ddrphy_bitslip310 <= 8'd0;
+	case (k7ddrphy_bitslip31_value0)
 		1'd0: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[8:1];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[9:2];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[10:3];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[11:4];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[12:5];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[13:6];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[14:7];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[15:8];
+			k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_k7ddrphy_bitslip312 <= 8'd0;
-	case (main_k7ddrphy_bitslip31_value1)
+	k7ddrphy_bitslip312 <= 8'd0;
+	case (k7ddrphy_bitslip31_value1)
 		1'd0: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[8:1];
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1];
 		end
 		1'd1: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[9:2];
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2];
 		end
 		2'd2: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[10:3];
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3];
 		end
 		2'd3: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[11:4];
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4];
 		end
 		3'd4: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[12:5];
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5];
 		end
 		3'd5: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[13:6];
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6];
 		end
 		3'd6: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[14:7];
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7];
 		end
 		3'd7: begin
-			main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[15:8];
-		end
-	endcase
-end
-assign main_k7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
-assign main_k7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
-assign main_k7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
-assign main_k7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
-assign main_k7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
-assign main_k7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
-assign main_k7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
-assign main_k7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
-assign main_k7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
-assign main_k7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
-assign main_k7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
-assign main_k7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
-assign main_k7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
-assign main_k7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
-assign main_litedramcore_master_p0_rddata = main_k7ddrphy_dfi_p0_rddata;
-assign main_litedramcore_master_p0_rddata_valid = main_k7ddrphy_dfi_p0_rddata_valid;
-assign main_k7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
-assign main_k7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
-assign main_k7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
-assign main_k7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
-assign main_k7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
-assign main_k7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
-assign main_k7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
-assign main_k7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
-assign main_k7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
-assign main_k7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
-assign main_k7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
-assign main_k7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
-assign main_k7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
-assign main_k7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
-assign main_litedramcore_master_p1_rddata = main_k7ddrphy_dfi_p1_rddata;
-assign main_litedramcore_master_p1_rddata_valid = main_k7ddrphy_dfi_p1_rddata_valid;
-assign main_k7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
-assign main_k7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
-assign main_k7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
-assign main_k7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
-assign main_k7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
-assign main_k7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
-assign main_k7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
-assign main_k7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
-assign main_k7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
-assign main_k7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
-assign main_k7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
-assign main_k7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
-assign main_k7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
-assign main_k7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
-assign main_litedramcore_master_p2_rddata = main_k7ddrphy_dfi_p2_rddata;
-assign main_litedramcore_master_p2_rddata_valid = main_k7ddrphy_dfi_p2_rddata_valid;
-assign main_k7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
-assign main_k7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
-assign main_k7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
-assign main_k7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
-assign main_k7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
-assign main_k7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
-assign main_k7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
-assign main_k7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
-assign main_k7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
-assign main_k7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
-assign main_k7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
-assign main_k7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
-assign main_k7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
-assign main_k7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
-assign main_litedramcore_master_p3_rddata = main_k7ddrphy_dfi_p3_rddata;
-assign main_litedramcore_master_p3_rddata_valid = main_k7ddrphy_dfi_p3_rddata_valid;
-assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
-assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
-assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
-assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
-assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
-assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
-assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
-assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
-assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
-assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
-assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
-assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
-assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
-assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
-assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
-assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
-assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
-assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
-assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
-assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
-assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
-assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
-assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
-assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
-assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
-assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
-assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
-assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
-assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
-assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
-assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
-assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
-assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
-assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
-assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
-assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
-assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
-assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
-assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
-assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
-assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
-assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
-assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
-assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
-assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
-assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
-assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
-assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
-assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
-assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
-assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
-assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
-assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
-assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
-assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
-assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
-assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
-assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
-assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
-assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
-assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
-assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
-assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
-assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
-always @(*) begin
-	main_litedramcore_master_p0_wrdata_mask <= 8'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
+			k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8];
+		end
+	endcase
+end
+assign k7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign k7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign k7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign k7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign k7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign k7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign k7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign k7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign k7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign k7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign k7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign k7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign k7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign k7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = k7ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = k7ddrphy_dfi_p0_rddata_valid;
+assign k7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign k7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign k7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign k7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign k7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign k7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign k7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign k7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign k7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign k7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign k7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign k7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign k7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign k7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = k7ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = k7ddrphy_dfi_p1_rddata_valid;
+assign k7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign k7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign k7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign k7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign k7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign k7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign k7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign k7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign k7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign k7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign k7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign k7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign k7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign k7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = k7ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = k7ddrphy_dfi_p2_rddata_valid;
+assign k7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign k7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign k7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign k7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign k7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign k7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign k7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign k7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign k7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign k7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign k7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign k7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign k7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign k7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = k7ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = k7ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+	litedramcore_csr_dfi_p0_rddata <= 64'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
+		litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
+	litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
+		litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
+	litedramcore_csr_dfi_p1_rddata <= 64'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
+		litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
+	litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
+		litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
+	litedramcore_csr_dfi_p2_rddata <= 64'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
+		litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+	litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
+		litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
+	litedramcore_csr_dfi_p3_rddata <= 64'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
+		litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
+	litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
+		litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
+	litedramcore_ext_dfi_p0_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end else begin
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
+	litedramcore_ext_dfi_p1_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
+	litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
+	litedramcore_ext_dfi_p2_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
+	litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
+	litedramcore_slave_p0_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_slave_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
+	litedramcore_ext_dfi_p3_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_mask <= 8'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
+	litedramcore_slave_p1_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
+	litedramcore_slave_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
+	litedramcore_slave_p2_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
+	litedramcore_slave_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
+	litedramcore_slave_p3_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+	litedramcore_slave_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
+	litedramcore_master_p0_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+		end else begin
+			litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+		end
 	end else begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
+		litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
+	litedramcore_master_p0_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+		end else begin
+			litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+		end
 	end else begin
+		litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
+	litedramcore_master_p0_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+		end else begin
+			litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
+		litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	litedramcore_master_p0_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+		end else begin
+			litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+		end
 	end else begin
+		litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
+	litedramcore_master_p0_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+		end else begin
+			litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
+		litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
+	litedramcore_master_p0_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+		end else begin
+			litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
+		litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
+	litedramcore_master_p0_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+		end else begin
+			litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+		end
 	end else begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
+		litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
+	litedramcore_master_p0_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+		end else begin
+			litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
+		litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+	litedramcore_master_p0_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+		end else begin
+			litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+		litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p0_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+		end else begin
+			litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+	litedramcore_master_p0_wrdata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+		end else begin
+			litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+		litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p0_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+		end else begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_mask <= 8'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
+	litedramcore_master_p0_wrdata_mask <= 8'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+		end else begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
+		litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
+	litedramcore_master_p0_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+		end else begin
+			litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+		litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+	litedramcore_master_p1_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+		end else begin
+			litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+		end
 	end else begin
-		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+		litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
+	litedramcore_master_p1_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+		end else begin
+			litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+		end
 	end else begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
+		litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
+	litedramcore_master_p1_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+		end else begin
+			litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
+		litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+	litedramcore_master_p1_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+		end else begin
+			litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
+		litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+	litedramcore_master_p1_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+		end else begin
+			litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
+		litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+	litedramcore_master_p1_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+		end else begin
+			litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+		end
 	end else begin
+		litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
+	litedramcore_master_p1_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+		end else begin
+			litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+		end
 	end else begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
+		litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	litedramcore_master_p1_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+		end else begin
+			litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+		end
 	end else begin
+		litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
+	litedramcore_master_p1_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+		end else begin
+			litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
+		litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
+	litedramcore_master_p1_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+		end else begin
+			litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
+		litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
+	litedramcore_master_p1_wrdata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+		end else begin
+			litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
+		litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
+	litedramcore_master_p1_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+		end else begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
+		litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
+	litedramcore_master_p1_wrdata_mask <= 8'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+		end else begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
+		litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p1_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+		end else begin
+			litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
+		litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
+	litedramcore_master_p2_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+		end else begin
+			litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
+		litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+		end else begin
+			litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+		litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_mask <= 8'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
+	litedramcore_master_p2_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+		end else begin
+			litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+		end
+	end else begin
+		litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+		end else begin
+			litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+		end
+	end else begin
+		litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+		end else begin
+			litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+		end
+	end else begin
+		litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+		end else begin
+			litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+		end
+	end else begin
+		litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+		end else begin
+			litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+		end
+	end else begin
+		litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+		end else begin
+			litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+		end
+	end else begin
+		litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+		end else begin
+			litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+		end
+	end else begin
+		litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+		end else begin
+			litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+		end
+	end else begin
+		litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p2_wrdata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+		end else begin
+			litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
+		litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	litedramcore_master_p2_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+		end else begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
+		litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
+	litedramcore_master_p2_wrdata_mask <= 8'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+		end else begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
+		litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+		end else begin
+			litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
+		litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
+	litedramcore_master_p3_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+		end else begin
+			litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+		end
 	end else begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
+		litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
+	litedramcore_master_p3_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+		end else begin
+			litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+		end
 	end else begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
+		litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+	litedramcore_master_p3_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+		end else begin
+			litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
+		litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
+	litedramcore_master_p3_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+		end else begin
+			litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
+		litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
+	litedramcore_master_p3_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+		end else begin
+			litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+		end
 	end else begin
+		litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
+	litedramcore_master_p3_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+		end else begin
+			litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
+		litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	litedramcore_master_p3_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+		end else begin
+			litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+		end
 	end else begin
+		litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
+	litedramcore_master_p3_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+		end else begin
+			litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+		end
 	end else begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
+		litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p3_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+		end else begin
+			litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+		litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
+	litedramcore_master_p3_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+		end else begin
+			litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
+		litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
+	litedramcore_master_p3_wrdata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+		end else begin
+			litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
+		litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
+	litedramcore_master_p3_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+		end else begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
+		litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata <= 64'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
+	litedramcore_master_p3_wrdata_mask <= 8'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+		end else begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
+		litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
+	litedramcore_master_p3_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+		end else begin
+			litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
-	end
-end
-assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p2_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p3_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p0_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p1_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p2_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p3_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
-always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+		litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+	end
+end
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
+always @(*) begin
+	litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+	litedramcore_csr_dfi_p0_we_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+	litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
-assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
-assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]);
-assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
-assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
-assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
+assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
+assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+	litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+	litedramcore_csr_dfi_p1_we_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+	litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
-assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
-assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]);
-assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
-assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
-assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
+assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
+assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		litedramcore_csr_dfi_p2_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+	litedramcore_csr_dfi_p2_we_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p2_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+	litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p2_cas_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
-assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
-assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]);
-assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
-assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
-assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
+assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
+assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+	litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		litedramcore_csr_dfi_p3_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+	litedramcore_csr_dfi_p3_we_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p3_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+	litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
-	end
-end
-assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
-assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
-assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]);
-assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]);
-assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
-assign main_litedramcore_inti_p3_wrdata_mask = 1'd0;
-assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
-assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
-assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
-assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
-assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
-assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
-assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
-assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
-assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
-assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
-assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
-assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
-assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
-assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
-assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
-assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
-assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
-assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
-assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
-assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
-assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
-assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
-assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
-assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
-assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
-assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
-assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
-assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
-assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
-assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
-assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
-assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
-assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
-assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
-assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
-assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
-assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
-assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
-assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
-assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
-assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
-assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
-assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
-assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
-assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
-assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
-assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
-assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
-assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
-assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
-assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
-assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
-assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
-assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
-assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
-assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
-assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
-assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
-assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
-assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
-assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
-assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
-assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
-assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
-assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
-assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
-assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
-assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
-assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-always @(*) begin
-	builder_refresher_next_state <= 2'd0;
-	builder_refresher_next_state <= builder_refresher_state;
-	case (builder_refresher_state)
-		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				builder_refresher_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					builder_refresher_next_state <= 2'd3;
+		litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+	end
+end
+assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
+assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
+assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+always @(*) begin
+	litedramcore_refresher_next_state <= 2'd0;
+	litedramcore_refresher_next_state <= litedramcore_refresher_state;
+	case (litedramcore_refresher_state)
+		1'd1: begin
+			if (litedramcore_cmd_ready) begin
+				litedramcore_refresher_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_refresher_next_state <= 2'd3;
 				end else begin
-					builder_refresher_next_state <= 1'd0;
+					litedramcore_refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				builder_refresher_next_state <= 1'd0;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
-				if (main_litedramcore_wants_refresh) begin
-					builder_refresher_next_state <= 1'd1;
+				if (litedramcore_wants_refresh) begin
+					litedramcore_refresher_next_state <= 1'd1;
 				end
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_valid <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
+			litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
 				end else begin
+					litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_valid <= 1'd0;
+			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_zqcs_executer_start <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
-			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_last <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+				end else begin
+					litedramcore_cmd_last <= 1'd1;
+				end
+			end
 		end
 		2'd3: begin
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_last <= 1'd1;
+			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_sequencer_start0 <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_cmd_ready) begin
+				litedramcore_sequencer_start0 <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
-				end
-			end
 		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
-			end
 		end
 		default: begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
-assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
-assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+	litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+		litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
 	end else begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
-assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+		litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+always @(*) begin
+	litedramcore_bankmachine0_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine0_next_state <= 4'd0;
-	builder_bankmachine0_next_state <= builder_bankmachine0_state;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_next_state <= 4'd0;
+	litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd7;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine0_refresh_req)) begin
-				builder_bankmachine0_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine0_refresh_req)) begin
+				litedramcore_bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine0_next_state <= 3'd6;
+			litedramcore_bankmachine0_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine0_next_state <= 2'd3;
+			litedramcore_bankmachine0_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine0_next_state <= 4'd8;
+			litedramcore_bankmachine0_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine0_next_state <= 1'd0;
+			litedramcore_bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-				builder_bankmachine0_next_state <= 3'd4;
+			if (litedramcore_bankmachine0_refresh_req) begin
+				litedramcore_bankmachine0_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
-								builder_bankmachine0_next_state <= 2'd2;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+								litedramcore_bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine0_next_state <= 1'd1;
+							litedramcore_bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine0_next_state <= 2'd3;
+						litedramcore_bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5820,8 +6239,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5829,9 +6248,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5842,24 +6258,71 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
 			end
 		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
 		3'd4: begin
 		end
 		3'd5: begin
@@ -5871,12 +6334,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -5887,15 +6353,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_open <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_open <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5913,18 +6379,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_close <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			if (litedramcore_bankmachine0_twtpcon_ready) begin
+				litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -5939,13 +6405,19 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -5958,12 +6430,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5974,18 +6446,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_open <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6003,12 +6472,35 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_close <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd2: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -6025,15 +6517,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6044,17 +6533,46 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 			end
 		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
 		3'd4: begin
 		end
 		3'd5: begin
@@ -6066,26 +6584,41 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6100,8 +6633,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6119,14 +6652,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6137,38 +6670,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+		litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+always @(*) begin
+	litedramcore_bankmachine1_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_next_state <= 4'd0;
+	litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine1_refresh_req)) begin
+				litedramcore_bankmachine1_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+				litedramcore_bankmachine1_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
-							end else begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+								litedramcore_bankmachine1_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6176,8 +6798,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6195,13 +6817,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6214,8 +6836,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6233,14 +6855,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -6251,127 +6873,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
-assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
-assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
-assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine1_next_state <= 4'd0;
-	builder_bankmachine1_next_state <= builder_bankmachine1_state;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				builder_bankmachine1_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine1_refresh_req)) begin
-				builder_bankmachine1_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-				builder_bankmachine1_next_state <= 3'd4;
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
-								builder_bankmachine1_next_state <= 2'd2;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
-							builder_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6379,8 +6912,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6388,8 +6921,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine1_twtpcon_ready) begin
+				litedramcore_bankmachine1_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -6405,18 +6938,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6430,12 +6963,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6446,15 +6979,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_open <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6472,18 +7005,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_close <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_open <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6498,15 +7031,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_close <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6517,35 +7053,17 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -6558,20 +7076,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -6584,35 +7117,20 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -6625,26 +7143,41 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6659,8 +7192,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6678,14 +7211,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6696,38 +7229,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+		litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+always @(*) begin
+	litedramcore_bankmachine2_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine2_next_state <= 4'd0;
+	litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine2_refresh_req)) begin
+				litedramcore_bankmachine2_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+				litedramcore_bankmachine2_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-							end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+								litedramcore_bankmachine2_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6735,8 +7357,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6754,13 +7376,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6773,8 +7395,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6792,14 +7414,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -6810,127 +7432,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
-assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
-assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine2_next_state <= 4'd0;
-	builder_bankmachine2_next_state <= builder_bankmachine2_state;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				builder_bankmachine2_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine2_refresh_req)) begin
-				builder_bankmachine2_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-				builder_bankmachine2_next_state <= 3'd4;
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
-								builder_bankmachine2_next_state <= 2'd2;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
 							end
 						end else begin
-							builder_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6938,8 +7471,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6947,8 +7480,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine2_twtpcon_ready) begin
+				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -6964,18 +7497,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6989,12 +7522,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7005,15 +7538,41 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_open <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine2_row_open <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_open <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7031,18 +7590,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_close <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_close <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7057,8 +7616,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7076,12 +7635,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7092,18 +7651,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7121,11 +7680,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7143,13 +7702,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7162,18 +7721,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7188,22 +7751,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7214,41 +7770,145 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+		litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+always @(*) begin
+	litedramcore_bankmachine3_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_next_state <= 4'd0;
+	litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine3_refresh_req)) begin
+				litedramcore_bankmachine3_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+				litedramcore_bankmachine3_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+								litedramcore_bankmachine3_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7256,8 +7916,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7275,13 +7935,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7294,8 +7954,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7313,13 +7973,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -7332,13 +7992,16 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7351,145 +8014,41 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
-assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
-assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
-assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine3_next_state <= 4'd0;
-	builder_bankmachine3_next_state <= builder_bankmachine3_state;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				builder_bankmachine3_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine3_refresh_req)) begin
-				builder_bankmachine3_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-				builder_bankmachine3_next_state <= 3'd4;
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
-								builder_bankmachine3_next_state <= 2'd2;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
-							builder_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7497,8 +8056,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7506,8 +8065,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine3_twtpcon_ready) begin
+				litedramcore_bankmachine3_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -7523,18 +8082,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7548,12 +8107,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7564,15 +8123,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_open <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_open <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7590,18 +8149,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_close <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_close <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7616,8 +8175,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7635,12 +8194,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7651,18 +8210,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7680,11 +8239,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7702,13 +8261,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7721,48 +8280,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7777,8 +8310,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7796,14 +8329,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7814,38 +8347,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+		litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+always @(*) begin
+	litedramcore_bankmachine4_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_next_state <= 4'd0;
+	litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine4_refresh_req)) begin
+				litedramcore_bankmachine4_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+				litedramcore_bankmachine4_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
-							end else begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+								litedramcore_bankmachine4_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7853,8 +8475,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7872,13 +8494,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7891,8 +8513,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7910,14 +8532,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -7928,127 +8550,38 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
-assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
-assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
-assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine4_next_state <= 4'd0;
-	builder_bankmachine4_next_state <= builder_bankmachine4_state;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				builder_bankmachine4_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine4_refresh_req)) begin
-				builder_bankmachine4_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-				builder_bankmachine4_next_state <= 3'd4;
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
-								builder_bankmachine4_next_state <= 2'd2;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
-							builder_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8056,8 +8589,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8065,8 +8598,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine4_twtpcon_ready) begin
+				litedramcore_bankmachine4_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -8082,18 +8615,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8107,12 +8640,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8123,15 +8656,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8149,39 +8682,16 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
-		end
-		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_open <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8194,37 +8704,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_close <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8239,12 +8734,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -8261,15 +8753,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8280,48 +8769,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8336,48 +8798,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-		end
 		2'd2: begin
 		end
 		2'd3: begin
@@ -8393,13 +8820,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8412,15 +8839,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8431,27 +8865,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8469,14 +8888,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+								litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8487,127 +8906,127 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
-assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
-assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+	litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+		litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
 	end else begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
-assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+		litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+always @(*) begin
+	litedramcore_bankmachine5_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine5_next_state <= 4'd0;
-	builder_bankmachine5_next_state <= builder_bankmachine5_state;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_next_state <= 4'd0;
+	litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd5;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				builder_bankmachine5_next_state <= 3'd5;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd7;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-				builder_bankmachine5_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine5_refresh_req)) begin
+				litedramcore_bankmachine5_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine5_next_state <= 3'd6;
+			litedramcore_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine5_next_state <= 2'd3;
+			litedramcore_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine5_next_state <= 4'd8;
+			litedramcore_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine5_next_state <= 1'd0;
+			litedramcore_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-				builder_bankmachine5_next_state <= 3'd4;
+			if (litedramcore_bankmachine5_refresh_req) begin
+				litedramcore_bankmachine5_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-								builder_bankmachine5_next_state <= 2'd2;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+								litedramcore_bankmachine5_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine5_next_state <= 1'd1;
+							litedramcore_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine5_next_state <= 2'd3;
+						litedramcore_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8615,8 +9034,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8624,9 +9043,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8637,23 +9053,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -8666,12 +9091,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+							end else begin
+							end
 						end else begin
 						end
 					end else begin
@@ -8682,16 +9110,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_open <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -8704,22 +9129,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_close <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			if (litedramcore_bankmachine5_twtpcon_ready) begin
+				litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -8734,13 +9174,19 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8753,12 +9199,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8769,18 +9215,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_open <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8798,18 +9241,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_close <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
-			end
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8819,35 +9262,20 @@ always @(*) begin
 		end
 		4'd8: begin
 		end
-		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
+		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8865,22 +9293,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8891,17 +9312,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8914,28 +9353,16 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -8952,13 +9379,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8971,15 +9398,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8990,27 +9424,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9028,14 +9447,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+								litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -9046,127 +9465,127 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
-assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
-assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+	litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+		litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
 	end else begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
-assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+		litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+always @(*) begin
+	litedramcore_bankmachine6_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine6_next_state <= 4'd0;
-	builder_bankmachine6_next_state <= builder_bankmachine6_state;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_next_state <= 4'd0;
+	litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd5;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				builder_bankmachine6_next_state <= 3'd5;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd7;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine6_refresh_req)) begin
-				builder_bankmachine6_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine6_refresh_req)) begin
+				litedramcore_bankmachine6_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine6_next_state <= 3'd6;
+			litedramcore_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine6_next_state <= 2'd3;
+			litedramcore_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine6_next_state <= 4'd8;
+			litedramcore_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine6_next_state <= 1'd0;
+			litedramcore_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-				builder_bankmachine6_next_state <= 3'd4;
+			if (litedramcore_bankmachine6_refresh_req) begin
+				litedramcore_bankmachine6_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
-								builder_bankmachine6_next_state <= 2'd2;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+								litedramcore_bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine6_next_state <= 1'd1;
+							litedramcore_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine6_next_state <= 2'd3;
+						litedramcore_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
@@ -9174,8 +9593,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9183,9 +9602,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9196,23 +9612,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -9225,12 +9650,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+							end else begin
+							end
 						end else begin
 						end
 					end else begin
@@ -9241,15 +9669,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9267,34 +9695,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
-	case (builder_bankmachine6_state)
-		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
-		end
-		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9312,12 +9714,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -9328,21 +9733,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (litedramcore_bankmachine6_twtpcon_ready) begin
+				litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9357,16 +9759,19 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -9379,15 +9784,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -9398,15 +9800,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_open <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9424,22 +9826,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_close <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-			end
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9454,8 +9852,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9473,15 +9871,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
-							end
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -9492,13 +9887,19 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -9511,28 +9912,16 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -9549,13 +9938,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -9568,8 +9957,38 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine6_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9587,14 +10006,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+								litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -9605,127 +10024,127 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
-assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
-assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+	litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+		litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
 	end else begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
-assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+		litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+always @(*) begin
+	litedramcore_bankmachine7_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine7_next_state <= 4'd0;
-	builder_bankmachine7_next_state <= builder_bankmachine7_state;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_next_state <= 4'd0;
+	litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd5;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				builder_bankmachine7_next_state <= 3'd5;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd7;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine7_refresh_req)) begin
-				builder_bankmachine7_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine7_refresh_req)) begin
+				litedramcore_bankmachine7_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine7_next_state <= 3'd6;
+			litedramcore_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine7_next_state <= 2'd3;
+			litedramcore_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine7_next_state <= 4'd8;
+			litedramcore_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine7_next_state <= 1'd0;
+			litedramcore_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-				builder_bankmachine7_next_state <= 3'd4;
+			if (litedramcore_bankmachine7_refresh_req) begin
+				litedramcore_bankmachine7_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
-								builder_bankmachine7_next_state <= 2'd2;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+								litedramcore_bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine7_next_state <= 1'd1;
+							litedramcore_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine7_next_state <= 2'd3;
+						litedramcore_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
@@ -9733,8 +10152,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9742,9 +10161,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9755,23 +10171,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -9784,12 +10209,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+							end else begin
+							end
 						end else begin
 						end
 					end else begin
@@ -9800,16 +10228,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_open <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -9822,22 +10247,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_close <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9852,8 +10292,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9861,6 +10301,9 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
+			if (litedramcore_bankmachine7_twtpcon_ready) begin
+				litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9871,34 +10314,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9912,20 +10343,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_open <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -9938,37 +10381,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_close <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9983,22 +10411,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10009,17 +10430,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -10032,28 +10471,16 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -10070,13 +10497,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -10089,15 +10516,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10108,27 +10542,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -10146,14 +10565,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+								litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -10164,265 +10583,266 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_rdcmdphase = (main_k7ddrphy_rdphase_storage - 1'd1);
-assign main_litedramcore_wrcmdphase = (main_k7ddrphy_wrphase_storage - 1'd1);
-assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
-assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
-assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
-assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
-assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
-assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
-assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
-assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
-assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
-assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign litedramcore_rdcmdphase = (k7ddrphy_rdphase_storage - 1'd1);
+assign litedramcore_wrcmdphase = (k7ddrphy_wrphase_storage - 1'd1);
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
 always @(*) begin
-	main_litedramcore_choose_cmd_valids <= 8'd0;
-	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids <= 8'd0;
+	litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
 end
-assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
-assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
-assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
-assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
-assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
-assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
-assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
+	litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
+	litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
+	litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	litedramcore_bankmachine0_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	litedramcore_bankmachine1_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	litedramcore_bankmachine2_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	litedramcore_bankmachine3_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	litedramcore_bankmachine4_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	litedramcore_bankmachine5_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	litedramcore_bankmachine6_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	litedramcore_bankmachine7_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
 end
-assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-	main_litedramcore_choose_req_valids <= 8'd0;
-	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids <= 8'd0;
+	litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
 end
-assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
-assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
-assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
-assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
-assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
-assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
-assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
+	litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
+	litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
+	litedramcore_choose_req_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
 	end
 end
-assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
-assign main_litedramcore_dfi_p0_reset_n = 1'd1;
-assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}};
-assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}};
-assign main_litedramcore_dfi_p1_reset_n = 1'd1;
-assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}};
-assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}};
-assign main_litedramcore_dfi_p2_reset_n = 1'd1;
-assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}};
-assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}};
-assign main_litedramcore_dfi_p3_reset_n = 1'd1;
-assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
-assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
-assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
 always @(*) begin
-	builder_multiplexer_next_state <= 4'd0;
-	builder_multiplexer_next_state <= builder_multiplexer_state;
-	case (builder_multiplexer_state)
+	litedramcore_multiplexer_next_state <= 4'd0;
+	litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (main_litedramcore_read_available) begin
-				if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
-					builder_multiplexer_next_state <= 2'd3;
+			if (litedramcore_read_available) begin
+				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+					litedramcore_multiplexer_next_state <= 2'd3;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
-			if (main_litedramcore_cmd_last) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_cmd_last) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_twtrcon_ready) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_twtrcon_ready) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			builder_multiplexer_next_state <= 3'd5;
+			litedramcore_multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			builder_multiplexer_next_state <= 3'd6;
+			litedramcore_multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_multiplexer_next_state <= 3'd7;
+			litedramcore_multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			builder_multiplexer_next_state <= 4'd8;
+			litedramcore_multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_multiplexer_next_state <= 4'd9;
+			litedramcore_multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			builder_multiplexer_next_state <= 4'd10;
+			litedramcore_multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			builder_multiplexer_next_state <= 1'd1;
+			litedramcore_multiplexer_next_state <= 1'd1;
 		end
 		default: begin
-			if (main_litedramcore_write_available) begin
-				if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
-					builder_multiplexer_next_state <= 3'd4;
+			if (litedramcore_write_available) begin
+				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+					litedramcore_multiplexer_next_state <= 3'd4;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel2 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel0 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((k7ddrphy_wrphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
+			if ((litedramcore_wrcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 		2'd2: begin
+			litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -10441,26 +10861,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((k7ddrphy_rdphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
+			if ((litedramcore_rdcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
 		end
 		2'd2: begin
+			litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -10479,23 +10896,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel1 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_k7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((k7ddrphy_wrphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if ((litedramcore_wrcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -10517,20 +10930,21 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_k7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((k7ddrphy_rdphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if ((litedramcore_rdcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en1 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			litedramcore_en1 <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -10551,17 +10965,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel2 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((k7ddrphy_wrphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -10583,17 +10999,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((k7ddrphy_rdphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_want_activates <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -10614,15 +11037,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel3 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((k7ddrphy_wrphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -10643,18 +11075,20 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((k7ddrphy_rdphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en0 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -10675,19 +11109,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			litedramcore_en0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -10708,23 +11141,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel0 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_reads <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_k7ddrphy_wrphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
 		end
 		2'd2: begin
-			main_litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -10743,23 +11172,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_k7ddrphy_rdphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
+			litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_writes <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -10782,15 +11205,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_k7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
 			end
 		end
 		2'd2: begin
@@ -10812,2184 +11233,2206 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_k7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
-			end
-		end
-	endcase
-end
-assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
-assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12;
-assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13;
-assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14;
-assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
-assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15;
-assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16;
-assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17;
-assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
-assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18;
-assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19;
-assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20;
-assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
-assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21;
-assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22;
-assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23;
-assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
-assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24;
-assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25;
-assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26;
-assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
-assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27;
-assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28;
-assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29;
-assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
-assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30;
-assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31;
-assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32;
-assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
-assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33;
-assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34;
-assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
-assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
-assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
-assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
-always @(*) begin
-	main_litedramcore_interface_wdata <= 256'd0;
-	case ({builder_new_master_wdata_ready1})
-		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+			end
+		end
+	endcase
+end
+assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
+assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
+always @(*) begin
+	litedramcore_interface_wdata <= 256'd0;
+	case ({litedramcore_new_master_wdata_ready1})
+		1'd1: begin
+			litedramcore_interface_wdata <= user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 32'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata_we <= 32'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 end
-assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
-assign builder_roundrobin0_grant = 1'd0;
-assign builder_roundrobin1_grant = 1'd0;
-assign builder_roundrobin2_grant = 1'd0;
-assign builder_roundrobin3_grant = 1'd0;
-assign builder_roundrobin4_grant = 1'd0;
-assign builder_roundrobin5_grant = 1'd0;
-assign builder_roundrobin6_grant = 1'd0;
-assign builder_roundrobin7_grant = 1'd0;
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-	builder_next_state <= 2'd0;
-	builder_next_state <= builder_state;
-	case (builder_state)
+	litedramcore_next_state <= 2'd0;
+	litedramcore_next_state <= litedramcore_state;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_next_state <= 2'd2;
+			litedramcore_next_state <= 2'd2;
 		end
 		2'd2: begin
-			builder_next_state <= 1'd0;
+			litedramcore_next_state <= 1'd0;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_next_state <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_dat_r <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value2 <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_ack <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
-			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value_ce2 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value_ce2 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 32'd0;
-	case (builder_state)
+	litedramcore_adr_next_value1 <= 14'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
-	case (builder_state)
+	litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_dat_r <= 32'd0;
-	case (builder_state)
+	litedramcore_we_next_value2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value1 <= 14'd0;
-	case (builder_state)
+	litedramcore_we_next_value_ce2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value1 <= 1'd0;
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
 			end
 		end
 	endcase
 end
-assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
-assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
-assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r;
-assign builder_litedramcore_wishbone_sel = main_wb_bus_sel;
-assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc;
-assign builder_litedramcore_wishbone_stb = main_wb_bus_stb;
-assign main_wb_bus_ack = builder_litedramcore_wishbone_ack;
-assign builder_litedramcore_wishbone_we = main_wb_bus_we;
-assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
-assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
-assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
-assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_done0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_re <= interface0_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_done0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
 	end
 end
-assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_error0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_error0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
-assign builder_csrbank0_init_done0_w = main_init_done_storage;
-assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
-assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rst0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rst0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[3:0];
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_dly_sel0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+	csrbank1_dly_sel0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_half_sys8x_taps0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+	csrbank1_half_sys8x_taps0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_wlevel_strobe_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wlevel_en0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_wlevel_strobe_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+	csrbank1_wlevel_en0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
 	end
 end
-assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_cdly_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_wlevel_strobe_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		k7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_k7ddrphy_cdly_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_wlevel_strobe_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		k7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_cdly_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_cdly_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		k7ddrphy_cdly_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_cdly_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_cdly_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		k7ddrphy_cdly_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0];
+assign k7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_cdly_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		k7ddrphy_cdly_inc_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_cdly_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		k7ddrphy_cdly_inc_re <= interface1_bank_bus_we;
 	end
 end
-assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_rdly_dq_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_rdly_dq_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		k7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_rdly_dq_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_rdly_dq_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		k7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_rdly_dq_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_rdly_dq_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		k7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_rdly_dq_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_rdly_dq_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		k7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
 	end
 end
-assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		k7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		k7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		k7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		k7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_wdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_wdly_dq_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_wdly_dq_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		k7ddrphy_wdly_dq_rst_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_k7ddrphy_wdly_dq_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_wdly_dq_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		k7ddrphy_wdly_dq_rst_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_wdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_wdly_dq_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_wdly_dq_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		k7ddrphy_wdly_dq_inc_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_k7ddrphy_wdly_dq_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_wdly_dq_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		k7ddrphy_wdly_dq_inc_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_wdly_dqs_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
-		main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_wdly_dqs_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+		k7ddrphy_wdly_dqs_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
-		main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_wdly_dqs_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+		k7ddrphy_wdly_dqs_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_wdly_dqs_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_wdly_dqs_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+		k7ddrphy_wdly_dqs_inc_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_wdly_dqs_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_wdly_dqs_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+		k7ddrphy_wdly_dqs_inc_re <= interface1_bank_bus_we;
 	end
 end
-assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
-		main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+		k7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
-		main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+		k7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign k7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
-		main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+		k7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
-		main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+		k7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rdphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank1_rdphase0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rdphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_wrphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wrphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank1_wrphase0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage;
-assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0];
-assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0];
-assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
-assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
+assign csrbank1_rst0_w = k7ddrphy_rst_storage;
+assign csrbank1_dly_sel0_w = k7ddrphy_dly_sel_storage[3:0];
+assign csrbank1_half_sys8x_taps0_w = k7ddrphy_half_sys8x_taps_storage[4:0];
+assign csrbank1_wlevel_en0_w = k7ddrphy_wlevel_en_storage;
+assign csrbank1_rdphase0_w = k7ddrphy_rdphase_storage[1:0];
+assign csrbank1_wrphase0_w = k7ddrphy_wrphase_storage[1:0];
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_control0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_control0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi2_wrdata1_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi2_wrdata1_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_rddata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi2_rddata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_rddata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi2_rddata1_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_rddata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi2_rddata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_rddata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi2_rddata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
+		csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
+		csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
+		litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
+		litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
+		csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
+		csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
+		csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
+		csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
+		csrbank2_dfii_pi3_wrdata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
+		csrbank2_dfii_pi3_wrdata1_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
+		csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
+		csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_rddata1_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
+		csrbank2_dfii_pi3_rddata1_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_rddata1_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
+		csrbank2_dfii_pi3_rddata1_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_rddata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
+		csrbank2_dfii_pi3_rddata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_rddata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
+		csrbank2_dfii_pi3_rddata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_sel = main_litedramcore_storage[0];
-assign main_litedramcore_cke = main_litedramcore_storage[1];
-assign main_litedramcore_odt = main_litedramcore_storage[2];
-assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[63:32];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[63:32];
-assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[63:32];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[63:32];
-assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[63:32];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[63:32];
-assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[63:32];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[63:32];
-assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
-assign builder_csr_interconnect_adr = builder_litedramcore_adr;
-assign builder_csr_interconnect_we = builder_litedramcore_we;
-assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
-assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r;
-assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-always @(*) begin
-	builder_rhs_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+assign litedramcore_sel = litedramcore_storage[0];
+assign litedramcore_cke = litedramcore_storage[1];
+assign litedramcore_odt = litedramcore_storage[2];
+assign litedramcore_reset_n = litedramcore_storage[3];
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
+assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
+assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
+assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
+assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
+assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32];
+assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0];
+assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we;
+assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
+assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
+assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
+assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
+assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
+assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32];
+assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0];
+assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we;
+assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
+assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
+assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
+assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
+assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
+assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
+assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0];
+assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[63:32];
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_rddata_status[63:32];
+assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_rddata_status[31:0];
+assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata0_we;
+assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
+assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
+assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
+assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
+assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
+assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
+assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0];
+assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[63:32];
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_rddata_status[63:32];
+assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_rddata_status[31:0];
+assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata0_we;
+assign csr_interconnect_adr = litedramcore_adr;
+assign csr_interconnect_we = litedramcore_we;
+assign csr_interconnect_dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = csr_interconnect_dat_r;
+assign interface0_bank_bus_adr = csr_interconnect_adr;
+assign interface1_bank_bus_adr = csr_interconnect_adr;
+assign interface2_bank_bus_adr = csr_interconnect_adr;
+assign interface0_bank_bus_we = csr_interconnect_we;
+assign interface1_bank_bus_we = csr_interconnect_we;
+assign interface2_bank_bus_we = csr_interconnect_we;
+assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
+assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+always @(*) begin
+	rhs_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed1 <= 15'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed1 <= 15'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed2 <= 3'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed2 <= 3'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed1 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed1 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed2 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed2 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed6 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed6 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed7 <= 15'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed7 <= 15'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed8 <= 3'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed8 <= 3'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed9 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed9 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed10 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed10 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed11 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed11 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed12 <= 22'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed12 <= 22'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed13 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed13 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed13 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed14 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed14 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed15 <= 22'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed15 <= 22'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed16 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed16 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed16 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed17 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed17 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed18 <= 22'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed18 <= 22'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed19 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed19 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed19 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed20 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed20 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed21 <= 22'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed21 <= 22'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed22 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed22 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed22 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed23 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed23 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed24 <= 22'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed24 <= 22'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed25 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed25 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed25 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed26 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed26 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed27 <= 22'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed27 <= 22'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed28 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed28 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed28 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed29 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed29 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed30 <= 22'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed30 <= 22'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed31 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed31 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed31 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed32 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed32 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed33 <= 22'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed33 <= 22'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed34 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed34 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed34 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed35 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed35 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed0 <= 3'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed0 <= 3'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed0 <= main_litedramcore_nop_ba[2:0];
+			array_muxed0 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed1 <= 15'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed1 <= 15'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed1 <= main_litedramcore_nop_a;
+			array_muxed1 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
+			array_muxed1 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed2 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed2 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed2 <= 1'd0;
+			array_muxed2 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed3 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed3 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed3 <= 1'd0;
+			array_muxed3 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed4 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed4 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed4 <= 1'd0;
+			array_muxed4 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed5 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed5 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed5 <= 1'd0;
+			array_muxed5 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed6 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed6 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed6 <= 1'd0;
+			array_muxed6 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed7 <= 3'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed7 <= 3'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed7 <= main_litedramcore_nop_ba[2:0];
+			array_muxed7 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed8 <= 15'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed8 <= 15'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed8 <= main_litedramcore_nop_a;
+			array_muxed8 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
+			array_muxed8 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed9 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed9 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed9 <= 1'd0;
+			array_muxed9 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed10 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed10 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed10 <= 1'd0;
+			array_muxed10 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed11 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed11 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed11 <= 1'd0;
+			array_muxed11 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed12 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed12 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed12 <= 1'd0;
+			array_muxed12 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed13 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed13 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed13 <= 1'd0;
+			array_muxed13 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed14 <= 3'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed14 <= 3'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed14 <= main_litedramcore_nop_ba[2:0];
+			array_muxed14 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed15 <= 15'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed15 <= 15'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed15 <= main_litedramcore_nop_a;
+			array_muxed15 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
+			array_muxed15 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed16 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed16 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed16 <= 1'd0;
+			array_muxed16 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed17 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed17 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed17 <= 1'd0;
+			array_muxed17 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed18 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed18 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed18 <= 1'd0;
+			array_muxed18 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed19 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed19 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed19 <= 1'd0;
+			array_muxed19 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed20 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed20 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed20 <= 1'd0;
+			array_muxed20 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed21 <= 3'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed21 <= 3'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed21 <= main_litedramcore_nop_ba[2:0];
+			array_muxed21 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed22 <= 15'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed22 <= 15'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed22 <= main_litedramcore_nop_a;
+			array_muxed22 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
+			array_muxed22 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed23 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed23 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed23 <= 1'd0;
+			array_muxed23 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed24 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed24 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed24 <= 1'd0;
+			array_muxed24 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed25 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed25 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed25 <= 1'd0;
+			array_muxed25 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed26 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed26 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed26 <= 1'd0;
+			array_muxed26 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed27 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed27 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed27 <= 1'd0;
+			array_muxed27 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
+assign xilinxasyncresetsynchronizerimpl0 = (~locked);
+assign xilinxasyncresetsynchronizerimpl1 = (~locked);
+assign xilinxasyncresetsynchronizerimpl2 = (~locked);
+assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 
 
 //------------------------------------------------------------------------------
@@ -12997,1295 +13440,1295 @@ assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-	if ((main_reset_counter != 1'd0)) begin
-		main_reset_counter <= (main_reset_counter - 1'd1);
+	if ((reset_counter != 1'd0)) begin
+		reset_counter <= (reset_counter - 1'd1);
 	end else begin
-		main_ic_reset <= 1'd0;
+		ic_reset <= 1'd0;
 	end
 	if (iodelay_rst) begin
-		main_reset_counter <= 4'd15;
-		main_ic_reset <= 1'd1;
+		reset_counter <= 4'd15;
+		ic_reset <= 1'd1;
 	end
 end
 
 always @(posedge sys_clk) begin
-	main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline;
-	main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip0_value0 <= (main_k7ddrphy_bitslip0_value0 + 1'd1);
+	k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline;
+	k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip0_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip0_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip0_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip0_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip1_value0 <= (main_k7ddrphy_bitslip1_value0 + 1'd1);
+	k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip1_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip1_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip1_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip1_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip2_value0 <= (main_k7ddrphy_bitslip2_value0 + 1'd1);
+	k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip2_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip2_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip2_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip2_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip3_value0 <= (main_k7ddrphy_bitslip3_value0 + 1'd1);
+	k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip3_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip3_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip3_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip3_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip0_value1 <= (main_k7ddrphy_bitslip0_value1 + 1'd1);
+	k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip0_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip0_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip0_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[4], main_k7ddrphy_dfi_p3_wrdata_mask[0], main_k7ddrphy_dfi_p2_wrdata_mask[4], main_k7ddrphy_dfi_p2_wrdata_mask[0], main_k7ddrphy_dfi_p1_wrdata_mask[4], main_k7ddrphy_dfi_p1_wrdata_mask[0], main_k7ddrphy_dfi_p0_wrdata_mask[4], main_k7ddrphy_dfi_p0_wrdata_mask[0]}, main_k7ddrphy_bitslip0_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip1_value1 <= (main_k7ddrphy_bitslip1_value1 + 1'd1);
+	k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip1_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip1_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip1_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[5], main_k7ddrphy_dfi_p3_wrdata_mask[1], main_k7ddrphy_dfi_p2_wrdata_mask[5], main_k7ddrphy_dfi_p2_wrdata_mask[1], main_k7ddrphy_dfi_p1_wrdata_mask[5], main_k7ddrphy_dfi_p1_wrdata_mask[1], main_k7ddrphy_dfi_p0_wrdata_mask[5], main_k7ddrphy_dfi_p0_wrdata_mask[1]}, main_k7ddrphy_bitslip1_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip2_value1 <= (main_k7ddrphy_bitslip2_value1 + 1'd1);
+	k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip2_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip2_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip2_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[6], main_k7ddrphy_dfi_p3_wrdata_mask[2], main_k7ddrphy_dfi_p2_wrdata_mask[6], main_k7ddrphy_dfi_p2_wrdata_mask[2], main_k7ddrphy_dfi_p1_wrdata_mask[6], main_k7ddrphy_dfi_p1_wrdata_mask[2], main_k7ddrphy_dfi_p0_wrdata_mask[6], main_k7ddrphy_dfi_p0_wrdata_mask[2]}, main_k7ddrphy_bitslip2_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip3_value1 <= (main_k7ddrphy_bitslip3_value1 + 1'd1);
+	k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip3_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip3_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip3_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[7], main_k7ddrphy_dfi_p3_wrdata_mask[3], main_k7ddrphy_dfi_p2_wrdata_mask[7], main_k7ddrphy_dfi_p2_wrdata_mask[3], main_k7ddrphy_dfi_p1_wrdata_mask[7], main_k7ddrphy_dfi_p1_wrdata_mask[3], main_k7ddrphy_dfi_p0_wrdata_mask[7], main_k7ddrphy_dfi_p0_wrdata_mask[3]}, main_k7ddrphy_bitslip3_r1[15:8]};
-	main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dq_oe_delay_tappeddelayline;
-	main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip0_value2 <= (main_k7ddrphy_bitslip0_value2 + 1'd1);
+	k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]};
+	k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline;
+	k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip0_value2 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip0_value2 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip0_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[32], main_k7ddrphy_dfi_p3_wrdata[0], main_k7ddrphy_dfi_p2_wrdata[32], main_k7ddrphy_dfi_p2_wrdata[0], main_k7ddrphy_dfi_p1_wrdata[32], main_k7ddrphy_dfi_p1_wrdata[0], main_k7ddrphy_dfi_p0_wrdata[32], main_k7ddrphy_dfi_p0_wrdata[0]}, main_k7ddrphy_bitslip0_r2[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip0_value3 <= (main_k7ddrphy_bitslip0_value3 + 1'd1);
+	k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip0_value3 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip0_value3 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip0_r3 <= {main_k7ddrphy_bitslip03, main_k7ddrphy_bitslip0_r3[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip1_value2 <= (main_k7ddrphy_bitslip1_value2 + 1'd1);
+	k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip1_value2 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip1_value2 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip1_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[33], main_k7ddrphy_dfi_p3_wrdata[1], main_k7ddrphy_dfi_p2_wrdata[33], main_k7ddrphy_dfi_p2_wrdata[1], main_k7ddrphy_dfi_p1_wrdata[33], main_k7ddrphy_dfi_p1_wrdata[1], main_k7ddrphy_dfi_p0_wrdata[33], main_k7ddrphy_dfi_p0_wrdata[1]}, main_k7ddrphy_bitslip1_r2[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip1_value3 <= (main_k7ddrphy_bitslip1_value3 + 1'd1);
+	k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip1_value3 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip1_value3 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip1_r3 <= {main_k7ddrphy_bitslip13, main_k7ddrphy_bitslip1_r3[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip2_value2 <= (main_k7ddrphy_bitslip2_value2 + 1'd1);
+	k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip2_value2 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip2_value2 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip2_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[34], main_k7ddrphy_dfi_p3_wrdata[2], main_k7ddrphy_dfi_p2_wrdata[34], main_k7ddrphy_dfi_p2_wrdata[2], main_k7ddrphy_dfi_p1_wrdata[34], main_k7ddrphy_dfi_p1_wrdata[2], main_k7ddrphy_dfi_p0_wrdata[34], main_k7ddrphy_dfi_p0_wrdata[2]}, main_k7ddrphy_bitslip2_r2[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip2_value3 <= (main_k7ddrphy_bitslip2_value3 + 1'd1);
+	k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip2_value3 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip2_value3 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip2_r3 <= {main_k7ddrphy_bitslip23, main_k7ddrphy_bitslip2_r3[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip3_value2 <= (main_k7ddrphy_bitslip3_value2 + 1'd1);
+	k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip3_value2 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip3_value2 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip3_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[35], main_k7ddrphy_dfi_p3_wrdata[3], main_k7ddrphy_dfi_p2_wrdata[35], main_k7ddrphy_dfi_p2_wrdata[3], main_k7ddrphy_dfi_p1_wrdata[35], main_k7ddrphy_dfi_p1_wrdata[3], main_k7ddrphy_dfi_p0_wrdata[35], main_k7ddrphy_dfi_p0_wrdata[3]}, main_k7ddrphy_bitslip3_r2[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip3_value3 <= (main_k7ddrphy_bitslip3_value3 + 1'd1);
+	k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip3_value3 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip3_value3 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip3_r3 <= {main_k7ddrphy_bitslip33, main_k7ddrphy_bitslip3_r3[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip4_value0 <= (main_k7ddrphy_bitslip4_value0 + 1'd1);
+	k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip4_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip4_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip4_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[36], main_k7ddrphy_dfi_p3_wrdata[4], main_k7ddrphy_dfi_p2_wrdata[36], main_k7ddrphy_dfi_p2_wrdata[4], main_k7ddrphy_dfi_p1_wrdata[36], main_k7ddrphy_dfi_p1_wrdata[4], main_k7ddrphy_dfi_p0_wrdata[36], main_k7ddrphy_dfi_p0_wrdata[4]}, main_k7ddrphy_bitslip4_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip4_value1 <= (main_k7ddrphy_bitslip4_value1 + 1'd1);
+	k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip4_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip4_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip4_r1 <= {main_k7ddrphy_bitslip41, main_k7ddrphy_bitslip4_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip5_value0 <= (main_k7ddrphy_bitslip5_value0 + 1'd1);
+	k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip5_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip5_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip5_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[37], main_k7ddrphy_dfi_p3_wrdata[5], main_k7ddrphy_dfi_p2_wrdata[37], main_k7ddrphy_dfi_p2_wrdata[5], main_k7ddrphy_dfi_p1_wrdata[37], main_k7ddrphy_dfi_p1_wrdata[5], main_k7ddrphy_dfi_p0_wrdata[37], main_k7ddrphy_dfi_p0_wrdata[5]}, main_k7ddrphy_bitslip5_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip5_value1 <= (main_k7ddrphy_bitslip5_value1 + 1'd1);
+	k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip5_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip5_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip5_r1 <= {main_k7ddrphy_bitslip51, main_k7ddrphy_bitslip5_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip6_value0 <= (main_k7ddrphy_bitslip6_value0 + 1'd1);
+	k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip6_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip6_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip6_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[38], main_k7ddrphy_dfi_p3_wrdata[6], main_k7ddrphy_dfi_p2_wrdata[38], main_k7ddrphy_dfi_p2_wrdata[6], main_k7ddrphy_dfi_p1_wrdata[38], main_k7ddrphy_dfi_p1_wrdata[6], main_k7ddrphy_dfi_p0_wrdata[38], main_k7ddrphy_dfi_p0_wrdata[6]}, main_k7ddrphy_bitslip6_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip6_value1 <= (main_k7ddrphy_bitslip6_value1 + 1'd1);
+	k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip6_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip6_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip6_r1 <= {main_k7ddrphy_bitslip61, main_k7ddrphy_bitslip6_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip7_value0 <= (main_k7ddrphy_bitslip7_value0 + 1'd1);
+	k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip7_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip7_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip7_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[39], main_k7ddrphy_dfi_p3_wrdata[7], main_k7ddrphy_dfi_p2_wrdata[39], main_k7ddrphy_dfi_p2_wrdata[7], main_k7ddrphy_dfi_p1_wrdata[39], main_k7ddrphy_dfi_p1_wrdata[7], main_k7ddrphy_dfi_p0_wrdata[39], main_k7ddrphy_dfi_p0_wrdata[7]}, main_k7ddrphy_bitslip7_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip7_value1 <= (main_k7ddrphy_bitslip7_value1 + 1'd1);
+	k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip7_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip7_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip7_r1 <= {main_k7ddrphy_bitslip71, main_k7ddrphy_bitslip7_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip8_value0 <= (main_k7ddrphy_bitslip8_value0 + 1'd1);
+	k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip8_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip8_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip8_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[40], main_k7ddrphy_dfi_p3_wrdata[8], main_k7ddrphy_dfi_p2_wrdata[40], main_k7ddrphy_dfi_p2_wrdata[8], main_k7ddrphy_dfi_p1_wrdata[40], main_k7ddrphy_dfi_p1_wrdata[8], main_k7ddrphy_dfi_p0_wrdata[40], main_k7ddrphy_dfi_p0_wrdata[8]}, main_k7ddrphy_bitslip8_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip8_value1 <= (main_k7ddrphy_bitslip8_value1 + 1'd1);
+	k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip8_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip8_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip8_r1 <= {main_k7ddrphy_bitslip81, main_k7ddrphy_bitslip8_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip9_value0 <= (main_k7ddrphy_bitslip9_value0 + 1'd1);
+	k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip9_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip9_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip9_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[41], main_k7ddrphy_dfi_p3_wrdata[9], main_k7ddrphy_dfi_p2_wrdata[41], main_k7ddrphy_dfi_p2_wrdata[9], main_k7ddrphy_dfi_p1_wrdata[41], main_k7ddrphy_dfi_p1_wrdata[9], main_k7ddrphy_dfi_p0_wrdata[41], main_k7ddrphy_dfi_p0_wrdata[9]}, main_k7ddrphy_bitslip9_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip9_value1 <= (main_k7ddrphy_bitslip9_value1 + 1'd1);
+	k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip9_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip9_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip9_r1 <= {main_k7ddrphy_bitslip91, main_k7ddrphy_bitslip9_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip10_value0 <= (main_k7ddrphy_bitslip10_value0 + 1'd1);
+	k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip10_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip10_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip10_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[42], main_k7ddrphy_dfi_p3_wrdata[10], main_k7ddrphy_dfi_p2_wrdata[42], main_k7ddrphy_dfi_p2_wrdata[10], main_k7ddrphy_dfi_p1_wrdata[42], main_k7ddrphy_dfi_p1_wrdata[10], main_k7ddrphy_dfi_p0_wrdata[42], main_k7ddrphy_dfi_p0_wrdata[10]}, main_k7ddrphy_bitslip10_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip10_value1 <= (main_k7ddrphy_bitslip10_value1 + 1'd1);
+	k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip10_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip10_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip10_r1 <= {main_k7ddrphy_bitslip101, main_k7ddrphy_bitslip10_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip11_value0 <= (main_k7ddrphy_bitslip11_value0 + 1'd1);
+	k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip11_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip11_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip11_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[43], main_k7ddrphy_dfi_p3_wrdata[11], main_k7ddrphy_dfi_p2_wrdata[43], main_k7ddrphy_dfi_p2_wrdata[11], main_k7ddrphy_dfi_p1_wrdata[43], main_k7ddrphy_dfi_p1_wrdata[11], main_k7ddrphy_dfi_p0_wrdata[43], main_k7ddrphy_dfi_p0_wrdata[11]}, main_k7ddrphy_bitslip11_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip11_value1 <= (main_k7ddrphy_bitslip11_value1 + 1'd1);
+	k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip11_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip11_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip11_r1 <= {main_k7ddrphy_bitslip111, main_k7ddrphy_bitslip11_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip12_value0 <= (main_k7ddrphy_bitslip12_value0 + 1'd1);
+	k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip12_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip12_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip12_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[44], main_k7ddrphy_dfi_p3_wrdata[12], main_k7ddrphy_dfi_p2_wrdata[44], main_k7ddrphy_dfi_p2_wrdata[12], main_k7ddrphy_dfi_p1_wrdata[44], main_k7ddrphy_dfi_p1_wrdata[12], main_k7ddrphy_dfi_p0_wrdata[44], main_k7ddrphy_dfi_p0_wrdata[12]}, main_k7ddrphy_bitslip12_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip12_value1 <= (main_k7ddrphy_bitslip12_value1 + 1'd1);
+	k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip12_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip12_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip12_r1 <= {main_k7ddrphy_bitslip121, main_k7ddrphy_bitslip12_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip13_value0 <= (main_k7ddrphy_bitslip13_value0 + 1'd1);
+	k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip13_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip13_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip13_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[45], main_k7ddrphy_dfi_p3_wrdata[13], main_k7ddrphy_dfi_p2_wrdata[45], main_k7ddrphy_dfi_p2_wrdata[13], main_k7ddrphy_dfi_p1_wrdata[45], main_k7ddrphy_dfi_p1_wrdata[13], main_k7ddrphy_dfi_p0_wrdata[45], main_k7ddrphy_dfi_p0_wrdata[13]}, main_k7ddrphy_bitslip13_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip13_value1 <= (main_k7ddrphy_bitslip13_value1 + 1'd1);
+	k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip13_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip13_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip13_r1 <= {main_k7ddrphy_bitslip131, main_k7ddrphy_bitslip13_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip14_value0 <= (main_k7ddrphy_bitslip14_value0 + 1'd1);
+	k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip14_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip14_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip14_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[46], main_k7ddrphy_dfi_p3_wrdata[14], main_k7ddrphy_dfi_p2_wrdata[46], main_k7ddrphy_dfi_p2_wrdata[14], main_k7ddrphy_dfi_p1_wrdata[46], main_k7ddrphy_dfi_p1_wrdata[14], main_k7ddrphy_dfi_p0_wrdata[46], main_k7ddrphy_dfi_p0_wrdata[14]}, main_k7ddrphy_bitslip14_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip14_value1 <= (main_k7ddrphy_bitslip14_value1 + 1'd1);
+	k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip14_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip14_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip14_r1 <= {main_k7ddrphy_bitslip141, main_k7ddrphy_bitslip14_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip15_value0 <= (main_k7ddrphy_bitslip15_value0 + 1'd1);
+	k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip15_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip15_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip15_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[47], main_k7ddrphy_dfi_p3_wrdata[15], main_k7ddrphy_dfi_p2_wrdata[47], main_k7ddrphy_dfi_p2_wrdata[15], main_k7ddrphy_dfi_p1_wrdata[47], main_k7ddrphy_dfi_p1_wrdata[15], main_k7ddrphy_dfi_p0_wrdata[47], main_k7ddrphy_dfi_p0_wrdata[15]}, main_k7ddrphy_bitslip15_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip15_value1 <= (main_k7ddrphy_bitslip15_value1 + 1'd1);
+	k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip15_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip15_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip15_r1 <= {main_k7ddrphy_bitslip151, main_k7ddrphy_bitslip15_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip16_value0 <= (main_k7ddrphy_bitslip16_value0 + 1'd1);
+	k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip16_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip16_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip16_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[48], main_k7ddrphy_dfi_p3_wrdata[16], main_k7ddrphy_dfi_p2_wrdata[48], main_k7ddrphy_dfi_p2_wrdata[16], main_k7ddrphy_dfi_p1_wrdata[48], main_k7ddrphy_dfi_p1_wrdata[16], main_k7ddrphy_dfi_p0_wrdata[48], main_k7ddrphy_dfi_p0_wrdata[16]}, main_k7ddrphy_bitslip16_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip16_value1 <= (main_k7ddrphy_bitslip16_value1 + 1'd1);
+	k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip16_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip16_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip16_r1 <= {main_k7ddrphy_bitslip161, main_k7ddrphy_bitslip16_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip17_value0 <= (main_k7ddrphy_bitslip17_value0 + 1'd1);
+	k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip17_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip17_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip17_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[49], main_k7ddrphy_dfi_p3_wrdata[17], main_k7ddrphy_dfi_p2_wrdata[49], main_k7ddrphy_dfi_p2_wrdata[17], main_k7ddrphy_dfi_p1_wrdata[49], main_k7ddrphy_dfi_p1_wrdata[17], main_k7ddrphy_dfi_p0_wrdata[49], main_k7ddrphy_dfi_p0_wrdata[17]}, main_k7ddrphy_bitslip17_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip17_value1 <= (main_k7ddrphy_bitslip17_value1 + 1'd1);
+	k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip17_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip17_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip17_r1 <= {main_k7ddrphy_bitslip171, main_k7ddrphy_bitslip17_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip18_value0 <= (main_k7ddrphy_bitslip18_value0 + 1'd1);
+	k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip18_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip18_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip18_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[50], main_k7ddrphy_dfi_p3_wrdata[18], main_k7ddrphy_dfi_p2_wrdata[50], main_k7ddrphy_dfi_p2_wrdata[18], main_k7ddrphy_dfi_p1_wrdata[50], main_k7ddrphy_dfi_p1_wrdata[18], main_k7ddrphy_dfi_p0_wrdata[50], main_k7ddrphy_dfi_p0_wrdata[18]}, main_k7ddrphy_bitslip18_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip18_value1 <= (main_k7ddrphy_bitslip18_value1 + 1'd1);
+	k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip18_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip18_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip18_r1 <= {main_k7ddrphy_bitslip181, main_k7ddrphy_bitslip18_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip19_value0 <= (main_k7ddrphy_bitslip19_value0 + 1'd1);
+	k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip19_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip19_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip19_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[51], main_k7ddrphy_dfi_p3_wrdata[19], main_k7ddrphy_dfi_p2_wrdata[51], main_k7ddrphy_dfi_p2_wrdata[19], main_k7ddrphy_dfi_p1_wrdata[51], main_k7ddrphy_dfi_p1_wrdata[19], main_k7ddrphy_dfi_p0_wrdata[51], main_k7ddrphy_dfi_p0_wrdata[19]}, main_k7ddrphy_bitslip19_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip19_value1 <= (main_k7ddrphy_bitslip19_value1 + 1'd1);
+	k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip19_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip19_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip19_r1 <= {main_k7ddrphy_bitslip191, main_k7ddrphy_bitslip19_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip20_value0 <= (main_k7ddrphy_bitslip20_value0 + 1'd1);
+	k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip20_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip20_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip20_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[52], main_k7ddrphy_dfi_p3_wrdata[20], main_k7ddrphy_dfi_p2_wrdata[52], main_k7ddrphy_dfi_p2_wrdata[20], main_k7ddrphy_dfi_p1_wrdata[52], main_k7ddrphy_dfi_p1_wrdata[20], main_k7ddrphy_dfi_p0_wrdata[52], main_k7ddrphy_dfi_p0_wrdata[20]}, main_k7ddrphy_bitslip20_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip20_value1 <= (main_k7ddrphy_bitslip20_value1 + 1'd1);
+	k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip20_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip20_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip20_r1 <= {main_k7ddrphy_bitslip201, main_k7ddrphy_bitslip20_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip21_value0 <= (main_k7ddrphy_bitslip21_value0 + 1'd1);
+	k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip21_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip21_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip21_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[53], main_k7ddrphy_dfi_p3_wrdata[21], main_k7ddrphy_dfi_p2_wrdata[53], main_k7ddrphy_dfi_p2_wrdata[21], main_k7ddrphy_dfi_p1_wrdata[53], main_k7ddrphy_dfi_p1_wrdata[21], main_k7ddrphy_dfi_p0_wrdata[53], main_k7ddrphy_dfi_p0_wrdata[21]}, main_k7ddrphy_bitslip21_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip21_value1 <= (main_k7ddrphy_bitslip21_value1 + 1'd1);
+	k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip21_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip21_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip21_r1 <= {main_k7ddrphy_bitslip211, main_k7ddrphy_bitslip21_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip22_value0 <= (main_k7ddrphy_bitslip22_value0 + 1'd1);
+	k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip22_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip22_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip22_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[54], main_k7ddrphy_dfi_p3_wrdata[22], main_k7ddrphy_dfi_p2_wrdata[54], main_k7ddrphy_dfi_p2_wrdata[22], main_k7ddrphy_dfi_p1_wrdata[54], main_k7ddrphy_dfi_p1_wrdata[22], main_k7ddrphy_dfi_p0_wrdata[54], main_k7ddrphy_dfi_p0_wrdata[22]}, main_k7ddrphy_bitslip22_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip22_value1 <= (main_k7ddrphy_bitslip22_value1 + 1'd1);
+	k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip22_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip22_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip22_r1 <= {main_k7ddrphy_bitslip221, main_k7ddrphy_bitslip22_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip23_value0 <= (main_k7ddrphy_bitslip23_value0 + 1'd1);
+	k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip23_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip23_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip23_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[55], main_k7ddrphy_dfi_p3_wrdata[23], main_k7ddrphy_dfi_p2_wrdata[55], main_k7ddrphy_dfi_p2_wrdata[23], main_k7ddrphy_dfi_p1_wrdata[55], main_k7ddrphy_dfi_p1_wrdata[23], main_k7ddrphy_dfi_p0_wrdata[55], main_k7ddrphy_dfi_p0_wrdata[23]}, main_k7ddrphy_bitslip23_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip23_value1 <= (main_k7ddrphy_bitslip23_value1 + 1'd1);
+	k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip23_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip23_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip23_r1 <= {main_k7ddrphy_bitslip231, main_k7ddrphy_bitslip23_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip24_value0 <= (main_k7ddrphy_bitslip24_value0 + 1'd1);
+	k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip24_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip24_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip24_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[56], main_k7ddrphy_dfi_p3_wrdata[24], main_k7ddrphy_dfi_p2_wrdata[56], main_k7ddrphy_dfi_p2_wrdata[24], main_k7ddrphy_dfi_p1_wrdata[56], main_k7ddrphy_dfi_p1_wrdata[24], main_k7ddrphy_dfi_p0_wrdata[56], main_k7ddrphy_dfi_p0_wrdata[24]}, main_k7ddrphy_bitslip24_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip24_value1 <= (main_k7ddrphy_bitslip24_value1 + 1'd1);
+	k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip24_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip24_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip24_r1 <= {main_k7ddrphy_bitslip241, main_k7ddrphy_bitslip24_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip25_value0 <= (main_k7ddrphy_bitslip25_value0 + 1'd1);
+	k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip25_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip25_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip25_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[57], main_k7ddrphy_dfi_p3_wrdata[25], main_k7ddrphy_dfi_p2_wrdata[57], main_k7ddrphy_dfi_p2_wrdata[25], main_k7ddrphy_dfi_p1_wrdata[57], main_k7ddrphy_dfi_p1_wrdata[25], main_k7ddrphy_dfi_p0_wrdata[57], main_k7ddrphy_dfi_p0_wrdata[25]}, main_k7ddrphy_bitslip25_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip25_value1 <= (main_k7ddrphy_bitslip25_value1 + 1'd1);
+	k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip25_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip25_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip25_r1 <= {main_k7ddrphy_bitslip251, main_k7ddrphy_bitslip25_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip26_value0 <= (main_k7ddrphy_bitslip26_value0 + 1'd1);
+	k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip26_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip26_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip26_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[58], main_k7ddrphy_dfi_p3_wrdata[26], main_k7ddrphy_dfi_p2_wrdata[58], main_k7ddrphy_dfi_p2_wrdata[26], main_k7ddrphy_dfi_p1_wrdata[58], main_k7ddrphy_dfi_p1_wrdata[26], main_k7ddrphy_dfi_p0_wrdata[58], main_k7ddrphy_dfi_p0_wrdata[26]}, main_k7ddrphy_bitslip26_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip26_value1 <= (main_k7ddrphy_bitslip26_value1 + 1'd1);
+	k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip26_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip26_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip26_r1 <= {main_k7ddrphy_bitslip261, main_k7ddrphy_bitslip26_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip27_value0 <= (main_k7ddrphy_bitslip27_value0 + 1'd1);
+	k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip27_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip27_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip27_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[59], main_k7ddrphy_dfi_p3_wrdata[27], main_k7ddrphy_dfi_p2_wrdata[59], main_k7ddrphy_dfi_p2_wrdata[27], main_k7ddrphy_dfi_p1_wrdata[59], main_k7ddrphy_dfi_p1_wrdata[27], main_k7ddrphy_dfi_p0_wrdata[59], main_k7ddrphy_dfi_p0_wrdata[27]}, main_k7ddrphy_bitslip27_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip27_value1 <= (main_k7ddrphy_bitslip27_value1 + 1'd1);
+	k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip27_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip27_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip27_r1 <= {main_k7ddrphy_bitslip271, main_k7ddrphy_bitslip27_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip28_value0 <= (main_k7ddrphy_bitslip28_value0 + 1'd1);
+	k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip28_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip28_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip28_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[60], main_k7ddrphy_dfi_p3_wrdata[28], main_k7ddrphy_dfi_p2_wrdata[60], main_k7ddrphy_dfi_p2_wrdata[28], main_k7ddrphy_dfi_p1_wrdata[60], main_k7ddrphy_dfi_p1_wrdata[28], main_k7ddrphy_dfi_p0_wrdata[60], main_k7ddrphy_dfi_p0_wrdata[28]}, main_k7ddrphy_bitslip28_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip28_value1 <= (main_k7ddrphy_bitslip28_value1 + 1'd1);
+	k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip28_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip28_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip28_r1 <= {main_k7ddrphy_bitslip281, main_k7ddrphy_bitslip28_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip29_value0 <= (main_k7ddrphy_bitslip29_value0 + 1'd1);
+	k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip29_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip29_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip29_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[61], main_k7ddrphy_dfi_p3_wrdata[29], main_k7ddrphy_dfi_p2_wrdata[61], main_k7ddrphy_dfi_p2_wrdata[29], main_k7ddrphy_dfi_p1_wrdata[61], main_k7ddrphy_dfi_p1_wrdata[29], main_k7ddrphy_dfi_p0_wrdata[61], main_k7ddrphy_dfi_p0_wrdata[29]}, main_k7ddrphy_bitslip29_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip29_value1 <= (main_k7ddrphy_bitslip29_value1 + 1'd1);
+	k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip29_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip29_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip29_r1 <= {main_k7ddrphy_bitslip291, main_k7ddrphy_bitslip29_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip30_value0 <= (main_k7ddrphy_bitslip30_value0 + 1'd1);
+	k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip30_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip30_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip30_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[62], main_k7ddrphy_dfi_p3_wrdata[30], main_k7ddrphy_dfi_p2_wrdata[62], main_k7ddrphy_dfi_p2_wrdata[30], main_k7ddrphy_dfi_p1_wrdata[62], main_k7ddrphy_dfi_p1_wrdata[30], main_k7ddrphy_dfi_p0_wrdata[62], main_k7ddrphy_dfi_p0_wrdata[30]}, main_k7ddrphy_bitslip30_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip30_value1 <= (main_k7ddrphy_bitslip30_value1 + 1'd1);
+	k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip30_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip30_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip30_r1 <= {main_k7ddrphy_bitslip301, main_k7ddrphy_bitslip30_r1[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip31_value0 <= (main_k7ddrphy_bitslip31_value0 + 1'd1);
+	k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip31_value0 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip31_value0 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip31_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[63], main_k7ddrphy_dfi_p3_wrdata[31], main_k7ddrphy_dfi_p2_wrdata[63], main_k7ddrphy_dfi_p2_wrdata[31], main_k7ddrphy_dfi_p1_wrdata[63], main_k7ddrphy_dfi_p1_wrdata[31], main_k7ddrphy_dfi_p0_wrdata[63], main_k7ddrphy_dfi_p0_wrdata[31]}, main_k7ddrphy_bitslip31_r0[15:8]};
-	if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
-		main_k7ddrphy_bitslip31_value1 <= (main_k7ddrphy_bitslip31_value1 + 1'd1);
+	k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]};
+	if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+		k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1);
 	end
-	if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
-		main_k7ddrphy_bitslip31_value1 <= 3'd7;
+	if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+		k7ddrphy_bitslip31_value1 <= 3'd7;
 	end
-	main_k7ddrphy_bitslip31_r1 <= {main_k7ddrphy_bitslip311, main_k7ddrphy_bitslip31_r1[15:8]};
-	main_k7ddrphy_rddata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_rddata_en | main_k7ddrphy_dfi_p1_rddata_en) | main_k7ddrphy_dfi_p2_rddata_en) | main_k7ddrphy_dfi_p3_rddata_en);
-	main_k7ddrphy_rddata_en_tappeddelayline1 <= main_k7ddrphy_rddata_en_tappeddelayline0;
-	main_k7ddrphy_rddata_en_tappeddelayline2 <= main_k7ddrphy_rddata_en_tappeddelayline1;
-	main_k7ddrphy_rddata_en_tappeddelayline3 <= main_k7ddrphy_rddata_en_tappeddelayline2;
-	main_k7ddrphy_rddata_en_tappeddelayline4 <= main_k7ddrphy_rddata_en_tappeddelayline3;
-	main_k7ddrphy_rddata_en_tappeddelayline5 <= main_k7ddrphy_rddata_en_tappeddelayline4;
-	main_k7ddrphy_rddata_en_tappeddelayline6 <= main_k7ddrphy_rddata_en_tappeddelayline5;
-	main_k7ddrphy_rddata_en_tappeddelayline7 <= main_k7ddrphy_rddata_en_tappeddelayline6;
-	main_k7ddrphy_wrdata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_wrdata_en | main_k7ddrphy_dfi_p1_wrdata_en) | main_k7ddrphy_dfi_p2_wrdata_en) | main_k7ddrphy_dfi_p3_wrdata_en);
-	main_k7ddrphy_wrdata_en_tappeddelayline1 <= main_k7ddrphy_wrdata_en_tappeddelayline0;
-	main_k7ddrphy_wrdata_en_tappeddelayline2 <= main_k7ddrphy_wrdata_en_tappeddelayline1;
-	if (main_litedramcore_inti_p0_rddata_valid) begin
-		main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata;
+	k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]};
+	k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en);
+	k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0;
+	k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1;
+	k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2;
+	k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3;
+	k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4;
+	k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5;
+	k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6;
+	k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en);
+	k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0;
+	k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1;
+	if (litedramcore_csr_dfi_p0_rddata_valid) begin
+		litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
 	end
-	if (main_litedramcore_inti_p1_rddata_valid) begin
-		main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata;
+	if (litedramcore_csr_dfi_p1_rddata_valid) begin
+		litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
 	end
-	if (main_litedramcore_inti_p2_rddata_valid) begin
-		main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata;
+	if (litedramcore_csr_dfi_p2_rddata_valid) begin
+		litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
 	end
-	if (main_litedramcore_inti_p3_rddata_valid) begin
-		main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata;
+	if (litedramcore_csr_dfi_p3_rddata_valid) begin
+		litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
 	end
-	if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
-		main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
+	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_timer_count1 <= 10'd781;
+		litedramcore_timer_count1 <= 10'd781;
 	end
-	main_litedramcore_postponer_req_o <= 1'd0;
-	if (main_litedramcore_postponer_req_i) begin
-		main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
-		if ((main_litedramcore_postponer_count == 1'd0)) begin
-			main_litedramcore_postponer_count <= 1'd0;
-			main_litedramcore_postponer_req_o <= 1'd1;
+	litedramcore_postponer_req_o <= 1'd0;
+	if (litedramcore_postponer_req_i) begin
+		litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+		if ((litedramcore_postponer_count == 1'd0)) begin
+			litedramcore_postponer_count <= 1'd0;
+			litedramcore_postponer_req_o <= 1'd1;
 		end
 	end
-	if (main_litedramcore_sequencer_start0) begin
-		main_litedramcore_sequencer_count <= 1'd0;
+	if (litedramcore_sequencer_start0) begin
+		litedramcore_sequencer_count <= 1'd0;
 	end else begin
-		if (main_litedramcore_sequencer_done1) begin
-			if ((main_litedramcore_sequencer_count != 1'd0)) begin
-				main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
-			end
-		end
-	end
-	main_litedramcore_cmd_payload_a <= 1'd0;
-	main_litedramcore_cmd_payload_ba <= 1'd0;
-	main_litedramcore_cmd_payload_cas <= 1'd0;
-	main_litedramcore_cmd_payload_ras <= 1'd0;
-	main_litedramcore_cmd_payload_we <= 1'd0;
-	main_litedramcore_sequencer_done1 <= 1'd0;
-	if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd1;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd55)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd55)) begin
-		main_litedramcore_sequencer_counter <= 1'd0;
+		if (litedramcore_sequencer_done1) begin
+			if ((litedramcore_sequencer_count != 1'd0)) begin
+				litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+			end
+		end
+	end
+	litedramcore_cmd_payload_a <= 1'd0;
+	litedramcore_cmd_payload_ba <= 1'd0;
+	litedramcore_cmd_payload_cas <= 1'd0;
+	litedramcore_cmd_payload_ras <= 1'd0;
+	litedramcore_cmd_payload_we <= 1'd0;
+	litedramcore_sequencer_done1 <= 1'd0;
+	if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd1;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd0;
+	end
+	if ((litedramcore_sequencer_counter == 6'd55)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 6'd55)) begin
+		litedramcore_sequencer_counter <= 1'd0;
 	end else begin
-		if ((main_litedramcore_sequencer_counter != 1'd0)) begin
-			main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1);
+		if ((litedramcore_sequencer_counter != 1'd0)) begin
+			litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_sequencer_start1) begin
-				main_litedramcore_sequencer_counter <= 1'd1;
+			if (litedramcore_sequencer_start1) begin
+				litedramcore_sequencer_counter <= 1'd1;
 			end
 		end
 	end
-	if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
-		main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
+	if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+		litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
-	end
-	main_litedramcore_zqcs_executer_done <= 1'd0;
-	if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
-	end
-	if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd1;
-	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_zqcs_executer_done <= 1'd1;
-	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_zqcs_executer_counter <= 1'd0;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
+	end
+	litedramcore_zqcs_executer_done <= 1'd0;
+	if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_zqcs_executer_done <= 1'd1;
+	end
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_zqcs_executer_counter <= 1'd0;
 	end else begin
-		if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin
-			main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1);
+		if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+			litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_zqcs_executer_start) begin
-				main_litedramcore_zqcs_executer_counter <= 1'd1;
+			if (litedramcore_zqcs_executer_start) begin
+				litedramcore_zqcs_executer_counter <= 1'd1;
 			end
 		end
 	end
-	builder_refresher_state <= builder_refresher_next_state;
-	if (main_litedramcore_bankmachine0_row_close) begin
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
+	litedramcore_refresher_state <= litedramcore_refresher_next_state;
+	if (litedramcore_bankmachine0_row_close) begin
+		litedramcore_bankmachine0_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine0_row_open) begin
-			main_litedramcore_bankmachine0_row_opened <= 1'd1;
-			main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine0_row_open) begin
+			litedramcore_bankmachine0_row_opened <= 1'd1;
+			litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+		litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+		litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine0_twtpcon_valid) begin
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine0_twtpcon_valid) begin
+		litedramcore_bankmachine0_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
-			main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+			litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trccon_valid) begin
-		main_litedramcore_bankmachine0_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine0_trccon_valid) begin
+		litedramcore_bankmachine0_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+			litedramcore_bankmachine0_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+			litedramcore_bankmachine0_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
-			main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trccon_ready)) begin
+			litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trascon_valid) begin
-		main_litedramcore_bankmachine0_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine0_trascon_valid) begin
+		litedramcore_bankmachine0_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+			litedramcore_bankmachine0_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+			litedramcore_bankmachine0_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
-			main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trascon_ready)) begin
+			litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine0_state <= builder_bankmachine0_next_state;
-	if (main_litedramcore_bankmachine1_row_close) begin
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
+	litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+	if (litedramcore_bankmachine1_row_close) begin
+		litedramcore_bankmachine1_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine1_row_open) begin
-			main_litedramcore_bankmachine1_row_opened <= 1'd1;
-			main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine1_row_open) begin
+			litedramcore_bankmachine1_row_opened <= 1'd1;
+			litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+		litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+		litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine1_twtpcon_valid) begin
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine1_twtpcon_valid) begin
+		litedramcore_bankmachine1_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
-			main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+			litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trccon_valid) begin
-		main_litedramcore_bankmachine1_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine1_trccon_valid) begin
+		litedramcore_bankmachine1_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+			litedramcore_bankmachine1_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+			litedramcore_bankmachine1_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
-			main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trccon_ready)) begin
+			litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trascon_valid) begin
-		main_litedramcore_bankmachine1_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine1_trascon_valid) begin
+		litedramcore_bankmachine1_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+			litedramcore_bankmachine1_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+			litedramcore_bankmachine1_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
-			main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trascon_ready)) begin
+			litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine1_state <= builder_bankmachine1_next_state;
-	if (main_litedramcore_bankmachine2_row_close) begin
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
+	litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+	if (litedramcore_bankmachine2_row_close) begin
+		litedramcore_bankmachine2_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine2_row_open) begin
-			main_litedramcore_bankmachine2_row_opened <= 1'd1;
-			main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine2_row_open) begin
+			litedramcore_bankmachine2_row_opened <= 1'd1;
+			litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+		litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+		litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine2_twtpcon_valid) begin
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine2_twtpcon_valid) begin
+		litedramcore_bankmachine2_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
-			main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+			litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trccon_valid) begin
-		main_litedramcore_bankmachine2_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine2_trccon_valid) begin
+		litedramcore_bankmachine2_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+			litedramcore_bankmachine2_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+			litedramcore_bankmachine2_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
-			main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trccon_ready)) begin
+			litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trascon_valid) begin
-		main_litedramcore_bankmachine2_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine2_trascon_valid) begin
+		litedramcore_bankmachine2_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+			litedramcore_bankmachine2_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+			litedramcore_bankmachine2_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
-			main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trascon_ready)) begin
+			litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine2_state <= builder_bankmachine2_next_state;
-	if (main_litedramcore_bankmachine3_row_close) begin
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
+	litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+	if (litedramcore_bankmachine3_row_close) begin
+		litedramcore_bankmachine3_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine3_row_open) begin
-			main_litedramcore_bankmachine3_row_opened <= 1'd1;
-			main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine3_row_open) begin
+			litedramcore_bankmachine3_row_opened <= 1'd1;
+			litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+		litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+		litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine3_twtpcon_valid) begin
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine3_twtpcon_valid) begin
+		litedramcore_bankmachine3_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
-			main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+			litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trccon_valid) begin
-		main_litedramcore_bankmachine3_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine3_trccon_valid) begin
+		litedramcore_bankmachine3_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+			litedramcore_bankmachine3_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+			litedramcore_bankmachine3_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
-			main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trccon_ready)) begin
+			litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trascon_valid) begin
-		main_litedramcore_bankmachine3_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine3_trascon_valid) begin
+		litedramcore_bankmachine3_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+			litedramcore_bankmachine3_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+			litedramcore_bankmachine3_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
-			main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trascon_ready)) begin
+			litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine3_state <= builder_bankmachine3_next_state;
-	if (main_litedramcore_bankmachine4_row_close) begin
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
+	litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+	if (litedramcore_bankmachine4_row_close) begin
+		litedramcore_bankmachine4_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine4_row_open) begin
-			main_litedramcore_bankmachine4_row_opened <= 1'd1;
-			main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine4_row_open) begin
+			litedramcore_bankmachine4_row_opened <= 1'd1;
+			litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+		litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+		litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine4_twtpcon_valid) begin
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine4_twtpcon_valid) begin
+		litedramcore_bankmachine4_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
-			main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+			litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trccon_valid) begin
-		main_litedramcore_bankmachine4_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine4_trccon_valid) begin
+		litedramcore_bankmachine4_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+			litedramcore_bankmachine4_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+			litedramcore_bankmachine4_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
-			main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trccon_ready)) begin
+			litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trascon_valid) begin
-		main_litedramcore_bankmachine4_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine4_trascon_valid) begin
+		litedramcore_bankmachine4_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+			litedramcore_bankmachine4_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+			litedramcore_bankmachine4_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
-			main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trascon_ready)) begin
+			litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine4_state <= builder_bankmachine4_next_state;
-	if (main_litedramcore_bankmachine5_row_close) begin
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
+	litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+	if (litedramcore_bankmachine5_row_close) begin
+		litedramcore_bankmachine5_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine5_row_open) begin
-			main_litedramcore_bankmachine5_row_opened <= 1'd1;
-			main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine5_row_open) begin
+			litedramcore_bankmachine5_row_opened <= 1'd1;
+			litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+		litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+		litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine5_twtpcon_valid) begin
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine5_twtpcon_valid) begin
+		litedramcore_bankmachine5_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
-			main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+			litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trccon_valid) begin
-		main_litedramcore_bankmachine5_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine5_trccon_valid) begin
+		litedramcore_bankmachine5_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+			litedramcore_bankmachine5_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+			litedramcore_bankmachine5_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
-			main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trccon_ready)) begin
+			litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trascon_valid) begin
-		main_litedramcore_bankmachine5_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine5_trascon_valid) begin
+		litedramcore_bankmachine5_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+			litedramcore_bankmachine5_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+			litedramcore_bankmachine5_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
-			main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trascon_ready)) begin
+			litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine5_state <= builder_bankmachine5_next_state;
-	if (main_litedramcore_bankmachine6_row_close) begin
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
+	litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+	if (litedramcore_bankmachine6_row_close) begin
+		litedramcore_bankmachine6_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine6_row_open) begin
-			main_litedramcore_bankmachine6_row_opened <= 1'd1;
-			main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine6_row_open) begin
+			litedramcore_bankmachine6_row_opened <= 1'd1;
+			litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+		litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+		litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine6_twtpcon_valid) begin
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine6_twtpcon_valid) begin
+		litedramcore_bankmachine6_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
-			main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+			litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trccon_valid) begin
-		main_litedramcore_bankmachine6_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine6_trccon_valid) begin
+		litedramcore_bankmachine6_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+			litedramcore_bankmachine6_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+			litedramcore_bankmachine6_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
-			main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trccon_ready)) begin
+			litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trascon_valid) begin
-		main_litedramcore_bankmachine6_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine6_trascon_valid) begin
+		litedramcore_bankmachine6_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+			litedramcore_bankmachine6_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+			litedramcore_bankmachine6_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
-			main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trascon_ready)) begin
+			litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine6_state <= builder_bankmachine6_next_state;
-	if (main_litedramcore_bankmachine7_row_close) begin
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
+	litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+	if (litedramcore_bankmachine7_row_close) begin
+		litedramcore_bankmachine7_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine7_row_open) begin
-			main_litedramcore_bankmachine7_row_opened <= 1'd1;
-			main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine7_row_open) begin
+			litedramcore_bankmachine7_row_opened <= 1'd1;
+			litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+		litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+		litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine7_twtpcon_valid) begin
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine7_twtpcon_valid) begin
+		litedramcore_bankmachine7_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
-			main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+			litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trccon_valid) begin
-		main_litedramcore_bankmachine7_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine7_trccon_valid) begin
+		litedramcore_bankmachine7_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+			litedramcore_bankmachine7_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+			litedramcore_bankmachine7_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
-			main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trccon_ready)) begin
+			litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trascon_valid) begin
-		main_litedramcore_bankmachine7_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine7_trascon_valid) begin
+		litedramcore_bankmachine7_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+			litedramcore_bankmachine7_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+			litedramcore_bankmachine7_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
-			main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trascon_ready)) begin
+			litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine7_state <= builder_bankmachine7_next_state;
-	if ((~main_litedramcore_en0)) begin
-		main_litedramcore_time0 <= 5'd31;
+	litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+	if ((~litedramcore_en0)) begin
+		litedramcore_time0 <= 5'd31;
 	end else begin
-		if ((~main_litedramcore_max_time0)) begin
-			main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
+		if ((~litedramcore_max_time0)) begin
+			litedramcore_time0 <= (litedramcore_time0 - 1'd1);
 		end
 	end
-	if ((~main_litedramcore_en1)) begin
-		main_litedramcore_time1 <= 4'd15;
+	if ((~litedramcore_en1)) begin
+		litedramcore_time1 <= 4'd15;
 	end else begin
-		if ((~main_litedramcore_max_time1)) begin
-			main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
+		if ((~litedramcore_max_time1)) begin
+			litedramcore_time1 <= (litedramcore_time1 - 1'd1);
 		end
 	end
-	if (main_litedramcore_choose_cmd_ce) begin
-		case (main_litedramcore_choose_cmd_grant)
+	if (litedramcore_choose_cmd_ce) begin
+		case (litedramcore_choose_cmd_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_cmd_request[1]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd1;
+				if (litedramcore_choose_cmd_request[1]) begin
+					litedramcore_choose_cmd_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[2]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd2;
+					if (litedramcore_choose_cmd_request[2]) begin
+						litedramcore_choose_cmd_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[3]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd3;
+						if (litedramcore_choose_cmd_request[3]) begin
+							litedramcore_choose_cmd_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[4]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd4;
+							if (litedramcore_choose_cmd_request[4]) begin
+								litedramcore_choose_cmd_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[5]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd5;
+								if (litedramcore_choose_cmd_request[5]) begin
+									litedramcore_choose_cmd_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[6]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd6;
+									if (litedramcore_choose_cmd_request[6]) begin
+										litedramcore_choose_cmd_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[7]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd7;
+										if (litedramcore_choose_cmd_request[7]) begin
+											litedramcore_choose_cmd_grant <= 3'd7;
 										end
 									end
 								end
@@ -14295,26 +14738,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_cmd_request[2]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd2;
+				if (litedramcore_choose_cmd_request[2]) begin
+					litedramcore_choose_cmd_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[3]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd3;
+					if (litedramcore_choose_cmd_request[3]) begin
+						litedramcore_choose_cmd_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[4]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd4;
+						if (litedramcore_choose_cmd_request[4]) begin
+							litedramcore_choose_cmd_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[5]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd5;
+							if (litedramcore_choose_cmd_request[5]) begin
+								litedramcore_choose_cmd_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[6]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd6;
+								if (litedramcore_choose_cmd_request[6]) begin
+									litedramcore_choose_cmd_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[7]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd7;
+									if (litedramcore_choose_cmd_request[7]) begin
+										litedramcore_choose_cmd_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[0]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd0;
+										if (litedramcore_choose_cmd_request[0]) begin
+											litedramcore_choose_cmd_grant <= 1'd0;
 										end
 									end
 								end
@@ -14324,26 +14767,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_cmd_request[3]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd3;
+				if (litedramcore_choose_cmd_request[3]) begin
+					litedramcore_choose_cmd_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[4]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd4;
+					if (litedramcore_choose_cmd_request[4]) begin
+						litedramcore_choose_cmd_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[5]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd5;
+						if (litedramcore_choose_cmd_request[5]) begin
+							litedramcore_choose_cmd_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[6]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd6;
+							if (litedramcore_choose_cmd_request[6]) begin
+								litedramcore_choose_cmd_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[7]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd7;
+								if (litedramcore_choose_cmd_request[7]) begin
+									litedramcore_choose_cmd_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[0]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd0;
+									if (litedramcore_choose_cmd_request[0]) begin
+										litedramcore_choose_cmd_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[1]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd1;
+										if (litedramcore_choose_cmd_request[1]) begin
+											litedramcore_choose_cmd_grant <= 1'd1;
 										end
 									end
 								end
@@ -14353,26 +14796,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_cmd_request[4]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd4;
+				if (litedramcore_choose_cmd_request[4]) begin
+					litedramcore_choose_cmd_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[5]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd5;
+					if (litedramcore_choose_cmd_request[5]) begin
+						litedramcore_choose_cmd_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[6]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd6;
+						if (litedramcore_choose_cmd_request[6]) begin
+							litedramcore_choose_cmd_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[7]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd7;
+							if (litedramcore_choose_cmd_request[7]) begin
+								litedramcore_choose_cmd_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[0]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd0;
+								if (litedramcore_choose_cmd_request[0]) begin
+									litedramcore_choose_cmd_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[1]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd1;
+									if (litedramcore_choose_cmd_request[1]) begin
+										litedramcore_choose_cmd_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[2]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd2;
+										if (litedramcore_choose_cmd_request[2]) begin
+											litedramcore_choose_cmd_grant <= 2'd2;
 										end
 									end
 								end
@@ -14382,26 +14825,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_cmd_request[5]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd5;
+				if (litedramcore_choose_cmd_request[5]) begin
+					litedramcore_choose_cmd_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[6]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd6;
+					if (litedramcore_choose_cmd_request[6]) begin
+						litedramcore_choose_cmd_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[7]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd7;
+						if (litedramcore_choose_cmd_request[7]) begin
+							litedramcore_choose_cmd_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[0]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd0;
+							if (litedramcore_choose_cmd_request[0]) begin
+								litedramcore_choose_cmd_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[1]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd1;
+								if (litedramcore_choose_cmd_request[1]) begin
+									litedramcore_choose_cmd_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[2]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd2;
+									if (litedramcore_choose_cmd_request[2]) begin
+										litedramcore_choose_cmd_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[3]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd3;
+										if (litedramcore_choose_cmd_request[3]) begin
+											litedramcore_choose_cmd_grant <= 2'd3;
 										end
 									end
 								end
@@ -14411,26 +14854,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_cmd_request[6]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd6;
+				if (litedramcore_choose_cmd_request[6]) begin
+					litedramcore_choose_cmd_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[7]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd7;
+					if (litedramcore_choose_cmd_request[7]) begin
+						litedramcore_choose_cmd_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[0]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd0;
+						if (litedramcore_choose_cmd_request[0]) begin
+							litedramcore_choose_cmd_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[1]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd1;
+							if (litedramcore_choose_cmd_request[1]) begin
+								litedramcore_choose_cmd_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[2]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd2;
+								if (litedramcore_choose_cmd_request[2]) begin
+									litedramcore_choose_cmd_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[3]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd3;
+									if (litedramcore_choose_cmd_request[3]) begin
+										litedramcore_choose_cmd_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[4]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd4;
+										if (litedramcore_choose_cmd_request[4]) begin
+											litedramcore_choose_cmd_grant <= 3'd4;
 										end
 									end
 								end
@@ -14440,26 +14883,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_cmd_request[7]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd7;
+				if (litedramcore_choose_cmd_request[7]) begin
+					litedramcore_choose_cmd_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[0]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd0;
+					if (litedramcore_choose_cmd_request[0]) begin
+						litedramcore_choose_cmd_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[1]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd1;
+						if (litedramcore_choose_cmd_request[1]) begin
+							litedramcore_choose_cmd_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[2]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd2;
+							if (litedramcore_choose_cmd_request[2]) begin
+								litedramcore_choose_cmd_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[3]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd3;
+								if (litedramcore_choose_cmd_request[3]) begin
+									litedramcore_choose_cmd_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[4]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd4;
+									if (litedramcore_choose_cmd_request[4]) begin
+										litedramcore_choose_cmd_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[5]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd5;
+										if (litedramcore_choose_cmd_request[5]) begin
+											litedramcore_choose_cmd_grant <= 3'd5;
 										end
 									end
 								end
@@ -14469,26 +14912,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_cmd_request[0]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd0;
+				if (litedramcore_choose_cmd_request[0]) begin
+					litedramcore_choose_cmd_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[1]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd1;
+					if (litedramcore_choose_cmd_request[1]) begin
+						litedramcore_choose_cmd_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[2]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd2;
+						if (litedramcore_choose_cmd_request[2]) begin
+							litedramcore_choose_cmd_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[3]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd3;
+							if (litedramcore_choose_cmd_request[3]) begin
+								litedramcore_choose_cmd_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[4]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd4;
+								if (litedramcore_choose_cmd_request[4]) begin
+									litedramcore_choose_cmd_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[5]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd5;
+									if (litedramcore_choose_cmd_request[5]) begin
+										litedramcore_choose_cmd_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[6]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd6;
+										if (litedramcore_choose_cmd_request[6]) begin
+											litedramcore_choose_cmd_grant <= 3'd6;
 										end
 									end
 								end
@@ -14499,29 +14942,29 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	if (main_litedramcore_choose_req_ce) begin
-		case (main_litedramcore_choose_req_grant)
+	if (litedramcore_choose_req_ce) begin
+		case (litedramcore_choose_req_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_req_request[1]) begin
-					main_litedramcore_choose_req_grant <= 1'd1;
+				if (litedramcore_choose_req_request[1]) begin
+					litedramcore_choose_req_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_req_request[2]) begin
-						main_litedramcore_choose_req_grant <= 2'd2;
+					if (litedramcore_choose_req_request[2]) begin
+						litedramcore_choose_req_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_req_request[3]) begin
-							main_litedramcore_choose_req_grant <= 2'd3;
+						if (litedramcore_choose_req_request[3]) begin
+							litedramcore_choose_req_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_req_request[4]) begin
-								main_litedramcore_choose_req_grant <= 3'd4;
+							if (litedramcore_choose_req_request[4]) begin
+								litedramcore_choose_req_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_req_request[5]) begin
-									main_litedramcore_choose_req_grant <= 3'd5;
+								if (litedramcore_choose_req_request[5]) begin
+									litedramcore_choose_req_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_req_request[6]) begin
-										main_litedramcore_choose_req_grant <= 3'd6;
+									if (litedramcore_choose_req_request[6]) begin
+										litedramcore_choose_req_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_req_request[7]) begin
-											main_litedramcore_choose_req_grant <= 3'd7;
+										if (litedramcore_choose_req_request[7]) begin
+											litedramcore_choose_req_grant <= 3'd7;
 										end
 									end
 								end
@@ -14531,26 +14974,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_req_request[2]) begin
-					main_litedramcore_choose_req_grant <= 2'd2;
+				if (litedramcore_choose_req_request[2]) begin
+					litedramcore_choose_req_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_req_request[3]) begin
-						main_litedramcore_choose_req_grant <= 2'd3;
+					if (litedramcore_choose_req_request[3]) begin
+						litedramcore_choose_req_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_req_request[4]) begin
-							main_litedramcore_choose_req_grant <= 3'd4;
+						if (litedramcore_choose_req_request[4]) begin
+							litedramcore_choose_req_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_req_request[5]) begin
-								main_litedramcore_choose_req_grant <= 3'd5;
+							if (litedramcore_choose_req_request[5]) begin
+								litedramcore_choose_req_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_req_request[6]) begin
-									main_litedramcore_choose_req_grant <= 3'd6;
+								if (litedramcore_choose_req_request[6]) begin
+									litedramcore_choose_req_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_req_request[7]) begin
-										main_litedramcore_choose_req_grant <= 3'd7;
+									if (litedramcore_choose_req_request[7]) begin
+										litedramcore_choose_req_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_req_request[0]) begin
-											main_litedramcore_choose_req_grant <= 1'd0;
+										if (litedramcore_choose_req_request[0]) begin
+											litedramcore_choose_req_grant <= 1'd0;
 										end
 									end
 								end
@@ -14560,26 +15003,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_req_request[3]) begin
-					main_litedramcore_choose_req_grant <= 2'd3;
+				if (litedramcore_choose_req_request[3]) begin
+					litedramcore_choose_req_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_req_request[4]) begin
-						main_litedramcore_choose_req_grant <= 3'd4;
+					if (litedramcore_choose_req_request[4]) begin
+						litedramcore_choose_req_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_req_request[5]) begin
-							main_litedramcore_choose_req_grant <= 3'd5;
+						if (litedramcore_choose_req_request[5]) begin
+							litedramcore_choose_req_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_req_request[6]) begin
-								main_litedramcore_choose_req_grant <= 3'd6;
+							if (litedramcore_choose_req_request[6]) begin
+								litedramcore_choose_req_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_req_request[7]) begin
-									main_litedramcore_choose_req_grant <= 3'd7;
+								if (litedramcore_choose_req_request[7]) begin
+									litedramcore_choose_req_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_req_request[0]) begin
-										main_litedramcore_choose_req_grant <= 1'd0;
+									if (litedramcore_choose_req_request[0]) begin
+										litedramcore_choose_req_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_req_request[1]) begin
-											main_litedramcore_choose_req_grant <= 1'd1;
+										if (litedramcore_choose_req_request[1]) begin
+											litedramcore_choose_req_grant <= 1'd1;
 										end
 									end
 								end
@@ -14589,26 +15032,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_req_request[4]) begin
-					main_litedramcore_choose_req_grant <= 3'd4;
+				if (litedramcore_choose_req_request[4]) begin
+					litedramcore_choose_req_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_req_request[5]) begin
-						main_litedramcore_choose_req_grant <= 3'd5;
+					if (litedramcore_choose_req_request[5]) begin
+						litedramcore_choose_req_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_req_request[6]) begin
-							main_litedramcore_choose_req_grant <= 3'd6;
+						if (litedramcore_choose_req_request[6]) begin
+							litedramcore_choose_req_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_req_request[7]) begin
-								main_litedramcore_choose_req_grant <= 3'd7;
+							if (litedramcore_choose_req_request[7]) begin
+								litedramcore_choose_req_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_req_request[0]) begin
-									main_litedramcore_choose_req_grant <= 1'd0;
+								if (litedramcore_choose_req_request[0]) begin
+									litedramcore_choose_req_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_req_request[1]) begin
-										main_litedramcore_choose_req_grant <= 1'd1;
+									if (litedramcore_choose_req_request[1]) begin
+										litedramcore_choose_req_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_req_request[2]) begin
-											main_litedramcore_choose_req_grant <= 2'd2;
+										if (litedramcore_choose_req_request[2]) begin
+											litedramcore_choose_req_grant <= 2'd2;
 										end
 									end
 								end
@@ -14618,26 +15061,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_req_request[5]) begin
-					main_litedramcore_choose_req_grant <= 3'd5;
+				if (litedramcore_choose_req_request[5]) begin
+					litedramcore_choose_req_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_req_request[6]) begin
-						main_litedramcore_choose_req_grant <= 3'd6;
+					if (litedramcore_choose_req_request[6]) begin
+						litedramcore_choose_req_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_req_request[7]) begin
-							main_litedramcore_choose_req_grant <= 3'd7;
+						if (litedramcore_choose_req_request[7]) begin
+							litedramcore_choose_req_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_req_request[0]) begin
-								main_litedramcore_choose_req_grant <= 1'd0;
+							if (litedramcore_choose_req_request[0]) begin
+								litedramcore_choose_req_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_req_request[1]) begin
-									main_litedramcore_choose_req_grant <= 1'd1;
+								if (litedramcore_choose_req_request[1]) begin
+									litedramcore_choose_req_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_req_request[2]) begin
-										main_litedramcore_choose_req_grant <= 2'd2;
+									if (litedramcore_choose_req_request[2]) begin
+										litedramcore_choose_req_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_req_request[3]) begin
-											main_litedramcore_choose_req_grant <= 2'd3;
+										if (litedramcore_choose_req_request[3]) begin
+											litedramcore_choose_req_grant <= 2'd3;
 										end
 									end
 								end
@@ -14647,26 +15090,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_req_request[6]) begin
-					main_litedramcore_choose_req_grant <= 3'd6;
+				if (litedramcore_choose_req_request[6]) begin
+					litedramcore_choose_req_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_req_request[7]) begin
-						main_litedramcore_choose_req_grant <= 3'd7;
+					if (litedramcore_choose_req_request[7]) begin
+						litedramcore_choose_req_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_req_request[0]) begin
-							main_litedramcore_choose_req_grant <= 1'd0;
+						if (litedramcore_choose_req_request[0]) begin
+							litedramcore_choose_req_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_req_request[1]) begin
-								main_litedramcore_choose_req_grant <= 1'd1;
+							if (litedramcore_choose_req_request[1]) begin
+								litedramcore_choose_req_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_req_request[2]) begin
-									main_litedramcore_choose_req_grant <= 2'd2;
+								if (litedramcore_choose_req_request[2]) begin
+									litedramcore_choose_req_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_req_request[3]) begin
-										main_litedramcore_choose_req_grant <= 2'd3;
+									if (litedramcore_choose_req_request[3]) begin
+										litedramcore_choose_req_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_req_request[4]) begin
-											main_litedramcore_choose_req_grant <= 3'd4;
+										if (litedramcore_choose_req_request[4]) begin
+											litedramcore_choose_req_grant <= 3'd4;
 										end
 									end
 								end
@@ -14676,26 +15119,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_req_request[7]) begin
-					main_litedramcore_choose_req_grant <= 3'd7;
+				if (litedramcore_choose_req_request[7]) begin
+					litedramcore_choose_req_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_req_request[0]) begin
-						main_litedramcore_choose_req_grant <= 1'd0;
+					if (litedramcore_choose_req_request[0]) begin
+						litedramcore_choose_req_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_req_request[1]) begin
-							main_litedramcore_choose_req_grant <= 1'd1;
+						if (litedramcore_choose_req_request[1]) begin
+							litedramcore_choose_req_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_req_request[2]) begin
-								main_litedramcore_choose_req_grant <= 2'd2;
+							if (litedramcore_choose_req_request[2]) begin
+								litedramcore_choose_req_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_req_request[3]) begin
-									main_litedramcore_choose_req_grant <= 2'd3;
+								if (litedramcore_choose_req_request[3]) begin
+									litedramcore_choose_req_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_req_request[4]) begin
-										main_litedramcore_choose_req_grant <= 3'd4;
+									if (litedramcore_choose_req_request[4]) begin
+										litedramcore_choose_req_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_req_request[5]) begin
-											main_litedramcore_choose_req_grant <= 3'd5;
+										if (litedramcore_choose_req_request[5]) begin
+											litedramcore_choose_req_grant <= 3'd5;
 										end
 									end
 								end
@@ -14705,26 +15148,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_req_request[0]) begin
-					main_litedramcore_choose_req_grant <= 1'd0;
+				if (litedramcore_choose_req_request[0]) begin
+					litedramcore_choose_req_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_req_request[1]) begin
-						main_litedramcore_choose_req_grant <= 1'd1;
+					if (litedramcore_choose_req_request[1]) begin
+						litedramcore_choose_req_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_req_request[2]) begin
-							main_litedramcore_choose_req_grant <= 2'd2;
+						if (litedramcore_choose_req_request[2]) begin
+							litedramcore_choose_req_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_req_request[3]) begin
-								main_litedramcore_choose_req_grant <= 2'd3;
+							if (litedramcore_choose_req_request[3]) begin
+								litedramcore_choose_req_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_req_request[4]) begin
-									main_litedramcore_choose_req_grant <= 3'd4;
+								if (litedramcore_choose_req_request[4]) begin
+									litedramcore_choose_req_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_req_request[5]) begin
-										main_litedramcore_choose_req_grant <= 3'd5;
+									if (litedramcore_choose_req_request[5]) begin
+										litedramcore_choose_req_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_req_request[6]) begin
-											main_litedramcore_choose_req_grant <= 3'd6;
+										if (litedramcore_choose_req_request[6]) begin
+											litedramcore_choose_req_grant <= 3'd6;
 										end
 									end
 								end
@@ -14735,733 +15178,733 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	main_litedramcore_dfi_p0_cs_n <= 1'd0;
-	main_litedramcore_dfi_p0_bank <= builder_array_muxed0;
-	main_litedramcore_dfi_p0_address <= builder_array_muxed1;
-	main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2);
-	main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3);
-	main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4);
-	main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5;
-	main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6;
-	main_litedramcore_dfi_p1_cs_n <= 1'd0;
-	main_litedramcore_dfi_p1_bank <= builder_array_muxed7;
-	main_litedramcore_dfi_p1_address <= builder_array_muxed8;
-	main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9);
-	main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10);
-	main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11);
-	main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12;
-	main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13;
-	main_litedramcore_dfi_p2_cs_n <= 1'd0;
-	main_litedramcore_dfi_p2_bank <= builder_array_muxed14;
-	main_litedramcore_dfi_p2_address <= builder_array_muxed15;
-	main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16);
-	main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17);
-	main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18);
-	main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19;
-	main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20;
-	main_litedramcore_dfi_p3_cs_n <= 1'd0;
-	main_litedramcore_dfi_p3_bank <= builder_array_muxed21;
-	main_litedramcore_dfi_p3_address <= builder_array_muxed22;
-	main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23);
-	main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24);
-	main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25);
-	main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26;
-	main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27;
-	if (main_litedramcore_trrdcon_valid) begin
-		main_litedramcore_trrdcon_count <= 1'd1;
+	litedramcore_dfi_p0_cs_n <= 1'd0;
+	litedramcore_dfi_p0_bank <= array_muxed0;
+	litedramcore_dfi_p0_address <= array_muxed1;
+	litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+	litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+	litedramcore_dfi_p0_we_n <= (~array_muxed4);
+	litedramcore_dfi_p0_rddata_en <= array_muxed5;
+	litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+	litedramcore_dfi_p1_cs_n <= 1'd0;
+	litedramcore_dfi_p1_bank <= array_muxed7;
+	litedramcore_dfi_p1_address <= array_muxed8;
+	litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+	litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+	litedramcore_dfi_p1_we_n <= (~array_muxed11);
+	litedramcore_dfi_p1_rddata_en <= array_muxed12;
+	litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+	litedramcore_dfi_p2_cs_n <= 1'd0;
+	litedramcore_dfi_p2_bank <= array_muxed14;
+	litedramcore_dfi_p2_address <= array_muxed15;
+	litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+	litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+	litedramcore_dfi_p2_we_n <= (~array_muxed18);
+	litedramcore_dfi_p2_rddata_en <= array_muxed19;
+	litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+	litedramcore_dfi_p3_cs_n <= 1'd0;
+	litedramcore_dfi_p3_bank <= array_muxed21;
+	litedramcore_dfi_p3_address <= array_muxed22;
+	litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+	litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+	litedramcore_dfi_p3_we_n <= (~array_muxed25);
+	litedramcore_dfi_p3_rddata_en <= array_muxed26;
+	litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+	if (litedramcore_trrdcon_valid) begin
+		litedramcore_trrdcon_count <= 1'd1;
 		if (1'd0) begin
-			main_litedramcore_trrdcon_ready <= 1'd1;
+			litedramcore_trrdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_trrdcon_ready <= 1'd0;
+			litedramcore_trrdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_trrdcon_ready)) begin
-			main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
-			if ((main_litedramcore_trrdcon_count == 1'd1)) begin
-				main_litedramcore_trrdcon_ready <= 1'd1;
+		if ((~litedramcore_trrdcon_ready)) begin
+			litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+			if ((litedramcore_trrdcon_count == 1'd1)) begin
+				litedramcore_trrdcon_ready <= 1'd1;
 			end
 		end
 	end
-	main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
-	if ((main_litedramcore_tfawcon_count < 3'd4)) begin
-		if ((main_litedramcore_tfawcon_count == 2'd3)) begin
-			main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
+	litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+	if ((litedramcore_tfawcon_count < 3'd4)) begin
+		if ((litedramcore_tfawcon_count == 2'd3)) begin
+			litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
 		end else begin
-			main_litedramcore_tfawcon_ready <= 1'd1;
+			litedramcore_tfawcon_ready <= 1'd1;
 		end
 	end
-	if (main_litedramcore_tccdcon_valid) begin
-		main_litedramcore_tccdcon_count <= 1'd0;
+	if (litedramcore_tccdcon_valid) begin
+		litedramcore_tccdcon_count <= 1'd0;
 		if (1'd1) begin
-			main_litedramcore_tccdcon_ready <= 1'd1;
+			litedramcore_tccdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_tccdcon_ready <= 1'd0;
+			litedramcore_tccdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_tccdcon_ready)) begin
-			main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
-			if ((main_litedramcore_tccdcon_count == 1'd1)) begin
-				main_litedramcore_tccdcon_ready <= 1'd1;
+		if ((~litedramcore_tccdcon_ready)) begin
+			litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+			if ((litedramcore_tccdcon_count == 1'd1)) begin
+				litedramcore_tccdcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_twtrcon_valid) begin
-		main_litedramcore_twtrcon_count <= 3'd4;
+	if (litedramcore_twtrcon_valid) begin
+		litedramcore_twtrcon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_twtrcon_ready <= 1'd1;
+			litedramcore_twtrcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_twtrcon_ready <= 1'd0;
+			litedramcore_twtrcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_twtrcon_ready)) begin
-			main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
-			if ((main_litedramcore_twtrcon_count == 1'd1)) begin
-				main_litedramcore_twtrcon_ready <= 1'd1;
-			end
-		end
-	end
-	builder_multiplexer_state <= builder_multiplexer_next_state;
-	builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
-	builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
-	builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
-	builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
-	builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
-	builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
-	builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
-	builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
-	builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
-	builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
-	builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
-	builder_state <= builder_next_state;
-	if (builder_litedramcore_dat_w_next_value_ce0) begin
-		builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0;
-	end
-	if (builder_litedramcore_adr_next_value_ce1) begin
-		builder_litedramcore_adr <= builder_litedramcore_adr_next_value1;
-	end
-	if (builder_litedramcore_we_next_value_ce2) begin
-		builder_litedramcore_we <= builder_litedramcore_we_next_value2;
-	end
-	builder_interface0_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank0_sel) begin
-		case (builder_interface0_bank_bus_adr[8:0])
+		if ((~litedramcore_twtrcon_ready)) begin
+			litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+			if ((litedramcore_twtrcon_count == 1'd1)) begin
+				litedramcore_twtrcon_ready <= 1'd1;
+			end
+		end
+	end
+	litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+	litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+	litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+	litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+	litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+	litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+	litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+	litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+	litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+	litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+	litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+	litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+	litedramcore_state <= litedramcore_next_state;
+	if (litedramcore_dat_w_next_value_ce0) begin
+		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+	end
+	if (litedramcore_adr_next_value_ce1) begin
+		litedramcore_adr <= litedramcore_adr_next_value1;
+	end
+	if (litedramcore_we_next_value_ce2) begin
+		litedramcore_we <= litedramcore_we_next_value2;
+	end
+	interface0_bank_bus_dat_r <= 1'd0;
+	if (csrbank0_sel) begin
+		case (interface0_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
 			end
 			1'd1: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank0_init_done0_re) begin
-		main_init_done_storage <= builder_csrbank0_init_done0_r;
+	if (csrbank0_init_done0_re) begin
+		init_done_storage <= csrbank0_init_done0_r;
 	end
-	main_init_done_re <= builder_csrbank0_init_done0_re;
-	if (builder_csrbank0_init_error0_re) begin
-		main_init_error_storage <= builder_csrbank0_init_error0_r;
+	init_done_re <= csrbank0_init_done0_re;
+	if (csrbank0_init_error0_re) begin
+		init_error_storage <= csrbank0_init_error0_r;
 	end
-	main_init_error_re <= builder_csrbank0_init_error0_re;
-	builder_interface1_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank1_sel) begin
-		case (builder_interface1_bank_bus_adr[8:0])
+	init_error_re <= csrbank0_init_error0_re;
+	interface1_bank_bus_dat_r <= 1'd0;
+	if (csrbank1_sel) begin
+		case (interface1_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rst0_w;
 			end
 			1'd1: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
 			end
 			2'd2: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
+				interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
 			end
 			2'd3: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wlevel_strobe_w;
+				interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
 			end
 			3'd4: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_rst_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w;
 			end
 			3'd5: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_inc_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_cdly_rst_w;
 			end
 			3'd6: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_cdly_inc_w;
 			end
 			3'd7: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_rst_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w;
 			end
 			4'd8: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_inc_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w;
 			end
 			4'd9: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w;
 			end
 			4'd10: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w;
 			end
 			4'd11: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_rst_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w;
 			end
 			4'd12: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_inc_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w;
 			end
 			4'd13: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_rst_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w;
 			end
 			4'd14: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_inc_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w;
 			end
 			4'd15: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w;
 			end
 			5'd16: begin
-				builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w;
 			end
 			5'd17: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
 			end
 			5'd18: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank1_rst0_re) begin
-		main_k7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
+	if (csrbank1_rst0_re) begin
+		k7ddrphy_rst_storage <= csrbank1_rst0_r;
 	end
-	main_k7ddrphy_rst_re <= builder_csrbank1_rst0_re;
-	if (builder_csrbank1_half_sys8x_taps0_re) begin
-		main_k7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+	k7ddrphy_rst_re <= csrbank1_rst0_re;
+	if (csrbank1_dly_sel0_re) begin
+		k7ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r;
 	end
-	main_k7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
-	if (builder_csrbank1_wlevel_en0_re) begin
-		main_k7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
+	k7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+	if (csrbank1_half_sys8x_taps0_re) begin
+		k7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
 	end
-	main_k7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
-	if (builder_csrbank1_dly_sel0_re) begin
-		main_k7ddrphy_dly_sel_storage[3:0] <= builder_csrbank1_dly_sel0_r;
+	k7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+	if (csrbank1_wlevel_en0_re) begin
+		k7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
 	end
-	main_k7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
-	if (builder_csrbank1_rdphase0_re) begin
-		main_k7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+	k7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+	if (csrbank1_rdphase0_re) begin
+		k7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
 	end
-	main_k7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
-	if (builder_csrbank1_wrphase0_re) begin
-		main_k7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+	k7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+	if (csrbank1_wrphase0_re) begin
+		k7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
 	end
-	main_k7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
-	builder_interface2_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank2_sel) begin
-		case (builder_interface2_bank_bus_adr[8:0])
+	k7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+	interface2_bank_bus_dat_r <= 1'd0;
+	if (csrbank2_sel) begin
+		case (interface2_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
 			end
 			1'd1: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
 			end
 			2'd2: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
 			end
 			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
 			end
 			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
 			end
 			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
 			end
 			5'd25: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
 			end
 			5'd26: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
 			end
 			5'd27: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
 			end
 			5'd28: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
 			end
 			5'd29: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
 			end
 			5'd30: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
 			end
 			5'd31: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
 			end
 			6'd32: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank2_dfii_control0_re) begin
-		main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+	if (csrbank2_dfii_control0_re) begin
+		litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
 	end
-	main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
-	if (builder_csrbank2_dfii_pi0_command0_re) begin
-		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
+	litedramcore_re <= csrbank2_dfii_control0_re;
+	if (csrbank2_dfii_pi0_command0_re) begin
+		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
 	end
-	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
+	litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+	if (csrbank2_dfii_pi0_address0_re) begin
+		litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
 	end
-	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
-	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+	litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+	if (csrbank2_dfii_pi0_baddress0_re) begin
+		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
 	end
-	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi0_wrdata1_r;
+	litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+	if (csrbank2_dfii_pi0_wrdata1_re) begin
+		litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
 	end
-	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+	if (csrbank2_dfii_pi0_wrdata0_re) begin
+		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
-	if (builder_csrbank2_dfii_pi1_command0_re) begin
-		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
+	litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+	litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
+	if (csrbank2_dfii_pi1_command0_re) begin
+		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
 	end
-	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
+	litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+	if (csrbank2_dfii_pi1_address0_re) begin
+		litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
 	end
-	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
-	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+	litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+	if (csrbank2_dfii_pi1_baddress0_re) begin
+		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
 	end
-	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi1_wrdata1_r;
+	litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+	if (csrbank2_dfii_pi1_wrdata1_re) begin
+		litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
 	end
-	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+	if (csrbank2_dfii_pi1_wrdata0_re) begin
+		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
-	if (builder_csrbank2_dfii_pi2_command0_re) begin
-		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
+	litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+	litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
+	if (csrbank2_dfii_pi2_command0_re) begin
+		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
 	end
-	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
+	litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+	if (csrbank2_dfii_pi2_address0_re) begin
+		litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
 	end
-	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
-	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+	litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+	if (csrbank2_dfii_pi2_baddress0_re) begin
+		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
 	end
-	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi2_wrdata1_r;
+	litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+	if (csrbank2_dfii_pi2_wrdata1_re) begin
+		litedramcore_phaseinjector2_wrdata_storage[63:32] <= csrbank2_dfii_pi2_wrdata1_r;
 	end
-	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+	if (csrbank2_dfii_pi2_wrdata0_re) begin
+		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
-	if (builder_csrbank2_dfii_pi3_command0_re) begin
-		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
+	litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+	litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata0_re;
+	if (csrbank2_dfii_pi3_command0_re) begin
+		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
 	end
-	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
+	litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+	if (csrbank2_dfii_pi3_address0_re) begin
+		litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
 	end
-	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
-	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+	litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+	if (csrbank2_dfii_pi3_baddress0_re) begin
+		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
 	end
-	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi3_wrdata1_r;
+	litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+	if (csrbank2_dfii_pi3_wrdata1_re) begin
+		litedramcore_phaseinjector3_wrdata_storage[63:32] <= csrbank2_dfii_pi3_wrdata1_r;
 	end
-	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+	if (csrbank2_dfii_pi3_wrdata0_re) begin
+		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
+	litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+	litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata0_re;
 	if (sys_rst) begin
-		main_k7ddrphy_rst_storage <= 1'd0;
-		main_k7ddrphy_rst_re <= 1'd0;
-		main_k7ddrphy_half_sys8x_taps_storage <= 5'd8;
-		main_k7ddrphy_half_sys8x_taps_re <= 1'd0;
-		main_k7ddrphy_wlevel_en_storage <= 1'd0;
-		main_k7ddrphy_wlevel_en_re <= 1'd0;
-		main_k7ddrphy_dly_sel_storage <= 4'd0;
-		main_k7ddrphy_dly_sel_re <= 1'd0;
-		main_k7ddrphy_rdphase_storage <= 2'd1;
-		main_k7ddrphy_rdphase_re <= 1'd0;
-		main_k7ddrphy_wrphase_storage <= 2'd2;
-		main_k7ddrphy_wrphase_re <= 1'd0;
-		main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_k7ddrphy_bitslip0_value0 <= 3'd7;
-		main_k7ddrphy_bitslip1_value0 <= 3'd7;
-		main_k7ddrphy_bitslip2_value0 <= 3'd7;
-		main_k7ddrphy_bitslip3_value0 <= 3'd7;
-		main_k7ddrphy_bitslip0_value1 <= 3'd7;
-		main_k7ddrphy_bitslip1_value1 <= 3'd7;
-		main_k7ddrphy_bitslip2_value1 <= 3'd7;
-		main_k7ddrphy_bitslip3_value1 <= 3'd7;
-		main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_k7ddrphy_bitslip0_value2 <= 3'd7;
-		main_k7ddrphy_bitslip0_value3 <= 3'd7;
-		main_k7ddrphy_bitslip1_value2 <= 3'd7;
-		main_k7ddrphy_bitslip1_value3 <= 3'd7;
-		main_k7ddrphy_bitslip2_value2 <= 3'd7;
-		main_k7ddrphy_bitslip2_value3 <= 3'd7;
-		main_k7ddrphy_bitslip3_value2 <= 3'd7;
-		main_k7ddrphy_bitslip3_value3 <= 3'd7;
-		main_k7ddrphy_bitslip4_value0 <= 3'd7;
-		main_k7ddrphy_bitslip4_value1 <= 3'd7;
-		main_k7ddrphy_bitslip5_value0 <= 3'd7;
-		main_k7ddrphy_bitslip5_value1 <= 3'd7;
-		main_k7ddrphy_bitslip6_value0 <= 3'd7;
-		main_k7ddrphy_bitslip6_value1 <= 3'd7;
-		main_k7ddrphy_bitslip7_value0 <= 3'd7;
-		main_k7ddrphy_bitslip7_value1 <= 3'd7;
-		main_k7ddrphy_bitslip8_value0 <= 3'd7;
-		main_k7ddrphy_bitslip8_value1 <= 3'd7;
-		main_k7ddrphy_bitslip9_value0 <= 3'd7;
-		main_k7ddrphy_bitslip9_value1 <= 3'd7;
-		main_k7ddrphy_bitslip10_value0 <= 3'd7;
-		main_k7ddrphy_bitslip10_value1 <= 3'd7;
-		main_k7ddrphy_bitslip11_value0 <= 3'd7;
-		main_k7ddrphy_bitslip11_value1 <= 3'd7;
-		main_k7ddrphy_bitslip12_value0 <= 3'd7;
-		main_k7ddrphy_bitslip12_value1 <= 3'd7;
-		main_k7ddrphy_bitslip13_value0 <= 3'd7;
-		main_k7ddrphy_bitslip13_value1 <= 3'd7;
-		main_k7ddrphy_bitslip14_value0 <= 3'd7;
-		main_k7ddrphy_bitslip14_value1 <= 3'd7;
-		main_k7ddrphy_bitslip15_value0 <= 3'd7;
-		main_k7ddrphy_bitslip15_value1 <= 3'd7;
-		main_k7ddrphy_bitslip16_value0 <= 3'd7;
-		main_k7ddrphy_bitslip16_value1 <= 3'd7;
-		main_k7ddrphy_bitslip17_value0 <= 3'd7;
-		main_k7ddrphy_bitslip17_value1 <= 3'd7;
-		main_k7ddrphy_bitslip18_value0 <= 3'd7;
-		main_k7ddrphy_bitslip18_value1 <= 3'd7;
-		main_k7ddrphy_bitslip19_value0 <= 3'd7;
-		main_k7ddrphy_bitslip19_value1 <= 3'd7;
-		main_k7ddrphy_bitslip20_value0 <= 3'd7;
-		main_k7ddrphy_bitslip20_value1 <= 3'd7;
-		main_k7ddrphy_bitslip21_value0 <= 3'd7;
-		main_k7ddrphy_bitslip21_value1 <= 3'd7;
-		main_k7ddrphy_bitslip22_value0 <= 3'd7;
-		main_k7ddrphy_bitslip22_value1 <= 3'd7;
-		main_k7ddrphy_bitslip23_value0 <= 3'd7;
-		main_k7ddrphy_bitslip23_value1 <= 3'd7;
-		main_k7ddrphy_bitslip24_value0 <= 3'd7;
-		main_k7ddrphy_bitslip24_value1 <= 3'd7;
-		main_k7ddrphy_bitslip25_value0 <= 3'd7;
-		main_k7ddrphy_bitslip25_value1 <= 3'd7;
-		main_k7ddrphy_bitslip26_value0 <= 3'd7;
-		main_k7ddrphy_bitslip26_value1 <= 3'd7;
-		main_k7ddrphy_bitslip27_value0 <= 3'd7;
-		main_k7ddrphy_bitslip27_value1 <= 3'd7;
-		main_k7ddrphy_bitslip28_value0 <= 3'd7;
-		main_k7ddrphy_bitslip28_value1 <= 3'd7;
-		main_k7ddrphy_bitslip29_value0 <= 3'd7;
-		main_k7ddrphy_bitslip29_value1 <= 3'd7;
-		main_k7ddrphy_bitslip30_value0 <= 3'd7;
-		main_k7ddrphy_bitslip30_value1 <= 3'd7;
-		main_k7ddrphy_bitslip31_value0 <= 3'd7;
-		main_k7ddrphy_bitslip31_value1 <= 3'd7;
-		main_k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-		main_k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-		main_k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-		main_k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-		main_k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-		main_k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-		main_k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-		main_k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-		main_k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-		main_k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-		main_k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-		main_litedramcore_storage <= 4'd1;
-		main_litedramcore_re <= 1'd0;
-		main_litedramcore_phaseinjector0_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector0_command_re <= 1'd0;
-		main_litedramcore_phaseinjector0_address_re <= 1'd0;
-		main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector0_rddata_status <= 64'd0;
-		main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector1_command_re <= 1'd0;
-		main_litedramcore_phaseinjector1_address_re <= 1'd0;
-		main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_rddata_status <= 64'd0;
-		main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector2_command_re <= 1'd0;
-		main_litedramcore_phaseinjector2_address_re <= 1'd0;
-		main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_rddata_status <= 64'd0;
-		main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector3_command_re <= 1'd0;
-		main_litedramcore_phaseinjector3_address_re <= 1'd0;
-		main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_rddata_status <= 64'd0;
-		main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
-		main_litedramcore_dfi_p0_address <= 15'd0;
-		main_litedramcore_dfi_p0_bank <= 3'd0;
-		main_litedramcore_dfi_p0_cas_n <= 1'd1;
-		main_litedramcore_dfi_p0_cs_n <= 1'd1;
-		main_litedramcore_dfi_p0_ras_n <= 1'd1;
-		main_litedramcore_dfi_p0_we_n <= 1'd1;
-		main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p0_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p1_address <= 15'd0;
-		main_litedramcore_dfi_p1_bank <= 3'd0;
-		main_litedramcore_dfi_p1_cas_n <= 1'd1;
-		main_litedramcore_dfi_p1_cs_n <= 1'd1;
-		main_litedramcore_dfi_p1_ras_n <= 1'd1;
-		main_litedramcore_dfi_p1_we_n <= 1'd1;
-		main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p1_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p2_address <= 15'd0;
-		main_litedramcore_dfi_p2_bank <= 3'd0;
-		main_litedramcore_dfi_p2_cas_n <= 1'd1;
-		main_litedramcore_dfi_p2_cs_n <= 1'd1;
-		main_litedramcore_dfi_p2_ras_n <= 1'd1;
-		main_litedramcore_dfi_p2_we_n <= 1'd1;
-		main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p2_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p3_address <= 15'd0;
-		main_litedramcore_dfi_p3_bank <= 3'd0;
-		main_litedramcore_dfi_p3_cas_n <= 1'd1;
-		main_litedramcore_dfi_p3_cs_n <= 1'd1;
-		main_litedramcore_dfi_p3_ras_n <= 1'd1;
-		main_litedramcore_dfi_p3_we_n <= 1'd1;
-		main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p3_rddata_en <= 1'd0;
-		main_litedramcore_cmd_payload_a <= 15'd0;
-		main_litedramcore_cmd_payload_ba <= 3'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_timer_count1 <= 10'd781;
-		main_litedramcore_postponer_req_o <= 1'd0;
-		main_litedramcore_postponer_count <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd0;
-		main_litedramcore_sequencer_counter <= 6'd0;
-		main_litedramcore_sequencer_count <= 1'd0;
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
-		main_litedramcore_zqcs_executer_done <= 1'd0;
-		main_litedramcore_zqcs_executer_counter <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine0_row <= 15'd0;
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine1_row <= 15'd0;
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine2_row <= 15'd0;
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine3_row <= 15'd0;
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine4_row <= 15'd0;
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine5_row <= 15'd0;
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine6_row <= 15'd0;
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine7_row <= 15'd0;
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trascon_count <= 3'd0;
-		main_litedramcore_choose_cmd_grant <= 3'd0;
-		main_litedramcore_choose_req_grant <= 3'd0;
-		main_litedramcore_trrdcon_ready <= 1'd0;
-		main_litedramcore_trrdcon_count <= 1'd0;
-		main_litedramcore_tfawcon_ready <= 1'd1;
-		main_litedramcore_tfawcon_window <= 5'd0;
-		main_litedramcore_tccdcon_ready <= 1'd0;
-		main_litedramcore_tccdcon_count <= 1'd0;
-		main_litedramcore_twtrcon_ready <= 1'd0;
-		main_litedramcore_twtrcon_count <= 3'd0;
-		main_litedramcore_time0 <= 5'd0;
-		main_litedramcore_time1 <= 4'd0;
-		main_init_done_storage <= 1'd0;
-		main_init_done_re <= 1'd0;
-		main_init_error_storage <= 1'd0;
-		main_init_error_re <= 1'd0;
-		builder_refresher_state <= 2'd0;
-		builder_bankmachine0_state <= 4'd0;
-		builder_bankmachine1_state <= 4'd0;
-		builder_bankmachine2_state <= 4'd0;
-		builder_bankmachine3_state <= 4'd0;
-		builder_bankmachine4_state <= 4'd0;
-		builder_bankmachine5_state <= 4'd0;
-		builder_bankmachine6_state <= 4'd0;
-		builder_bankmachine7_state <= 4'd0;
-		builder_multiplexer_state <= 4'd0;
-		builder_new_master_wdata_ready0 <= 1'd0;
-		builder_new_master_wdata_ready1 <= 1'd0;
-		builder_new_master_rdata_valid0 <= 1'd0;
-		builder_new_master_rdata_valid1 <= 1'd0;
-		builder_new_master_rdata_valid2 <= 1'd0;
-		builder_new_master_rdata_valid3 <= 1'd0;
-		builder_new_master_rdata_valid4 <= 1'd0;
-		builder_new_master_rdata_valid5 <= 1'd0;
-		builder_new_master_rdata_valid6 <= 1'd0;
-		builder_new_master_rdata_valid7 <= 1'd0;
-		builder_new_master_rdata_valid8 <= 1'd0;
-		builder_litedramcore_we <= 1'd0;
-		builder_state <= 2'd0;
+		k7ddrphy_rst_storage <= 1'd0;
+		k7ddrphy_rst_re <= 1'd0;
+		k7ddrphy_dly_sel_storage <= 4'd0;
+		k7ddrphy_dly_sel_re <= 1'd0;
+		k7ddrphy_half_sys8x_taps_storage <= 5'd8;
+		k7ddrphy_half_sys8x_taps_re <= 1'd0;
+		k7ddrphy_wlevel_en_storage <= 1'd0;
+		k7ddrphy_wlevel_en_re <= 1'd0;
+		k7ddrphy_rdphase_storage <= 2'd1;
+		k7ddrphy_rdphase_re <= 1'd0;
+		k7ddrphy_wrphase_storage <= 2'd2;
+		k7ddrphy_wrphase_re <= 1'd0;
+		k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		k7ddrphy_bitslip0_value0 <= 3'd7;
+		k7ddrphy_bitslip1_value0 <= 3'd7;
+		k7ddrphy_bitslip2_value0 <= 3'd7;
+		k7ddrphy_bitslip3_value0 <= 3'd7;
+		k7ddrphy_bitslip0_value1 <= 3'd7;
+		k7ddrphy_bitslip1_value1 <= 3'd7;
+		k7ddrphy_bitslip2_value1 <= 3'd7;
+		k7ddrphy_bitslip3_value1 <= 3'd7;
+		k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		k7ddrphy_bitslip0_value2 <= 3'd7;
+		k7ddrphy_bitslip0_value3 <= 3'd7;
+		k7ddrphy_bitslip1_value2 <= 3'd7;
+		k7ddrphy_bitslip1_value3 <= 3'd7;
+		k7ddrphy_bitslip2_value2 <= 3'd7;
+		k7ddrphy_bitslip2_value3 <= 3'd7;
+		k7ddrphy_bitslip3_value2 <= 3'd7;
+		k7ddrphy_bitslip3_value3 <= 3'd7;
+		k7ddrphy_bitslip4_value0 <= 3'd7;
+		k7ddrphy_bitslip4_value1 <= 3'd7;
+		k7ddrphy_bitslip5_value0 <= 3'd7;
+		k7ddrphy_bitslip5_value1 <= 3'd7;
+		k7ddrphy_bitslip6_value0 <= 3'd7;
+		k7ddrphy_bitslip6_value1 <= 3'd7;
+		k7ddrphy_bitslip7_value0 <= 3'd7;
+		k7ddrphy_bitslip7_value1 <= 3'd7;
+		k7ddrphy_bitslip8_value0 <= 3'd7;
+		k7ddrphy_bitslip8_value1 <= 3'd7;
+		k7ddrphy_bitslip9_value0 <= 3'd7;
+		k7ddrphy_bitslip9_value1 <= 3'd7;
+		k7ddrphy_bitslip10_value0 <= 3'd7;
+		k7ddrphy_bitslip10_value1 <= 3'd7;
+		k7ddrphy_bitslip11_value0 <= 3'd7;
+		k7ddrphy_bitslip11_value1 <= 3'd7;
+		k7ddrphy_bitslip12_value0 <= 3'd7;
+		k7ddrphy_bitslip12_value1 <= 3'd7;
+		k7ddrphy_bitslip13_value0 <= 3'd7;
+		k7ddrphy_bitslip13_value1 <= 3'd7;
+		k7ddrphy_bitslip14_value0 <= 3'd7;
+		k7ddrphy_bitslip14_value1 <= 3'd7;
+		k7ddrphy_bitslip15_value0 <= 3'd7;
+		k7ddrphy_bitslip15_value1 <= 3'd7;
+		k7ddrphy_bitslip16_value0 <= 3'd7;
+		k7ddrphy_bitslip16_value1 <= 3'd7;
+		k7ddrphy_bitslip17_value0 <= 3'd7;
+		k7ddrphy_bitslip17_value1 <= 3'd7;
+		k7ddrphy_bitslip18_value0 <= 3'd7;
+		k7ddrphy_bitslip18_value1 <= 3'd7;
+		k7ddrphy_bitslip19_value0 <= 3'd7;
+		k7ddrphy_bitslip19_value1 <= 3'd7;
+		k7ddrphy_bitslip20_value0 <= 3'd7;
+		k7ddrphy_bitslip20_value1 <= 3'd7;
+		k7ddrphy_bitslip21_value0 <= 3'd7;
+		k7ddrphy_bitslip21_value1 <= 3'd7;
+		k7ddrphy_bitslip22_value0 <= 3'd7;
+		k7ddrphy_bitslip22_value1 <= 3'd7;
+		k7ddrphy_bitslip23_value0 <= 3'd7;
+		k7ddrphy_bitslip23_value1 <= 3'd7;
+		k7ddrphy_bitslip24_value0 <= 3'd7;
+		k7ddrphy_bitslip24_value1 <= 3'd7;
+		k7ddrphy_bitslip25_value0 <= 3'd7;
+		k7ddrphy_bitslip25_value1 <= 3'd7;
+		k7ddrphy_bitslip26_value0 <= 3'd7;
+		k7ddrphy_bitslip26_value1 <= 3'd7;
+		k7ddrphy_bitslip27_value0 <= 3'd7;
+		k7ddrphy_bitslip27_value1 <= 3'd7;
+		k7ddrphy_bitslip28_value0 <= 3'd7;
+		k7ddrphy_bitslip28_value1 <= 3'd7;
+		k7ddrphy_bitslip29_value0 <= 3'd7;
+		k7ddrphy_bitslip29_value1 <= 3'd7;
+		k7ddrphy_bitslip30_value0 <= 3'd7;
+		k7ddrphy_bitslip30_value1 <= 3'd7;
+		k7ddrphy_bitslip31_value0 <= 3'd7;
+		k7ddrphy_bitslip31_value1 <= 3'd7;
+		k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+		k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+		k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+		k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+		k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+		k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+		k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+		k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+		k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+		k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+		k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+		litedramcore_storage <= 4'd1;
+		litedramcore_re <= 1'd0;
+		litedramcore_phaseinjector0_command_storage <= 6'd0;
+		litedramcore_phaseinjector0_command_re <= 1'd0;
+		litedramcore_phaseinjector0_address_re <= 1'd0;
+		litedramcore_phaseinjector0_baddress_re <= 1'd0;
+		litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector0_rddata_status <= 64'd0;
+		litedramcore_phaseinjector0_rddata_re <= 1'd0;
+		litedramcore_phaseinjector1_command_storage <= 6'd0;
+		litedramcore_phaseinjector1_command_re <= 1'd0;
+		litedramcore_phaseinjector1_address_re <= 1'd0;
+		litedramcore_phaseinjector1_baddress_re <= 1'd0;
+		litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector1_rddata_status <= 64'd0;
+		litedramcore_phaseinjector1_rddata_re <= 1'd0;
+		litedramcore_phaseinjector2_command_storage <= 6'd0;
+		litedramcore_phaseinjector2_command_re <= 1'd0;
+		litedramcore_phaseinjector2_address_re <= 1'd0;
+		litedramcore_phaseinjector2_baddress_re <= 1'd0;
+		litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector2_rddata_status <= 64'd0;
+		litedramcore_phaseinjector2_rddata_re <= 1'd0;
+		litedramcore_phaseinjector3_command_storage <= 6'd0;
+		litedramcore_phaseinjector3_command_re <= 1'd0;
+		litedramcore_phaseinjector3_address_re <= 1'd0;
+		litedramcore_phaseinjector3_baddress_re <= 1'd0;
+		litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector3_rddata_status <= 64'd0;
+		litedramcore_phaseinjector3_rddata_re <= 1'd0;
+		litedramcore_dfi_p0_address <= 15'd0;
+		litedramcore_dfi_p0_bank <= 3'd0;
+		litedramcore_dfi_p0_cas_n <= 1'd1;
+		litedramcore_dfi_p0_cs_n <= 1'd1;
+		litedramcore_dfi_p0_ras_n <= 1'd1;
+		litedramcore_dfi_p0_we_n <= 1'd1;
+		litedramcore_dfi_p0_wrdata_en <= 1'd0;
+		litedramcore_dfi_p0_rddata_en <= 1'd0;
+		litedramcore_dfi_p1_address <= 15'd0;
+		litedramcore_dfi_p1_bank <= 3'd0;
+		litedramcore_dfi_p1_cas_n <= 1'd1;
+		litedramcore_dfi_p1_cs_n <= 1'd1;
+		litedramcore_dfi_p1_ras_n <= 1'd1;
+		litedramcore_dfi_p1_we_n <= 1'd1;
+		litedramcore_dfi_p1_wrdata_en <= 1'd0;
+		litedramcore_dfi_p1_rddata_en <= 1'd0;
+		litedramcore_dfi_p2_address <= 15'd0;
+		litedramcore_dfi_p2_bank <= 3'd0;
+		litedramcore_dfi_p2_cas_n <= 1'd1;
+		litedramcore_dfi_p2_cs_n <= 1'd1;
+		litedramcore_dfi_p2_ras_n <= 1'd1;
+		litedramcore_dfi_p2_we_n <= 1'd1;
+		litedramcore_dfi_p2_wrdata_en <= 1'd0;
+		litedramcore_dfi_p2_rddata_en <= 1'd0;
+		litedramcore_dfi_p3_address <= 15'd0;
+		litedramcore_dfi_p3_bank <= 3'd0;
+		litedramcore_dfi_p3_cas_n <= 1'd1;
+		litedramcore_dfi_p3_cs_n <= 1'd1;
+		litedramcore_dfi_p3_ras_n <= 1'd1;
+		litedramcore_dfi_p3_we_n <= 1'd1;
+		litedramcore_dfi_p3_wrdata_en <= 1'd0;
+		litedramcore_dfi_p3_rddata_en <= 1'd0;
+		litedramcore_cmd_payload_a <= 15'd0;
+		litedramcore_cmd_payload_ba <= 3'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_timer_count1 <= 10'd781;
+		litedramcore_postponer_req_o <= 1'd0;
+		litedramcore_postponer_count <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd0;
+		litedramcore_sequencer_counter <= 6'd0;
+		litedramcore_sequencer_count <= 1'd0;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_executer_done <= 1'd0;
+		litedramcore_zqcs_executer_counter <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine0_row <= 15'd0;
+		litedramcore_bankmachine0_row_opened <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine0_trccon_ready <= 1'd0;
+		litedramcore_bankmachine0_trccon_count <= 3'd0;
+		litedramcore_bankmachine0_trascon_ready <= 1'd0;
+		litedramcore_bankmachine0_trascon_count <= 3'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine1_row <= 15'd0;
+		litedramcore_bankmachine1_row_opened <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine1_trccon_ready <= 1'd0;
+		litedramcore_bankmachine1_trccon_count <= 3'd0;
+		litedramcore_bankmachine1_trascon_ready <= 1'd0;
+		litedramcore_bankmachine1_trascon_count <= 3'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine2_row <= 15'd0;
+		litedramcore_bankmachine2_row_opened <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine2_trccon_ready <= 1'd0;
+		litedramcore_bankmachine2_trccon_count <= 3'd0;
+		litedramcore_bankmachine2_trascon_ready <= 1'd0;
+		litedramcore_bankmachine2_trascon_count <= 3'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine3_row <= 15'd0;
+		litedramcore_bankmachine3_row_opened <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine3_trccon_ready <= 1'd0;
+		litedramcore_bankmachine3_trccon_count <= 3'd0;
+		litedramcore_bankmachine3_trascon_ready <= 1'd0;
+		litedramcore_bankmachine3_trascon_count <= 3'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine4_row <= 15'd0;
+		litedramcore_bankmachine4_row_opened <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine4_trccon_ready <= 1'd0;
+		litedramcore_bankmachine4_trccon_count <= 3'd0;
+		litedramcore_bankmachine4_trascon_ready <= 1'd0;
+		litedramcore_bankmachine4_trascon_count <= 3'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine5_row <= 15'd0;
+		litedramcore_bankmachine5_row_opened <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine5_trccon_ready <= 1'd0;
+		litedramcore_bankmachine5_trccon_count <= 3'd0;
+		litedramcore_bankmachine5_trascon_ready <= 1'd0;
+		litedramcore_bankmachine5_trascon_count <= 3'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine6_row <= 15'd0;
+		litedramcore_bankmachine6_row_opened <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine6_trccon_ready <= 1'd0;
+		litedramcore_bankmachine6_trccon_count <= 3'd0;
+		litedramcore_bankmachine6_trascon_ready <= 1'd0;
+		litedramcore_bankmachine6_trascon_count <= 3'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine7_row <= 15'd0;
+		litedramcore_bankmachine7_row_opened <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine7_trccon_ready <= 1'd0;
+		litedramcore_bankmachine7_trccon_count <= 3'd0;
+		litedramcore_bankmachine7_trascon_ready <= 1'd0;
+		litedramcore_bankmachine7_trascon_count <= 3'd0;
+		litedramcore_choose_cmd_grant <= 3'd0;
+		litedramcore_choose_req_grant <= 3'd0;
+		litedramcore_trrdcon_ready <= 1'd0;
+		litedramcore_trrdcon_count <= 1'd0;
+		litedramcore_tfawcon_ready <= 1'd1;
+		litedramcore_tfawcon_window <= 5'd0;
+		litedramcore_tccdcon_ready <= 1'd0;
+		litedramcore_tccdcon_count <= 1'd0;
+		litedramcore_twtrcon_ready <= 1'd0;
+		litedramcore_twtrcon_count <= 3'd0;
+		litedramcore_time0 <= 5'd0;
+		litedramcore_time1 <= 4'd0;
+		init_done_storage <= 1'd0;
+		init_done_re <= 1'd0;
+		init_error_storage <= 1'd0;
+		init_error_re <= 1'd0;
+		litedramcore_we <= 1'd0;
+		litedramcore_refresher_state <= 2'd0;
+		litedramcore_bankmachine0_state <= 4'd0;
+		litedramcore_bankmachine1_state <= 4'd0;
+		litedramcore_bankmachine2_state <= 4'd0;
+		litedramcore_bankmachine3_state <= 4'd0;
+		litedramcore_bankmachine4_state <= 4'd0;
+		litedramcore_bankmachine5_state <= 4'd0;
+		litedramcore_bankmachine6_state <= 4'd0;
+		litedramcore_bankmachine7_state <= 4'd0;
+		litedramcore_multiplexer_state <= 4'd0;
+		litedramcore_new_master_wdata_ready0 <= 1'd0;
+		litedramcore_new_master_wdata_ready1 <= 1'd0;
+		litedramcore_new_master_rdata_valid0 <= 1'd0;
+		litedramcore_new_master_rdata_valid1 <= 1'd0;
+		litedramcore_new_master_rdata_valid2 <= 1'd0;
+		litedramcore_new_master_rdata_valid3 <= 1'd0;
+		litedramcore_new_master_rdata_valid4 <= 1'd0;
+		litedramcore_new_master_rdata_valid5 <= 1'd0;
+		litedramcore_new_master_rdata_valid6 <= 1'd0;
+		litedramcore_new_master_rdata_valid7 <= 1'd0;
+		litedramcore_new_master_rdata_valid8 <= 1'd0;
+		litedramcore_state <= 2'd0;
 	end
 end
 
@@ -15471,28 +15914,28 @@ end
 //------------------------------------------------------------------------------
 
 BUFG BUFG(
-	.I(main_clkout0),
-	.O(main_clkout_buf0)
+	.I(clkout0),
+	.O(clkout_buf0)
 );
 
 BUFG BUFG_1(
-	.I(main_clkout1),
-	.O(main_clkout_buf1)
+	.I(clkout1),
+	.O(clkout_buf1)
 );
 
 BUFG BUFG_2(
-	.I(main_clkout2),
-	.O(main_clkout_buf2)
+	.I(clkout2),
+	.O(clkout_buf2)
 );
 
 BUFG BUFG_3(
-	.I(main_clkout3),
-	.O(main_clkout_buf3)
+	.I(clkout3),
+	.O(clkout_buf3)
 );
 
 IDELAYCTRL IDELAYCTRL(
 	.REFCLK(iodelay_clk),
-	.RST(main_ic_reset)
+	.RST(ic_reset)
 );
 
 OSERDESE2 #(
@@ -15513,8 +15956,8 @@ OSERDESE2 #(
 	.D7(1'd0),
 	.D8(1'd1),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_sd_clk_se_nodelay)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_sd_clk_se_nodelay)
 );
 
 ODELAYE2 #(
@@ -15528,16 +15971,16 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_sd_clk_se_delayed),
-	.ODATAIN(main_k7ddrphy_sd_clk_se_nodelay)
+	.DATAOUT(k7ddrphy_sd_clk_se_delayed),
+	.ODATAIN(k7ddrphy_sd_clk_se_nodelay)
 );
 
 OBUFDS OBUFDS(
-	.I(main_k7ddrphy_sd_clk_se_delayed),
+	.I(k7ddrphy_sd_clk_se_delayed),
 	.O(ddram_clk_p),
 	.OB(ddram_clk_n)
 );
@@ -15551,17 +15994,17 @@ OSERDESE2 #(
 ) OSERDESE2_1 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_reset_n),
-	.D2(main_k7ddrphy_dfi_p0_reset_n),
-	.D3(main_k7ddrphy_dfi_p1_reset_n),
-	.D4(main_k7ddrphy_dfi_p1_reset_n),
-	.D5(main_k7ddrphy_dfi_p2_reset_n),
-	.D6(main_k7ddrphy_dfi_p2_reset_n),
-	.D7(main_k7ddrphy_dfi_p3_reset_n),
-	.D8(main_k7ddrphy_dfi_p3_reset_n),
+	.D1(k7ddrphy_dfi_p0_reset_n),
+	.D2(k7ddrphy_dfi_p0_reset_n),
+	.D3(k7ddrphy_dfi_p1_reset_n),
+	.D4(k7ddrphy_dfi_p1_reset_n),
+	.D5(k7ddrphy_dfi_p2_reset_n),
+	.D6(k7ddrphy_dfi_p2_reset_n),
+	.D7(k7ddrphy_dfi_p3_reset_n),
+	.D8(k7ddrphy_dfi_p3_reset_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq0)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq0)
 );
 
 ODELAYE2 #(
@@ -15575,12 +16018,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_1 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_reset_n),
-	.ODATAIN(main_k7ddrphy_oq0)
+	.ODATAIN(k7ddrphy_oq0)
 );
 
 OSERDESE2 #(
@@ -15592,17 +16035,17 @@ OSERDESE2 #(
 ) OSERDESE2_2 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_cs_n),
-	.D2(main_k7ddrphy_dfi_p0_cs_n),
-	.D3(main_k7ddrphy_dfi_p1_cs_n),
-	.D4(main_k7ddrphy_dfi_p1_cs_n),
-	.D5(main_k7ddrphy_dfi_p2_cs_n),
-	.D6(main_k7ddrphy_dfi_p2_cs_n),
-	.D7(main_k7ddrphy_dfi_p3_cs_n),
-	.D8(main_k7ddrphy_dfi_p3_cs_n),
+	.D1(k7ddrphy_dfi_p0_cs_n),
+	.D2(k7ddrphy_dfi_p0_cs_n),
+	.D3(k7ddrphy_dfi_p1_cs_n),
+	.D4(k7ddrphy_dfi_p1_cs_n),
+	.D5(k7ddrphy_dfi_p2_cs_n),
+	.D6(k7ddrphy_dfi_p2_cs_n),
+	.D7(k7ddrphy_dfi_p3_cs_n),
+	.D8(k7ddrphy_dfi_p3_cs_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq1)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq1)
 );
 
 ODELAYE2 #(
@@ -15616,12 +16059,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_2 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_cs_n),
-	.ODATAIN(main_k7ddrphy_oq1)
+	.ODATAIN(k7ddrphy_oq1)
 );
 
 OSERDESE2 #(
@@ -15633,17 +16076,17 @@ OSERDESE2 #(
 ) OSERDESE2_3 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[0]),
-	.D2(main_k7ddrphy_dfi_p0_address[0]),
-	.D3(main_k7ddrphy_dfi_p1_address[0]),
-	.D4(main_k7ddrphy_dfi_p1_address[0]),
-	.D5(main_k7ddrphy_dfi_p2_address[0]),
-	.D6(main_k7ddrphy_dfi_p2_address[0]),
-	.D7(main_k7ddrphy_dfi_p3_address[0]),
-	.D8(main_k7ddrphy_dfi_p3_address[0]),
+	.D1(k7ddrphy_dfi_p0_address[0]),
+	.D2(k7ddrphy_dfi_p0_address[0]),
+	.D3(k7ddrphy_dfi_p1_address[0]),
+	.D4(k7ddrphy_dfi_p1_address[0]),
+	.D5(k7ddrphy_dfi_p2_address[0]),
+	.D6(k7ddrphy_dfi_p2_address[0]),
+	.D7(k7ddrphy_dfi_p3_address[0]),
+	.D8(k7ddrphy_dfi_p3_address[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq2)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq2)
 );
 
 ODELAYE2 #(
@@ -15657,12 +16100,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_3 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[0]),
-	.ODATAIN(main_k7ddrphy_oq2)
+	.ODATAIN(k7ddrphy_oq2)
 );
 
 OSERDESE2 #(
@@ -15674,17 +16117,17 @@ OSERDESE2 #(
 ) OSERDESE2_4 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[1]),
-	.D2(main_k7ddrphy_dfi_p0_address[1]),
-	.D3(main_k7ddrphy_dfi_p1_address[1]),
-	.D4(main_k7ddrphy_dfi_p1_address[1]),
-	.D5(main_k7ddrphy_dfi_p2_address[1]),
-	.D6(main_k7ddrphy_dfi_p2_address[1]),
-	.D7(main_k7ddrphy_dfi_p3_address[1]),
-	.D8(main_k7ddrphy_dfi_p3_address[1]),
+	.D1(k7ddrphy_dfi_p0_address[1]),
+	.D2(k7ddrphy_dfi_p0_address[1]),
+	.D3(k7ddrphy_dfi_p1_address[1]),
+	.D4(k7ddrphy_dfi_p1_address[1]),
+	.D5(k7ddrphy_dfi_p2_address[1]),
+	.D6(k7ddrphy_dfi_p2_address[1]),
+	.D7(k7ddrphy_dfi_p3_address[1]),
+	.D8(k7ddrphy_dfi_p3_address[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq3)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq3)
 );
 
 ODELAYE2 #(
@@ -15698,12 +16141,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_4 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[1]),
-	.ODATAIN(main_k7ddrphy_oq3)
+	.ODATAIN(k7ddrphy_oq3)
 );
 
 OSERDESE2 #(
@@ -15715,17 +16158,17 @@ OSERDESE2 #(
 ) OSERDESE2_5 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[2]),
-	.D2(main_k7ddrphy_dfi_p0_address[2]),
-	.D3(main_k7ddrphy_dfi_p1_address[2]),
-	.D4(main_k7ddrphy_dfi_p1_address[2]),
-	.D5(main_k7ddrphy_dfi_p2_address[2]),
-	.D6(main_k7ddrphy_dfi_p2_address[2]),
-	.D7(main_k7ddrphy_dfi_p3_address[2]),
-	.D8(main_k7ddrphy_dfi_p3_address[2]),
+	.D1(k7ddrphy_dfi_p0_address[2]),
+	.D2(k7ddrphy_dfi_p0_address[2]),
+	.D3(k7ddrphy_dfi_p1_address[2]),
+	.D4(k7ddrphy_dfi_p1_address[2]),
+	.D5(k7ddrphy_dfi_p2_address[2]),
+	.D6(k7ddrphy_dfi_p2_address[2]),
+	.D7(k7ddrphy_dfi_p3_address[2]),
+	.D8(k7ddrphy_dfi_p3_address[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq4)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq4)
 );
 
 ODELAYE2 #(
@@ -15739,12 +16182,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_5 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[2]),
-	.ODATAIN(main_k7ddrphy_oq4)
+	.ODATAIN(k7ddrphy_oq4)
 );
 
 OSERDESE2 #(
@@ -15756,17 +16199,17 @@ OSERDESE2 #(
 ) OSERDESE2_6 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[3]),
-	.D2(main_k7ddrphy_dfi_p0_address[3]),
-	.D3(main_k7ddrphy_dfi_p1_address[3]),
-	.D4(main_k7ddrphy_dfi_p1_address[3]),
-	.D5(main_k7ddrphy_dfi_p2_address[3]),
-	.D6(main_k7ddrphy_dfi_p2_address[3]),
-	.D7(main_k7ddrphy_dfi_p3_address[3]),
-	.D8(main_k7ddrphy_dfi_p3_address[3]),
+	.D1(k7ddrphy_dfi_p0_address[3]),
+	.D2(k7ddrphy_dfi_p0_address[3]),
+	.D3(k7ddrphy_dfi_p1_address[3]),
+	.D4(k7ddrphy_dfi_p1_address[3]),
+	.D5(k7ddrphy_dfi_p2_address[3]),
+	.D6(k7ddrphy_dfi_p2_address[3]),
+	.D7(k7ddrphy_dfi_p3_address[3]),
+	.D8(k7ddrphy_dfi_p3_address[3]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq5)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq5)
 );
 
 ODELAYE2 #(
@@ -15780,12 +16223,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_6 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[3]),
-	.ODATAIN(main_k7ddrphy_oq5)
+	.ODATAIN(k7ddrphy_oq5)
 );
 
 OSERDESE2 #(
@@ -15797,17 +16240,17 @@ OSERDESE2 #(
 ) OSERDESE2_7 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[4]),
-	.D2(main_k7ddrphy_dfi_p0_address[4]),
-	.D3(main_k7ddrphy_dfi_p1_address[4]),
-	.D4(main_k7ddrphy_dfi_p1_address[4]),
-	.D5(main_k7ddrphy_dfi_p2_address[4]),
-	.D6(main_k7ddrphy_dfi_p2_address[4]),
-	.D7(main_k7ddrphy_dfi_p3_address[4]),
-	.D8(main_k7ddrphy_dfi_p3_address[4]),
+	.D1(k7ddrphy_dfi_p0_address[4]),
+	.D2(k7ddrphy_dfi_p0_address[4]),
+	.D3(k7ddrphy_dfi_p1_address[4]),
+	.D4(k7ddrphy_dfi_p1_address[4]),
+	.D5(k7ddrphy_dfi_p2_address[4]),
+	.D6(k7ddrphy_dfi_p2_address[4]),
+	.D7(k7ddrphy_dfi_p3_address[4]),
+	.D8(k7ddrphy_dfi_p3_address[4]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq6)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq6)
 );
 
 ODELAYE2 #(
@@ -15821,12 +16264,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_7 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[4]),
-	.ODATAIN(main_k7ddrphy_oq6)
+	.ODATAIN(k7ddrphy_oq6)
 );
 
 OSERDESE2 #(
@@ -15838,17 +16281,17 @@ OSERDESE2 #(
 ) OSERDESE2_8 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[5]),
-	.D2(main_k7ddrphy_dfi_p0_address[5]),
-	.D3(main_k7ddrphy_dfi_p1_address[5]),
-	.D4(main_k7ddrphy_dfi_p1_address[5]),
-	.D5(main_k7ddrphy_dfi_p2_address[5]),
-	.D6(main_k7ddrphy_dfi_p2_address[5]),
-	.D7(main_k7ddrphy_dfi_p3_address[5]),
-	.D8(main_k7ddrphy_dfi_p3_address[5]),
+	.D1(k7ddrphy_dfi_p0_address[5]),
+	.D2(k7ddrphy_dfi_p0_address[5]),
+	.D3(k7ddrphy_dfi_p1_address[5]),
+	.D4(k7ddrphy_dfi_p1_address[5]),
+	.D5(k7ddrphy_dfi_p2_address[5]),
+	.D6(k7ddrphy_dfi_p2_address[5]),
+	.D7(k7ddrphy_dfi_p3_address[5]),
+	.D8(k7ddrphy_dfi_p3_address[5]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq7)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq7)
 );
 
 ODELAYE2 #(
@@ -15862,12 +16305,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_8 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[5]),
-	.ODATAIN(main_k7ddrphy_oq7)
+	.ODATAIN(k7ddrphy_oq7)
 );
 
 OSERDESE2 #(
@@ -15879,17 +16322,17 @@ OSERDESE2 #(
 ) OSERDESE2_9 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[6]),
-	.D2(main_k7ddrphy_dfi_p0_address[6]),
-	.D3(main_k7ddrphy_dfi_p1_address[6]),
-	.D4(main_k7ddrphy_dfi_p1_address[6]),
-	.D5(main_k7ddrphy_dfi_p2_address[6]),
-	.D6(main_k7ddrphy_dfi_p2_address[6]),
-	.D7(main_k7ddrphy_dfi_p3_address[6]),
-	.D8(main_k7ddrphy_dfi_p3_address[6]),
+	.D1(k7ddrphy_dfi_p0_address[6]),
+	.D2(k7ddrphy_dfi_p0_address[6]),
+	.D3(k7ddrphy_dfi_p1_address[6]),
+	.D4(k7ddrphy_dfi_p1_address[6]),
+	.D5(k7ddrphy_dfi_p2_address[6]),
+	.D6(k7ddrphy_dfi_p2_address[6]),
+	.D7(k7ddrphy_dfi_p3_address[6]),
+	.D8(k7ddrphy_dfi_p3_address[6]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq8)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq8)
 );
 
 ODELAYE2 #(
@@ -15903,12 +16346,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_9 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[6]),
-	.ODATAIN(main_k7ddrphy_oq8)
+	.ODATAIN(k7ddrphy_oq8)
 );
 
 OSERDESE2 #(
@@ -15920,17 +16363,17 @@ OSERDESE2 #(
 ) OSERDESE2_10 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[7]),
-	.D2(main_k7ddrphy_dfi_p0_address[7]),
-	.D3(main_k7ddrphy_dfi_p1_address[7]),
-	.D4(main_k7ddrphy_dfi_p1_address[7]),
-	.D5(main_k7ddrphy_dfi_p2_address[7]),
-	.D6(main_k7ddrphy_dfi_p2_address[7]),
-	.D7(main_k7ddrphy_dfi_p3_address[7]),
-	.D8(main_k7ddrphy_dfi_p3_address[7]),
+	.D1(k7ddrphy_dfi_p0_address[7]),
+	.D2(k7ddrphy_dfi_p0_address[7]),
+	.D3(k7ddrphy_dfi_p1_address[7]),
+	.D4(k7ddrphy_dfi_p1_address[7]),
+	.D5(k7ddrphy_dfi_p2_address[7]),
+	.D6(k7ddrphy_dfi_p2_address[7]),
+	.D7(k7ddrphy_dfi_p3_address[7]),
+	.D8(k7ddrphy_dfi_p3_address[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq9)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq9)
 );
 
 ODELAYE2 #(
@@ -15944,12 +16387,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_10 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[7]),
-	.ODATAIN(main_k7ddrphy_oq9)
+	.ODATAIN(k7ddrphy_oq9)
 );
 
 OSERDESE2 #(
@@ -15961,17 +16404,17 @@ OSERDESE2 #(
 ) OSERDESE2_11 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[8]),
-	.D2(main_k7ddrphy_dfi_p0_address[8]),
-	.D3(main_k7ddrphy_dfi_p1_address[8]),
-	.D4(main_k7ddrphy_dfi_p1_address[8]),
-	.D5(main_k7ddrphy_dfi_p2_address[8]),
-	.D6(main_k7ddrphy_dfi_p2_address[8]),
-	.D7(main_k7ddrphy_dfi_p3_address[8]),
-	.D8(main_k7ddrphy_dfi_p3_address[8]),
+	.D1(k7ddrphy_dfi_p0_address[8]),
+	.D2(k7ddrphy_dfi_p0_address[8]),
+	.D3(k7ddrphy_dfi_p1_address[8]),
+	.D4(k7ddrphy_dfi_p1_address[8]),
+	.D5(k7ddrphy_dfi_p2_address[8]),
+	.D6(k7ddrphy_dfi_p2_address[8]),
+	.D7(k7ddrphy_dfi_p3_address[8]),
+	.D8(k7ddrphy_dfi_p3_address[8]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq10)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq10)
 );
 
 ODELAYE2 #(
@@ -15985,12 +16428,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_11 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[8]),
-	.ODATAIN(main_k7ddrphy_oq10)
+	.ODATAIN(k7ddrphy_oq10)
 );
 
 OSERDESE2 #(
@@ -16002,17 +16445,17 @@ OSERDESE2 #(
 ) OSERDESE2_12 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[9]),
-	.D2(main_k7ddrphy_dfi_p0_address[9]),
-	.D3(main_k7ddrphy_dfi_p1_address[9]),
-	.D4(main_k7ddrphy_dfi_p1_address[9]),
-	.D5(main_k7ddrphy_dfi_p2_address[9]),
-	.D6(main_k7ddrphy_dfi_p2_address[9]),
-	.D7(main_k7ddrphy_dfi_p3_address[9]),
-	.D8(main_k7ddrphy_dfi_p3_address[9]),
+	.D1(k7ddrphy_dfi_p0_address[9]),
+	.D2(k7ddrphy_dfi_p0_address[9]),
+	.D3(k7ddrphy_dfi_p1_address[9]),
+	.D4(k7ddrphy_dfi_p1_address[9]),
+	.D5(k7ddrphy_dfi_p2_address[9]),
+	.D6(k7ddrphy_dfi_p2_address[9]),
+	.D7(k7ddrphy_dfi_p3_address[9]),
+	.D8(k7ddrphy_dfi_p3_address[9]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq11)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq11)
 );
 
 ODELAYE2 #(
@@ -16026,12 +16469,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_12 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[9]),
-	.ODATAIN(main_k7ddrphy_oq11)
+	.ODATAIN(k7ddrphy_oq11)
 );
 
 OSERDESE2 #(
@@ -16043,17 +16486,17 @@ OSERDESE2 #(
 ) OSERDESE2_13 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[10]),
-	.D2(main_k7ddrphy_dfi_p0_address[10]),
-	.D3(main_k7ddrphy_dfi_p1_address[10]),
-	.D4(main_k7ddrphy_dfi_p1_address[10]),
-	.D5(main_k7ddrphy_dfi_p2_address[10]),
-	.D6(main_k7ddrphy_dfi_p2_address[10]),
-	.D7(main_k7ddrphy_dfi_p3_address[10]),
-	.D8(main_k7ddrphy_dfi_p3_address[10]),
+	.D1(k7ddrphy_dfi_p0_address[10]),
+	.D2(k7ddrphy_dfi_p0_address[10]),
+	.D3(k7ddrphy_dfi_p1_address[10]),
+	.D4(k7ddrphy_dfi_p1_address[10]),
+	.D5(k7ddrphy_dfi_p2_address[10]),
+	.D6(k7ddrphy_dfi_p2_address[10]),
+	.D7(k7ddrphy_dfi_p3_address[10]),
+	.D8(k7ddrphy_dfi_p3_address[10]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq12)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq12)
 );
 
 ODELAYE2 #(
@@ -16067,12 +16510,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_13 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[10]),
-	.ODATAIN(main_k7ddrphy_oq12)
+	.ODATAIN(k7ddrphy_oq12)
 );
 
 OSERDESE2 #(
@@ -16084,17 +16527,17 @@ OSERDESE2 #(
 ) OSERDESE2_14 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[11]),
-	.D2(main_k7ddrphy_dfi_p0_address[11]),
-	.D3(main_k7ddrphy_dfi_p1_address[11]),
-	.D4(main_k7ddrphy_dfi_p1_address[11]),
-	.D5(main_k7ddrphy_dfi_p2_address[11]),
-	.D6(main_k7ddrphy_dfi_p2_address[11]),
-	.D7(main_k7ddrphy_dfi_p3_address[11]),
-	.D8(main_k7ddrphy_dfi_p3_address[11]),
+	.D1(k7ddrphy_dfi_p0_address[11]),
+	.D2(k7ddrphy_dfi_p0_address[11]),
+	.D3(k7ddrphy_dfi_p1_address[11]),
+	.D4(k7ddrphy_dfi_p1_address[11]),
+	.D5(k7ddrphy_dfi_p2_address[11]),
+	.D6(k7ddrphy_dfi_p2_address[11]),
+	.D7(k7ddrphy_dfi_p3_address[11]),
+	.D8(k7ddrphy_dfi_p3_address[11]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq13)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq13)
 );
 
 ODELAYE2 #(
@@ -16108,12 +16551,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_14 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[11]),
-	.ODATAIN(main_k7ddrphy_oq13)
+	.ODATAIN(k7ddrphy_oq13)
 );
 
 OSERDESE2 #(
@@ -16125,17 +16568,17 @@ OSERDESE2 #(
 ) OSERDESE2_15 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[12]),
-	.D2(main_k7ddrphy_dfi_p0_address[12]),
-	.D3(main_k7ddrphy_dfi_p1_address[12]),
-	.D4(main_k7ddrphy_dfi_p1_address[12]),
-	.D5(main_k7ddrphy_dfi_p2_address[12]),
-	.D6(main_k7ddrphy_dfi_p2_address[12]),
-	.D7(main_k7ddrphy_dfi_p3_address[12]),
-	.D8(main_k7ddrphy_dfi_p3_address[12]),
+	.D1(k7ddrphy_dfi_p0_address[12]),
+	.D2(k7ddrphy_dfi_p0_address[12]),
+	.D3(k7ddrphy_dfi_p1_address[12]),
+	.D4(k7ddrphy_dfi_p1_address[12]),
+	.D5(k7ddrphy_dfi_p2_address[12]),
+	.D6(k7ddrphy_dfi_p2_address[12]),
+	.D7(k7ddrphy_dfi_p3_address[12]),
+	.D8(k7ddrphy_dfi_p3_address[12]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq14)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq14)
 );
 
 ODELAYE2 #(
@@ -16149,12 +16592,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_15 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[12]),
-	.ODATAIN(main_k7ddrphy_oq14)
+	.ODATAIN(k7ddrphy_oq14)
 );
 
 OSERDESE2 #(
@@ -16166,17 +16609,17 @@ OSERDESE2 #(
 ) OSERDESE2_16 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[13]),
-	.D2(main_k7ddrphy_dfi_p0_address[13]),
-	.D3(main_k7ddrphy_dfi_p1_address[13]),
-	.D4(main_k7ddrphy_dfi_p1_address[13]),
-	.D5(main_k7ddrphy_dfi_p2_address[13]),
-	.D6(main_k7ddrphy_dfi_p2_address[13]),
-	.D7(main_k7ddrphy_dfi_p3_address[13]),
-	.D8(main_k7ddrphy_dfi_p3_address[13]),
+	.D1(k7ddrphy_dfi_p0_address[13]),
+	.D2(k7ddrphy_dfi_p0_address[13]),
+	.D3(k7ddrphy_dfi_p1_address[13]),
+	.D4(k7ddrphy_dfi_p1_address[13]),
+	.D5(k7ddrphy_dfi_p2_address[13]),
+	.D6(k7ddrphy_dfi_p2_address[13]),
+	.D7(k7ddrphy_dfi_p3_address[13]),
+	.D8(k7ddrphy_dfi_p3_address[13]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq15)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq15)
 );
 
 ODELAYE2 #(
@@ -16190,12 +16633,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_16 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[13]),
-	.ODATAIN(main_k7ddrphy_oq15)
+	.ODATAIN(k7ddrphy_oq15)
 );
 
 OSERDESE2 #(
@@ -16207,17 +16650,17 @@ OSERDESE2 #(
 ) OSERDESE2_17 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_address[14]),
-	.D2(main_k7ddrphy_dfi_p0_address[14]),
-	.D3(main_k7ddrphy_dfi_p1_address[14]),
-	.D4(main_k7ddrphy_dfi_p1_address[14]),
-	.D5(main_k7ddrphy_dfi_p2_address[14]),
-	.D6(main_k7ddrphy_dfi_p2_address[14]),
-	.D7(main_k7ddrphy_dfi_p3_address[14]),
-	.D8(main_k7ddrphy_dfi_p3_address[14]),
+	.D1(k7ddrphy_dfi_p0_address[14]),
+	.D2(k7ddrphy_dfi_p0_address[14]),
+	.D3(k7ddrphy_dfi_p1_address[14]),
+	.D4(k7ddrphy_dfi_p1_address[14]),
+	.D5(k7ddrphy_dfi_p2_address[14]),
+	.D6(k7ddrphy_dfi_p2_address[14]),
+	.D7(k7ddrphy_dfi_p3_address[14]),
+	.D8(k7ddrphy_dfi_p3_address[14]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq16)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq16)
 );
 
 ODELAYE2 #(
@@ -16231,12 +16674,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_17 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[14]),
-	.ODATAIN(main_k7ddrphy_oq16)
+	.ODATAIN(k7ddrphy_oq16)
 );
 
 OSERDESE2 #(
@@ -16248,17 +16691,17 @@ OSERDESE2 #(
 ) OSERDESE2_18 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_bank[0]),
-	.D2(main_k7ddrphy_dfi_p0_bank[0]),
-	.D3(main_k7ddrphy_dfi_p1_bank[0]),
-	.D4(main_k7ddrphy_dfi_p1_bank[0]),
-	.D5(main_k7ddrphy_dfi_p2_bank[0]),
-	.D6(main_k7ddrphy_dfi_p2_bank[0]),
-	.D7(main_k7ddrphy_dfi_p3_bank[0]),
-	.D8(main_k7ddrphy_dfi_p3_bank[0]),
+	.D1(k7ddrphy_dfi_p0_bank[0]),
+	.D2(k7ddrphy_dfi_p0_bank[0]),
+	.D3(k7ddrphy_dfi_p1_bank[0]),
+	.D4(k7ddrphy_dfi_p1_bank[0]),
+	.D5(k7ddrphy_dfi_p2_bank[0]),
+	.D6(k7ddrphy_dfi_p2_bank[0]),
+	.D7(k7ddrphy_dfi_p3_bank[0]),
+	.D8(k7ddrphy_dfi_p3_bank[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq17)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq17)
 );
 
 ODELAYE2 #(
@@ -16272,12 +16715,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_18 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_ba[0]),
-	.ODATAIN(main_k7ddrphy_oq17)
+	.DATAOUT(k7ddrphy_pads_ba[0]),
+	.ODATAIN(k7ddrphy_oq17)
 );
 
 OSERDESE2 #(
@@ -16289,17 +16732,17 @@ OSERDESE2 #(
 ) OSERDESE2_19 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_bank[1]),
-	.D2(main_k7ddrphy_dfi_p0_bank[1]),
-	.D3(main_k7ddrphy_dfi_p1_bank[1]),
-	.D4(main_k7ddrphy_dfi_p1_bank[1]),
-	.D5(main_k7ddrphy_dfi_p2_bank[1]),
-	.D6(main_k7ddrphy_dfi_p2_bank[1]),
-	.D7(main_k7ddrphy_dfi_p3_bank[1]),
-	.D8(main_k7ddrphy_dfi_p3_bank[1]),
+	.D1(k7ddrphy_dfi_p0_bank[1]),
+	.D2(k7ddrphy_dfi_p0_bank[1]),
+	.D3(k7ddrphy_dfi_p1_bank[1]),
+	.D4(k7ddrphy_dfi_p1_bank[1]),
+	.D5(k7ddrphy_dfi_p2_bank[1]),
+	.D6(k7ddrphy_dfi_p2_bank[1]),
+	.D7(k7ddrphy_dfi_p3_bank[1]),
+	.D8(k7ddrphy_dfi_p3_bank[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq18)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq18)
 );
 
 ODELAYE2 #(
@@ -16313,12 +16756,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_19 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_ba[1]),
-	.ODATAIN(main_k7ddrphy_oq18)
+	.DATAOUT(k7ddrphy_pads_ba[1]),
+	.ODATAIN(k7ddrphy_oq18)
 );
 
 OSERDESE2 #(
@@ -16330,17 +16773,17 @@ OSERDESE2 #(
 ) OSERDESE2_20 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_bank[2]),
-	.D2(main_k7ddrphy_dfi_p0_bank[2]),
-	.D3(main_k7ddrphy_dfi_p1_bank[2]),
-	.D4(main_k7ddrphy_dfi_p1_bank[2]),
-	.D5(main_k7ddrphy_dfi_p2_bank[2]),
-	.D6(main_k7ddrphy_dfi_p2_bank[2]),
-	.D7(main_k7ddrphy_dfi_p3_bank[2]),
-	.D8(main_k7ddrphy_dfi_p3_bank[2]),
+	.D1(k7ddrphy_dfi_p0_bank[2]),
+	.D2(k7ddrphy_dfi_p0_bank[2]),
+	.D3(k7ddrphy_dfi_p1_bank[2]),
+	.D4(k7ddrphy_dfi_p1_bank[2]),
+	.D5(k7ddrphy_dfi_p2_bank[2]),
+	.D6(k7ddrphy_dfi_p2_bank[2]),
+	.D7(k7ddrphy_dfi_p3_bank[2]),
+	.D8(k7ddrphy_dfi_p3_bank[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq19)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq19)
 );
 
 ODELAYE2 #(
@@ -16354,12 +16797,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_20 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_ba[2]),
-	.ODATAIN(main_k7ddrphy_oq19)
+	.DATAOUT(k7ddrphy_pads_ba[2]),
+	.ODATAIN(k7ddrphy_oq19)
 );
 
 OSERDESE2 #(
@@ -16371,17 +16814,17 @@ OSERDESE2 #(
 ) OSERDESE2_21 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_ras_n),
-	.D2(main_k7ddrphy_dfi_p0_ras_n),
-	.D3(main_k7ddrphy_dfi_p1_ras_n),
-	.D4(main_k7ddrphy_dfi_p1_ras_n),
-	.D5(main_k7ddrphy_dfi_p2_ras_n),
-	.D6(main_k7ddrphy_dfi_p2_ras_n),
-	.D7(main_k7ddrphy_dfi_p3_ras_n),
-	.D8(main_k7ddrphy_dfi_p3_ras_n),
+	.D1(k7ddrphy_dfi_p0_ras_n),
+	.D2(k7ddrphy_dfi_p0_ras_n),
+	.D3(k7ddrphy_dfi_p1_ras_n),
+	.D4(k7ddrphy_dfi_p1_ras_n),
+	.D5(k7ddrphy_dfi_p2_ras_n),
+	.D6(k7ddrphy_dfi_p2_ras_n),
+	.D7(k7ddrphy_dfi_p3_ras_n),
+	.D8(k7ddrphy_dfi_p3_ras_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq20)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq20)
 );
 
 ODELAYE2 #(
@@ -16395,12 +16838,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_21 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_ras_n),
-	.ODATAIN(main_k7ddrphy_oq20)
+	.ODATAIN(k7ddrphy_oq20)
 );
 
 OSERDESE2 #(
@@ -16412,17 +16855,17 @@ OSERDESE2 #(
 ) OSERDESE2_22 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_cas_n),
-	.D2(main_k7ddrphy_dfi_p0_cas_n),
-	.D3(main_k7ddrphy_dfi_p1_cas_n),
-	.D4(main_k7ddrphy_dfi_p1_cas_n),
-	.D5(main_k7ddrphy_dfi_p2_cas_n),
-	.D6(main_k7ddrphy_dfi_p2_cas_n),
-	.D7(main_k7ddrphy_dfi_p3_cas_n),
-	.D8(main_k7ddrphy_dfi_p3_cas_n),
+	.D1(k7ddrphy_dfi_p0_cas_n),
+	.D2(k7ddrphy_dfi_p0_cas_n),
+	.D3(k7ddrphy_dfi_p1_cas_n),
+	.D4(k7ddrphy_dfi_p1_cas_n),
+	.D5(k7ddrphy_dfi_p2_cas_n),
+	.D6(k7ddrphy_dfi_p2_cas_n),
+	.D7(k7ddrphy_dfi_p3_cas_n),
+	.D8(k7ddrphy_dfi_p3_cas_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq21)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq21)
 );
 
 ODELAYE2 #(
@@ -16436,12 +16879,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_22 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_cas_n),
-	.ODATAIN(main_k7ddrphy_oq21)
+	.ODATAIN(k7ddrphy_oq21)
 );
 
 OSERDESE2 #(
@@ -16453,17 +16896,17 @@ OSERDESE2 #(
 ) OSERDESE2_23 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_we_n),
-	.D2(main_k7ddrphy_dfi_p0_we_n),
-	.D3(main_k7ddrphy_dfi_p1_we_n),
-	.D4(main_k7ddrphy_dfi_p1_we_n),
-	.D5(main_k7ddrphy_dfi_p2_we_n),
-	.D6(main_k7ddrphy_dfi_p2_we_n),
-	.D7(main_k7ddrphy_dfi_p3_we_n),
-	.D8(main_k7ddrphy_dfi_p3_we_n),
+	.D1(k7ddrphy_dfi_p0_we_n),
+	.D2(k7ddrphy_dfi_p0_we_n),
+	.D3(k7ddrphy_dfi_p1_we_n),
+	.D4(k7ddrphy_dfi_p1_we_n),
+	.D5(k7ddrphy_dfi_p2_we_n),
+	.D6(k7ddrphy_dfi_p2_we_n),
+	.D7(k7ddrphy_dfi_p3_we_n),
+	.D8(k7ddrphy_dfi_p3_we_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq22)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq22)
 );
 
 ODELAYE2 #(
@@ -16477,12 +16920,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_23 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_we_n),
-	.ODATAIN(main_k7ddrphy_oq22)
+	.ODATAIN(k7ddrphy_oq22)
 );
 
 OSERDESE2 #(
@@ -16494,17 +16937,17 @@ OSERDESE2 #(
 ) OSERDESE2_24 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_cke),
-	.D2(main_k7ddrphy_dfi_p0_cke),
-	.D3(main_k7ddrphy_dfi_p1_cke),
-	.D4(main_k7ddrphy_dfi_p1_cke),
-	.D5(main_k7ddrphy_dfi_p2_cke),
-	.D6(main_k7ddrphy_dfi_p2_cke),
-	.D7(main_k7ddrphy_dfi_p3_cke),
-	.D8(main_k7ddrphy_dfi_p3_cke),
+	.D1(k7ddrphy_dfi_p0_cke),
+	.D2(k7ddrphy_dfi_p0_cke),
+	.D3(k7ddrphy_dfi_p1_cke),
+	.D4(k7ddrphy_dfi_p1_cke),
+	.D5(k7ddrphy_dfi_p2_cke),
+	.D6(k7ddrphy_dfi_p2_cke),
+	.D7(k7ddrphy_dfi_p3_cke),
+	.D8(k7ddrphy_dfi_p3_cke),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq23)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq23)
 );
 
 ODELAYE2 #(
@@ -16518,12 +16961,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_24 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_cke),
-	.ODATAIN(main_k7ddrphy_oq23)
+	.ODATAIN(k7ddrphy_oq23)
 );
 
 OSERDESE2 #(
@@ -16535,17 +16978,17 @@ OSERDESE2 #(
 ) OSERDESE2_25 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_dfi_p0_odt),
-	.D2(main_k7ddrphy_dfi_p0_odt),
-	.D3(main_k7ddrphy_dfi_p1_odt),
-	.D4(main_k7ddrphy_dfi_p1_odt),
-	.D5(main_k7ddrphy_dfi_p2_odt),
-	.D6(main_k7ddrphy_dfi_p2_odt),
-	.D7(main_k7ddrphy_dfi_p3_odt),
-	.D8(main_k7ddrphy_dfi_p3_odt),
+	.D1(k7ddrphy_dfi_p0_odt),
+	.D2(k7ddrphy_dfi_p0_odt),
+	.D3(k7ddrphy_dfi_p1_odt),
+	.D4(k7ddrphy_dfi_p1_odt),
+	.D5(k7ddrphy_dfi_p2_odt),
+	.D6(k7ddrphy_dfi_p2_odt),
+	.D7(k7ddrphy_dfi_p3_odt),
+	.D8(k7ddrphy_dfi_p3_odt),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_oq24)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_oq24)
 );
 
 ODELAYE2 #(
@@ -16559,12 +17002,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_25 (
 	.C(sys_clk),
-	.CE(main_k7ddrphy_cdly_inc_re),
+	.CE(k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_odt),
-	.ODATAIN(main_k7ddrphy_oq24)
+	.ODATAIN(k7ddrphy_oq24)
 );
 
 OSERDESE2 #(
@@ -16576,21 +17019,21 @@ OSERDESE2 #(
 ) OSERDESE2_26 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip00[0]),
-	.D2(main_k7ddrphy_bitslip00[1]),
-	.D3(main_k7ddrphy_bitslip00[2]),
-	.D4(main_k7ddrphy_bitslip00[3]),
-	.D5(main_k7ddrphy_bitslip00[4]),
-	.D6(main_k7ddrphy_bitslip00[5]),
-	.D7(main_k7ddrphy_bitslip00[6]),
-	.D8(main_k7ddrphy_bitslip00[7]),
+	.D1(k7ddrphy_bitslip00[0]),
+	.D2(k7ddrphy_bitslip00[1]),
+	.D3(k7ddrphy_bitslip00[2]),
+	.D4(k7ddrphy_bitslip00[3]),
+	.D5(k7ddrphy_bitslip00[4]),
+	.D6(k7ddrphy_bitslip00[5]),
+	.D7(k7ddrphy_bitslip00[6]),
+	.D8(k7ddrphy_bitslip00[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_k7ddrphy_dqs_o_no_delay0),
-	.OQ(main_k7ddrphy0),
-	.TQ(main_k7ddrphy_dqs_t0)
+	.OFB(k7ddrphy_dqs_o_no_delay0),
+	.OQ(k7ddrphy0),
+	.TQ(k7ddrphy_dqs_t0)
 );
 
 ODELAYE2 #(
@@ -16604,17 +17047,17 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_26 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dqs_o_delayed0),
-	.ODATAIN(main_k7ddrphy_dqs_o_no_delay0)
+	.DATAOUT(k7ddrphy_dqs_o_delayed0),
+	.ODATAIN(k7ddrphy_dqs_o_no_delay0)
 );
 
 IOBUFDS IOBUFDS(
-	.I(main_k7ddrphy_dqs_o_delayed0),
-	.T(main_k7ddrphy_dqs_t0),
+	.I(k7ddrphy_dqs_o_delayed0),
+	.T(k7ddrphy_dqs_t0),
 	.IO(ddram_dqs_p[0]),
 	.IOB(ddram_dqs_n[0])
 );
@@ -16628,21 +17071,21 @@ OSERDESE2 #(
 ) OSERDESE2_27 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip10[0]),
-	.D2(main_k7ddrphy_bitslip10[1]),
-	.D3(main_k7ddrphy_bitslip10[2]),
-	.D4(main_k7ddrphy_bitslip10[3]),
-	.D5(main_k7ddrphy_bitslip10[4]),
-	.D6(main_k7ddrphy_bitslip10[5]),
-	.D7(main_k7ddrphy_bitslip10[6]),
-	.D8(main_k7ddrphy_bitslip10[7]),
+	.D1(k7ddrphy_bitslip10[0]),
+	.D2(k7ddrphy_bitslip10[1]),
+	.D3(k7ddrphy_bitslip10[2]),
+	.D4(k7ddrphy_bitslip10[3]),
+	.D5(k7ddrphy_bitslip10[4]),
+	.D6(k7ddrphy_bitslip10[5]),
+	.D7(k7ddrphy_bitslip10[6]),
+	.D8(k7ddrphy_bitslip10[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_k7ddrphy_dqs_o_no_delay1),
-	.OQ(main_k7ddrphy1),
-	.TQ(main_k7ddrphy_dqs_t1)
+	.OFB(k7ddrphy_dqs_o_no_delay1),
+	.OQ(k7ddrphy1),
+	.TQ(k7ddrphy_dqs_t1)
 );
 
 ODELAYE2 #(
@@ -16656,17 +17099,17 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_27 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dqs_o_delayed1),
-	.ODATAIN(main_k7ddrphy_dqs_o_no_delay1)
+	.DATAOUT(k7ddrphy_dqs_o_delayed1),
+	.ODATAIN(k7ddrphy_dqs_o_no_delay1)
 );
 
 IOBUFDS IOBUFDS_1(
-	.I(main_k7ddrphy_dqs_o_delayed1),
-	.T(main_k7ddrphy_dqs_t1),
+	.I(k7ddrphy_dqs_o_delayed1),
+	.T(k7ddrphy_dqs_t1),
 	.IO(ddram_dqs_p[1]),
 	.IOB(ddram_dqs_n[1])
 );
@@ -16680,21 +17123,21 @@ OSERDESE2 #(
 ) OSERDESE2_28 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip20[0]),
-	.D2(main_k7ddrphy_bitslip20[1]),
-	.D3(main_k7ddrphy_bitslip20[2]),
-	.D4(main_k7ddrphy_bitslip20[3]),
-	.D5(main_k7ddrphy_bitslip20[4]),
-	.D6(main_k7ddrphy_bitslip20[5]),
-	.D7(main_k7ddrphy_bitslip20[6]),
-	.D8(main_k7ddrphy_bitslip20[7]),
+	.D1(k7ddrphy_bitslip20[0]),
+	.D2(k7ddrphy_bitslip20[1]),
+	.D3(k7ddrphy_bitslip20[2]),
+	.D4(k7ddrphy_bitslip20[3]),
+	.D5(k7ddrphy_bitslip20[4]),
+	.D6(k7ddrphy_bitslip20[5]),
+	.D7(k7ddrphy_bitslip20[6]),
+	.D8(k7ddrphy_bitslip20[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_k7ddrphy_dqs_o_no_delay2),
-	.OQ(main_k7ddrphy2),
-	.TQ(main_k7ddrphy_dqs_t2)
+	.OFB(k7ddrphy_dqs_o_no_delay2),
+	.OQ(k7ddrphy2),
+	.TQ(k7ddrphy_dqs_t2)
 );
 
 ODELAYE2 #(
@@ -16708,17 +17151,17 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_28 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dqs_o_delayed2),
-	.ODATAIN(main_k7ddrphy_dqs_o_no_delay2)
+	.DATAOUT(k7ddrphy_dqs_o_delayed2),
+	.ODATAIN(k7ddrphy_dqs_o_no_delay2)
 );
 
 IOBUFDS IOBUFDS_2(
-	.I(main_k7ddrphy_dqs_o_delayed2),
-	.T(main_k7ddrphy_dqs_t2),
+	.I(k7ddrphy_dqs_o_delayed2),
+	.T(k7ddrphy_dqs_t2),
 	.IO(ddram_dqs_p[2]),
 	.IOB(ddram_dqs_n[2])
 );
@@ -16732,21 +17175,21 @@ OSERDESE2 #(
 ) OSERDESE2_29 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip30[0]),
-	.D2(main_k7ddrphy_bitslip30[1]),
-	.D3(main_k7ddrphy_bitslip30[2]),
-	.D4(main_k7ddrphy_bitslip30[3]),
-	.D5(main_k7ddrphy_bitslip30[4]),
-	.D6(main_k7ddrphy_bitslip30[5]),
-	.D7(main_k7ddrphy_bitslip30[6]),
-	.D8(main_k7ddrphy_bitslip30[7]),
+	.D1(k7ddrphy_bitslip30[0]),
+	.D2(k7ddrphy_bitslip30[1]),
+	.D3(k7ddrphy_bitslip30[2]),
+	.D4(k7ddrphy_bitslip30[3]),
+	.D5(k7ddrphy_bitslip30[4]),
+	.D6(k7ddrphy_bitslip30[5]),
+	.D7(k7ddrphy_bitslip30[6]),
+	.D8(k7ddrphy_bitslip30[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_k7ddrphy_dqs_o_no_delay3),
-	.OQ(main_k7ddrphy3),
-	.TQ(main_k7ddrphy_dqs_t3)
+	.OFB(k7ddrphy_dqs_o_no_delay3),
+	.OQ(k7ddrphy3),
+	.TQ(k7ddrphy_dqs_t3)
 );
 
 ODELAYE2 #(
@@ -16760,17 +17203,17 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_29 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dqs_o_delayed3),
-	.ODATAIN(main_k7ddrphy_dqs_o_no_delay3)
+	.DATAOUT(k7ddrphy_dqs_o_delayed3),
+	.ODATAIN(k7ddrphy_dqs_o_no_delay3)
 );
 
 IOBUFDS IOBUFDS_3(
-	.I(main_k7ddrphy_dqs_o_delayed3),
-	.T(main_k7ddrphy_dqs_t3),
+	.I(k7ddrphy_dqs_o_delayed3),
+	.T(k7ddrphy_dqs_t3),
 	.IO(ddram_dqs_p[3]),
 	.IOB(ddram_dqs_n[3])
 );
@@ -16784,17 +17227,17 @@ OSERDESE2 #(
 ) OSERDESE2_30 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip01[0]),
-	.D2(main_k7ddrphy_bitslip01[1]),
-	.D3(main_k7ddrphy_bitslip01[2]),
-	.D4(main_k7ddrphy_bitslip01[3]),
-	.D5(main_k7ddrphy_bitslip01[4]),
-	.D6(main_k7ddrphy_bitslip01[5]),
-	.D7(main_k7ddrphy_bitslip01[6]),
-	.D8(main_k7ddrphy_bitslip01[7]),
+	.D1(k7ddrphy_bitslip01[0]),
+	.D2(k7ddrphy_bitslip01[1]),
+	.D3(k7ddrphy_bitslip01[2]),
+	.D4(k7ddrphy_bitslip01[3]),
+	.D5(k7ddrphy_bitslip01[4]),
+	.D6(k7ddrphy_bitslip01[5]),
+	.D7(k7ddrphy_bitslip01[6]),
+	.D8(k7ddrphy_bitslip01[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_dm_o_nodelay0)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_dm_o_nodelay0)
 );
 
 ODELAYE2 #(
@@ -16808,12 +17251,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_30 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_dm[0]),
-	.ODATAIN(main_k7ddrphy_dm_o_nodelay0)
+	.ODATAIN(k7ddrphy_dm_o_nodelay0)
 );
 
 OSERDESE2 #(
@@ -16825,17 +17268,17 @@ OSERDESE2 #(
 ) OSERDESE2_31 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip11[0]),
-	.D2(main_k7ddrphy_bitslip11[1]),
-	.D3(main_k7ddrphy_bitslip11[2]),
-	.D4(main_k7ddrphy_bitslip11[3]),
-	.D5(main_k7ddrphy_bitslip11[4]),
-	.D6(main_k7ddrphy_bitslip11[5]),
-	.D7(main_k7ddrphy_bitslip11[6]),
-	.D8(main_k7ddrphy_bitslip11[7]),
+	.D1(k7ddrphy_bitslip11[0]),
+	.D2(k7ddrphy_bitslip11[1]),
+	.D3(k7ddrphy_bitslip11[2]),
+	.D4(k7ddrphy_bitslip11[3]),
+	.D5(k7ddrphy_bitslip11[4]),
+	.D6(k7ddrphy_bitslip11[5]),
+	.D7(k7ddrphy_bitslip11[6]),
+	.D8(k7ddrphy_bitslip11[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_dm_o_nodelay1)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_dm_o_nodelay1)
 );
 
 ODELAYE2 #(
@@ -16849,12 +17292,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_31 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_dm[1]),
-	.ODATAIN(main_k7ddrphy_dm_o_nodelay1)
+	.ODATAIN(k7ddrphy_dm_o_nodelay1)
 );
 
 OSERDESE2 #(
@@ -16866,17 +17309,17 @@ OSERDESE2 #(
 ) OSERDESE2_32 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip21[0]),
-	.D2(main_k7ddrphy_bitslip21[1]),
-	.D3(main_k7ddrphy_bitslip21[2]),
-	.D4(main_k7ddrphy_bitslip21[3]),
-	.D5(main_k7ddrphy_bitslip21[4]),
-	.D6(main_k7ddrphy_bitslip21[5]),
-	.D7(main_k7ddrphy_bitslip21[6]),
-	.D8(main_k7ddrphy_bitslip21[7]),
+	.D1(k7ddrphy_bitslip21[0]),
+	.D2(k7ddrphy_bitslip21[1]),
+	.D3(k7ddrphy_bitslip21[2]),
+	.D4(k7ddrphy_bitslip21[3]),
+	.D5(k7ddrphy_bitslip21[4]),
+	.D6(k7ddrphy_bitslip21[5]),
+	.D7(k7ddrphy_bitslip21[6]),
+	.D8(k7ddrphy_bitslip21[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_dm_o_nodelay2)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_dm_o_nodelay2)
 );
 
 ODELAYE2 #(
@@ -16890,12 +17333,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_32 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_dm[2]),
-	.ODATAIN(main_k7ddrphy_dm_o_nodelay2)
+	.ODATAIN(k7ddrphy_dm_o_nodelay2)
 );
 
 OSERDESE2 #(
@@ -16907,17 +17350,17 @@ OSERDESE2 #(
 ) OSERDESE2_33 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip31[0]),
-	.D2(main_k7ddrphy_bitslip31[1]),
-	.D3(main_k7ddrphy_bitslip31[2]),
-	.D4(main_k7ddrphy_bitslip31[3]),
-	.D5(main_k7ddrphy_bitslip31[4]),
-	.D6(main_k7ddrphy_bitslip31[5]),
-	.D7(main_k7ddrphy_bitslip31[6]),
-	.D8(main_k7ddrphy_bitslip31[7]),
+	.D1(k7ddrphy_bitslip31[0]),
+	.D2(k7ddrphy_bitslip31[1]),
+	.D3(k7ddrphy_bitslip31[2]),
+	.D4(k7ddrphy_bitslip31[3]),
+	.D5(k7ddrphy_bitslip31[4]),
+	.D6(k7ddrphy_bitslip31[5]),
+	.D7(k7ddrphy_bitslip31[6]),
+	.D8(k7ddrphy_bitslip31[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.OQ(main_k7ddrphy_dm_o_nodelay3)
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.OQ(k7ddrphy_dm_o_nodelay3)
 );
 
 ODELAYE2 #(
@@ -16931,12 +17374,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_33 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_dm[3]),
-	.ODATAIN(main_k7ddrphy_dm_o_nodelay3)
+	.ODATAIN(k7ddrphy_dm_o_nodelay3)
 );
 
 OSERDESE2 #(
@@ -16948,20 +17391,20 @@ OSERDESE2 #(
 ) OSERDESE2_34 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip02[0]),
-	.D2(main_k7ddrphy_bitslip02[1]),
-	.D3(main_k7ddrphy_bitslip02[2]),
-	.D4(main_k7ddrphy_bitslip02[3]),
-	.D5(main_k7ddrphy_bitslip02[4]),
-	.D6(main_k7ddrphy_bitslip02[5]),
-	.D7(main_k7ddrphy_bitslip02[6]),
-	.D8(main_k7ddrphy_bitslip02[7]),
+	.D1(k7ddrphy_bitslip02[0]),
+	.D2(k7ddrphy_bitslip02[1]),
+	.D3(k7ddrphy_bitslip02[2]),
+	.D4(k7ddrphy_bitslip02[3]),
+	.D5(k7ddrphy_bitslip02[4]),
+	.D6(k7ddrphy_bitslip02[5]),
+	.D7(k7ddrphy_bitslip02[6]),
+	.D8(k7ddrphy_bitslip02[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay0),
-	.TQ(main_k7ddrphy_dq_t0)
+	.OQ(k7ddrphy_dq_o_nodelay0),
+	.TQ(k7ddrphy_dq_t0)
 );
 
 ISERDESE2 #(
@@ -16977,16 +17420,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip03[7]),
-	.Q2(main_k7ddrphy_bitslip03[6]),
-	.Q3(main_k7ddrphy_bitslip03[5]),
-	.Q4(main_k7ddrphy_bitslip03[4]),
-	.Q5(main_k7ddrphy_bitslip03[3]),
-	.Q6(main_k7ddrphy_bitslip03[2]),
-	.Q7(main_k7ddrphy_bitslip03[1]),
-	.Q8(main_k7ddrphy_bitslip03[0])
+	.DDLY(k7ddrphy_dq_i_delayed0),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip03[7]),
+	.Q2(k7ddrphy_bitslip03[6]),
+	.Q3(k7ddrphy_bitslip03[5]),
+	.Q4(k7ddrphy_bitslip03[4]),
+	.Q5(k7ddrphy_bitslip03[3]),
+	.Q6(k7ddrphy_bitslip03[2]),
+	.Q7(k7ddrphy_bitslip03[1]),
+	.Q8(k7ddrphy_bitslip03[0])
 );
 
 ODELAYE2 #(
@@ -17000,12 +17443,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_34 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed0),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay0)
+	.DATAOUT(k7ddrphy_dq_o_delayed0),
+	.ODATAIN(k7ddrphy_dq_o_nodelay0)
 );
 
 IDELAYE2 #(
@@ -17019,19 +17462,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay0),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay0),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed0)
+	.DATAOUT(k7ddrphy_dq_i_delayed0)
 );
 
 IOBUF IOBUF(
-	.I(main_k7ddrphy_dq_o_delayed0),
-	.T(main_k7ddrphy_dq_t0),
+	.I(k7ddrphy_dq_o_delayed0),
+	.T(k7ddrphy_dq_t0),
 	.IO(ddram_dq[0]),
-	.O(main_k7ddrphy_dq_i_nodelay0)
+	.O(k7ddrphy_dq_i_nodelay0)
 );
 
 OSERDESE2 #(
@@ -17043,20 +17486,20 @@ OSERDESE2 #(
 ) OSERDESE2_35 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip12[0]),
-	.D2(main_k7ddrphy_bitslip12[1]),
-	.D3(main_k7ddrphy_bitslip12[2]),
-	.D4(main_k7ddrphy_bitslip12[3]),
-	.D5(main_k7ddrphy_bitslip12[4]),
-	.D6(main_k7ddrphy_bitslip12[5]),
-	.D7(main_k7ddrphy_bitslip12[6]),
-	.D8(main_k7ddrphy_bitslip12[7]),
+	.D1(k7ddrphy_bitslip12[0]),
+	.D2(k7ddrphy_bitslip12[1]),
+	.D3(k7ddrphy_bitslip12[2]),
+	.D4(k7ddrphy_bitslip12[3]),
+	.D5(k7ddrphy_bitslip12[4]),
+	.D6(k7ddrphy_bitslip12[5]),
+	.D7(k7ddrphy_bitslip12[6]),
+	.D8(k7ddrphy_bitslip12[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay1),
-	.TQ(main_k7ddrphy_dq_t1)
+	.OQ(k7ddrphy_dq_o_nodelay1),
+	.TQ(k7ddrphy_dq_t1)
 );
 
 ISERDESE2 #(
@@ -17072,16 +17515,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip13[7]),
-	.Q2(main_k7ddrphy_bitslip13[6]),
-	.Q3(main_k7ddrphy_bitslip13[5]),
-	.Q4(main_k7ddrphy_bitslip13[4]),
-	.Q5(main_k7ddrphy_bitslip13[3]),
-	.Q6(main_k7ddrphy_bitslip13[2]),
-	.Q7(main_k7ddrphy_bitslip13[1]),
-	.Q8(main_k7ddrphy_bitslip13[0])
+	.DDLY(k7ddrphy_dq_i_delayed1),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip13[7]),
+	.Q2(k7ddrphy_bitslip13[6]),
+	.Q3(k7ddrphy_bitslip13[5]),
+	.Q4(k7ddrphy_bitslip13[4]),
+	.Q5(k7ddrphy_bitslip13[3]),
+	.Q6(k7ddrphy_bitslip13[2]),
+	.Q7(k7ddrphy_bitslip13[1]),
+	.Q8(k7ddrphy_bitslip13[0])
 );
 
 ODELAYE2 #(
@@ -17095,12 +17538,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_35 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed1),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay1)
+	.DATAOUT(k7ddrphy_dq_o_delayed1),
+	.ODATAIN(k7ddrphy_dq_o_nodelay1)
 );
 
 IDELAYE2 #(
@@ -17114,19 +17557,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_1 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay1),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay1),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed1)
+	.DATAOUT(k7ddrphy_dq_i_delayed1)
 );
 
 IOBUF IOBUF_1(
-	.I(main_k7ddrphy_dq_o_delayed1),
-	.T(main_k7ddrphy_dq_t1),
+	.I(k7ddrphy_dq_o_delayed1),
+	.T(k7ddrphy_dq_t1),
 	.IO(ddram_dq[1]),
-	.O(main_k7ddrphy_dq_i_nodelay1)
+	.O(k7ddrphy_dq_i_nodelay1)
 );
 
 OSERDESE2 #(
@@ -17138,20 +17581,20 @@ OSERDESE2 #(
 ) OSERDESE2_36 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip22[0]),
-	.D2(main_k7ddrphy_bitslip22[1]),
-	.D3(main_k7ddrphy_bitslip22[2]),
-	.D4(main_k7ddrphy_bitslip22[3]),
-	.D5(main_k7ddrphy_bitslip22[4]),
-	.D6(main_k7ddrphy_bitslip22[5]),
-	.D7(main_k7ddrphy_bitslip22[6]),
-	.D8(main_k7ddrphy_bitslip22[7]),
+	.D1(k7ddrphy_bitslip22[0]),
+	.D2(k7ddrphy_bitslip22[1]),
+	.D3(k7ddrphy_bitslip22[2]),
+	.D4(k7ddrphy_bitslip22[3]),
+	.D5(k7ddrphy_bitslip22[4]),
+	.D6(k7ddrphy_bitslip22[5]),
+	.D7(k7ddrphy_bitslip22[6]),
+	.D8(k7ddrphy_bitslip22[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay2),
-	.TQ(main_k7ddrphy_dq_t2)
+	.OQ(k7ddrphy_dq_o_nodelay2),
+	.TQ(k7ddrphy_dq_t2)
 );
 
 ISERDESE2 #(
@@ -17167,16 +17610,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip23[7]),
-	.Q2(main_k7ddrphy_bitslip23[6]),
-	.Q3(main_k7ddrphy_bitslip23[5]),
-	.Q4(main_k7ddrphy_bitslip23[4]),
-	.Q5(main_k7ddrphy_bitslip23[3]),
-	.Q6(main_k7ddrphy_bitslip23[2]),
-	.Q7(main_k7ddrphy_bitslip23[1]),
-	.Q8(main_k7ddrphy_bitslip23[0])
+	.DDLY(k7ddrphy_dq_i_delayed2),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip23[7]),
+	.Q2(k7ddrphy_bitslip23[6]),
+	.Q3(k7ddrphy_bitslip23[5]),
+	.Q4(k7ddrphy_bitslip23[4]),
+	.Q5(k7ddrphy_bitslip23[3]),
+	.Q6(k7ddrphy_bitslip23[2]),
+	.Q7(k7ddrphy_bitslip23[1]),
+	.Q8(k7ddrphy_bitslip23[0])
 );
 
 ODELAYE2 #(
@@ -17190,12 +17633,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_36 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed2),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay2)
+	.DATAOUT(k7ddrphy_dq_o_delayed2),
+	.ODATAIN(k7ddrphy_dq_o_nodelay2)
 );
 
 IDELAYE2 #(
@@ -17209,19 +17652,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_2 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay2),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay2),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed2)
+	.DATAOUT(k7ddrphy_dq_i_delayed2)
 );
 
 IOBUF IOBUF_2(
-	.I(main_k7ddrphy_dq_o_delayed2),
-	.T(main_k7ddrphy_dq_t2),
+	.I(k7ddrphy_dq_o_delayed2),
+	.T(k7ddrphy_dq_t2),
 	.IO(ddram_dq[2]),
-	.O(main_k7ddrphy_dq_i_nodelay2)
+	.O(k7ddrphy_dq_i_nodelay2)
 );
 
 OSERDESE2 #(
@@ -17233,20 +17676,20 @@ OSERDESE2 #(
 ) OSERDESE2_37 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip32[0]),
-	.D2(main_k7ddrphy_bitslip32[1]),
-	.D3(main_k7ddrphy_bitslip32[2]),
-	.D4(main_k7ddrphy_bitslip32[3]),
-	.D5(main_k7ddrphy_bitslip32[4]),
-	.D6(main_k7ddrphy_bitslip32[5]),
-	.D7(main_k7ddrphy_bitslip32[6]),
-	.D8(main_k7ddrphy_bitslip32[7]),
+	.D1(k7ddrphy_bitslip32[0]),
+	.D2(k7ddrphy_bitslip32[1]),
+	.D3(k7ddrphy_bitslip32[2]),
+	.D4(k7ddrphy_bitslip32[3]),
+	.D5(k7ddrphy_bitslip32[4]),
+	.D6(k7ddrphy_bitslip32[5]),
+	.D7(k7ddrphy_bitslip32[6]),
+	.D8(k7ddrphy_bitslip32[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay3),
-	.TQ(main_k7ddrphy_dq_t3)
+	.OQ(k7ddrphy_dq_o_nodelay3),
+	.TQ(k7ddrphy_dq_t3)
 );
 
 ISERDESE2 #(
@@ -17262,16 +17705,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip33[7]),
-	.Q2(main_k7ddrphy_bitslip33[6]),
-	.Q3(main_k7ddrphy_bitslip33[5]),
-	.Q4(main_k7ddrphy_bitslip33[4]),
-	.Q5(main_k7ddrphy_bitslip33[3]),
-	.Q6(main_k7ddrphy_bitslip33[2]),
-	.Q7(main_k7ddrphy_bitslip33[1]),
-	.Q8(main_k7ddrphy_bitslip33[0])
+	.DDLY(k7ddrphy_dq_i_delayed3),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip33[7]),
+	.Q2(k7ddrphy_bitslip33[6]),
+	.Q3(k7ddrphy_bitslip33[5]),
+	.Q4(k7ddrphy_bitslip33[4]),
+	.Q5(k7ddrphy_bitslip33[3]),
+	.Q6(k7ddrphy_bitslip33[2]),
+	.Q7(k7ddrphy_bitslip33[1]),
+	.Q8(k7ddrphy_bitslip33[0])
 );
 
 ODELAYE2 #(
@@ -17285,12 +17728,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_37 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed3),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay3)
+	.DATAOUT(k7ddrphy_dq_o_delayed3),
+	.ODATAIN(k7ddrphy_dq_o_nodelay3)
 );
 
 IDELAYE2 #(
@@ -17304,19 +17747,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_3 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay3),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay3),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed3)
+	.DATAOUT(k7ddrphy_dq_i_delayed3)
 );
 
 IOBUF IOBUF_3(
-	.I(main_k7ddrphy_dq_o_delayed3),
-	.T(main_k7ddrphy_dq_t3),
+	.I(k7ddrphy_dq_o_delayed3),
+	.T(k7ddrphy_dq_t3),
 	.IO(ddram_dq[3]),
-	.O(main_k7ddrphy_dq_i_nodelay3)
+	.O(k7ddrphy_dq_i_nodelay3)
 );
 
 OSERDESE2 #(
@@ -17328,20 +17771,20 @@ OSERDESE2 #(
 ) OSERDESE2_38 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip40[0]),
-	.D2(main_k7ddrphy_bitslip40[1]),
-	.D3(main_k7ddrphy_bitslip40[2]),
-	.D4(main_k7ddrphy_bitslip40[3]),
-	.D5(main_k7ddrphy_bitslip40[4]),
-	.D6(main_k7ddrphy_bitslip40[5]),
-	.D7(main_k7ddrphy_bitslip40[6]),
-	.D8(main_k7ddrphy_bitslip40[7]),
+	.D1(k7ddrphy_bitslip40[0]),
+	.D2(k7ddrphy_bitslip40[1]),
+	.D3(k7ddrphy_bitslip40[2]),
+	.D4(k7ddrphy_bitslip40[3]),
+	.D5(k7ddrphy_bitslip40[4]),
+	.D6(k7ddrphy_bitslip40[5]),
+	.D7(k7ddrphy_bitslip40[6]),
+	.D8(k7ddrphy_bitslip40[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay4),
-	.TQ(main_k7ddrphy_dq_t4)
+	.OQ(k7ddrphy_dq_o_nodelay4),
+	.TQ(k7ddrphy_dq_t4)
 );
 
 ISERDESE2 #(
@@ -17357,16 +17800,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip41[7]),
-	.Q2(main_k7ddrphy_bitslip41[6]),
-	.Q3(main_k7ddrphy_bitslip41[5]),
-	.Q4(main_k7ddrphy_bitslip41[4]),
-	.Q5(main_k7ddrphy_bitslip41[3]),
-	.Q6(main_k7ddrphy_bitslip41[2]),
-	.Q7(main_k7ddrphy_bitslip41[1]),
-	.Q8(main_k7ddrphy_bitslip41[0])
+	.DDLY(k7ddrphy_dq_i_delayed4),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip41[7]),
+	.Q2(k7ddrphy_bitslip41[6]),
+	.Q3(k7ddrphy_bitslip41[5]),
+	.Q4(k7ddrphy_bitslip41[4]),
+	.Q5(k7ddrphy_bitslip41[3]),
+	.Q6(k7ddrphy_bitslip41[2]),
+	.Q7(k7ddrphy_bitslip41[1]),
+	.Q8(k7ddrphy_bitslip41[0])
 );
 
 ODELAYE2 #(
@@ -17380,12 +17823,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_38 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed4),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay4)
+	.DATAOUT(k7ddrphy_dq_o_delayed4),
+	.ODATAIN(k7ddrphy_dq_o_nodelay4)
 );
 
 IDELAYE2 #(
@@ -17399,19 +17842,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_4 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay4),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay4),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed4)
+	.DATAOUT(k7ddrphy_dq_i_delayed4)
 );
 
 IOBUF IOBUF_4(
-	.I(main_k7ddrphy_dq_o_delayed4),
-	.T(main_k7ddrphy_dq_t4),
+	.I(k7ddrphy_dq_o_delayed4),
+	.T(k7ddrphy_dq_t4),
 	.IO(ddram_dq[4]),
-	.O(main_k7ddrphy_dq_i_nodelay4)
+	.O(k7ddrphy_dq_i_nodelay4)
 );
 
 OSERDESE2 #(
@@ -17423,20 +17866,20 @@ OSERDESE2 #(
 ) OSERDESE2_39 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip50[0]),
-	.D2(main_k7ddrphy_bitslip50[1]),
-	.D3(main_k7ddrphy_bitslip50[2]),
-	.D4(main_k7ddrphy_bitslip50[3]),
-	.D5(main_k7ddrphy_bitslip50[4]),
-	.D6(main_k7ddrphy_bitslip50[5]),
-	.D7(main_k7ddrphy_bitslip50[6]),
-	.D8(main_k7ddrphy_bitslip50[7]),
+	.D1(k7ddrphy_bitslip50[0]),
+	.D2(k7ddrphy_bitslip50[1]),
+	.D3(k7ddrphy_bitslip50[2]),
+	.D4(k7ddrphy_bitslip50[3]),
+	.D5(k7ddrphy_bitslip50[4]),
+	.D6(k7ddrphy_bitslip50[5]),
+	.D7(k7ddrphy_bitslip50[6]),
+	.D8(k7ddrphy_bitslip50[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay5),
-	.TQ(main_k7ddrphy_dq_t5)
+	.OQ(k7ddrphy_dq_o_nodelay5),
+	.TQ(k7ddrphy_dq_t5)
 );
 
 ISERDESE2 #(
@@ -17452,16 +17895,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip51[7]),
-	.Q2(main_k7ddrphy_bitslip51[6]),
-	.Q3(main_k7ddrphy_bitslip51[5]),
-	.Q4(main_k7ddrphy_bitslip51[4]),
-	.Q5(main_k7ddrphy_bitslip51[3]),
-	.Q6(main_k7ddrphy_bitslip51[2]),
-	.Q7(main_k7ddrphy_bitslip51[1]),
-	.Q8(main_k7ddrphy_bitslip51[0])
+	.DDLY(k7ddrphy_dq_i_delayed5),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip51[7]),
+	.Q2(k7ddrphy_bitslip51[6]),
+	.Q3(k7ddrphy_bitslip51[5]),
+	.Q4(k7ddrphy_bitslip51[4]),
+	.Q5(k7ddrphy_bitslip51[3]),
+	.Q6(k7ddrphy_bitslip51[2]),
+	.Q7(k7ddrphy_bitslip51[1]),
+	.Q8(k7ddrphy_bitslip51[0])
 );
 
 ODELAYE2 #(
@@ -17475,12 +17918,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_39 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed5),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay5)
+	.DATAOUT(k7ddrphy_dq_o_delayed5),
+	.ODATAIN(k7ddrphy_dq_o_nodelay5)
 );
 
 IDELAYE2 #(
@@ -17494,19 +17937,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_5 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay5),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay5),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed5)
+	.DATAOUT(k7ddrphy_dq_i_delayed5)
 );
 
 IOBUF IOBUF_5(
-	.I(main_k7ddrphy_dq_o_delayed5),
-	.T(main_k7ddrphy_dq_t5),
+	.I(k7ddrphy_dq_o_delayed5),
+	.T(k7ddrphy_dq_t5),
 	.IO(ddram_dq[5]),
-	.O(main_k7ddrphy_dq_i_nodelay5)
+	.O(k7ddrphy_dq_i_nodelay5)
 );
 
 OSERDESE2 #(
@@ -17518,20 +17961,20 @@ OSERDESE2 #(
 ) OSERDESE2_40 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip60[0]),
-	.D2(main_k7ddrphy_bitslip60[1]),
-	.D3(main_k7ddrphy_bitslip60[2]),
-	.D4(main_k7ddrphy_bitslip60[3]),
-	.D5(main_k7ddrphy_bitslip60[4]),
-	.D6(main_k7ddrphy_bitslip60[5]),
-	.D7(main_k7ddrphy_bitslip60[6]),
-	.D8(main_k7ddrphy_bitslip60[7]),
+	.D1(k7ddrphy_bitslip60[0]),
+	.D2(k7ddrphy_bitslip60[1]),
+	.D3(k7ddrphy_bitslip60[2]),
+	.D4(k7ddrphy_bitslip60[3]),
+	.D5(k7ddrphy_bitslip60[4]),
+	.D6(k7ddrphy_bitslip60[5]),
+	.D7(k7ddrphy_bitslip60[6]),
+	.D8(k7ddrphy_bitslip60[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay6),
-	.TQ(main_k7ddrphy_dq_t6)
+	.OQ(k7ddrphy_dq_o_nodelay6),
+	.TQ(k7ddrphy_dq_t6)
 );
 
 ISERDESE2 #(
@@ -17547,16 +17990,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip61[7]),
-	.Q2(main_k7ddrphy_bitslip61[6]),
-	.Q3(main_k7ddrphy_bitslip61[5]),
-	.Q4(main_k7ddrphy_bitslip61[4]),
-	.Q5(main_k7ddrphy_bitslip61[3]),
-	.Q6(main_k7ddrphy_bitslip61[2]),
-	.Q7(main_k7ddrphy_bitslip61[1]),
-	.Q8(main_k7ddrphy_bitslip61[0])
+	.DDLY(k7ddrphy_dq_i_delayed6),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip61[7]),
+	.Q2(k7ddrphy_bitslip61[6]),
+	.Q3(k7ddrphy_bitslip61[5]),
+	.Q4(k7ddrphy_bitslip61[4]),
+	.Q5(k7ddrphy_bitslip61[3]),
+	.Q6(k7ddrphy_bitslip61[2]),
+	.Q7(k7ddrphy_bitslip61[1]),
+	.Q8(k7ddrphy_bitslip61[0])
 );
 
 ODELAYE2 #(
@@ -17570,12 +18013,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_40 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed6),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay6)
+	.DATAOUT(k7ddrphy_dq_o_delayed6),
+	.ODATAIN(k7ddrphy_dq_o_nodelay6)
 );
 
 IDELAYE2 #(
@@ -17589,19 +18032,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_6 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay6),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay6),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed6)
+	.DATAOUT(k7ddrphy_dq_i_delayed6)
 );
 
 IOBUF IOBUF_6(
-	.I(main_k7ddrphy_dq_o_delayed6),
-	.T(main_k7ddrphy_dq_t6),
+	.I(k7ddrphy_dq_o_delayed6),
+	.T(k7ddrphy_dq_t6),
 	.IO(ddram_dq[6]),
-	.O(main_k7ddrphy_dq_i_nodelay6)
+	.O(k7ddrphy_dq_i_nodelay6)
 );
 
 OSERDESE2 #(
@@ -17613,20 +18056,20 @@ OSERDESE2 #(
 ) OSERDESE2_41 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip70[0]),
-	.D2(main_k7ddrphy_bitslip70[1]),
-	.D3(main_k7ddrphy_bitslip70[2]),
-	.D4(main_k7ddrphy_bitslip70[3]),
-	.D5(main_k7ddrphy_bitslip70[4]),
-	.D6(main_k7ddrphy_bitslip70[5]),
-	.D7(main_k7ddrphy_bitslip70[6]),
-	.D8(main_k7ddrphy_bitslip70[7]),
+	.D1(k7ddrphy_bitslip70[0]),
+	.D2(k7ddrphy_bitslip70[1]),
+	.D3(k7ddrphy_bitslip70[2]),
+	.D4(k7ddrphy_bitslip70[3]),
+	.D5(k7ddrphy_bitslip70[4]),
+	.D6(k7ddrphy_bitslip70[5]),
+	.D7(k7ddrphy_bitslip70[6]),
+	.D8(k7ddrphy_bitslip70[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay7),
-	.TQ(main_k7ddrphy_dq_t7)
+	.OQ(k7ddrphy_dq_o_nodelay7),
+	.TQ(k7ddrphy_dq_t7)
 );
 
 ISERDESE2 #(
@@ -17642,16 +18085,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip71[7]),
-	.Q2(main_k7ddrphy_bitslip71[6]),
-	.Q3(main_k7ddrphy_bitslip71[5]),
-	.Q4(main_k7ddrphy_bitslip71[4]),
-	.Q5(main_k7ddrphy_bitslip71[3]),
-	.Q6(main_k7ddrphy_bitslip71[2]),
-	.Q7(main_k7ddrphy_bitslip71[1]),
-	.Q8(main_k7ddrphy_bitslip71[0])
+	.DDLY(k7ddrphy_dq_i_delayed7),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip71[7]),
+	.Q2(k7ddrphy_bitslip71[6]),
+	.Q3(k7ddrphy_bitslip71[5]),
+	.Q4(k7ddrphy_bitslip71[4]),
+	.Q5(k7ddrphy_bitslip71[3]),
+	.Q6(k7ddrphy_bitslip71[2]),
+	.Q7(k7ddrphy_bitslip71[1]),
+	.Q8(k7ddrphy_bitslip71[0])
 );
 
 ODELAYE2 #(
@@ -17665,12 +18108,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_41 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed7),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay7)
+	.DATAOUT(k7ddrphy_dq_o_delayed7),
+	.ODATAIN(k7ddrphy_dq_o_nodelay7)
 );
 
 IDELAYE2 #(
@@ -17684,19 +18127,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_7 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay7),
+	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay7),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed7)
+	.DATAOUT(k7ddrphy_dq_i_delayed7)
 );
 
 IOBUF IOBUF_7(
-	.I(main_k7ddrphy_dq_o_delayed7),
-	.T(main_k7ddrphy_dq_t7),
+	.I(k7ddrphy_dq_o_delayed7),
+	.T(k7ddrphy_dq_t7),
 	.IO(ddram_dq[7]),
-	.O(main_k7ddrphy_dq_i_nodelay7)
+	.O(k7ddrphy_dq_i_nodelay7)
 );
 
 OSERDESE2 #(
@@ -17708,20 +18151,20 @@ OSERDESE2 #(
 ) OSERDESE2_42 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip80[0]),
-	.D2(main_k7ddrphy_bitslip80[1]),
-	.D3(main_k7ddrphy_bitslip80[2]),
-	.D4(main_k7ddrphy_bitslip80[3]),
-	.D5(main_k7ddrphy_bitslip80[4]),
-	.D6(main_k7ddrphy_bitslip80[5]),
-	.D7(main_k7ddrphy_bitslip80[6]),
-	.D8(main_k7ddrphy_bitslip80[7]),
+	.D1(k7ddrphy_bitslip80[0]),
+	.D2(k7ddrphy_bitslip80[1]),
+	.D3(k7ddrphy_bitslip80[2]),
+	.D4(k7ddrphy_bitslip80[3]),
+	.D5(k7ddrphy_bitslip80[4]),
+	.D6(k7ddrphy_bitslip80[5]),
+	.D7(k7ddrphy_bitslip80[6]),
+	.D8(k7ddrphy_bitslip80[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay8),
-	.TQ(main_k7ddrphy_dq_t8)
+	.OQ(k7ddrphy_dq_o_nodelay8),
+	.TQ(k7ddrphy_dq_t8)
 );
 
 ISERDESE2 #(
@@ -17737,16 +18180,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip81[7]),
-	.Q2(main_k7ddrphy_bitslip81[6]),
-	.Q3(main_k7ddrphy_bitslip81[5]),
-	.Q4(main_k7ddrphy_bitslip81[4]),
-	.Q5(main_k7ddrphy_bitslip81[3]),
-	.Q6(main_k7ddrphy_bitslip81[2]),
-	.Q7(main_k7ddrphy_bitslip81[1]),
-	.Q8(main_k7ddrphy_bitslip81[0])
+	.DDLY(k7ddrphy_dq_i_delayed8),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip81[7]),
+	.Q2(k7ddrphy_bitslip81[6]),
+	.Q3(k7ddrphy_bitslip81[5]),
+	.Q4(k7ddrphy_bitslip81[4]),
+	.Q5(k7ddrphy_bitslip81[3]),
+	.Q6(k7ddrphy_bitslip81[2]),
+	.Q7(k7ddrphy_bitslip81[1]),
+	.Q8(k7ddrphy_bitslip81[0])
 );
 
 ODELAYE2 #(
@@ -17760,12 +18203,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_42 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed8),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay8)
+	.DATAOUT(k7ddrphy_dq_o_delayed8),
+	.ODATAIN(k7ddrphy_dq_o_nodelay8)
 );
 
 IDELAYE2 #(
@@ -17779,19 +18222,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_8 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay8),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay8),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed8)
+	.DATAOUT(k7ddrphy_dq_i_delayed8)
 );
 
 IOBUF IOBUF_8(
-	.I(main_k7ddrphy_dq_o_delayed8),
-	.T(main_k7ddrphy_dq_t8),
+	.I(k7ddrphy_dq_o_delayed8),
+	.T(k7ddrphy_dq_t8),
 	.IO(ddram_dq[8]),
-	.O(main_k7ddrphy_dq_i_nodelay8)
+	.O(k7ddrphy_dq_i_nodelay8)
 );
 
 OSERDESE2 #(
@@ -17803,20 +18246,20 @@ OSERDESE2 #(
 ) OSERDESE2_43 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip90[0]),
-	.D2(main_k7ddrphy_bitslip90[1]),
-	.D3(main_k7ddrphy_bitslip90[2]),
-	.D4(main_k7ddrphy_bitslip90[3]),
-	.D5(main_k7ddrphy_bitslip90[4]),
-	.D6(main_k7ddrphy_bitslip90[5]),
-	.D7(main_k7ddrphy_bitslip90[6]),
-	.D8(main_k7ddrphy_bitslip90[7]),
+	.D1(k7ddrphy_bitslip90[0]),
+	.D2(k7ddrphy_bitslip90[1]),
+	.D3(k7ddrphy_bitslip90[2]),
+	.D4(k7ddrphy_bitslip90[3]),
+	.D5(k7ddrphy_bitslip90[4]),
+	.D6(k7ddrphy_bitslip90[5]),
+	.D7(k7ddrphy_bitslip90[6]),
+	.D8(k7ddrphy_bitslip90[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay9),
-	.TQ(main_k7ddrphy_dq_t9)
+	.OQ(k7ddrphy_dq_o_nodelay9),
+	.TQ(k7ddrphy_dq_t9)
 );
 
 ISERDESE2 #(
@@ -17832,16 +18275,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip91[7]),
-	.Q2(main_k7ddrphy_bitslip91[6]),
-	.Q3(main_k7ddrphy_bitslip91[5]),
-	.Q4(main_k7ddrphy_bitslip91[4]),
-	.Q5(main_k7ddrphy_bitslip91[3]),
-	.Q6(main_k7ddrphy_bitslip91[2]),
-	.Q7(main_k7ddrphy_bitslip91[1]),
-	.Q8(main_k7ddrphy_bitslip91[0])
+	.DDLY(k7ddrphy_dq_i_delayed9),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip91[7]),
+	.Q2(k7ddrphy_bitslip91[6]),
+	.Q3(k7ddrphy_bitslip91[5]),
+	.Q4(k7ddrphy_bitslip91[4]),
+	.Q5(k7ddrphy_bitslip91[3]),
+	.Q6(k7ddrphy_bitslip91[2]),
+	.Q7(k7ddrphy_bitslip91[1]),
+	.Q8(k7ddrphy_bitslip91[0])
 );
 
 ODELAYE2 #(
@@ -17855,12 +18298,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_43 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed9),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay9)
+	.DATAOUT(k7ddrphy_dq_o_delayed9),
+	.ODATAIN(k7ddrphy_dq_o_nodelay9)
 );
 
 IDELAYE2 #(
@@ -17874,19 +18317,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_9 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay9),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay9),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed9)
+	.DATAOUT(k7ddrphy_dq_i_delayed9)
 );
 
 IOBUF IOBUF_9(
-	.I(main_k7ddrphy_dq_o_delayed9),
-	.T(main_k7ddrphy_dq_t9),
+	.I(k7ddrphy_dq_o_delayed9),
+	.T(k7ddrphy_dq_t9),
 	.IO(ddram_dq[9]),
-	.O(main_k7ddrphy_dq_i_nodelay9)
+	.O(k7ddrphy_dq_i_nodelay9)
 );
 
 OSERDESE2 #(
@@ -17898,20 +18341,20 @@ OSERDESE2 #(
 ) OSERDESE2_44 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip100[0]),
-	.D2(main_k7ddrphy_bitslip100[1]),
-	.D3(main_k7ddrphy_bitslip100[2]),
-	.D4(main_k7ddrphy_bitslip100[3]),
-	.D5(main_k7ddrphy_bitslip100[4]),
-	.D6(main_k7ddrphy_bitslip100[5]),
-	.D7(main_k7ddrphy_bitslip100[6]),
-	.D8(main_k7ddrphy_bitslip100[7]),
+	.D1(k7ddrphy_bitslip100[0]),
+	.D2(k7ddrphy_bitslip100[1]),
+	.D3(k7ddrphy_bitslip100[2]),
+	.D4(k7ddrphy_bitslip100[3]),
+	.D5(k7ddrphy_bitslip100[4]),
+	.D6(k7ddrphy_bitslip100[5]),
+	.D7(k7ddrphy_bitslip100[6]),
+	.D8(k7ddrphy_bitslip100[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay10),
-	.TQ(main_k7ddrphy_dq_t10)
+	.OQ(k7ddrphy_dq_o_nodelay10),
+	.TQ(k7ddrphy_dq_t10)
 );
 
 ISERDESE2 #(
@@ -17927,16 +18370,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip101[7]),
-	.Q2(main_k7ddrphy_bitslip101[6]),
-	.Q3(main_k7ddrphy_bitslip101[5]),
-	.Q4(main_k7ddrphy_bitslip101[4]),
-	.Q5(main_k7ddrphy_bitslip101[3]),
-	.Q6(main_k7ddrphy_bitslip101[2]),
-	.Q7(main_k7ddrphy_bitslip101[1]),
-	.Q8(main_k7ddrphy_bitslip101[0])
+	.DDLY(k7ddrphy_dq_i_delayed10),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip101[7]),
+	.Q2(k7ddrphy_bitslip101[6]),
+	.Q3(k7ddrphy_bitslip101[5]),
+	.Q4(k7ddrphy_bitslip101[4]),
+	.Q5(k7ddrphy_bitslip101[3]),
+	.Q6(k7ddrphy_bitslip101[2]),
+	.Q7(k7ddrphy_bitslip101[1]),
+	.Q8(k7ddrphy_bitslip101[0])
 );
 
 ODELAYE2 #(
@@ -17950,12 +18393,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_44 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed10),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay10)
+	.DATAOUT(k7ddrphy_dq_o_delayed10),
+	.ODATAIN(k7ddrphy_dq_o_nodelay10)
 );
 
 IDELAYE2 #(
@@ -17969,19 +18412,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_10 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay10),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay10),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed10)
+	.DATAOUT(k7ddrphy_dq_i_delayed10)
 );
 
 IOBUF IOBUF_10(
-	.I(main_k7ddrphy_dq_o_delayed10),
-	.T(main_k7ddrphy_dq_t10),
+	.I(k7ddrphy_dq_o_delayed10),
+	.T(k7ddrphy_dq_t10),
 	.IO(ddram_dq[10]),
-	.O(main_k7ddrphy_dq_i_nodelay10)
+	.O(k7ddrphy_dq_i_nodelay10)
 );
 
 OSERDESE2 #(
@@ -17993,20 +18436,20 @@ OSERDESE2 #(
 ) OSERDESE2_45 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip110[0]),
-	.D2(main_k7ddrphy_bitslip110[1]),
-	.D3(main_k7ddrphy_bitslip110[2]),
-	.D4(main_k7ddrphy_bitslip110[3]),
-	.D5(main_k7ddrphy_bitslip110[4]),
-	.D6(main_k7ddrphy_bitslip110[5]),
-	.D7(main_k7ddrphy_bitslip110[6]),
-	.D8(main_k7ddrphy_bitslip110[7]),
+	.D1(k7ddrphy_bitslip110[0]),
+	.D2(k7ddrphy_bitslip110[1]),
+	.D3(k7ddrphy_bitslip110[2]),
+	.D4(k7ddrphy_bitslip110[3]),
+	.D5(k7ddrphy_bitslip110[4]),
+	.D6(k7ddrphy_bitslip110[5]),
+	.D7(k7ddrphy_bitslip110[6]),
+	.D8(k7ddrphy_bitslip110[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay11),
-	.TQ(main_k7ddrphy_dq_t11)
+	.OQ(k7ddrphy_dq_o_nodelay11),
+	.TQ(k7ddrphy_dq_t11)
 );
 
 ISERDESE2 #(
@@ -18022,16 +18465,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip111[7]),
-	.Q2(main_k7ddrphy_bitslip111[6]),
-	.Q3(main_k7ddrphy_bitslip111[5]),
-	.Q4(main_k7ddrphy_bitslip111[4]),
-	.Q5(main_k7ddrphy_bitslip111[3]),
-	.Q6(main_k7ddrphy_bitslip111[2]),
-	.Q7(main_k7ddrphy_bitslip111[1]),
-	.Q8(main_k7ddrphy_bitslip111[0])
+	.DDLY(k7ddrphy_dq_i_delayed11),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip111[7]),
+	.Q2(k7ddrphy_bitslip111[6]),
+	.Q3(k7ddrphy_bitslip111[5]),
+	.Q4(k7ddrphy_bitslip111[4]),
+	.Q5(k7ddrphy_bitslip111[3]),
+	.Q6(k7ddrphy_bitslip111[2]),
+	.Q7(k7ddrphy_bitslip111[1]),
+	.Q8(k7ddrphy_bitslip111[0])
 );
 
 ODELAYE2 #(
@@ -18045,12 +18488,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_45 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed11),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay11)
+	.DATAOUT(k7ddrphy_dq_o_delayed11),
+	.ODATAIN(k7ddrphy_dq_o_nodelay11)
 );
 
 IDELAYE2 #(
@@ -18064,19 +18507,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_11 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay11),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay11),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed11)
+	.DATAOUT(k7ddrphy_dq_i_delayed11)
 );
 
 IOBUF IOBUF_11(
-	.I(main_k7ddrphy_dq_o_delayed11),
-	.T(main_k7ddrphy_dq_t11),
+	.I(k7ddrphy_dq_o_delayed11),
+	.T(k7ddrphy_dq_t11),
 	.IO(ddram_dq[11]),
-	.O(main_k7ddrphy_dq_i_nodelay11)
+	.O(k7ddrphy_dq_i_nodelay11)
 );
 
 OSERDESE2 #(
@@ -18088,20 +18531,20 @@ OSERDESE2 #(
 ) OSERDESE2_46 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip120[0]),
-	.D2(main_k7ddrphy_bitslip120[1]),
-	.D3(main_k7ddrphy_bitslip120[2]),
-	.D4(main_k7ddrphy_bitslip120[3]),
-	.D5(main_k7ddrphy_bitslip120[4]),
-	.D6(main_k7ddrphy_bitslip120[5]),
-	.D7(main_k7ddrphy_bitslip120[6]),
-	.D8(main_k7ddrphy_bitslip120[7]),
+	.D1(k7ddrphy_bitslip120[0]),
+	.D2(k7ddrphy_bitslip120[1]),
+	.D3(k7ddrphy_bitslip120[2]),
+	.D4(k7ddrphy_bitslip120[3]),
+	.D5(k7ddrphy_bitslip120[4]),
+	.D6(k7ddrphy_bitslip120[5]),
+	.D7(k7ddrphy_bitslip120[6]),
+	.D8(k7ddrphy_bitslip120[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay12),
-	.TQ(main_k7ddrphy_dq_t12)
+	.OQ(k7ddrphy_dq_o_nodelay12),
+	.TQ(k7ddrphy_dq_t12)
 );
 
 ISERDESE2 #(
@@ -18117,16 +18560,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip121[7]),
-	.Q2(main_k7ddrphy_bitslip121[6]),
-	.Q3(main_k7ddrphy_bitslip121[5]),
-	.Q4(main_k7ddrphy_bitslip121[4]),
-	.Q5(main_k7ddrphy_bitslip121[3]),
-	.Q6(main_k7ddrphy_bitslip121[2]),
-	.Q7(main_k7ddrphy_bitslip121[1]),
-	.Q8(main_k7ddrphy_bitslip121[0])
+	.DDLY(k7ddrphy_dq_i_delayed12),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip121[7]),
+	.Q2(k7ddrphy_bitslip121[6]),
+	.Q3(k7ddrphy_bitslip121[5]),
+	.Q4(k7ddrphy_bitslip121[4]),
+	.Q5(k7ddrphy_bitslip121[3]),
+	.Q6(k7ddrphy_bitslip121[2]),
+	.Q7(k7ddrphy_bitslip121[1]),
+	.Q8(k7ddrphy_bitslip121[0])
 );
 
 ODELAYE2 #(
@@ -18140,12 +18583,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_46 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed12),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay12)
+	.DATAOUT(k7ddrphy_dq_o_delayed12),
+	.ODATAIN(k7ddrphy_dq_o_nodelay12)
 );
 
 IDELAYE2 #(
@@ -18159,19 +18602,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_12 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay12),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay12),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed12)
+	.DATAOUT(k7ddrphy_dq_i_delayed12)
 );
 
 IOBUF IOBUF_12(
-	.I(main_k7ddrphy_dq_o_delayed12),
-	.T(main_k7ddrphy_dq_t12),
+	.I(k7ddrphy_dq_o_delayed12),
+	.T(k7ddrphy_dq_t12),
 	.IO(ddram_dq[12]),
-	.O(main_k7ddrphy_dq_i_nodelay12)
+	.O(k7ddrphy_dq_i_nodelay12)
 );
 
 OSERDESE2 #(
@@ -18183,20 +18626,20 @@ OSERDESE2 #(
 ) OSERDESE2_47 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip130[0]),
-	.D2(main_k7ddrphy_bitslip130[1]),
-	.D3(main_k7ddrphy_bitslip130[2]),
-	.D4(main_k7ddrphy_bitslip130[3]),
-	.D5(main_k7ddrphy_bitslip130[4]),
-	.D6(main_k7ddrphy_bitslip130[5]),
-	.D7(main_k7ddrphy_bitslip130[6]),
-	.D8(main_k7ddrphy_bitslip130[7]),
+	.D1(k7ddrphy_bitslip130[0]),
+	.D2(k7ddrphy_bitslip130[1]),
+	.D3(k7ddrphy_bitslip130[2]),
+	.D4(k7ddrphy_bitslip130[3]),
+	.D5(k7ddrphy_bitslip130[4]),
+	.D6(k7ddrphy_bitslip130[5]),
+	.D7(k7ddrphy_bitslip130[6]),
+	.D8(k7ddrphy_bitslip130[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay13),
-	.TQ(main_k7ddrphy_dq_t13)
+	.OQ(k7ddrphy_dq_o_nodelay13),
+	.TQ(k7ddrphy_dq_t13)
 );
 
 ISERDESE2 #(
@@ -18212,16 +18655,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip131[7]),
-	.Q2(main_k7ddrphy_bitslip131[6]),
-	.Q3(main_k7ddrphy_bitslip131[5]),
-	.Q4(main_k7ddrphy_bitslip131[4]),
-	.Q5(main_k7ddrphy_bitslip131[3]),
-	.Q6(main_k7ddrphy_bitslip131[2]),
-	.Q7(main_k7ddrphy_bitslip131[1]),
-	.Q8(main_k7ddrphy_bitslip131[0])
+	.DDLY(k7ddrphy_dq_i_delayed13),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip131[7]),
+	.Q2(k7ddrphy_bitslip131[6]),
+	.Q3(k7ddrphy_bitslip131[5]),
+	.Q4(k7ddrphy_bitslip131[4]),
+	.Q5(k7ddrphy_bitslip131[3]),
+	.Q6(k7ddrphy_bitslip131[2]),
+	.Q7(k7ddrphy_bitslip131[1]),
+	.Q8(k7ddrphy_bitslip131[0])
 );
 
 ODELAYE2 #(
@@ -18235,12 +18678,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_47 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed13),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay13)
+	.DATAOUT(k7ddrphy_dq_o_delayed13),
+	.ODATAIN(k7ddrphy_dq_o_nodelay13)
 );
 
 IDELAYE2 #(
@@ -18254,19 +18697,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_13 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay13),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay13),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed13)
+	.DATAOUT(k7ddrphy_dq_i_delayed13)
 );
 
 IOBUF IOBUF_13(
-	.I(main_k7ddrphy_dq_o_delayed13),
-	.T(main_k7ddrphy_dq_t13),
+	.I(k7ddrphy_dq_o_delayed13),
+	.T(k7ddrphy_dq_t13),
 	.IO(ddram_dq[13]),
-	.O(main_k7ddrphy_dq_i_nodelay13)
+	.O(k7ddrphy_dq_i_nodelay13)
 );
 
 OSERDESE2 #(
@@ -18278,20 +18721,20 @@ OSERDESE2 #(
 ) OSERDESE2_48 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip140[0]),
-	.D2(main_k7ddrphy_bitslip140[1]),
-	.D3(main_k7ddrphy_bitslip140[2]),
-	.D4(main_k7ddrphy_bitslip140[3]),
-	.D5(main_k7ddrphy_bitslip140[4]),
-	.D6(main_k7ddrphy_bitslip140[5]),
-	.D7(main_k7ddrphy_bitslip140[6]),
-	.D8(main_k7ddrphy_bitslip140[7]),
+	.D1(k7ddrphy_bitslip140[0]),
+	.D2(k7ddrphy_bitslip140[1]),
+	.D3(k7ddrphy_bitslip140[2]),
+	.D4(k7ddrphy_bitslip140[3]),
+	.D5(k7ddrphy_bitslip140[4]),
+	.D6(k7ddrphy_bitslip140[5]),
+	.D7(k7ddrphy_bitslip140[6]),
+	.D8(k7ddrphy_bitslip140[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay14),
-	.TQ(main_k7ddrphy_dq_t14)
+	.OQ(k7ddrphy_dq_o_nodelay14),
+	.TQ(k7ddrphy_dq_t14)
 );
 
 ISERDESE2 #(
@@ -18307,16 +18750,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip141[7]),
-	.Q2(main_k7ddrphy_bitslip141[6]),
-	.Q3(main_k7ddrphy_bitslip141[5]),
-	.Q4(main_k7ddrphy_bitslip141[4]),
-	.Q5(main_k7ddrphy_bitslip141[3]),
-	.Q6(main_k7ddrphy_bitslip141[2]),
-	.Q7(main_k7ddrphy_bitslip141[1]),
-	.Q8(main_k7ddrphy_bitslip141[0])
+	.DDLY(k7ddrphy_dq_i_delayed14),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip141[7]),
+	.Q2(k7ddrphy_bitslip141[6]),
+	.Q3(k7ddrphy_bitslip141[5]),
+	.Q4(k7ddrphy_bitslip141[4]),
+	.Q5(k7ddrphy_bitslip141[3]),
+	.Q6(k7ddrphy_bitslip141[2]),
+	.Q7(k7ddrphy_bitslip141[1]),
+	.Q8(k7ddrphy_bitslip141[0])
 );
 
 ODELAYE2 #(
@@ -18330,12 +18773,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_48 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed14),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay14)
+	.DATAOUT(k7ddrphy_dq_o_delayed14),
+	.ODATAIN(k7ddrphy_dq_o_nodelay14)
 );
 
 IDELAYE2 #(
@@ -18349,19 +18792,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_14 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay14),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay14),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed14)
+	.DATAOUT(k7ddrphy_dq_i_delayed14)
 );
 
 IOBUF IOBUF_14(
-	.I(main_k7ddrphy_dq_o_delayed14),
-	.T(main_k7ddrphy_dq_t14),
+	.I(k7ddrphy_dq_o_delayed14),
+	.T(k7ddrphy_dq_t14),
 	.IO(ddram_dq[14]),
-	.O(main_k7ddrphy_dq_i_nodelay14)
+	.O(k7ddrphy_dq_i_nodelay14)
 );
 
 OSERDESE2 #(
@@ -18373,20 +18816,20 @@ OSERDESE2 #(
 ) OSERDESE2_49 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip150[0]),
-	.D2(main_k7ddrphy_bitslip150[1]),
-	.D3(main_k7ddrphy_bitslip150[2]),
-	.D4(main_k7ddrphy_bitslip150[3]),
-	.D5(main_k7ddrphy_bitslip150[4]),
-	.D6(main_k7ddrphy_bitslip150[5]),
-	.D7(main_k7ddrphy_bitslip150[6]),
-	.D8(main_k7ddrphy_bitslip150[7]),
+	.D1(k7ddrphy_bitslip150[0]),
+	.D2(k7ddrphy_bitslip150[1]),
+	.D3(k7ddrphy_bitslip150[2]),
+	.D4(k7ddrphy_bitslip150[3]),
+	.D5(k7ddrphy_bitslip150[4]),
+	.D6(k7ddrphy_bitslip150[5]),
+	.D7(k7ddrphy_bitslip150[6]),
+	.D8(k7ddrphy_bitslip150[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay15),
-	.TQ(main_k7ddrphy_dq_t15)
+	.OQ(k7ddrphy_dq_o_nodelay15),
+	.TQ(k7ddrphy_dq_t15)
 );
 
 ISERDESE2 #(
@@ -18402,16 +18845,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip151[7]),
-	.Q2(main_k7ddrphy_bitslip151[6]),
-	.Q3(main_k7ddrphy_bitslip151[5]),
-	.Q4(main_k7ddrphy_bitslip151[4]),
-	.Q5(main_k7ddrphy_bitslip151[3]),
-	.Q6(main_k7ddrphy_bitslip151[2]),
-	.Q7(main_k7ddrphy_bitslip151[1]),
-	.Q8(main_k7ddrphy_bitslip151[0])
+	.DDLY(k7ddrphy_dq_i_delayed15),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip151[7]),
+	.Q2(k7ddrphy_bitslip151[6]),
+	.Q3(k7ddrphy_bitslip151[5]),
+	.Q4(k7ddrphy_bitslip151[4]),
+	.Q5(k7ddrphy_bitslip151[3]),
+	.Q6(k7ddrphy_bitslip151[2]),
+	.Q7(k7ddrphy_bitslip151[1]),
+	.Q8(k7ddrphy_bitslip151[0])
 );
 
 ODELAYE2 #(
@@ -18425,12 +18868,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_49 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed15),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay15)
+	.DATAOUT(k7ddrphy_dq_o_delayed15),
+	.ODATAIN(k7ddrphy_dq_o_nodelay15)
 );
 
 IDELAYE2 #(
@@ -18444,19 +18887,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_15 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay15),
+	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay15),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed15)
+	.DATAOUT(k7ddrphy_dq_i_delayed15)
 );
 
 IOBUF IOBUF_15(
-	.I(main_k7ddrphy_dq_o_delayed15),
-	.T(main_k7ddrphy_dq_t15),
+	.I(k7ddrphy_dq_o_delayed15),
+	.T(k7ddrphy_dq_t15),
 	.IO(ddram_dq[15]),
-	.O(main_k7ddrphy_dq_i_nodelay15)
+	.O(k7ddrphy_dq_i_nodelay15)
 );
 
 OSERDESE2 #(
@@ -18468,20 +18911,20 @@ OSERDESE2 #(
 ) OSERDESE2_50 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip160[0]),
-	.D2(main_k7ddrphy_bitslip160[1]),
-	.D3(main_k7ddrphy_bitslip160[2]),
-	.D4(main_k7ddrphy_bitslip160[3]),
-	.D5(main_k7ddrphy_bitslip160[4]),
-	.D6(main_k7ddrphy_bitslip160[5]),
-	.D7(main_k7ddrphy_bitslip160[6]),
-	.D8(main_k7ddrphy_bitslip160[7]),
+	.D1(k7ddrphy_bitslip160[0]),
+	.D2(k7ddrphy_bitslip160[1]),
+	.D3(k7ddrphy_bitslip160[2]),
+	.D4(k7ddrphy_bitslip160[3]),
+	.D5(k7ddrphy_bitslip160[4]),
+	.D6(k7ddrphy_bitslip160[5]),
+	.D7(k7ddrphy_bitslip160[6]),
+	.D8(k7ddrphy_bitslip160[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay16),
-	.TQ(main_k7ddrphy_dq_t16)
+	.OQ(k7ddrphy_dq_o_nodelay16),
+	.TQ(k7ddrphy_dq_t16)
 );
 
 ISERDESE2 #(
@@ -18497,16 +18940,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed16),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip161[7]),
-	.Q2(main_k7ddrphy_bitslip161[6]),
-	.Q3(main_k7ddrphy_bitslip161[5]),
-	.Q4(main_k7ddrphy_bitslip161[4]),
-	.Q5(main_k7ddrphy_bitslip161[3]),
-	.Q6(main_k7ddrphy_bitslip161[2]),
-	.Q7(main_k7ddrphy_bitslip161[1]),
-	.Q8(main_k7ddrphy_bitslip161[0])
+	.DDLY(k7ddrphy_dq_i_delayed16),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip161[7]),
+	.Q2(k7ddrphy_bitslip161[6]),
+	.Q3(k7ddrphy_bitslip161[5]),
+	.Q4(k7ddrphy_bitslip161[4]),
+	.Q5(k7ddrphy_bitslip161[3]),
+	.Q6(k7ddrphy_bitslip161[2]),
+	.Q7(k7ddrphy_bitslip161[1]),
+	.Q8(k7ddrphy_bitslip161[0])
 );
 
 ODELAYE2 #(
@@ -18520,12 +18963,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_50 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed16),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay16)
+	.DATAOUT(k7ddrphy_dq_o_delayed16),
+	.ODATAIN(k7ddrphy_dq_o_nodelay16)
 );
 
 IDELAYE2 #(
@@ -18539,19 +18982,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_16 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay16),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay16),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed16)
+	.DATAOUT(k7ddrphy_dq_i_delayed16)
 );
 
 IOBUF IOBUF_16(
-	.I(main_k7ddrphy_dq_o_delayed16),
-	.T(main_k7ddrphy_dq_t16),
+	.I(k7ddrphy_dq_o_delayed16),
+	.T(k7ddrphy_dq_t16),
 	.IO(ddram_dq[16]),
-	.O(main_k7ddrphy_dq_i_nodelay16)
+	.O(k7ddrphy_dq_i_nodelay16)
 );
 
 OSERDESE2 #(
@@ -18563,20 +19006,20 @@ OSERDESE2 #(
 ) OSERDESE2_51 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip170[0]),
-	.D2(main_k7ddrphy_bitslip170[1]),
-	.D3(main_k7ddrphy_bitslip170[2]),
-	.D4(main_k7ddrphy_bitslip170[3]),
-	.D5(main_k7ddrphy_bitslip170[4]),
-	.D6(main_k7ddrphy_bitslip170[5]),
-	.D7(main_k7ddrphy_bitslip170[6]),
-	.D8(main_k7ddrphy_bitslip170[7]),
+	.D1(k7ddrphy_bitslip170[0]),
+	.D2(k7ddrphy_bitslip170[1]),
+	.D3(k7ddrphy_bitslip170[2]),
+	.D4(k7ddrphy_bitslip170[3]),
+	.D5(k7ddrphy_bitslip170[4]),
+	.D6(k7ddrphy_bitslip170[5]),
+	.D7(k7ddrphy_bitslip170[6]),
+	.D8(k7ddrphy_bitslip170[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay17),
-	.TQ(main_k7ddrphy_dq_t17)
+	.OQ(k7ddrphy_dq_o_nodelay17),
+	.TQ(k7ddrphy_dq_t17)
 );
 
 ISERDESE2 #(
@@ -18592,16 +19035,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed17),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip171[7]),
-	.Q2(main_k7ddrphy_bitslip171[6]),
-	.Q3(main_k7ddrphy_bitslip171[5]),
-	.Q4(main_k7ddrphy_bitslip171[4]),
-	.Q5(main_k7ddrphy_bitslip171[3]),
-	.Q6(main_k7ddrphy_bitslip171[2]),
-	.Q7(main_k7ddrphy_bitslip171[1]),
-	.Q8(main_k7ddrphy_bitslip171[0])
+	.DDLY(k7ddrphy_dq_i_delayed17),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip171[7]),
+	.Q2(k7ddrphy_bitslip171[6]),
+	.Q3(k7ddrphy_bitslip171[5]),
+	.Q4(k7ddrphy_bitslip171[4]),
+	.Q5(k7ddrphy_bitslip171[3]),
+	.Q6(k7ddrphy_bitslip171[2]),
+	.Q7(k7ddrphy_bitslip171[1]),
+	.Q8(k7ddrphy_bitslip171[0])
 );
 
 ODELAYE2 #(
@@ -18615,12 +19058,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_51 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed17),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay17)
+	.DATAOUT(k7ddrphy_dq_o_delayed17),
+	.ODATAIN(k7ddrphy_dq_o_nodelay17)
 );
 
 IDELAYE2 #(
@@ -18634,19 +19077,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_17 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay17),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay17),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed17)
+	.DATAOUT(k7ddrphy_dq_i_delayed17)
 );
 
 IOBUF IOBUF_17(
-	.I(main_k7ddrphy_dq_o_delayed17),
-	.T(main_k7ddrphy_dq_t17),
+	.I(k7ddrphy_dq_o_delayed17),
+	.T(k7ddrphy_dq_t17),
 	.IO(ddram_dq[17]),
-	.O(main_k7ddrphy_dq_i_nodelay17)
+	.O(k7ddrphy_dq_i_nodelay17)
 );
 
 OSERDESE2 #(
@@ -18658,20 +19101,20 @@ OSERDESE2 #(
 ) OSERDESE2_52 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip180[0]),
-	.D2(main_k7ddrphy_bitslip180[1]),
-	.D3(main_k7ddrphy_bitslip180[2]),
-	.D4(main_k7ddrphy_bitslip180[3]),
-	.D5(main_k7ddrphy_bitslip180[4]),
-	.D6(main_k7ddrphy_bitslip180[5]),
-	.D7(main_k7ddrphy_bitslip180[6]),
-	.D8(main_k7ddrphy_bitslip180[7]),
+	.D1(k7ddrphy_bitslip180[0]),
+	.D2(k7ddrphy_bitslip180[1]),
+	.D3(k7ddrphy_bitslip180[2]),
+	.D4(k7ddrphy_bitslip180[3]),
+	.D5(k7ddrphy_bitslip180[4]),
+	.D6(k7ddrphy_bitslip180[5]),
+	.D7(k7ddrphy_bitslip180[6]),
+	.D8(k7ddrphy_bitslip180[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay18),
-	.TQ(main_k7ddrphy_dq_t18)
+	.OQ(k7ddrphy_dq_o_nodelay18),
+	.TQ(k7ddrphy_dq_t18)
 );
 
 ISERDESE2 #(
@@ -18687,16 +19130,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed18),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip181[7]),
-	.Q2(main_k7ddrphy_bitslip181[6]),
-	.Q3(main_k7ddrphy_bitslip181[5]),
-	.Q4(main_k7ddrphy_bitslip181[4]),
-	.Q5(main_k7ddrphy_bitslip181[3]),
-	.Q6(main_k7ddrphy_bitslip181[2]),
-	.Q7(main_k7ddrphy_bitslip181[1]),
-	.Q8(main_k7ddrphy_bitslip181[0])
+	.DDLY(k7ddrphy_dq_i_delayed18),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip181[7]),
+	.Q2(k7ddrphy_bitslip181[6]),
+	.Q3(k7ddrphy_bitslip181[5]),
+	.Q4(k7ddrphy_bitslip181[4]),
+	.Q5(k7ddrphy_bitslip181[3]),
+	.Q6(k7ddrphy_bitslip181[2]),
+	.Q7(k7ddrphy_bitslip181[1]),
+	.Q8(k7ddrphy_bitslip181[0])
 );
 
 ODELAYE2 #(
@@ -18710,12 +19153,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_52 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed18),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay18)
+	.DATAOUT(k7ddrphy_dq_o_delayed18),
+	.ODATAIN(k7ddrphy_dq_o_nodelay18)
 );
 
 IDELAYE2 #(
@@ -18729,19 +19172,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_18 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay18),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay18),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed18)
+	.DATAOUT(k7ddrphy_dq_i_delayed18)
 );
 
 IOBUF IOBUF_18(
-	.I(main_k7ddrphy_dq_o_delayed18),
-	.T(main_k7ddrphy_dq_t18),
+	.I(k7ddrphy_dq_o_delayed18),
+	.T(k7ddrphy_dq_t18),
 	.IO(ddram_dq[18]),
-	.O(main_k7ddrphy_dq_i_nodelay18)
+	.O(k7ddrphy_dq_i_nodelay18)
 );
 
 OSERDESE2 #(
@@ -18753,20 +19196,20 @@ OSERDESE2 #(
 ) OSERDESE2_53 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip190[0]),
-	.D2(main_k7ddrphy_bitslip190[1]),
-	.D3(main_k7ddrphy_bitslip190[2]),
-	.D4(main_k7ddrphy_bitslip190[3]),
-	.D5(main_k7ddrphy_bitslip190[4]),
-	.D6(main_k7ddrphy_bitslip190[5]),
-	.D7(main_k7ddrphy_bitslip190[6]),
-	.D8(main_k7ddrphy_bitslip190[7]),
+	.D1(k7ddrphy_bitslip190[0]),
+	.D2(k7ddrphy_bitslip190[1]),
+	.D3(k7ddrphy_bitslip190[2]),
+	.D4(k7ddrphy_bitslip190[3]),
+	.D5(k7ddrphy_bitslip190[4]),
+	.D6(k7ddrphy_bitslip190[5]),
+	.D7(k7ddrphy_bitslip190[6]),
+	.D8(k7ddrphy_bitslip190[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay19),
-	.TQ(main_k7ddrphy_dq_t19)
+	.OQ(k7ddrphy_dq_o_nodelay19),
+	.TQ(k7ddrphy_dq_t19)
 );
 
 ISERDESE2 #(
@@ -18782,16 +19225,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed19),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip191[7]),
-	.Q2(main_k7ddrphy_bitslip191[6]),
-	.Q3(main_k7ddrphy_bitslip191[5]),
-	.Q4(main_k7ddrphy_bitslip191[4]),
-	.Q5(main_k7ddrphy_bitslip191[3]),
-	.Q6(main_k7ddrphy_bitslip191[2]),
-	.Q7(main_k7ddrphy_bitslip191[1]),
-	.Q8(main_k7ddrphy_bitslip191[0])
+	.DDLY(k7ddrphy_dq_i_delayed19),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip191[7]),
+	.Q2(k7ddrphy_bitslip191[6]),
+	.Q3(k7ddrphy_bitslip191[5]),
+	.Q4(k7ddrphy_bitslip191[4]),
+	.Q5(k7ddrphy_bitslip191[3]),
+	.Q6(k7ddrphy_bitslip191[2]),
+	.Q7(k7ddrphy_bitslip191[1]),
+	.Q8(k7ddrphy_bitslip191[0])
 );
 
 ODELAYE2 #(
@@ -18805,12 +19248,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_53 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed19),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay19)
+	.DATAOUT(k7ddrphy_dq_o_delayed19),
+	.ODATAIN(k7ddrphy_dq_o_nodelay19)
 );
 
 IDELAYE2 #(
@@ -18824,19 +19267,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_19 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay19),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay19),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed19)
+	.DATAOUT(k7ddrphy_dq_i_delayed19)
 );
 
 IOBUF IOBUF_19(
-	.I(main_k7ddrphy_dq_o_delayed19),
-	.T(main_k7ddrphy_dq_t19),
+	.I(k7ddrphy_dq_o_delayed19),
+	.T(k7ddrphy_dq_t19),
 	.IO(ddram_dq[19]),
-	.O(main_k7ddrphy_dq_i_nodelay19)
+	.O(k7ddrphy_dq_i_nodelay19)
 );
 
 OSERDESE2 #(
@@ -18848,20 +19291,20 @@ OSERDESE2 #(
 ) OSERDESE2_54 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip200[0]),
-	.D2(main_k7ddrphy_bitslip200[1]),
-	.D3(main_k7ddrphy_bitslip200[2]),
-	.D4(main_k7ddrphy_bitslip200[3]),
-	.D5(main_k7ddrphy_bitslip200[4]),
-	.D6(main_k7ddrphy_bitslip200[5]),
-	.D7(main_k7ddrphy_bitslip200[6]),
-	.D8(main_k7ddrphy_bitslip200[7]),
+	.D1(k7ddrphy_bitslip200[0]),
+	.D2(k7ddrphy_bitslip200[1]),
+	.D3(k7ddrphy_bitslip200[2]),
+	.D4(k7ddrphy_bitslip200[3]),
+	.D5(k7ddrphy_bitslip200[4]),
+	.D6(k7ddrphy_bitslip200[5]),
+	.D7(k7ddrphy_bitslip200[6]),
+	.D8(k7ddrphy_bitslip200[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay20),
-	.TQ(main_k7ddrphy_dq_t20)
+	.OQ(k7ddrphy_dq_o_nodelay20),
+	.TQ(k7ddrphy_dq_t20)
 );
 
 ISERDESE2 #(
@@ -18877,16 +19320,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed20),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip201[7]),
-	.Q2(main_k7ddrphy_bitslip201[6]),
-	.Q3(main_k7ddrphy_bitslip201[5]),
-	.Q4(main_k7ddrphy_bitslip201[4]),
-	.Q5(main_k7ddrphy_bitslip201[3]),
-	.Q6(main_k7ddrphy_bitslip201[2]),
-	.Q7(main_k7ddrphy_bitslip201[1]),
-	.Q8(main_k7ddrphy_bitslip201[0])
+	.DDLY(k7ddrphy_dq_i_delayed20),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip201[7]),
+	.Q2(k7ddrphy_bitslip201[6]),
+	.Q3(k7ddrphy_bitslip201[5]),
+	.Q4(k7ddrphy_bitslip201[4]),
+	.Q5(k7ddrphy_bitslip201[3]),
+	.Q6(k7ddrphy_bitslip201[2]),
+	.Q7(k7ddrphy_bitslip201[1]),
+	.Q8(k7ddrphy_bitslip201[0])
 );
 
 ODELAYE2 #(
@@ -18900,12 +19343,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_54 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed20),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay20)
+	.DATAOUT(k7ddrphy_dq_o_delayed20),
+	.ODATAIN(k7ddrphy_dq_o_nodelay20)
 );
 
 IDELAYE2 #(
@@ -18919,19 +19362,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_20 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay20),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay20),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed20)
+	.DATAOUT(k7ddrphy_dq_i_delayed20)
 );
 
 IOBUF IOBUF_20(
-	.I(main_k7ddrphy_dq_o_delayed20),
-	.T(main_k7ddrphy_dq_t20),
+	.I(k7ddrphy_dq_o_delayed20),
+	.T(k7ddrphy_dq_t20),
 	.IO(ddram_dq[20]),
-	.O(main_k7ddrphy_dq_i_nodelay20)
+	.O(k7ddrphy_dq_i_nodelay20)
 );
 
 OSERDESE2 #(
@@ -18943,20 +19386,20 @@ OSERDESE2 #(
 ) OSERDESE2_55 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip210[0]),
-	.D2(main_k7ddrphy_bitslip210[1]),
-	.D3(main_k7ddrphy_bitslip210[2]),
-	.D4(main_k7ddrphy_bitslip210[3]),
-	.D5(main_k7ddrphy_bitslip210[4]),
-	.D6(main_k7ddrphy_bitslip210[5]),
-	.D7(main_k7ddrphy_bitslip210[6]),
-	.D8(main_k7ddrphy_bitslip210[7]),
+	.D1(k7ddrphy_bitslip210[0]),
+	.D2(k7ddrphy_bitslip210[1]),
+	.D3(k7ddrphy_bitslip210[2]),
+	.D4(k7ddrphy_bitslip210[3]),
+	.D5(k7ddrphy_bitslip210[4]),
+	.D6(k7ddrphy_bitslip210[5]),
+	.D7(k7ddrphy_bitslip210[6]),
+	.D8(k7ddrphy_bitslip210[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay21),
-	.TQ(main_k7ddrphy_dq_t21)
+	.OQ(k7ddrphy_dq_o_nodelay21),
+	.TQ(k7ddrphy_dq_t21)
 );
 
 ISERDESE2 #(
@@ -18972,16 +19415,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed21),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip211[7]),
-	.Q2(main_k7ddrphy_bitslip211[6]),
-	.Q3(main_k7ddrphy_bitslip211[5]),
-	.Q4(main_k7ddrphy_bitslip211[4]),
-	.Q5(main_k7ddrphy_bitslip211[3]),
-	.Q6(main_k7ddrphy_bitslip211[2]),
-	.Q7(main_k7ddrphy_bitslip211[1]),
-	.Q8(main_k7ddrphy_bitslip211[0])
+	.DDLY(k7ddrphy_dq_i_delayed21),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip211[7]),
+	.Q2(k7ddrphy_bitslip211[6]),
+	.Q3(k7ddrphy_bitslip211[5]),
+	.Q4(k7ddrphy_bitslip211[4]),
+	.Q5(k7ddrphy_bitslip211[3]),
+	.Q6(k7ddrphy_bitslip211[2]),
+	.Q7(k7ddrphy_bitslip211[1]),
+	.Q8(k7ddrphy_bitslip211[0])
 );
 
 ODELAYE2 #(
@@ -18995,12 +19438,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_55 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed21),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay21)
+	.DATAOUT(k7ddrphy_dq_o_delayed21),
+	.ODATAIN(k7ddrphy_dq_o_nodelay21)
 );
 
 IDELAYE2 #(
@@ -19014,19 +19457,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_21 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay21),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay21),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed21)
+	.DATAOUT(k7ddrphy_dq_i_delayed21)
 );
 
 IOBUF IOBUF_21(
-	.I(main_k7ddrphy_dq_o_delayed21),
-	.T(main_k7ddrphy_dq_t21),
+	.I(k7ddrphy_dq_o_delayed21),
+	.T(k7ddrphy_dq_t21),
 	.IO(ddram_dq[21]),
-	.O(main_k7ddrphy_dq_i_nodelay21)
+	.O(k7ddrphy_dq_i_nodelay21)
 );
 
 OSERDESE2 #(
@@ -19038,20 +19481,20 @@ OSERDESE2 #(
 ) OSERDESE2_56 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip220[0]),
-	.D2(main_k7ddrphy_bitslip220[1]),
-	.D3(main_k7ddrphy_bitslip220[2]),
-	.D4(main_k7ddrphy_bitslip220[3]),
-	.D5(main_k7ddrphy_bitslip220[4]),
-	.D6(main_k7ddrphy_bitslip220[5]),
-	.D7(main_k7ddrphy_bitslip220[6]),
-	.D8(main_k7ddrphy_bitslip220[7]),
+	.D1(k7ddrphy_bitslip220[0]),
+	.D2(k7ddrphy_bitslip220[1]),
+	.D3(k7ddrphy_bitslip220[2]),
+	.D4(k7ddrphy_bitslip220[3]),
+	.D5(k7ddrphy_bitslip220[4]),
+	.D6(k7ddrphy_bitslip220[5]),
+	.D7(k7ddrphy_bitslip220[6]),
+	.D8(k7ddrphy_bitslip220[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay22),
-	.TQ(main_k7ddrphy_dq_t22)
+	.OQ(k7ddrphy_dq_o_nodelay22),
+	.TQ(k7ddrphy_dq_t22)
 );
 
 ISERDESE2 #(
@@ -19067,16 +19510,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed22),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip221[7]),
-	.Q2(main_k7ddrphy_bitslip221[6]),
-	.Q3(main_k7ddrphy_bitslip221[5]),
-	.Q4(main_k7ddrphy_bitslip221[4]),
-	.Q5(main_k7ddrphy_bitslip221[3]),
-	.Q6(main_k7ddrphy_bitslip221[2]),
-	.Q7(main_k7ddrphy_bitslip221[1]),
-	.Q8(main_k7ddrphy_bitslip221[0])
+	.DDLY(k7ddrphy_dq_i_delayed22),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip221[7]),
+	.Q2(k7ddrphy_bitslip221[6]),
+	.Q3(k7ddrphy_bitslip221[5]),
+	.Q4(k7ddrphy_bitslip221[4]),
+	.Q5(k7ddrphy_bitslip221[3]),
+	.Q6(k7ddrphy_bitslip221[2]),
+	.Q7(k7ddrphy_bitslip221[1]),
+	.Q8(k7ddrphy_bitslip221[0])
 );
 
 ODELAYE2 #(
@@ -19090,12 +19533,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_56 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed22),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay22)
+	.DATAOUT(k7ddrphy_dq_o_delayed22),
+	.ODATAIN(k7ddrphy_dq_o_nodelay22)
 );
 
 IDELAYE2 #(
@@ -19109,19 +19552,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_22 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay22),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay22),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed22)
+	.DATAOUT(k7ddrphy_dq_i_delayed22)
 );
 
 IOBUF IOBUF_22(
-	.I(main_k7ddrphy_dq_o_delayed22),
-	.T(main_k7ddrphy_dq_t22),
+	.I(k7ddrphy_dq_o_delayed22),
+	.T(k7ddrphy_dq_t22),
 	.IO(ddram_dq[22]),
-	.O(main_k7ddrphy_dq_i_nodelay22)
+	.O(k7ddrphy_dq_i_nodelay22)
 );
 
 OSERDESE2 #(
@@ -19133,20 +19576,20 @@ OSERDESE2 #(
 ) OSERDESE2_57 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip230[0]),
-	.D2(main_k7ddrphy_bitslip230[1]),
-	.D3(main_k7ddrphy_bitslip230[2]),
-	.D4(main_k7ddrphy_bitslip230[3]),
-	.D5(main_k7ddrphy_bitslip230[4]),
-	.D6(main_k7ddrphy_bitslip230[5]),
-	.D7(main_k7ddrphy_bitslip230[6]),
-	.D8(main_k7ddrphy_bitslip230[7]),
+	.D1(k7ddrphy_bitslip230[0]),
+	.D2(k7ddrphy_bitslip230[1]),
+	.D3(k7ddrphy_bitslip230[2]),
+	.D4(k7ddrphy_bitslip230[3]),
+	.D5(k7ddrphy_bitslip230[4]),
+	.D6(k7ddrphy_bitslip230[5]),
+	.D7(k7ddrphy_bitslip230[6]),
+	.D8(k7ddrphy_bitslip230[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay23),
-	.TQ(main_k7ddrphy_dq_t23)
+	.OQ(k7ddrphy_dq_o_nodelay23),
+	.TQ(k7ddrphy_dq_t23)
 );
 
 ISERDESE2 #(
@@ -19162,16 +19605,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed23),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip231[7]),
-	.Q2(main_k7ddrphy_bitslip231[6]),
-	.Q3(main_k7ddrphy_bitslip231[5]),
-	.Q4(main_k7ddrphy_bitslip231[4]),
-	.Q5(main_k7ddrphy_bitslip231[3]),
-	.Q6(main_k7ddrphy_bitslip231[2]),
-	.Q7(main_k7ddrphy_bitslip231[1]),
-	.Q8(main_k7ddrphy_bitslip231[0])
+	.DDLY(k7ddrphy_dq_i_delayed23),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip231[7]),
+	.Q2(k7ddrphy_bitslip231[6]),
+	.Q3(k7ddrphy_bitslip231[5]),
+	.Q4(k7ddrphy_bitslip231[4]),
+	.Q5(k7ddrphy_bitslip231[3]),
+	.Q6(k7ddrphy_bitslip231[2]),
+	.Q7(k7ddrphy_bitslip231[1]),
+	.Q8(k7ddrphy_bitslip231[0])
 );
 
 ODELAYE2 #(
@@ -19185,12 +19628,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_57 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed23),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay23)
+	.DATAOUT(k7ddrphy_dq_o_delayed23),
+	.ODATAIN(k7ddrphy_dq_o_nodelay23)
 );
 
 IDELAYE2 #(
@@ -19204,19 +19647,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_23 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay23),
+	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay23),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed23)
+	.DATAOUT(k7ddrphy_dq_i_delayed23)
 );
 
 IOBUF IOBUF_23(
-	.I(main_k7ddrphy_dq_o_delayed23),
-	.T(main_k7ddrphy_dq_t23),
+	.I(k7ddrphy_dq_o_delayed23),
+	.T(k7ddrphy_dq_t23),
 	.IO(ddram_dq[23]),
-	.O(main_k7ddrphy_dq_i_nodelay23)
+	.O(k7ddrphy_dq_i_nodelay23)
 );
 
 OSERDESE2 #(
@@ -19228,20 +19671,20 @@ OSERDESE2 #(
 ) OSERDESE2_58 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip240[0]),
-	.D2(main_k7ddrphy_bitslip240[1]),
-	.D3(main_k7ddrphy_bitslip240[2]),
-	.D4(main_k7ddrphy_bitslip240[3]),
-	.D5(main_k7ddrphy_bitslip240[4]),
-	.D6(main_k7ddrphy_bitslip240[5]),
-	.D7(main_k7ddrphy_bitslip240[6]),
-	.D8(main_k7ddrphy_bitslip240[7]),
+	.D1(k7ddrphy_bitslip240[0]),
+	.D2(k7ddrphy_bitslip240[1]),
+	.D3(k7ddrphy_bitslip240[2]),
+	.D4(k7ddrphy_bitslip240[3]),
+	.D5(k7ddrphy_bitslip240[4]),
+	.D6(k7ddrphy_bitslip240[5]),
+	.D7(k7ddrphy_bitslip240[6]),
+	.D8(k7ddrphy_bitslip240[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay24),
-	.TQ(main_k7ddrphy_dq_t24)
+	.OQ(k7ddrphy_dq_o_nodelay24),
+	.TQ(k7ddrphy_dq_t24)
 );
 
 ISERDESE2 #(
@@ -19257,16 +19700,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed24),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip241[7]),
-	.Q2(main_k7ddrphy_bitslip241[6]),
-	.Q3(main_k7ddrphy_bitslip241[5]),
-	.Q4(main_k7ddrphy_bitslip241[4]),
-	.Q5(main_k7ddrphy_bitslip241[3]),
-	.Q6(main_k7ddrphy_bitslip241[2]),
-	.Q7(main_k7ddrphy_bitslip241[1]),
-	.Q8(main_k7ddrphy_bitslip241[0])
+	.DDLY(k7ddrphy_dq_i_delayed24),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip241[7]),
+	.Q2(k7ddrphy_bitslip241[6]),
+	.Q3(k7ddrphy_bitslip241[5]),
+	.Q4(k7ddrphy_bitslip241[4]),
+	.Q5(k7ddrphy_bitslip241[3]),
+	.Q6(k7ddrphy_bitslip241[2]),
+	.Q7(k7ddrphy_bitslip241[1]),
+	.Q8(k7ddrphy_bitslip241[0])
 );
 
 ODELAYE2 #(
@@ -19280,12 +19723,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_58 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed24),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay24)
+	.DATAOUT(k7ddrphy_dq_o_delayed24),
+	.ODATAIN(k7ddrphy_dq_o_nodelay24)
 );
 
 IDELAYE2 #(
@@ -19299,19 +19742,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_24 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay24),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay24),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed24)
+	.DATAOUT(k7ddrphy_dq_i_delayed24)
 );
 
 IOBUF IOBUF_24(
-	.I(main_k7ddrphy_dq_o_delayed24),
-	.T(main_k7ddrphy_dq_t24),
+	.I(k7ddrphy_dq_o_delayed24),
+	.T(k7ddrphy_dq_t24),
 	.IO(ddram_dq[24]),
-	.O(main_k7ddrphy_dq_i_nodelay24)
+	.O(k7ddrphy_dq_i_nodelay24)
 );
 
 OSERDESE2 #(
@@ -19323,20 +19766,20 @@ OSERDESE2 #(
 ) OSERDESE2_59 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip250[0]),
-	.D2(main_k7ddrphy_bitslip250[1]),
-	.D3(main_k7ddrphy_bitslip250[2]),
-	.D4(main_k7ddrphy_bitslip250[3]),
-	.D5(main_k7ddrphy_bitslip250[4]),
-	.D6(main_k7ddrphy_bitslip250[5]),
-	.D7(main_k7ddrphy_bitslip250[6]),
-	.D8(main_k7ddrphy_bitslip250[7]),
+	.D1(k7ddrphy_bitslip250[0]),
+	.D2(k7ddrphy_bitslip250[1]),
+	.D3(k7ddrphy_bitslip250[2]),
+	.D4(k7ddrphy_bitslip250[3]),
+	.D5(k7ddrphy_bitslip250[4]),
+	.D6(k7ddrphy_bitslip250[5]),
+	.D7(k7ddrphy_bitslip250[6]),
+	.D8(k7ddrphy_bitslip250[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay25),
-	.TQ(main_k7ddrphy_dq_t25)
+	.OQ(k7ddrphy_dq_o_nodelay25),
+	.TQ(k7ddrphy_dq_t25)
 );
 
 ISERDESE2 #(
@@ -19352,16 +19795,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed25),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip251[7]),
-	.Q2(main_k7ddrphy_bitslip251[6]),
-	.Q3(main_k7ddrphy_bitslip251[5]),
-	.Q4(main_k7ddrphy_bitslip251[4]),
-	.Q5(main_k7ddrphy_bitslip251[3]),
-	.Q6(main_k7ddrphy_bitslip251[2]),
-	.Q7(main_k7ddrphy_bitslip251[1]),
-	.Q8(main_k7ddrphy_bitslip251[0])
+	.DDLY(k7ddrphy_dq_i_delayed25),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip251[7]),
+	.Q2(k7ddrphy_bitslip251[6]),
+	.Q3(k7ddrphy_bitslip251[5]),
+	.Q4(k7ddrphy_bitslip251[4]),
+	.Q5(k7ddrphy_bitslip251[3]),
+	.Q6(k7ddrphy_bitslip251[2]),
+	.Q7(k7ddrphy_bitslip251[1]),
+	.Q8(k7ddrphy_bitslip251[0])
 );
 
 ODELAYE2 #(
@@ -19375,12 +19818,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_59 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed25),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay25)
+	.DATAOUT(k7ddrphy_dq_o_delayed25),
+	.ODATAIN(k7ddrphy_dq_o_nodelay25)
 );
 
 IDELAYE2 #(
@@ -19394,19 +19837,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_25 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay25),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay25),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed25)
+	.DATAOUT(k7ddrphy_dq_i_delayed25)
 );
 
 IOBUF IOBUF_25(
-	.I(main_k7ddrphy_dq_o_delayed25),
-	.T(main_k7ddrphy_dq_t25),
+	.I(k7ddrphy_dq_o_delayed25),
+	.T(k7ddrphy_dq_t25),
 	.IO(ddram_dq[25]),
-	.O(main_k7ddrphy_dq_i_nodelay25)
+	.O(k7ddrphy_dq_i_nodelay25)
 );
 
 OSERDESE2 #(
@@ -19418,20 +19861,20 @@ OSERDESE2 #(
 ) OSERDESE2_60 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip260[0]),
-	.D2(main_k7ddrphy_bitslip260[1]),
-	.D3(main_k7ddrphy_bitslip260[2]),
-	.D4(main_k7ddrphy_bitslip260[3]),
-	.D5(main_k7ddrphy_bitslip260[4]),
-	.D6(main_k7ddrphy_bitslip260[5]),
-	.D7(main_k7ddrphy_bitslip260[6]),
-	.D8(main_k7ddrphy_bitslip260[7]),
+	.D1(k7ddrphy_bitslip260[0]),
+	.D2(k7ddrphy_bitslip260[1]),
+	.D3(k7ddrphy_bitslip260[2]),
+	.D4(k7ddrphy_bitslip260[3]),
+	.D5(k7ddrphy_bitslip260[4]),
+	.D6(k7ddrphy_bitslip260[5]),
+	.D7(k7ddrphy_bitslip260[6]),
+	.D8(k7ddrphy_bitslip260[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay26),
-	.TQ(main_k7ddrphy_dq_t26)
+	.OQ(k7ddrphy_dq_o_nodelay26),
+	.TQ(k7ddrphy_dq_t26)
 );
 
 ISERDESE2 #(
@@ -19447,16 +19890,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed26),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip261[7]),
-	.Q2(main_k7ddrphy_bitslip261[6]),
-	.Q3(main_k7ddrphy_bitslip261[5]),
-	.Q4(main_k7ddrphy_bitslip261[4]),
-	.Q5(main_k7ddrphy_bitslip261[3]),
-	.Q6(main_k7ddrphy_bitslip261[2]),
-	.Q7(main_k7ddrphy_bitslip261[1]),
-	.Q8(main_k7ddrphy_bitslip261[0])
+	.DDLY(k7ddrphy_dq_i_delayed26),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip261[7]),
+	.Q2(k7ddrphy_bitslip261[6]),
+	.Q3(k7ddrphy_bitslip261[5]),
+	.Q4(k7ddrphy_bitslip261[4]),
+	.Q5(k7ddrphy_bitslip261[3]),
+	.Q6(k7ddrphy_bitslip261[2]),
+	.Q7(k7ddrphy_bitslip261[1]),
+	.Q8(k7ddrphy_bitslip261[0])
 );
 
 ODELAYE2 #(
@@ -19470,12 +19913,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_60 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed26),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay26)
+	.DATAOUT(k7ddrphy_dq_o_delayed26),
+	.ODATAIN(k7ddrphy_dq_o_nodelay26)
 );
 
 IDELAYE2 #(
@@ -19489,19 +19932,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_26 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay26),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay26),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed26)
+	.DATAOUT(k7ddrphy_dq_i_delayed26)
 );
 
 IOBUF IOBUF_26(
-	.I(main_k7ddrphy_dq_o_delayed26),
-	.T(main_k7ddrphy_dq_t26),
+	.I(k7ddrphy_dq_o_delayed26),
+	.T(k7ddrphy_dq_t26),
 	.IO(ddram_dq[26]),
-	.O(main_k7ddrphy_dq_i_nodelay26)
+	.O(k7ddrphy_dq_i_nodelay26)
 );
 
 OSERDESE2 #(
@@ -19513,20 +19956,20 @@ OSERDESE2 #(
 ) OSERDESE2_61 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip270[0]),
-	.D2(main_k7ddrphy_bitslip270[1]),
-	.D3(main_k7ddrphy_bitslip270[2]),
-	.D4(main_k7ddrphy_bitslip270[3]),
-	.D5(main_k7ddrphy_bitslip270[4]),
-	.D6(main_k7ddrphy_bitslip270[5]),
-	.D7(main_k7ddrphy_bitslip270[6]),
-	.D8(main_k7ddrphy_bitslip270[7]),
+	.D1(k7ddrphy_bitslip270[0]),
+	.D2(k7ddrphy_bitslip270[1]),
+	.D3(k7ddrphy_bitslip270[2]),
+	.D4(k7ddrphy_bitslip270[3]),
+	.D5(k7ddrphy_bitslip270[4]),
+	.D6(k7ddrphy_bitslip270[5]),
+	.D7(k7ddrphy_bitslip270[6]),
+	.D8(k7ddrphy_bitslip270[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay27),
-	.TQ(main_k7ddrphy_dq_t27)
+	.OQ(k7ddrphy_dq_o_nodelay27),
+	.TQ(k7ddrphy_dq_t27)
 );
 
 ISERDESE2 #(
@@ -19542,16 +19985,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed27),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip271[7]),
-	.Q2(main_k7ddrphy_bitslip271[6]),
-	.Q3(main_k7ddrphy_bitslip271[5]),
-	.Q4(main_k7ddrphy_bitslip271[4]),
-	.Q5(main_k7ddrphy_bitslip271[3]),
-	.Q6(main_k7ddrphy_bitslip271[2]),
-	.Q7(main_k7ddrphy_bitslip271[1]),
-	.Q8(main_k7ddrphy_bitslip271[0])
+	.DDLY(k7ddrphy_dq_i_delayed27),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip271[7]),
+	.Q2(k7ddrphy_bitslip271[6]),
+	.Q3(k7ddrphy_bitslip271[5]),
+	.Q4(k7ddrphy_bitslip271[4]),
+	.Q5(k7ddrphy_bitslip271[3]),
+	.Q6(k7ddrphy_bitslip271[2]),
+	.Q7(k7ddrphy_bitslip271[1]),
+	.Q8(k7ddrphy_bitslip271[0])
 );
 
 ODELAYE2 #(
@@ -19565,12 +20008,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_61 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed27),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay27)
+	.DATAOUT(k7ddrphy_dq_o_delayed27),
+	.ODATAIN(k7ddrphy_dq_o_nodelay27)
 );
 
 IDELAYE2 #(
@@ -19584,19 +20027,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_27 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay27),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay27),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed27)
+	.DATAOUT(k7ddrphy_dq_i_delayed27)
 );
 
 IOBUF IOBUF_27(
-	.I(main_k7ddrphy_dq_o_delayed27),
-	.T(main_k7ddrphy_dq_t27),
+	.I(k7ddrphy_dq_o_delayed27),
+	.T(k7ddrphy_dq_t27),
 	.IO(ddram_dq[27]),
-	.O(main_k7ddrphy_dq_i_nodelay27)
+	.O(k7ddrphy_dq_i_nodelay27)
 );
 
 OSERDESE2 #(
@@ -19608,20 +20051,20 @@ OSERDESE2 #(
 ) OSERDESE2_62 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip280[0]),
-	.D2(main_k7ddrphy_bitslip280[1]),
-	.D3(main_k7ddrphy_bitslip280[2]),
-	.D4(main_k7ddrphy_bitslip280[3]),
-	.D5(main_k7ddrphy_bitslip280[4]),
-	.D6(main_k7ddrphy_bitslip280[5]),
-	.D7(main_k7ddrphy_bitslip280[6]),
-	.D8(main_k7ddrphy_bitslip280[7]),
+	.D1(k7ddrphy_bitslip280[0]),
+	.D2(k7ddrphy_bitslip280[1]),
+	.D3(k7ddrphy_bitslip280[2]),
+	.D4(k7ddrphy_bitslip280[3]),
+	.D5(k7ddrphy_bitslip280[4]),
+	.D6(k7ddrphy_bitslip280[5]),
+	.D7(k7ddrphy_bitslip280[6]),
+	.D8(k7ddrphy_bitslip280[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay28),
-	.TQ(main_k7ddrphy_dq_t28)
+	.OQ(k7ddrphy_dq_o_nodelay28),
+	.TQ(k7ddrphy_dq_t28)
 );
 
 ISERDESE2 #(
@@ -19637,16 +20080,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed28),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip281[7]),
-	.Q2(main_k7ddrphy_bitslip281[6]),
-	.Q3(main_k7ddrphy_bitslip281[5]),
-	.Q4(main_k7ddrphy_bitslip281[4]),
-	.Q5(main_k7ddrphy_bitslip281[3]),
-	.Q6(main_k7ddrphy_bitslip281[2]),
-	.Q7(main_k7ddrphy_bitslip281[1]),
-	.Q8(main_k7ddrphy_bitslip281[0])
+	.DDLY(k7ddrphy_dq_i_delayed28),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip281[7]),
+	.Q2(k7ddrphy_bitslip281[6]),
+	.Q3(k7ddrphy_bitslip281[5]),
+	.Q4(k7ddrphy_bitslip281[4]),
+	.Q5(k7ddrphy_bitslip281[3]),
+	.Q6(k7ddrphy_bitslip281[2]),
+	.Q7(k7ddrphy_bitslip281[1]),
+	.Q8(k7ddrphy_bitslip281[0])
 );
 
 ODELAYE2 #(
@@ -19660,12 +20103,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_62 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed28),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay28)
+	.DATAOUT(k7ddrphy_dq_o_delayed28),
+	.ODATAIN(k7ddrphy_dq_o_nodelay28)
 );
 
 IDELAYE2 #(
@@ -19679,19 +20122,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_28 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay28),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay28),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed28)
+	.DATAOUT(k7ddrphy_dq_i_delayed28)
 );
 
 IOBUF IOBUF_28(
-	.I(main_k7ddrphy_dq_o_delayed28),
-	.T(main_k7ddrphy_dq_t28),
+	.I(k7ddrphy_dq_o_delayed28),
+	.T(k7ddrphy_dq_t28),
 	.IO(ddram_dq[28]),
-	.O(main_k7ddrphy_dq_i_nodelay28)
+	.O(k7ddrphy_dq_i_nodelay28)
 );
 
 OSERDESE2 #(
@@ -19703,20 +20146,20 @@ OSERDESE2 #(
 ) OSERDESE2_63 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip290[0]),
-	.D2(main_k7ddrphy_bitslip290[1]),
-	.D3(main_k7ddrphy_bitslip290[2]),
-	.D4(main_k7ddrphy_bitslip290[3]),
-	.D5(main_k7ddrphy_bitslip290[4]),
-	.D6(main_k7ddrphy_bitslip290[5]),
-	.D7(main_k7ddrphy_bitslip290[6]),
-	.D8(main_k7ddrphy_bitslip290[7]),
+	.D1(k7ddrphy_bitslip290[0]),
+	.D2(k7ddrphy_bitslip290[1]),
+	.D3(k7ddrphy_bitslip290[2]),
+	.D4(k7ddrphy_bitslip290[3]),
+	.D5(k7ddrphy_bitslip290[4]),
+	.D6(k7ddrphy_bitslip290[5]),
+	.D7(k7ddrphy_bitslip290[6]),
+	.D8(k7ddrphy_bitslip290[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay29),
-	.TQ(main_k7ddrphy_dq_t29)
+	.OQ(k7ddrphy_dq_o_nodelay29),
+	.TQ(k7ddrphy_dq_t29)
 );
 
 ISERDESE2 #(
@@ -19732,16 +20175,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed29),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip291[7]),
-	.Q2(main_k7ddrphy_bitslip291[6]),
-	.Q3(main_k7ddrphy_bitslip291[5]),
-	.Q4(main_k7ddrphy_bitslip291[4]),
-	.Q5(main_k7ddrphy_bitslip291[3]),
-	.Q6(main_k7ddrphy_bitslip291[2]),
-	.Q7(main_k7ddrphy_bitslip291[1]),
-	.Q8(main_k7ddrphy_bitslip291[0])
+	.DDLY(k7ddrphy_dq_i_delayed29),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip291[7]),
+	.Q2(k7ddrphy_bitslip291[6]),
+	.Q3(k7ddrphy_bitslip291[5]),
+	.Q4(k7ddrphy_bitslip291[4]),
+	.Q5(k7ddrphy_bitslip291[3]),
+	.Q6(k7ddrphy_bitslip291[2]),
+	.Q7(k7ddrphy_bitslip291[1]),
+	.Q8(k7ddrphy_bitslip291[0])
 );
 
 ODELAYE2 #(
@@ -19755,12 +20198,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_63 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed29),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay29)
+	.DATAOUT(k7ddrphy_dq_o_delayed29),
+	.ODATAIN(k7ddrphy_dq_o_nodelay29)
 );
 
 IDELAYE2 #(
@@ -19774,19 +20217,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_29 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay29),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay29),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed29)
+	.DATAOUT(k7ddrphy_dq_i_delayed29)
 );
 
 IOBUF IOBUF_29(
-	.I(main_k7ddrphy_dq_o_delayed29),
-	.T(main_k7ddrphy_dq_t29),
+	.I(k7ddrphy_dq_o_delayed29),
+	.T(k7ddrphy_dq_t29),
 	.IO(ddram_dq[29]),
-	.O(main_k7ddrphy_dq_i_nodelay29)
+	.O(k7ddrphy_dq_i_nodelay29)
 );
 
 OSERDESE2 #(
@@ -19798,20 +20241,20 @@ OSERDESE2 #(
 ) OSERDESE2_64 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip300[0]),
-	.D2(main_k7ddrphy_bitslip300[1]),
-	.D3(main_k7ddrphy_bitslip300[2]),
-	.D4(main_k7ddrphy_bitslip300[3]),
-	.D5(main_k7ddrphy_bitslip300[4]),
-	.D6(main_k7ddrphy_bitslip300[5]),
-	.D7(main_k7ddrphy_bitslip300[6]),
-	.D8(main_k7ddrphy_bitslip300[7]),
+	.D1(k7ddrphy_bitslip300[0]),
+	.D2(k7ddrphy_bitslip300[1]),
+	.D3(k7ddrphy_bitslip300[2]),
+	.D4(k7ddrphy_bitslip300[3]),
+	.D5(k7ddrphy_bitslip300[4]),
+	.D6(k7ddrphy_bitslip300[5]),
+	.D7(k7ddrphy_bitslip300[6]),
+	.D8(k7ddrphy_bitslip300[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay30),
-	.TQ(main_k7ddrphy_dq_t30)
+	.OQ(k7ddrphy_dq_o_nodelay30),
+	.TQ(k7ddrphy_dq_t30)
 );
 
 ISERDESE2 #(
@@ -19827,16 +20270,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed30),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip301[7]),
-	.Q2(main_k7ddrphy_bitslip301[6]),
-	.Q3(main_k7ddrphy_bitslip301[5]),
-	.Q4(main_k7ddrphy_bitslip301[4]),
-	.Q5(main_k7ddrphy_bitslip301[3]),
-	.Q6(main_k7ddrphy_bitslip301[2]),
-	.Q7(main_k7ddrphy_bitslip301[1]),
-	.Q8(main_k7ddrphy_bitslip301[0])
+	.DDLY(k7ddrphy_dq_i_delayed30),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip301[7]),
+	.Q2(k7ddrphy_bitslip301[6]),
+	.Q3(k7ddrphy_bitslip301[5]),
+	.Q4(k7ddrphy_bitslip301[4]),
+	.Q5(k7ddrphy_bitslip301[3]),
+	.Q6(k7ddrphy_bitslip301[2]),
+	.Q7(k7ddrphy_bitslip301[1]),
+	.Q8(k7ddrphy_bitslip301[0])
 );
 
 ODELAYE2 #(
@@ -19850,12 +20293,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_64 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed30),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay30)
+	.DATAOUT(k7ddrphy_dq_o_delayed30),
+	.ODATAIN(k7ddrphy_dq_o_nodelay30)
 );
 
 IDELAYE2 #(
@@ -19869,19 +20312,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_30 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay30),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay30),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed30)
+	.DATAOUT(k7ddrphy_dq_i_delayed30)
 );
 
 IOBUF IOBUF_30(
-	.I(main_k7ddrphy_dq_o_delayed30),
-	.T(main_k7ddrphy_dq_t30),
+	.I(k7ddrphy_dq_o_delayed30),
+	.T(k7ddrphy_dq_t30),
 	.IO(ddram_dq[30]),
-	.O(main_k7ddrphy_dq_i_nodelay30)
+	.O(k7ddrphy_dq_i_nodelay30)
 );
 
 OSERDESE2 #(
@@ -19893,20 +20336,20 @@ OSERDESE2 #(
 ) OSERDESE2_65 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_k7ddrphy_bitslip310[0]),
-	.D2(main_k7ddrphy_bitslip310[1]),
-	.D3(main_k7ddrphy_bitslip310[2]),
-	.D4(main_k7ddrphy_bitslip310[3]),
-	.D5(main_k7ddrphy_bitslip310[4]),
-	.D6(main_k7ddrphy_bitslip310[5]),
-	.D7(main_k7ddrphy_bitslip310[6]),
-	.D8(main_k7ddrphy_bitslip310[7]),
+	.D1(k7ddrphy_bitslip310[0]),
+	.D2(k7ddrphy_bitslip310[1]),
+	.D3(k7ddrphy_bitslip310[2]),
+	.D4(k7ddrphy_bitslip310[3]),
+	.D5(k7ddrphy_bitslip310[4]),
+	.D6(k7ddrphy_bitslip310[5]),
+	.D7(k7ddrphy_bitslip310[6]),
+	.D8(k7ddrphy_bitslip310[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.T1((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_k7ddrphy_dq_o_nodelay31),
-	.TQ(main_k7ddrphy_dq_t31)
+	.OQ(k7ddrphy_dq_o_nodelay31),
+	.TQ(k7ddrphy_dq_t31)
 );
 
 ISERDESE2 #(
@@ -19922,16 +20365,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_k7ddrphy_dq_i_delayed31),
-	.RST((sys_rst | main_k7ddrphy_rst_storage)),
-	.Q1(main_k7ddrphy_bitslip311[7]),
-	.Q2(main_k7ddrphy_bitslip311[6]),
-	.Q3(main_k7ddrphy_bitslip311[5]),
-	.Q4(main_k7ddrphy_bitslip311[4]),
-	.Q5(main_k7ddrphy_bitslip311[3]),
-	.Q6(main_k7ddrphy_bitslip311[2]),
-	.Q7(main_k7ddrphy_bitslip311[1]),
-	.Q8(main_k7ddrphy_bitslip311[0])
+	.DDLY(k7ddrphy_dq_i_delayed31),
+	.RST((sys_rst | k7ddrphy_rst_storage)),
+	.Q1(k7ddrphy_bitslip311[7]),
+	.Q2(k7ddrphy_bitslip311[6]),
+	.Q3(k7ddrphy_bitslip311[5]),
+	.Q4(k7ddrphy_bitslip311[4]),
+	.Q5(k7ddrphy_bitslip311[3]),
+	.Q6(k7ddrphy_bitslip311[2]),
+	.Q7(k7ddrphy_bitslip311[1]),
+	.Q8(k7ddrphy_bitslip311[0])
 );
 
 ODELAYE2 #(
@@ -19945,12 +20388,12 @@ ODELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) ODELAYE2_65 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_o_delayed31),
-	.ODATAIN(main_k7ddrphy_dq_o_nodelay31)
+	.DATAOUT(k7ddrphy_dq_o_delayed31),
+	.ODATAIN(k7ddrphy_dq_o_nodelay31)
 );
 
 IDELAYE2 #(
@@ -19964,19 +20407,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_31 (
 	.C(sys_clk),
-	.CE((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_k7ddrphy_dq_i_nodelay31),
+	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(k7ddrphy_dq_i_nodelay31),
 	.INC(1'd1),
-	.LD(((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_k7ddrphy_dq_i_delayed31)
+	.DATAOUT(k7ddrphy_dq_i_delayed31)
 );
 
 IOBUF IOBUF_31(
-	.I(main_k7ddrphy_dq_o_delayed31),
-	.T(main_k7ddrphy_dq_t31),
+	.I(k7ddrphy_dq_o_delayed31),
+	.T(k7ddrphy_dq_t31),
 	.IO(ddram_dq[31]),
-	.O(main_k7ddrphy_dq_i_nodelay31)
+	.O(k7ddrphy_dq_i_nodelay31)
 );
 
 //------------------------------------------------------------------------------
@@ -19987,14 +20430,14 @@ IOBUF IOBUF_31(
 reg [24:0] storage[0:15];
 reg [24:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
-		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+		storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+	storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20005,14 +20448,14 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_1[0:15];
 reg [24:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
-		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+		storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20023,14 +20466,14 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_2[0:15];
 reg [24:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
-		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+		storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20041,14 +20484,14 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_3[0:15];
 reg [24:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
-		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+		storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20059,14 +20502,14 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_4[0:15];
 reg [24:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
-		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+		storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20077,14 +20520,14 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_5[0:15];
 reg [24:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
-		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+		storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20095,14 +20538,14 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_6[0:15];
 reg [24:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
-		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+		storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20113,62 +20556,78 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_7[0:15];
 reg [24:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
-		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+		storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
 
-FD FD(
-	.C(main_clkin),
-	.D(main_reset),
-	.Q(builder_reset0)
+FDCE FDCE(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(reset),
+	.Q(litedramcore_reset0)
 );
 
-FD FD_1(
-	.C(main_clkin),
-	.D(builder_reset0),
-	.Q(builder_reset1)
+FDCE FDCE_1(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset0),
+	.Q(litedramcore_reset1)
 );
 
-FD FD_2(
-	.C(main_clkin),
-	.D(builder_reset1),
-	.Q(builder_reset2)
+FDCE FDCE_2(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset1),
+	.Q(litedramcore_reset2)
 );
 
-FD FD_3(
-	.C(main_clkin),
-	.D(builder_reset2),
-	.Q(builder_reset3)
+FDCE FDCE_3(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset2),
+	.Q(litedramcore_reset3)
 );
 
-FD FD_4(
-	.C(main_clkin),
-	.D(builder_reset3),
-	.Q(builder_reset4)
+FDCE FDCE_4(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset3),
+	.Q(litedramcore_reset4)
 );
 
-FD FD_5(
-	.C(main_clkin),
-	.D(builder_reset4),
-	.Q(builder_reset5)
+FDCE FDCE_5(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset4),
+	.Q(litedramcore_reset5)
 );
 
-FD FD_6(
-	.C(main_clkin),
-	.D(builder_reset5),
-	.Q(builder_reset6)
+FDCE FDCE_6(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset5),
+	.Q(litedramcore_reset6)
 );
 
-FD FD_7(
-	.C(main_clkin),
-	.D(builder_reset6),
-	.Q(builder_reset7)
+FDCE FDCE_7(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset6),
+	.Q(litedramcore_reset7)
 );
 
 PLLE2_ADV #(
@@ -20186,16 +20645,16 @@ PLLE2_ADV #(
 	.REF_JITTER1(0.01),
 	.STARTUP_WAIT("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(builder_pll_fb),
-	.CLKIN1(main_clkin),
-	.PWRDWN(main_power_down),
-	.RST(builder_reset7),
-	.CLKFBOUT(builder_pll_fb),
-	.CLKOUT0(main_clkout0),
-	.CLKOUT1(main_clkout1),
-	.CLKOUT2(main_clkout2),
-	.CLKOUT3(main_clkout3),
-	.LOCKED(main_locked)
+	.CLKFBIN(litedramcore_pll_fb),
+	.CLKIN1(clkin),
+	.PWRDWN(power_down),
+	.RST(litedramcore_reset7),
+	.CLKFBOUT(litedramcore_pll_fb),
+	.CLKOUT0(clkout0),
+	.CLKOUT1(clkout1),
+	.CLKOUT2(clkout2),
+	.CLKOUT3(clkout3),
+	.LOCKED(locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -20204,8 +20663,8 @@ PLLE2_ADV #(
 	.C(iodelay_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
-	.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl0),
+	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -20213,8 +20672,8 @@ PLLE2_ADV #(
 ) FDPE_1 (
 	.C(iodelay_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
+	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl0),
 	.Q(iodelay_rst)
 );
 
@@ -20224,8 +20683,8 @@ PLLE2_ADV #(
 	.C(sys_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
-	.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl1),
+	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -20233,8 +20692,8 @@ PLLE2_ADV #(
 ) FDPE_3 (
 	.C(sys_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
+	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl1),
 	.Q(sys_rst)
 );
 
@@ -20244,8 +20703,8 @@ PLLE2_ADV #(
 	.C(sys4x_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -20253,9 +20712,9 @@ PLLE2_ADV #(
 ) FDPE_5 (
 	.C(sys4x_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_expr)
+	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -20264,8 +20723,8 @@ PLLE2_ADV #(
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -20273,13 +20732,13 @@ PLLE2_ADV #(
 ) FDPE_7 (
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_expr)
+	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-01-14 08:32:12.
+//  Auto-Generated by LiteX on 2022-08-04 21:06:58.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init
index 1b6e88e..9006b18 100644
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10e0658cff00
+618c10d8658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
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diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index e3f6682..0453ea2 100644
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-01-14 08:32:10
+// LiteX sha1 : 6932fc51
+// Date       : 2022-08-04 21:06:57
 //------------------------------------------------------------------------------
 
 
@@ -69,4066 +69,4485 @@ module litedram_core (
 // Signals
 //------------------------------------------------------------------------------
 
-reg  main_rst = 1'd0;
+reg  rst_1 = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
 wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
-wire main_reset;
-reg  main_power_down = 1'd0;
-wire main_locked;
-wire main_clkin;
-wire main_clkout0;
-wire main_clkout_buf0;
-wire main_clkout1;
-wire main_clkout_buf1;
-wire main_clkout2;
-wire main_clkout_buf2;
-wire main_clkout3;
-wire main_clkout_buf3;
-reg  [3:0] main_reset_counter = 4'd15;
-reg  main_ic_reset = 1'd1;
-reg  main_a7ddrphy_rst_storage = 1'd0;
-reg  main_a7ddrphy_rst_re = 1'd0;
-reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg  main_a7ddrphy_wlevel_en_re = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
-wire main_a7ddrphy_wlevel_strobe_r;
-reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg  main_a7ddrphy_dly_sel_re = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_rst_r;
-reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_inc_r;
-reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg  main_a7ddrphy_rdphase_re = 1'd0;
-reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg  main_a7ddrphy_wrphase_re = 1'd0;
-wire [14:0] main_a7ddrphy_dfi_p0_address;
-wire [2:0] main_a7ddrphy_dfi_p0_bank;
-wire main_a7ddrphy_dfi_p0_cas_n;
-wire main_a7ddrphy_dfi_p0_cs_n;
-wire main_a7ddrphy_dfi_p0_ras_n;
-wire main_a7ddrphy_dfi_p0_we_n;
-wire main_a7ddrphy_dfi_p0_cke;
-wire main_a7ddrphy_dfi_p0_odt;
-wire main_a7ddrphy_dfi_p0_reset_n;
-wire main_a7ddrphy_dfi_p0_act_n;
-wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
-wire main_a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
-wire main_a7ddrphy_dfi_p0_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p0_rddata_valid;
-wire [14:0] main_a7ddrphy_dfi_p1_address;
-wire [2:0] main_a7ddrphy_dfi_p1_bank;
-wire main_a7ddrphy_dfi_p1_cas_n;
-wire main_a7ddrphy_dfi_p1_cs_n;
-wire main_a7ddrphy_dfi_p1_ras_n;
-wire main_a7ddrphy_dfi_p1_we_n;
-wire main_a7ddrphy_dfi_p1_cke;
-wire main_a7ddrphy_dfi_p1_odt;
-wire main_a7ddrphy_dfi_p1_reset_n;
-wire main_a7ddrphy_dfi_p1_act_n;
-wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
-wire main_a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
-wire main_a7ddrphy_dfi_p1_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p1_rddata_valid;
-wire [14:0] main_a7ddrphy_dfi_p2_address;
-wire [2:0] main_a7ddrphy_dfi_p2_bank;
-wire main_a7ddrphy_dfi_p2_cas_n;
-wire main_a7ddrphy_dfi_p2_cs_n;
-wire main_a7ddrphy_dfi_p2_ras_n;
-wire main_a7ddrphy_dfi_p2_we_n;
-wire main_a7ddrphy_dfi_p2_cke;
-wire main_a7ddrphy_dfi_p2_odt;
-wire main_a7ddrphy_dfi_p2_reset_n;
-wire main_a7ddrphy_dfi_p2_act_n;
-wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
-wire main_a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
-wire main_a7ddrphy_dfi_p2_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p2_rddata_valid;
-wire [14:0] main_a7ddrphy_dfi_p3_address;
-wire [2:0] main_a7ddrphy_dfi_p3_bank;
-wire main_a7ddrphy_dfi_p3_cas_n;
-wire main_a7ddrphy_dfi_p3_cs_n;
-wire main_a7ddrphy_dfi_p3_ras_n;
-wire main_a7ddrphy_dfi_p3_we_n;
-wire main_a7ddrphy_dfi_p3_cke;
-wire main_a7ddrphy_dfi_p3_odt;
-wire main_a7ddrphy_dfi_p3_reset_n;
-wire main_a7ddrphy_dfi_p3_act_n;
-wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
-wire main_a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
-wire main_a7ddrphy_dfi_p3_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p3_rddata_valid;
-wire main_a7ddrphy_sd_clk_se_nodelay;
-reg  main_a7ddrphy_dqs_oe = 1'd0;
-wire main_a7ddrphy_dqs_preamble;
-wire main_a7ddrphy_dqs_postamble;
-wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_dqspattern0 = 1'd0;
-reg  main_a7ddrphy_dqspattern1 = 1'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
-wire main_a7ddrphy_dqs_o_no_delay0;
-wire main_a7ddrphy_dqs_t0;
-reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
-wire main_a7ddrphy0;
-wire main_a7ddrphy_dqs_o_no_delay1;
-wire main_a7ddrphy_dqs_t1;
-reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
-wire main_a7ddrphy1;
-reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
-wire main_a7ddrphy_dq_oe;
-wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire main_a7ddrphy_dq_o_nodelay0;
-wire main_a7ddrphy_dq_i_nodelay0;
-wire main_a7ddrphy_dq_i_delayed0;
-wire main_a7ddrphy_dq_t0;
-reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip03;
-reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay1;
-wire main_a7ddrphy_dq_i_nodelay1;
-wire main_a7ddrphy_dq_i_delayed1;
-wire main_a7ddrphy_dq_t1;
-reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip13;
-reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay2;
-wire main_a7ddrphy_dq_i_nodelay2;
-wire main_a7ddrphy_dq_i_delayed2;
-wire main_a7ddrphy_dq_t2;
-reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip21;
-reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay3;
-wire main_a7ddrphy_dq_i_nodelay3;
-wire main_a7ddrphy_dq_i_delayed3;
-wire main_a7ddrphy_dq_t3;
-reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip31;
-reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay4;
-wire main_a7ddrphy_dq_i_nodelay4;
-wire main_a7ddrphy_dq_i_delayed4;
-wire main_a7ddrphy_dq_t4;
-reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip41;
-reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay5;
-wire main_a7ddrphy_dq_i_nodelay5;
-wire main_a7ddrphy_dq_i_delayed5;
-wire main_a7ddrphy_dq_t5;
-reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip51;
-reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay6;
-wire main_a7ddrphy_dq_i_nodelay6;
-wire main_a7ddrphy_dq_i_delayed6;
-wire main_a7ddrphy_dq_t6;
-reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip61;
-reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay7;
-wire main_a7ddrphy_dq_i_nodelay7;
-wire main_a7ddrphy_dq_i_delayed7;
-wire main_a7ddrphy_dq_t7;
-reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip71;
-reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay8;
-wire main_a7ddrphy_dq_i_nodelay8;
-wire main_a7ddrphy_dq_i_delayed8;
-wire main_a7ddrphy_dq_t8;
-reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip81;
-reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay9;
-wire main_a7ddrphy_dq_i_nodelay9;
-wire main_a7ddrphy_dq_i_delayed9;
-wire main_a7ddrphy_dq_t9;
-reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip91;
-reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay10;
-wire main_a7ddrphy_dq_i_nodelay10;
-wire main_a7ddrphy_dq_i_delayed10;
-wire main_a7ddrphy_dq_t10;
-reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip101;
-reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay11;
-wire main_a7ddrphy_dq_i_nodelay11;
-wire main_a7ddrphy_dq_i_delayed11;
-wire main_a7ddrphy_dq_t11;
-reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip111;
-reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay12;
-wire main_a7ddrphy_dq_i_nodelay12;
-wire main_a7ddrphy_dq_i_delayed12;
-wire main_a7ddrphy_dq_t12;
-reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip121;
-reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay13;
-wire main_a7ddrphy_dq_i_nodelay13;
-wire main_a7ddrphy_dq_i_delayed13;
-wire main_a7ddrphy_dq_t13;
-reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip131;
-reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay14;
-wire main_a7ddrphy_dq_i_nodelay14;
-wire main_a7ddrphy_dq_i_delayed14;
-wire main_a7ddrphy_dq_t14;
-reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip141;
-reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay15;
-wire main_a7ddrphy_dq_i_nodelay15;
-wire main_a7ddrphy_dq_i_delayed15;
-wire main_a7ddrphy_dq_t15;
-reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip151;
-reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [14:0] main_litedramcore_inti_p0_address;
-wire [2:0] main_litedramcore_inti_p0_bank;
-reg  main_litedramcore_inti_p0_cas_n = 1'd1;
-reg  main_litedramcore_inti_p0_cs_n = 1'd1;
-reg  main_litedramcore_inti_p0_ras_n = 1'd1;
-reg  main_litedramcore_inti_p0_we_n = 1'd1;
-wire main_litedramcore_inti_p0_cke;
-wire main_litedramcore_inti_p0_odt;
-wire main_litedramcore_inti_p0_reset_n;
-reg  main_litedramcore_inti_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p0_wrdata;
-wire main_litedramcore_inti_p0_wrdata_en;
-wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
-wire main_litedramcore_inti_p0_rddata_en;
-reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_inti_p1_address;
-wire [2:0] main_litedramcore_inti_p1_bank;
-reg  main_litedramcore_inti_p1_cas_n = 1'd1;
-reg  main_litedramcore_inti_p1_cs_n = 1'd1;
-reg  main_litedramcore_inti_p1_ras_n = 1'd1;
-reg  main_litedramcore_inti_p1_we_n = 1'd1;
-wire main_litedramcore_inti_p1_cke;
-wire main_litedramcore_inti_p1_odt;
-wire main_litedramcore_inti_p1_reset_n;
-reg  main_litedramcore_inti_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p1_wrdata;
-wire main_litedramcore_inti_p1_wrdata_en;
-wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
-wire main_litedramcore_inti_p1_rddata_en;
-reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_inti_p2_address;
-wire [2:0] main_litedramcore_inti_p2_bank;
-reg  main_litedramcore_inti_p2_cas_n = 1'd1;
-reg  main_litedramcore_inti_p2_cs_n = 1'd1;
-reg  main_litedramcore_inti_p2_ras_n = 1'd1;
-reg  main_litedramcore_inti_p2_we_n = 1'd1;
-wire main_litedramcore_inti_p2_cke;
-wire main_litedramcore_inti_p2_odt;
-wire main_litedramcore_inti_p2_reset_n;
-reg  main_litedramcore_inti_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p2_wrdata;
-wire main_litedramcore_inti_p2_wrdata_en;
-wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
-wire main_litedramcore_inti_p2_rddata_en;
-reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_inti_p3_address;
-wire [2:0] main_litedramcore_inti_p3_bank;
-reg  main_litedramcore_inti_p3_cas_n = 1'd1;
-reg  main_litedramcore_inti_p3_cs_n = 1'd1;
-reg  main_litedramcore_inti_p3_ras_n = 1'd1;
-reg  main_litedramcore_inti_p3_we_n = 1'd1;
-wire main_litedramcore_inti_p3_cke;
-wire main_litedramcore_inti_p3_odt;
-wire main_litedramcore_inti_p3_reset_n;
-reg  main_litedramcore_inti_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p3_wrdata;
-wire main_litedramcore_inti_p3_wrdata_en;
-wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
-wire main_litedramcore_inti_p3_rddata_en;
-reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p0_address;
-wire [2:0] main_litedramcore_slave_p0_bank;
-wire main_litedramcore_slave_p0_cas_n;
-wire main_litedramcore_slave_p0_cs_n;
-wire main_litedramcore_slave_p0_ras_n;
-wire main_litedramcore_slave_p0_we_n;
-wire main_litedramcore_slave_p0_cke;
-wire main_litedramcore_slave_p0_odt;
-wire main_litedramcore_slave_p0_reset_n;
-wire main_litedramcore_slave_p0_act_n;
-wire [31:0] main_litedramcore_slave_p0_wrdata;
-wire main_litedramcore_slave_p0_wrdata_en;
-wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
-wire main_litedramcore_slave_p0_rddata_en;
-reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p1_address;
-wire [2:0] main_litedramcore_slave_p1_bank;
-wire main_litedramcore_slave_p1_cas_n;
-wire main_litedramcore_slave_p1_cs_n;
-wire main_litedramcore_slave_p1_ras_n;
-wire main_litedramcore_slave_p1_we_n;
-wire main_litedramcore_slave_p1_cke;
-wire main_litedramcore_slave_p1_odt;
-wire main_litedramcore_slave_p1_reset_n;
-wire main_litedramcore_slave_p1_act_n;
-wire [31:0] main_litedramcore_slave_p1_wrdata;
-wire main_litedramcore_slave_p1_wrdata_en;
-wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
-wire main_litedramcore_slave_p1_rddata_en;
-reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p2_address;
-wire [2:0] main_litedramcore_slave_p2_bank;
-wire main_litedramcore_slave_p2_cas_n;
-wire main_litedramcore_slave_p2_cs_n;
-wire main_litedramcore_slave_p2_ras_n;
-wire main_litedramcore_slave_p2_we_n;
-wire main_litedramcore_slave_p2_cke;
-wire main_litedramcore_slave_p2_odt;
-wire main_litedramcore_slave_p2_reset_n;
-wire main_litedramcore_slave_p2_act_n;
-wire [31:0] main_litedramcore_slave_p2_wrdata;
-wire main_litedramcore_slave_p2_wrdata_en;
-wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
-wire main_litedramcore_slave_p2_rddata_en;
-reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [14:0] main_litedramcore_slave_p3_address;
-wire [2:0] main_litedramcore_slave_p3_bank;
-wire main_litedramcore_slave_p3_cas_n;
-wire main_litedramcore_slave_p3_cs_n;
-wire main_litedramcore_slave_p3_ras_n;
-wire main_litedramcore_slave_p3_we_n;
-wire main_litedramcore_slave_p3_cke;
-wire main_litedramcore_slave_p3_odt;
-wire main_litedramcore_slave_p3_reset_n;
-wire main_litedramcore_slave_p3_act_n;
-wire [31:0] main_litedramcore_slave_p3_wrdata;
-wire main_litedramcore_slave_p3_wrdata_en;
-wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
-wire main_litedramcore_slave_p3_rddata_en;
-reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg  [14:0] main_litedramcore_master_p0_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg  main_litedramcore_master_p0_cas_n = 1'd1;
-reg  main_litedramcore_master_p0_cs_n = 1'd1;
-reg  main_litedramcore_master_p0_ras_n = 1'd1;
-reg  main_litedramcore_master_p0_we_n = 1'd1;
-reg  main_litedramcore_master_p0_cke = 1'd0;
-reg  main_litedramcore_master_p0_odt = 1'd0;
-reg  main_litedramcore_master_p0_reset_n = 1'd0;
-reg  main_litedramcore_master_p0_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p0_rddata;
-wire main_litedramcore_master_p0_rddata_valid;
-reg  [14:0] main_litedramcore_master_p1_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg  main_litedramcore_master_p1_cas_n = 1'd1;
-reg  main_litedramcore_master_p1_cs_n = 1'd1;
-reg  main_litedramcore_master_p1_ras_n = 1'd1;
-reg  main_litedramcore_master_p1_we_n = 1'd1;
-reg  main_litedramcore_master_p1_cke = 1'd0;
-reg  main_litedramcore_master_p1_odt = 1'd0;
-reg  main_litedramcore_master_p1_reset_n = 1'd0;
-reg  main_litedramcore_master_p1_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p1_rddata;
-wire main_litedramcore_master_p1_rddata_valid;
-reg  [14:0] main_litedramcore_master_p2_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg  main_litedramcore_master_p2_cas_n = 1'd1;
-reg  main_litedramcore_master_p2_cs_n = 1'd1;
-reg  main_litedramcore_master_p2_ras_n = 1'd1;
-reg  main_litedramcore_master_p2_we_n = 1'd1;
-reg  main_litedramcore_master_p2_cke = 1'd0;
-reg  main_litedramcore_master_p2_odt = 1'd0;
-reg  main_litedramcore_master_p2_reset_n = 1'd0;
-reg  main_litedramcore_master_p2_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p2_rddata;
-wire main_litedramcore_master_p2_rddata_valid;
-reg  [14:0] main_litedramcore_master_p3_address = 15'd0;
-reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg  main_litedramcore_master_p3_cas_n = 1'd1;
-reg  main_litedramcore_master_p3_cs_n = 1'd1;
-reg  main_litedramcore_master_p3_ras_n = 1'd1;
-reg  main_litedramcore_master_p3_we_n = 1'd1;
-reg  main_litedramcore_master_p3_cke = 1'd0;
-reg  main_litedramcore_master_p3_odt = 1'd0;
-reg  main_litedramcore_master_p3_reset_n = 1'd0;
-reg  main_litedramcore_master_p3_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p3_rddata;
-wire main_litedramcore_master_p3_rddata_valid;
-wire main_litedramcore_sel;
-wire main_litedramcore_cke;
-wire main_litedramcore_odt;
-wire main_litedramcore_reset_n;
-reg  [3:0] main_litedramcore_storage = 4'd1;
-reg  main_litedramcore_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector0_command_issue_r;
-reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector0_rddata_we;
-reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector1_command_issue_r;
-reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector1_rddata_we;
-reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector2_command_issue_r;
-reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector2_rddata_we;
-reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector3_command_issue_r;
-reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg  [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
-reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector3_rddata_we;
-reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire main_litedramcore_interface_bank0_valid;
-wire main_litedramcore_interface_bank0_ready;
-wire main_litedramcore_interface_bank0_we;
-wire [21:0] main_litedramcore_interface_bank0_addr;
-wire main_litedramcore_interface_bank0_lock;
-wire main_litedramcore_interface_bank0_wdata_ready;
-wire main_litedramcore_interface_bank0_rdata_valid;
-wire main_litedramcore_interface_bank1_valid;
-wire main_litedramcore_interface_bank1_ready;
-wire main_litedramcore_interface_bank1_we;
-wire [21:0] main_litedramcore_interface_bank1_addr;
-wire main_litedramcore_interface_bank1_lock;
-wire main_litedramcore_interface_bank1_wdata_ready;
-wire main_litedramcore_interface_bank1_rdata_valid;
-wire main_litedramcore_interface_bank2_valid;
-wire main_litedramcore_interface_bank2_ready;
-wire main_litedramcore_interface_bank2_we;
-wire [21:0] main_litedramcore_interface_bank2_addr;
-wire main_litedramcore_interface_bank2_lock;
-wire main_litedramcore_interface_bank2_wdata_ready;
-wire main_litedramcore_interface_bank2_rdata_valid;
-wire main_litedramcore_interface_bank3_valid;
-wire main_litedramcore_interface_bank3_ready;
-wire main_litedramcore_interface_bank3_we;
-wire [21:0] main_litedramcore_interface_bank3_addr;
-wire main_litedramcore_interface_bank3_lock;
-wire main_litedramcore_interface_bank3_wdata_ready;
-wire main_litedramcore_interface_bank3_rdata_valid;
-wire main_litedramcore_interface_bank4_valid;
-wire main_litedramcore_interface_bank4_ready;
-wire main_litedramcore_interface_bank4_we;
-wire [21:0] main_litedramcore_interface_bank4_addr;
-wire main_litedramcore_interface_bank4_lock;
-wire main_litedramcore_interface_bank4_wdata_ready;
-wire main_litedramcore_interface_bank4_rdata_valid;
-wire main_litedramcore_interface_bank5_valid;
-wire main_litedramcore_interface_bank5_ready;
-wire main_litedramcore_interface_bank5_we;
-wire [21:0] main_litedramcore_interface_bank5_addr;
-wire main_litedramcore_interface_bank5_lock;
-wire main_litedramcore_interface_bank5_wdata_ready;
-wire main_litedramcore_interface_bank5_rdata_valid;
-wire main_litedramcore_interface_bank6_valid;
-wire main_litedramcore_interface_bank6_ready;
-wire main_litedramcore_interface_bank6_we;
-wire [21:0] main_litedramcore_interface_bank6_addr;
-wire main_litedramcore_interface_bank6_lock;
-wire main_litedramcore_interface_bank6_wdata_ready;
-wire main_litedramcore_interface_bank6_rdata_valid;
-wire main_litedramcore_interface_bank7_valid;
-wire main_litedramcore_interface_bank7_ready;
-wire main_litedramcore_interface_bank7_we;
-wire [21:0] main_litedramcore_interface_bank7_addr;
-wire main_litedramcore_interface_bank7_lock;
-wire main_litedramcore_interface_bank7_wdata_ready;
-wire main_litedramcore_interface_bank7_rdata_valid;
-reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] main_litedramcore_interface_rdata;
-reg  [14:0] main_litedramcore_dfi_p0_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p0_we_n = 1'd1;
-wire main_litedramcore_dfi_p0_cke;
-wire main_litedramcore_dfi_p0_odt;
-wire main_litedramcore_dfi_p0_reset_n;
-reg  main_litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p0_rddata;
-wire main_litedramcore_dfi_p0_rddata_valid;
-reg  [14:0] main_litedramcore_dfi_p1_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p1_we_n = 1'd1;
-wire main_litedramcore_dfi_p1_cke;
-wire main_litedramcore_dfi_p1_odt;
-wire main_litedramcore_dfi_p1_reset_n;
-reg  main_litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p1_rddata;
-wire main_litedramcore_dfi_p1_rddata_valid;
-reg  [14:0] main_litedramcore_dfi_p2_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p2_we_n = 1'd1;
-wire main_litedramcore_dfi_p2_cke;
-wire main_litedramcore_dfi_p2_odt;
-wire main_litedramcore_dfi_p2_reset_n;
-reg  main_litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p2_rddata;
-wire main_litedramcore_dfi_p2_rddata_valid;
-reg  [14:0] main_litedramcore_dfi_p3_address = 15'd0;
-reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p3_we_n = 1'd1;
-wire main_litedramcore_dfi_p3_cke;
-wire main_litedramcore_dfi_p3_odt;
-wire main_litedramcore_dfi_p3_reset_n;
-reg  main_litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p3_rddata;
-wire main_litedramcore_dfi_p3_rddata_valid;
-reg  main_litedramcore_cmd_valid = 1'd0;
-reg  main_litedramcore_cmd_ready = 1'd0;
-reg  main_litedramcore_cmd_last = 1'd0;
-reg  [14:0] main_litedramcore_cmd_payload_a = 15'd0;
-reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg  main_litedramcore_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_cmd_payload_we = 1'd0;
-reg  main_litedramcore_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_cmd_payload_is_write = 1'd0;
-wire main_litedramcore_wants_refresh;
-wire main_litedramcore_wants_zqcs;
-wire main_litedramcore_timer_wait;
-wire main_litedramcore_timer_done0;
-wire [9:0] main_litedramcore_timer_count0;
-wire main_litedramcore_timer_done1;
-reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
-wire main_litedramcore_postponer_req_i;
-reg  main_litedramcore_postponer_req_o = 1'd0;
-reg  main_litedramcore_postponer_count = 1'd0;
-reg  main_litedramcore_sequencer_start0 = 1'd0;
-wire main_litedramcore_sequencer_done0;
-wire main_litedramcore_sequencer_start1;
-reg  main_litedramcore_sequencer_done1 = 1'd0;
-reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg  main_litedramcore_sequencer_count = 1'd0;
-wire main_litedramcore_zqcs_timer_wait;
-wire main_litedramcore_zqcs_timer_done0;
-wire [26:0] main_litedramcore_zqcs_timer_count0;
-wire main_litedramcore_zqcs_timer_done1;
-reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg  main_litedramcore_zqcs_executer_start = 1'd0;
-reg  main_litedramcore_zqcs_executer_done = 1'd0;
-reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
-wire main_litedramcore_bankmachine0_req_valid;
-wire main_litedramcore_bankmachine0_req_ready;
-wire main_litedramcore_bankmachine0_req_we;
-wire [21:0] main_litedramcore_bankmachine0_req_addr;
-wire main_litedramcore_bankmachine0_req_lock;
-reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine0_refresh_req;
-reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine0_row = 15'd0;
-reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
-wire main_litedramcore_bankmachine0_row_hit;
-reg  main_litedramcore_bankmachine0_row_open = 1'd0;
-reg  main_litedramcore_bankmachine0_row_close = 1'd0;
-reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine1_req_valid;
-wire main_litedramcore_bankmachine1_req_ready;
-wire main_litedramcore_bankmachine1_req_we;
-wire [21:0] main_litedramcore_bankmachine1_req_addr;
-wire main_litedramcore_bankmachine1_req_lock;
-reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine1_refresh_req;
-reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine1_row = 15'd0;
-reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
-wire main_litedramcore_bankmachine1_row_hit;
-reg  main_litedramcore_bankmachine1_row_open = 1'd0;
-reg  main_litedramcore_bankmachine1_row_close = 1'd0;
-reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine2_req_valid;
-wire main_litedramcore_bankmachine2_req_ready;
-wire main_litedramcore_bankmachine2_req_we;
-wire [21:0] main_litedramcore_bankmachine2_req_addr;
-wire main_litedramcore_bankmachine2_req_lock;
-reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine2_refresh_req;
-reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine2_row = 15'd0;
-reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
-wire main_litedramcore_bankmachine2_row_hit;
-reg  main_litedramcore_bankmachine2_row_open = 1'd0;
-reg  main_litedramcore_bankmachine2_row_close = 1'd0;
-reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine3_req_valid;
-wire main_litedramcore_bankmachine3_req_ready;
-wire main_litedramcore_bankmachine3_req_we;
-wire [21:0] main_litedramcore_bankmachine3_req_addr;
-wire main_litedramcore_bankmachine3_req_lock;
-reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine3_refresh_req;
-reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine3_row = 15'd0;
-reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
-wire main_litedramcore_bankmachine3_row_hit;
-reg  main_litedramcore_bankmachine3_row_open = 1'd0;
-reg  main_litedramcore_bankmachine3_row_close = 1'd0;
-reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine4_req_valid;
-wire main_litedramcore_bankmachine4_req_ready;
-wire main_litedramcore_bankmachine4_req_we;
-wire [21:0] main_litedramcore_bankmachine4_req_addr;
-wire main_litedramcore_bankmachine4_req_lock;
-reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine4_refresh_req;
-reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine4_row = 15'd0;
-reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
-wire main_litedramcore_bankmachine4_row_hit;
-reg  main_litedramcore_bankmachine4_row_open = 1'd0;
-reg  main_litedramcore_bankmachine4_row_close = 1'd0;
-reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine5_req_valid;
-wire main_litedramcore_bankmachine5_req_ready;
-wire main_litedramcore_bankmachine5_req_we;
-wire [21:0] main_litedramcore_bankmachine5_req_addr;
-wire main_litedramcore_bankmachine5_req_lock;
-reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine5_refresh_req;
-reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine5_row = 15'd0;
-reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
-wire main_litedramcore_bankmachine5_row_hit;
-reg  main_litedramcore_bankmachine5_row_open = 1'd0;
-reg  main_litedramcore_bankmachine5_row_close = 1'd0;
-reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine6_req_valid;
-wire main_litedramcore_bankmachine6_req_ready;
-wire main_litedramcore_bankmachine6_req_we;
-wire [21:0] main_litedramcore_bankmachine6_req_addr;
-wire main_litedramcore_bankmachine6_req_lock;
-reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine6_refresh_req;
-reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine6_row = 15'd0;
-reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
-wire main_litedramcore_bankmachine6_row_hit;
-reg  main_litedramcore_bankmachine6_row_open = 1'd0;
-reg  main_litedramcore_bankmachine6_row_close = 1'd0;
-reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine7_req_valid;
-wire main_litedramcore_bankmachine7_req_ready;
-wire main_litedramcore_bankmachine7_req_we;
-wire [21:0] main_litedramcore_bankmachine7_req_addr;
-wire main_litedramcore_bankmachine7_req_lock;
-reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine7_refresh_req;
-reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg  [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg  [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg  [14:0] main_litedramcore_bankmachine7_row = 15'd0;
-reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
-wire main_litedramcore_bankmachine7_row_hit;
-reg  main_litedramcore_bankmachine7_row_open = 1'd0;
-reg  main_litedramcore_bankmachine7_row_close = 1'd0;
-reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
-wire main_litedramcore_ras_allowed;
-wire main_litedramcore_cas_allowed;
-wire [1:0] main_litedramcore_rdcmdphase;
-wire [1:0] main_litedramcore_wrcmdphase;
-reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_valid;
-reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire main_litedramcore_choose_cmd_cmd_payload_is_read;
-wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_cmd_request;
-reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
-wire main_litedramcore_choose_cmd_ce;
-reg  main_litedramcore_choose_req_want_reads = 1'd0;
-reg  main_litedramcore_choose_req_want_writes = 1'd0;
-reg  main_litedramcore_choose_req_want_cmds = 1'd0;
-reg  main_litedramcore_choose_req_want_activates = 1'd0;
-wire main_litedramcore_choose_req_cmd_valid;
-reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
-wire [14:0] main_litedramcore_choose_req_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_req_cmd_payload_is_cmd;
-wire main_litedramcore_choose_req_cmd_payload_is_read;
-wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_req_request;
-reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
-wire main_litedramcore_choose_req_ce;
-reg  [14:0] main_litedramcore_nop_a = 15'd0;
-reg  [2:0] main_litedramcore_nop_ba = 3'd0;
-reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg  main_litedramcore_steerer0 = 1'd1;
-reg  main_litedramcore_steerer1 = 1'd1;
-reg  main_litedramcore_steerer2 = 1'd1;
-reg  main_litedramcore_steerer3 = 1'd1;
-reg  main_litedramcore_steerer4 = 1'd1;
-reg  main_litedramcore_steerer5 = 1'd1;
-reg  main_litedramcore_steerer6 = 1'd1;
-reg  main_litedramcore_steerer7 = 1'd1;
-wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
-reg  main_litedramcore_trrdcon_count = 1'd0;
-wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] main_litedramcore_tfawcon_count;
-reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
-wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
-reg  main_litedramcore_tccdcon_count = 1'd0;
-wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
-wire main_litedramcore_read_available;
-wire main_litedramcore_write_available;
-reg  main_litedramcore_en0 = 1'd0;
-wire main_litedramcore_max_time0;
-reg  [4:0] main_litedramcore_time0 = 5'd0;
-reg  main_litedramcore_en1 = 1'd0;
-wire main_litedramcore_max_time1;
-reg  [3:0] main_litedramcore_time1 = 4'd0;
-wire main_litedramcore_go_to_refresh;
-reg  main_init_done_storage = 1'd0;
-reg  main_init_done_re = 1'd0;
-reg  main_init_error_storage = 1'd0;
-reg  main_init_error_re = 1'd0;
-wire [29:0] main_wb_bus_adr;
-wire [31:0] main_wb_bus_dat_w;
-wire [31:0] main_wb_bus_dat_r;
-wire [3:0] main_wb_bus_sel;
-wire main_wb_bus_cyc;
-wire main_wb_bus_stb;
-wire main_wb_bus_ack;
-wire main_wb_bus_we;
-wire [2:0] main_wb_bus_cti;
-wire [1:0] main_wb_bus_bte;
-wire main_wb_bus_err;
-wire main_user_enable;
-wire main_user_port_cmd_valid;
-wire main_user_port_cmd_ready;
-wire main_user_port_cmd_payload_we;
-wire [24:0] main_user_port_cmd_payload_addr;
-wire main_user_port_wdata_valid;
-wire main_user_port_wdata_ready;
-wire [127:0] main_user_port_wdata_payload_data;
-wire [15:0] main_user_port_wdata_payload_we;
-wire main_user_port_rdata_valid;
-wire main_user_port_rdata_ready;
-wire [127:0] main_user_port_rdata_payload_data;
-wire builder_reset0;
-wire builder_reset1;
-wire builder_reset2;
-wire builder_reset3;
-wire builder_reset4;
-wire builder_reset5;
-wire builder_reset6;
-wire builder_reset7;
-wire builder_pll_fb;
-reg  [1:0] builder_refresher_state = 2'd0;
-reg  [1:0] builder_refresher_next_state = 2'd0;
-reg  [3:0] builder_bankmachine0_state = 4'd0;
-reg  [3:0] builder_bankmachine0_next_state = 4'd0;
-reg  [3:0] builder_bankmachine1_state = 4'd0;
-reg  [3:0] builder_bankmachine1_next_state = 4'd0;
-reg  [3:0] builder_bankmachine2_state = 4'd0;
-reg  [3:0] builder_bankmachine2_next_state = 4'd0;
-reg  [3:0] builder_bankmachine3_state = 4'd0;
-reg  [3:0] builder_bankmachine3_next_state = 4'd0;
-reg  [3:0] builder_bankmachine4_state = 4'd0;
-reg  [3:0] builder_bankmachine4_next_state = 4'd0;
-reg  [3:0] builder_bankmachine5_state = 4'd0;
-reg  [3:0] builder_bankmachine5_next_state = 4'd0;
-reg  [3:0] builder_bankmachine6_state = 4'd0;
-reg  [3:0] builder_bankmachine6_next_state = 4'd0;
-reg  [3:0] builder_bankmachine7_state = 4'd0;
-reg  [3:0] builder_bankmachine7_next_state = 4'd0;
-reg  [3:0] builder_multiplexer_state = 4'd0;
-reg  [3:0] builder_multiplexer_next_state = 4'd0;
-wire builder_roundrobin0_request;
-wire builder_roundrobin0_grant;
-wire builder_roundrobin0_ce;
-wire builder_roundrobin1_request;
-wire builder_roundrobin1_grant;
-wire builder_roundrobin1_ce;
-wire builder_roundrobin2_request;
-wire builder_roundrobin2_grant;
-wire builder_roundrobin2_ce;
-wire builder_roundrobin3_request;
-wire builder_roundrobin3_grant;
-wire builder_roundrobin3_ce;
-wire builder_roundrobin4_request;
-wire builder_roundrobin4_grant;
-wire builder_roundrobin4_ce;
-wire builder_roundrobin5_request;
-wire builder_roundrobin5_grant;
-wire builder_roundrobin5_ce;
-wire builder_roundrobin6_request;
-wire builder_roundrobin6_grant;
-wire builder_roundrobin6_ce;
-wire builder_roundrobin7_request;
-wire builder_roundrobin7_grant;
-wire builder_roundrobin7_ce;
-reg  builder_locked0 = 1'd0;
-reg  builder_locked1 = 1'd0;
-reg  builder_locked2 = 1'd0;
-reg  builder_locked3 = 1'd0;
-reg  builder_locked4 = 1'd0;
-reg  builder_locked5 = 1'd0;
-reg  builder_locked6 = 1'd0;
-reg  builder_locked7 = 1'd0;
-reg  builder_new_master_wdata_ready0 = 1'd0;
-reg  builder_new_master_wdata_ready1 = 1'd0;
-reg  builder_new_master_rdata_valid0 = 1'd0;
-reg  builder_new_master_rdata_valid1 = 1'd0;
-reg  builder_new_master_rdata_valid2 = 1'd0;
-reg  builder_new_master_rdata_valid3 = 1'd0;
-reg  builder_new_master_rdata_valid4 = 1'd0;
-reg  builder_new_master_rdata_valid5 = 1'd0;
-reg  builder_new_master_rdata_valid6 = 1'd0;
-reg  builder_new_master_rdata_valid7 = 1'd0;
-reg  builder_new_master_rdata_valid8 = 1'd0;
-reg  [13:0] builder_litedramcore_adr = 14'd0;
-reg  builder_litedramcore_we = 1'd0;
-reg  [31:0] builder_litedramcore_dat_w = 32'd0;
-wire [31:0] builder_litedramcore_dat_r;
-wire [29:0] builder_litedramcore_wishbone_adr;
-wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] builder_litedramcore_wishbone_sel;
-wire builder_litedramcore_wishbone_cyc;
-wire builder_litedramcore_wishbone_stb;
-reg  builder_litedramcore_wishbone_ack = 1'd0;
-wire builder_litedramcore_wishbone_we;
-wire [2:0] builder_litedramcore_wishbone_cti;
-wire [1:0] builder_litedramcore_wishbone_bte;
-reg  builder_litedramcore_wishbone_err = 1'd0;
-wire [13:0] builder_interface0_bank_bus_adr;
-wire builder_interface0_bank_bus_we;
-wire [31:0] builder_interface0_bank_bus_dat_w;
-reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank0_init_done0_re = 1'd0;
-wire builder_csrbank0_init_done0_r;
-reg  builder_csrbank0_init_done0_we = 1'd0;
-wire builder_csrbank0_init_done0_w;
-reg  builder_csrbank0_init_error0_re = 1'd0;
-wire builder_csrbank0_init_error0_r;
-reg  builder_csrbank0_init_error0_we = 1'd0;
-wire builder_csrbank0_init_error0_w;
-wire builder_csrbank0_sel;
-wire [13:0] builder_interface1_bank_bus_adr;
-wire builder_interface1_bank_bus_we;
-wire [31:0] builder_interface1_bank_bus_dat_w;
-reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank1_rst0_re = 1'd0;
-wire builder_csrbank1_rst0_r;
-reg  builder_csrbank1_rst0_we = 1'd0;
-wire builder_csrbank1_rst0_w;
-reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg  builder_csrbank1_wlevel_en0_re = 1'd0;
-wire builder_csrbank1_wlevel_en0_r;
-reg  builder_csrbank1_wlevel_en0_we = 1'd0;
-wire builder_csrbank1_wlevel_en0_w;
-reg  builder_csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_r;
-reg  builder_csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_w;
-reg  builder_csrbank1_rdphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_r;
-reg  builder_csrbank1_rdphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_w;
-reg  builder_csrbank1_wrphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_r;
-reg  builder_csrbank1_wrphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_w;
-wire builder_csrbank1_sel;
-wire [13:0] builder_interface2_bank_bus_adr;
-wire builder_interface2_bank_bus_we;
-wire [31:0] builder_interface2_bank_bus_dat_w;
-reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_r;
-reg  builder_csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_w;
-reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi0_address0_r;
-reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi0_address0_w;
-reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
-reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
-reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi1_address0_r;
-reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi1_address0_w;
-reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
-reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
-reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi2_address0_r;
-reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi2_address0_w;
-reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
-reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
-reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi3_address0_r;
-reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [14:0] builder_csrbank2_dfii_pi3_address0_w;
-reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
-reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
-wire builder_csrbank2_sel;
-wire [13:0] builder_csr_interconnect_adr;
-wire builder_csr_interconnect_we;
-wire [31:0] builder_csr_interconnect_dat_w;
-wire [31:0] builder_csr_interconnect_dat_r;
-reg  [1:0] builder_state = 2'd0;
-reg  [1:0] builder_next_state = 2'd0;
-reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
-reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg  builder_litedramcore_we_next_value2 = 1'd0;
-reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg  builder_rhs_array_muxed0 = 1'd0;
-reg  [14:0] builder_rhs_array_muxed1 = 15'd0;
-reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg  builder_rhs_array_muxed3 = 1'd0;
-reg  builder_rhs_array_muxed4 = 1'd0;
-reg  builder_rhs_array_muxed5 = 1'd0;
-reg  builder_t_array_muxed0 = 1'd0;
-reg  builder_t_array_muxed1 = 1'd0;
-reg  builder_t_array_muxed2 = 1'd0;
-reg  builder_rhs_array_muxed6 = 1'd0;
-reg  [14:0] builder_rhs_array_muxed7 = 15'd0;
-reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg  builder_rhs_array_muxed9 = 1'd0;
-reg  builder_rhs_array_muxed10 = 1'd0;
-reg  builder_rhs_array_muxed11 = 1'd0;
-reg  builder_t_array_muxed3 = 1'd0;
-reg  builder_t_array_muxed4 = 1'd0;
-reg  builder_t_array_muxed5 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed12 = 22'd0;
-reg  builder_rhs_array_muxed13 = 1'd0;
-reg  builder_rhs_array_muxed14 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed15 = 22'd0;
-reg  builder_rhs_array_muxed16 = 1'd0;
-reg  builder_rhs_array_muxed17 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed18 = 22'd0;
-reg  builder_rhs_array_muxed19 = 1'd0;
-reg  builder_rhs_array_muxed20 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed21 = 22'd0;
-reg  builder_rhs_array_muxed22 = 1'd0;
-reg  builder_rhs_array_muxed23 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed24 = 22'd0;
-reg  builder_rhs_array_muxed25 = 1'd0;
-reg  builder_rhs_array_muxed26 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed27 = 22'd0;
-reg  builder_rhs_array_muxed28 = 1'd0;
-reg  builder_rhs_array_muxed29 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed30 = 22'd0;
-reg  builder_rhs_array_muxed31 = 1'd0;
-reg  builder_rhs_array_muxed32 = 1'd0;
-reg  [21:0] builder_rhs_array_muxed33 = 22'd0;
-reg  builder_rhs_array_muxed34 = 1'd0;
-reg  builder_rhs_array_muxed35 = 1'd0;
-reg  [2:0] builder_array_muxed0 = 3'd0;
-reg  [14:0] builder_array_muxed1 = 15'd0;
-reg  builder_array_muxed2 = 1'd0;
-reg  builder_array_muxed3 = 1'd0;
-reg  builder_array_muxed4 = 1'd0;
-reg  builder_array_muxed5 = 1'd0;
-reg  builder_array_muxed6 = 1'd0;
-reg  [2:0] builder_array_muxed7 = 3'd0;
-reg  [14:0] builder_array_muxed8 = 15'd0;
-reg  builder_array_muxed9 = 1'd0;
-reg  builder_array_muxed10 = 1'd0;
-reg  builder_array_muxed11 = 1'd0;
-reg  builder_array_muxed12 = 1'd0;
-reg  builder_array_muxed13 = 1'd0;
-reg  [2:0] builder_array_muxed14 = 3'd0;
-reg  [14:0] builder_array_muxed15 = 15'd0;
-reg  builder_array_muxed16 = 1'd0;
-reg  builder_array_muxed17 = 1'd0;
-reg  builder_array_muxed18 = 1'd0;
-reg  builder_array_muxed19 = 1'd0;
-reg  builder_array_muxed20 = 1'd0;
-reg  [2:0] builder_array_muxed21 = 3'd0;
-reg  [14:0] builder_array_muxed22 = 15'd0;
-reg  builder_array_muxed23 = 1'd0;
-reg  builder_array_muxed24 = 1'd0;
-reg  builder_array_muxed25 = 1'd0;
-reg  builder_array_muxed26 = 1'd0;
-reg  builder_array_muxed27 = 1'd0;
-wire builder_xilinxasyncresetsynchronizerimpl0;
-wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl1;
-wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2;
-wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2_expr;
-wire builder_xilinxasyncresetsynchronizerimpl3;
-wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire reset;
+reg  power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg  [3:0] reset_counter = 4'd15;
+reg  ic_reset = 1'd1;
+reg  a7ddrphy_rst_storage = 1'd0;
+reg  a7ddrphy_rst_re = 1'd0;
+reg  [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg  a7ddrphy_dly_sel_re = 1'd0;
+reg  [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  a7ddrphy_wlevel_en_storage = 1'd0;
+reg  a7ddrphy_wlevel_en_re = 1'd0;
+reg  a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg  a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg  a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg  a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg  a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg  a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg  a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg  a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg  a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg  a7ddrphy_wrphase_re = 1'd0;
+wire [14:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [14:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [14:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [14:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg  a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_dqspattern0 = 1'd0;
+reg  a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg  [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg  [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg  [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg  [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg  [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg  [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg  [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg  [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg  [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg  [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg  [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg  [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg  [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg  [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg  [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg  [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg  [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg  [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg  [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg  [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg  [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg  [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg  [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg  [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg  [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg  [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg  [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg  [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg  [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg  [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg  [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg  [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg  [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg  [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg  [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [14:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg  [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg  litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg  [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg  litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg  [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg  litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg  [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg  litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_master_p0_address = 15'd0;
+reg  [2:0] litedramcore_master_p0_bank = 3'd0;
+reg  litedramcore_master_p0_cas_n = 1'd1;
+reg  litedramcore_master_p0_cs_n = 1'd1;
+reg  litedramcore_master_p0_ras_n = 1'd1;
+reg  litedramcore_master_p0_we_n = 1'd1;
+reg  litedramcore_master_p0_cke = 1'd0;
+reg  litedramcore_master_p0_odt = 1'd0;
+reg  litedramcore_master_p0_reset_n = 1'd0;
+reg  litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg  litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg  [14:0] litedramcore_master_p1_address = 15'd0;
+reg  [2:0] litedramcore_master_p1_bank = 3'd0;
+reg  litedramcore_master_p1_cas_n = 1'd1;
+reg  litedramcore_master_p1_cs_n = 1'd1;
+reg  litedramcore_master_p1_ras_n = 1'd1;
+reg  litedramcore_master_p1_we_n = 1'd1;
+reg  litedramcore_master_p1_cke = 1'd0;
+reg  litedramcore_master_p1_odt = 1'd0;
+reg  litedramcore_master_p1_reset_n = 1'd0;
+reg  litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg  litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg  [14:0] litedramcore_master_p2_address = 15'd0;
+reg  [2:0] litedramcore_master_p2_bank = 3'd0;
+reg  litedramcore_master_p2_cas_n = 1'd1;
+reg  litedramcore_master_p2_cs_n = 1'd1;
+reg  litedramcore_master_p2_ras_n = 1'd1;
+reg  litedramcore_master_p2_we_n = 1'd1;
+reg  litedramcore_master_p2_cke = 1'd0;
+reg  litedramcore_master_p2_odt = 1'd0;
+reg  litedramcore_master_p2_reset_n = 1'd0;
+reg  litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg  litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg  [14:0] litedramcore_master_p3_address = 15'd0;
+reg  [2:0] litedramcore_master_p3_bank = 3'd0;
+reg  litedramcore_master_p3_cas_n = 1'd1;
+reg  litedramcore_master_p3_cs_n = 1'd1;
+reg  litedramcore_master_p3_ras_n = 1'd1;
+reg  litedramcore_master_p3_we_n = 1'd1;
+reg  litedramcore_master_p3_cke = 1'd0;
+reg  litedramcore_master_p3_odt = 1'd0;
+reg  litedramcore_master_p3_reset_n = 1'd0;
+reg  litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg  litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [14:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg  litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg  litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg  litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg  litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg  litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg  litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg  litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg  litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg  litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cke = 1'd0;
+reg  litedramcore_ext_dfi_p0_odt = 1'd0;
+reg  litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg  litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cke = 1'd0;
+reg  litedramcore_ext_dfi_p1_odt = 1'd0;
+reg  litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg  litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cke = 1'd0;
+reg  litedramcore_ext_dfi_p2_odt = 1'd0;
+reg  litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg  litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cke = 1'd0;
+reg  litedramcore_ext_dfi_p3_odt = 1'd0;
+reg  litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg  litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg  [3:0] litedramcore_storage = 4'd1;
+reg  litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  litedramcore_phaseinjector0_command_re = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg  litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg  litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg  litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  litedramcore_phaseinjector1_command_re = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg  litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg  litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg  litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  litedramcore_phaseinjector2_command_re = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg  litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
+reg  litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg  litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  litedramcore_phaseinjector3_command_re = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg  litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
+reg  litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg  litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [21:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [21:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [21:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [21:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [21:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [21:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [21:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [21:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg  [127:0] litedramcore_interface_wdata = 128'd0;
+reg  [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg  [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg  litedramcore_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg  litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg  litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg  litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg  [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg  litedramcore_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg  litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg  litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg  litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg  [14:0] litedramcore_dfi_p2_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg  litedramcore_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg  litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg  litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg  litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg  [14:0] litedramcore_dfi_p3_address = 15'd0;
+reg  [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg  litedramcore_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg  litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg  litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg  litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg  litedramcore_cmd_valid = 1'd0;
+reg  litedramcore_cmd_ready = 1'd0;
+reg  litedramcore_cmd_last = 1'd0;
+reg  [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg  [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg  litedramcore_cmd_payload_cas = 1'd0;
+reg  litedramcore_cmd_payload_ras = 1'd0;
+reg  litedramcore_cmd_payload_we = 1'd0;
+reg  litedramcore_cmd_payload_is_read = 1'd0;
+reg  litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg  [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg  litedramcore_postponer_req_o = 1'd0;
+reg  litedramcore_postponer_count = 1'd0;
+reg  litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg  litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] litedramcore_sequencer_counter = 6'd0;
+reg  litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg  [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  litedramcore_zqcs_executer_start = 1'd0;
+reg  litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [21:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg  litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg  litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg  litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg  [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine0_row = 15'd0;
+reg  litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg  litedramcore_bankmachine0_row_open = 1'd0;
+reg  litedramcore_bankmachine0_row_close = 1'd0;
+reg  litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [21:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg  litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg  litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg  litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg  [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine1_row = 15'd0;
+reg  litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg  litedramcore_bankmachine1_row_open = 1'd0;
+reg  litedramcore_bankmachine1_row_close = 1'd0;
+reg  litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [21:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg  litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg  litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg  litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg  [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine2_row = 15'd0;
+reg  litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg  litedramcore_bankmachine2_row_open = 1'd0;
+reg  litedramcore_bankmachine2_row_close = 1'd0;
+reg  litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [21:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg  litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg  litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg  litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg  [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine3_row = 15'd0;
+reg  litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg  litedramcore_bankmachine3_row_open = 1'd0;
+reg  litedramcore_bankmachine3_row_close = 1'd0;
+reg  litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [21:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg  litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg  litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg  litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg  [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine4_row = 15'd0;
+reg  litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg  litedramcore_bankmachine4_row_open = 1'd0;
+reg  litedramcore_bankmachine4_row_close = 1'd0;
+reg  litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [21:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg  litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg  litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg  litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg  [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine5_row = 15'd0;
+reg  litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg  litedramcore_bankmachine5_row_open = 1'd0;
+reg  litedramcore_bankmachine5_row_close = 1'd0;
+reg  litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [21:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg  litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg  litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg  litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg  [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine6_row = 15'd0;
+reg  litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg  litedramcore_bankmachine6_row_open = 1'd0;
+reg  litedramcore_bankmachine6_row_close = 1'd0;
+reg  litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [21:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg  litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg  litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg  litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg  [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg  [14:0] litedramcore_bankmachine7_row = 15'd0;
+reg  litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg  litedramcore_bankmachine7_row_open = 1'd0;
+reg  litedramcore_bankmachine7_row_close = 1'd0;
+reg  litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg  litedramcore_choose_cmd_want_reads = 1'd0;
+reg  litedramcore_choose_cmd_want_writes = 1'd0;
+reg  litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg  litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg  litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg  [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg  litedramcore_choose_req_want_reads = 1'd0;
+reg  litedramcore_choose_req_want_writes = 1'd0;
+reg  litedramcore_choose_req_want_cmds = 1'd0;
+reg  litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg  litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg  litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg  [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg  [14:0] litedramcore_nop_a = 15'd0;
+reg  [2:0] litedramcore_nop_ba = 3'd0;
+reg  [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg  litedramcore_steerer0 = 1'd1;
+reg  litedramcore_steerer1 = 1'd1;
+reg  litedramcore_steerer2 = 1'd1;
+reg  litedramcore_steerer3 = 1'd1;
+reg  litedramcore_steerer4 = 1'd1;
+reg  litedramcore_steerer5 = 1'd1;
+reg  litedramcore_steerer6 = 1'd1;
+reg  litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_trrdcon_ready = 1'd0;
+reg  litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg  [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tccdcon_ready = 1'd0;
+reg  litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg  litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg  [4:0] litedramcore_time0 = 5'd0;
+reg  litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg  [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg  init_done_storage = 1'd0;
+reg  init_done_re = 1'd0;
+reg  init_error_storage = 1'd0;
+reg  init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [24:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg  [13:0] litedramcore_adr = 14'd0;
+reg  litedramcore_we = 1'd0;
+reg  [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg  [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg  litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg  litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg  [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg  csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg  csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg  csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg  csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg  [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg  csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg  csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg  csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg  csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg  csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg  csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg  csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg  csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg  csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg  csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg  csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg  csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg  [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg  csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg  csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg  csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg  csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg  csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_r;
+reg  csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_w;
+reg  csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg  csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg  csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg  csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg  csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg  csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg  csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg  csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg  csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_r;
+reg  csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_w;
+reg  csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg  csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg  csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg  csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg  csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg  csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg  csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg  csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg  csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_r;
+reg  csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_w;
+reg  csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg  csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg  csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg  csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg  csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg  csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg  csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg  csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg  csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_r;
+reg  csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_w;
+reg  csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg  csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg  csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg  csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg  csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg  csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg  [1:0] litedramcore_refresher_state = 2'd0;
+reg  [1:0] litedramcore_refresher_next_state = 2'd0;
+reg  [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg  litedramcore_locked0 = 1'd0;
+reg  litedramcore_locked1 = 1'd0;
+reg  litedramcore_locked2 = 1'd0;
+reg  litedramcore_locked3 = 1'd0;
+reg  litedramcore_locked4 = 1'd0;
+reg  litedramcore_locked5 = 1'd0;
+reg  litedramcore_locked6 = 1'd0;
+reg  litedramcore_locked7 = 1'd0;
+reg  litedramcore_new_master_wdata_ready0 = 1'd0;
+reg  litedramcore_new_master_wdata_ready1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid0 = 1'd0;
+reg  litedramcore_new_master_rdata_valid1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid2 = 1'd0;
+reg  litedramcore_new_master_rdata_valid3 = 1'd0;
+reg  litedramcore_new_master_rdata_valid4 = 1'd0;
+reg  litedramcore_new_master_rdata_valid5 = 1'd0;
+reg  litedramcore_new_master_rdata_valid6 = 1'd0;
+reg  litedramcore_new_master_rdata_valid7 = 1'd0;
+reg  litedramcore_new_master_rdata_valid8 = 1'd0;
+reg  [1:0] litedramcore_state = 2'd0;
+reg  [1:0] litedramcore_next_state = 2'd0;
+reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg  litedramcore_adr_next_value_ce1 = 1'd0;
+reg  litedramcore_we_next_value2 = 1'd0;
+reg  litedramcore_we_next_value_ce2 = 1'd0;
+reg  rhs_array_muxed0 = 1'd0;
+reg  [14:0] rhs_array_muxed1 = 15'd0;
+reg  [2:0] rhs_array_muxed2 = 3'd0;
+reg  rhs_array_muxed3 = 1'd0;
+reg  rhs_array_muxed4 = 1'd0;
+reg  rhs_array_muxed5 = 1'd0;
+reg  t_array_muxed0 = 1'd0;
+reg  t_array_muxed1 = 1'd0;
+reg  t_array_muxed2 = 1'd0;
+reg  rhs_array_muxed6 = 1'd0;
+reg  [14:0] rhs_array_muxed7 = 15'd0;
+reg  [2:0] rhs_array_muxed8 = 3'd0;
+reg  rhs_array_muxed9 = 1'd0;
+reg  rhs_array_muxed10 = 1'd0;
+reg  rhs_array_muxed11 = 1'd0;
+reg  t_array_muxed3 = 1'd0;
+reg  t_array_muxed4 = 1'd0;
+reg  t_array_muxed5 = 1'd0;
+reg  [21:0] rhs_array_muxed12 = 22'd0;
+reg  rhs_array_muxed13 = 1'd0;
+reg  rhs_array_muxed14 = 1'd0;
+reg  [21:0] rhs_array_muxed15 = 22'd0;
+reg  rhs_array_muxed16 = 1'd0;
+reg  rhs_array_muxed17 = 1'd0;
+reg  [21:0] rhs_array_muxed18 = 22'd0;
+reg  rhs_array_muxed19 = 1'd0;
+reg  rhs_array_muxed20 = 1'd0;
+reg  [21:0] rhs_array_muxed21 = 22'd0;
+reg  rhs_array_muxed22 = 1'd0;
+reg  rhs_array_muxed23 = 1'd0;
+reg  [21:0] rhs_array_muxed24 = 22'd0;
+reg  rhs_array_muxed25 = 1'd0;
+reg  rhs_array_muxed26 = 1'd0;
+reg  [21:0] rhs_array_muxed27 = 22'd0;
+reg  rhs_array_muxed28 = 1'd0;
+reg  rhs_array_muxed29 = 1'd0;
+reg  [21:0] rhs_array_muxed30 = 22'd0;
+reg  rhs_array_muxed31 = 1'd0;
+reg  rhs_array_muxed32 = 1'd0;
+reg  [21:0] rhs_array_muxed33 = 22'd0;
+reg  rhs_array_muxed34 = 1'd0;
+reg  rhs_array_muxed35 = 1'd0;
+reg  [2:0] array_muxed0 = 3'd0;
+reg  [14:0] array_muxed1 = 15'd0;
+reg  array_muxed2 = 1'd0;
+reg  array_muxed3 = 1'd0;
+reg  array_muxed4 = 1'd0;
+reg  array_muxed5 = 1'd0;
+reg  array_muxed6 = 1'd0;
+reg  [2:0] array_muxed7 = 3'd0;
+reg  [14:0] array_muxed8 = 15'd0;
+reg  array_muxed9 = 1'd0;
+reg  array_muxed10 = 1'd0;
+reg  array_muxed11 = 1'd0;
+reg  array_muxed12 = 1'd0;
+reg  array_muxed13 = 1'd0;
+reg  [2:0] array_muxed14 = 3'd0;
+reg  [14:0] array_muxed15 = 15'd0;
+reg  array_muxed16 = 1'd0;
+reg  array_muxed17 = 1'd0;
+reg  array_muxed18 = 1'd0;
+reg  array_muxed19 = 1'd0;
+reg  array_muxed20 = 1'd0;
+reg  [2:0] array_muxed21 = 3'd0;
+reg  [14:0] array_muxed22 = 15'd0;
+reg  array_muxed23 = 1'd0;
+reg  array_muxed24 = 1'd0;
+reg  array_muxed25 = 1'd0;
+reg  array_muxed26 = 1'd0;
+reg  array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = main_init_done_storage;
-assign init_error = main_init_error_storage;
-assign main_wb_bus_adr = wb_ctrl_adr;
-assign main_wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = main_wb_bus_dat_r;
-assign main_wb_bus_sel = wb_ctrl_sel;
-assign main_wb_bus_cyc = wb_ctrl_cyc;
-assign main_wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = main_wb_bus_ack;
-assign main_wb_bus_we = wb_ctrl_we;
-assign main_wb_bus_cti = wb_ctrl_cti;
-assign main_wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = main_wb_bus_err;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_enable = 1'd1;
-assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
-assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
-assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
-assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
-assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
-assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
-assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = (rst | main_rst);
-assign pll_locked = main_locked;
-assign main_clkin = clk;
-assign iodelay_clk = main_clkout_buf0;
-assign sys_clk = main_clkout_buf1;
-assign sys4x_clk = main_clkout_buf2;
-assign sys4x_dqs_clk = main_clkout_buf3;
-assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
-assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-always @(*) begin
-	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
-	main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
-	main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
-	main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
-	main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
-	main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
-	main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
-	main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
-	main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
-	main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
-	main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
-	main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
-	main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
-	main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
-	main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
-	main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
-	main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
-	main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
-	main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
-	main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
-	main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
-	main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
-	main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
-	main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
-	main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
-	main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
-	main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
-	main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
-	main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
-	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
-	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
-	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
-	main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
-	main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
-	main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
-	main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
-	main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
-	main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
-	main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
-	main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
-	main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
-	main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
-	main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
-	main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
-	main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
-	main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
-	main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
-	main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
-	main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
-	main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
-	main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
-	main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
-	main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
-	main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
-	main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
-	main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
-	main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
-	main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
-	main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
-	main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
-	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
-	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
-	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
-	main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
-	main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
-	main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
-	main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
-	main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
-	main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
-	main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
-	main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
-	main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
-	main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
-	main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
-	main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
-	main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
-	main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
-	main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
-	main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
-	main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
-	main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
-	main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
-	main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
-	main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
-	main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
-	main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
-	main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
-	main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
-	main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
-	main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
-	main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
-	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
-	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
-	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
-	main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
-	main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
-	main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
-	main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
-	main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
-	main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
-	main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
-	main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
-	main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
-	main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
-	main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
-	main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
-	main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
-	main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
-	main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
-	main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
-	main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
-	main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
-	main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
-	main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
-	main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
-	main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
-	main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
-	main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
-	main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
-	main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
-	main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
-	main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
-	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
-	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
-	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-end
-assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-	main_a7ddrphy_dqs_oe <= 1'd0;
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqs_oe <= 1'd1;
-	end else begin
-		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
-	end
-end
-assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-always @(*) begin
-	main_a7ddrphy_dqspattern_o0 <= 8'd0;
-	main_a7ddrphy_dqspattern_o0 <= 7'd85;
-	if (main_a7ddrphy_dqspattern0) begin
-		main_a7ddrphy_dqspattern_o0 <= 5'd21;
-	end
-	if (main_a7ddrphy_dqspattern1) begin
-		main_a7ddrphy_dqspattern_o0 <= 7'd84;
-	end
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqspattern_o0 <= 1'd0;
-		if (main_a7ddrphy_wlevel_strobe_re) begin
-			main_a7ddrphy_dqspattern_o0 <= 1'd1;
-		end
-	end
-end
-always @(*) begin
-	main_a7ddrphy_bitslip00 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value0)
+assign user_enable = 1'd1;
+assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
+assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
+assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
+assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign reset = (rst | rst_1);
+assign pll_locked = locked;
+assign clkin = clk;
+assign iodelay_clk = clkout_buf0;
+assign sys_clk = clkout_buf1;
+assign sys4x_clk = clkout_buf2;
+assign sys4x_dqs_clk = clkout_buf3;
+assign ddram_ba = a7ddrphy_pads_ba;
+assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
+assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
+always @(*) begin
+	a7ddrphy_dfi_p0_rddata <= 32'd0;
+	a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+	a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+	a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+	a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+	a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+	a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+	a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+	a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+	a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+	a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+	a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+	a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+	a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+	a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+	a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+	a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+	a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+	a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+	a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+	a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+	a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+	a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+	a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+	a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+	a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+	a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+	a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+	a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+	a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+	a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+	a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+	a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+	a7ddrphy_dfi_p1_rddata <= 32'd0;
+	a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+	a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+	a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+	a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+	a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+	a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+	a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+	a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+	a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+	a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+	a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+	a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+	a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+	a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+	a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+	a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+	a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+	a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+	a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+	a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+	a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+	a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+	a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+	a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+	a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+	a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+	a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+	a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+	a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+	a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+	a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+	a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+	a7ddrphy_dfi_p2_rddata <= 32'd0;
+	a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+	a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+	a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+	a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+	a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+	a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+	a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+	a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+	a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+	a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+	a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+	a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+	a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+	a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+	a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+	a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+	a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+	a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+	a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+	a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+	a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+	a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+	a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+	a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+	a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+	a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+	a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+	a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+	a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+	a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+	a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+	a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+	a7ddrphy_dfi_p3_rddata <= 32'd0;
+	a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+	a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+	a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+	a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+	a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+	a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+	a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+	a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+	a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+	a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+	a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+	a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+	a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+	a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+	a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+	a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+	a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+	a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+	a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+	a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+	a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+	a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+	a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+	a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+	a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+	a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+	a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+	a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+	a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+	a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+	a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+	a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+end
+assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+	a7ddrphy_dqs_oe <= 1'd0;
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqs_oe <= 1'd1;
+	end else begin
+		a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+	end
+end
+assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+always @(*) begin
+	a7ddrphy_dqspattern_o0 <= 8'd0;
+	a7ddrphy_dqspattern_o0 <= 7'd85;
+	if (a7ddrphy_dqspattern0) begin
+		a7ddrphy_dqspattern_o0 <= 5'd21;
+	end
+	if (a7ddrphy_dqspattern1) begin
+		a7ddrphy_dqspattern_o0 <= 7'd84;
+	end
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqspattern_o0 <= 1'd0;
+		if (a7ddrphy_wlevel_strobe_re) begin
+			a7ddrphy_dqspattern_o0 <= 1'd1;
+		end
+	end
+end
+always @(*) begin
+	a7ddrphy_bitslip00 <= 8'd0;
+	case (a7ddrphy_bitslip0_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip10 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value0)
+	a7ddrphy_bitslip10 <= 8'd0;
+	case (a7ddrphy_bitslip1_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip01 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value1)
+	a7ddrphy_bitslip01 <= 8'd0;
+	case (a7ddrphy_bitslip0_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip11 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value1)
+	a7ddrphy_bitslip11 <= 8'd0;
+	case (a7ddrphy_bitslip1_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip02 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value2)
+	a7ddrphy_bitslip02 <= 8'd0;
+	case (a7ddrphy_bitslip0_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip04 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value3)
+	a7ddrphy_bitslip04 <= 8'd0;
+	case (a7ddrphy_bitslip0_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip12 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value2)
+	a7ddrphy_bitslip12 <= 8'd0;
+	case (a7ddrphy_bitslip1_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip14 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value3)
+	a7ddrphy_bitslip14 <= 8'd0;
+	case (a7ddrphy_bitslip1_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip20 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value0)
+	a7ddrphy_bitslip20 <= 8'd0;
+	case (a7ddrphy_bitslip2_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip22 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value1)
+	a7ddrphy_bitslip22 <= 8'd0;
+	case (a7ddrphy_bitslip2_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip30 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value0)
+	a7ddrphy_bitslip30 <= 8'd0;
+	case (a7ddrphy_bitslip3_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip32 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value1)
+	a7ddrphy_bitslip32 <= 8'd0;
+	case (a7ddrphy_bitslip3_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip40 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value0)
+	a7ddrphy_bitslip40 <= 8'd0;
+	case (a7ddrphy_bitslip4_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip42 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value1)
+	a7ddrphy_bitslip42 <= 8'd0;
+	case (a7ddrphy_bitslip4_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip50 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value0)
+	a7ddrphy_bitslip50 <= 8'd0;
+	case (a7ddrphy_bitslip5_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip52 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value1)
+	a7ddrphy_bitslip52 <= 8'd0;
+	case (a7ddrphy_bitslip5_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip60 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value0)
+	a7ddrphy_bitslip60 <= 8'd0;
+	case (a7ddrphy_bitslip6_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip62 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value1)
+	a7ddrphy_bitslip62 <= 8'd0;
+	case (a7ddrphy_bitslip6_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip70 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value0)
+	a7ddrphy_bitslip70 <= 8'd0;
+	case (a7ddrphy_bitslip7_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip72 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value1)
+	a7ddrphy_bitslip72 <= 8'd0;
+	case (a7ddrphy_bitslip7_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip80 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value0)
+	a7ddrphy_bitslip80 <= 8'd0;
+	case (a7ddrphy_bitslip8_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip82 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value1)
+	a7ddrphy_bitslip82 <= 8'd0;
+	case (a7ddrphy_bitslip8_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip90 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value0)
+	a7ddrphy_bitslip90 <= 8'd0;
+	case (a7ddrphy_bitslip9_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip92 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value1)
+	a7ddrphy_bitslip92 <= 8'd0;
+	case (a7ddrphy_bitslip9_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip100 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value0)
+	a7ddrphy_bitslip100 <= 8'd0;
+	case (a7ddrphy_bitslip10_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip102 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value1)
+	a7ddrphy_bitslip102 <= 8'd0;
+	case (a7ddrphy_bitslip10_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip110 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value0)
+	a7ddrphy_bitslip110 <= 8'd0;
+	case (a7ddrphy_bitslip11_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip112 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value1)
+	a7ddrphy_bitslip112 <= 8'd0;
+	case (a7ddrphy_bitslip11_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip120 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value0)
+	a7ddrphy_bitslip120 <= 8'd0;
+	case (a7ddrphy_bitslip12_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip122 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value1)
+	a7ddrphy_bitslip122 <= 8'd0;
+	case (a7ddrphy_bitslip12_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip130 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value0)
+	a7ddrphy_bitslip130 <= 8'd0;
+	case (a7ddrphy_bitslip13_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip132 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value1)
+	a7ddrphy_bitslip132 <= 8'd0;
+	case (a7ddrphy_bitslip13_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip140 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value0)
+	a7ddrphy_bitslip140 <= 8'd0;
+	case (a7ddrphy_bitslip14_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip142 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value1)
+	a7ddrphy_bitslip142 <= 8'd0;
+	case (a7ddrphy_bitslip14_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip150 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value0)
+	a7ddrphy_bitslip150 <= 8'd0;
+	case (a7ddrphy_bitslip15_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip152 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value1)
+	a7ddrphy_bitslip152 <= 8'd0;
+	case (a7ddrphy_bitslip15_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
-		end
-		1'd1: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
-		end
-		2'd2: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
-		end
-		2'd3: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
-		end
-		3'd4: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
-		end
-		3'd5: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
-		end
-		3'd6: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
-		end
-		3'd7: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
-		end
-	endcase
-end
-assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
-assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
-assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
-assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
-assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
-assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
-assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
-assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
-assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
-assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
-assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
-assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
-assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
-assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
-assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
-assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
-assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
-assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
-assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
-assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
-assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
-assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
-assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
-assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
-assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
-assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
-assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
-assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
-assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
-assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
-assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
-assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
-assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
-assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
-assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
-assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
-assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
-assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
-assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
-assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
-assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
-assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
-assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
-assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
-assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
-assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
-assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
-assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
-assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
-assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
-assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
-assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
-assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
-assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
-assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
-assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
-assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
-assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
-assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
-assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
-assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
-assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
-assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
-assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
-assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
-assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
-assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
-assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
-assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
-assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
-assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
-assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
-assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
-assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
-assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
-assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
-assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
-assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
-assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
-assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
-assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
-assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
-assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
-assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
-assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
-assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
-assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
-assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
-assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
-assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
-assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
-assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
-assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
-assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
-assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
-assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
-assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
-assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
-assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
-assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
-assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
-assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
-assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
-assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
-assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
-assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
-assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
-assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
-assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
-assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
-assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
-assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
-assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
-assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
-assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
-assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
-assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
-assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
-assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
-assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
-assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
-assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
-assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
-assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
-assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
-assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
-assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
-assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+		end
+		1'd1: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+		end
+		2'd2: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+		end
+		2'd3: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+		end
+		3'd4: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+		end
+		3'd5: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+		end
+		3'd6: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+		end
+		3'd7: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+		end
+	endcase
+end
+assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
+assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
+assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
+assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+	litedramcore_csr_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+	end
+end
 always @(*) begin
-	main_litedramcore_master_p3_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+	litedramcore_csr_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
+		litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+	litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
+		litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+	litedramcore_csr_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
+		litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
+	litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
+		litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	litedramcore_ext_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+		end else begin
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
+	litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
+	litedramcore_ext_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
+	litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
+	litedramcore_ext_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
+	litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_slave_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
+	litedramcore_slave_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_ext_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
+	litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	litedramcore_slave_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
+	litedramcore_slave_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
+	litedramcore_slave_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
+	litedramcore_slave_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+	litedramcore_slave_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
+	litedramcore_slave_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
+	litedramcore_master_p0_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+		end else begin
+			litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+		end
 	end else begin
+		litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
+	litedramcore_master_p0_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+		end else begin
+			litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+		end
 	end else begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
+		litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	litedramcore_master_p0_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+		end else begin
+			litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+		end
 	end else begin
+		litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
+	litedramcore_master_p0_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+		end else begin
+			litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
+		litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
+	litedramcore_master_p0_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+		end else begin
+			litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
+		litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
+	litedramcore_master_p0_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+		end else begin
+			litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
+		litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
+	litedramcore_master_p0_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+		end else begin
+			litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+		end
 	end else begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
+		litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
+	litedramcore_master_p0_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+		end else begin
+			litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
+		litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p0_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+		end else begin
+			litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
+		litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
+	litedramcore_master_p0_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+		end else begin
+			litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
+		litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p0_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+		end else begin
+			litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+		litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
+	litedramcore_master_p0_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+		end else begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
+		litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
+	litedramcore_master_p0_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+		end else begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
+		litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
+	litedramcore_master_p0_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+		end else begin
+			litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
+		litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
+	litedramcore_master_p1_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+		end else begin
+			litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+		end
 	end else begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
+		litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
+	litedramcore_master_p1_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+		end else begin
+			litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+		end
 	end else begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
+		litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+	litedramcore_master_p1_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+		end else begin
+			litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
+		litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
+	litedramcore_master_p1_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+		end else begin
+			litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
+		litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
+	litedramcore_master_p1_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+		end else begin
+			litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+		end
 	end else begin
+		litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
+	litedramcore_master_p1_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+		end else begin
+			litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
+		litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	litedramcore_master_p1_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+		end else begin
+			litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+		end
 	end else begin
+		litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
+	litedramcore_master_p1_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+		end else begin
+			litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+		end
 	end else begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
+		litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
+	litedramcore_master_p1_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+		end else begin
+			litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
+		litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
+	litedramcore_master_p1_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+		end else begin
+			litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
+		litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
+	litedramcore_master_p1_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+		end else begin
+			litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
+		litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
+	litedramcore_master_p1_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+		end else begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
+		litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p1_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+		end else begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
+		litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
+	litedramcore_master_p1_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+		end else begin
+			litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
+		litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+		end else begin
+			litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+		litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
+	litedramcore_master_p2_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+		end else begin
+			litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
+		litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
+	litedramcore_master_p2_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+		end else begin
+			litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
+		litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
+	litedramcore_master_p2_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+		end else begin
+			litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
+		litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
+	litedramcore_master_p2_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+		end else begin
+			litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
+		litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
+	litedramcore_master_p2_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+		end else begin
+			litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
+		litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+	litedramcore_master_p2_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+		end else begin
+			litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+		end
 	end else begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
+		litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
+	litedramcore_master_p2_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+		end else begin
+			litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
+		litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
+	litedramcore_master_p2_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+		end else begin
+			litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+		end
 	end else begin
+		litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
+	litedramcore_master_p2_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+		end else begin
+			litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
+		litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	litedramcore_master_p2_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+		end else begin
+			litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+		end
 	end else begin
+		litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
+	litedramcore_master_p2_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+		end else begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
+		litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
+	litedramcore_master_p2_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+		end else begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
+		litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
+	litedramcore_master_p2_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+		end else begin
+			litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
+		litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
+	litedramcore_master_p3_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+		end else begin
+			litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+		end
 	end else begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
+		litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+	litedramcore_master_p3_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+		end else begin
+			litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+		end
+	end else begin
+		litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+	end
+end
+always @(*) begin
+	litedramcore_master_p3_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+		end else begin
+			litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+		end
+	end else begin
+		litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p3_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+		end else begin
+			litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+		end
+	end else begin
+		litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p3_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+		end else begin
+			litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+		litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p3_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+		end else begin
+			litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+	litedramcore_master_p3_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+		end else begin
+			litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+		litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p3_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+		end else begin
+			litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+		end
+	end else begin
+		litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+	end
+end
+always @(*) begin
+	litedramcore_master_p3_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+		end else begin
+			litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
+	litedramcore_master_p3_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+		end else begin
+			litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
+		litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
+	litedramcore_master_p3_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+		end else begin
+			litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+		litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_address <= 15'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+	litedramcore_master_p3_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+		end else begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+		litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
+	litedramcore_master_p3_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+		end else begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
+		litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
+	litedramcore_master_p3_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+		end else begin
+			litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
+		litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
 	end
 end
-assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p2_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p3_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p0_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p1_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p2_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p3_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+	litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+	litedramcore_csr_dfi_p0_we_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+	litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
 	end
 end
-assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
-assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
-assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]);
-assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
-assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
-assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
+assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
+assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+	litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+	litedramcore_csr_dfi_p1_we_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+	litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
 	end
 end
-assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
-assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
-assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]);
-assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
-assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
-assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
+assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
+assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+	litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p2_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	litedramcore_csr_dfi_p2_we_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p2_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		litedramcore_csr_dfi_p2_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+	litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
 	end
 end
-assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
-assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
-assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]);
-assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
-assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
-assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
+assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
+assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+	litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p3_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+	litedramcore_csr_dfi_p3_we_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p3_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		litedramcore_csr_dfi_p3_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+	litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
 	end
 end
-assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
-assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
-assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]);
-assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]);
-assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
-assign main_litedramcore_inti_p3_wrdata_mask = 1'd0;
-assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
-assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
-assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
-assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
-assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
-assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
-assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
-assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
-assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
-assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
-assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
-assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
-assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
-assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
-assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
-assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
-assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
-assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
-assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
-assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
-assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
-assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
-assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
-assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
-assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
-assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
-assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
-assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
-assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
-assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
-assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
-assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
-assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
-assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
-assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
-assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
-assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
-assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
-assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
-assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
-assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
-assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
-assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
-assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
-assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
-assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
-assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
-assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
-assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
-assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
-assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
-assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
-assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
-assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
-assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
-assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
-assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
-assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
-assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
-assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
-assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
-assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
-assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
-assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
-assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
-assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
-assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
-assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
-assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-always @(*) begin
-	builder_refresher_next_state <= 2'd0;
-	builder_refresher_next_state <= builder_refresher_state;
-	case (builder_refresher_state)
-		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				builder_refresher_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					builder_refresher_next_state <= 2'd3;
+assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
+assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
+assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+always @(*) begin
+	litedramcore_refresher_next_state <= 2'd0;
+	litedramcore_refresher_next_state <= litedramcore_refresher_state;
+	case (litedramcore_refresher_state)
+		1'd1: begin
+			if (litedramcore_cmd_ready) begin
+				litedramcore_refresher_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_refresher_next_state <= 2'd3;
 				end else begin
-					builder_refresher_next_state <= 1'd0;
+					litedramcore_refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				builder_refresher_next_state <= 1'd0;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
-				if (main_litedramcore_wants_refresh) begin
-					builder_refresher_next_state <= 1'd1;
+				if (litedramcore_wants_refresh) begin
+					litedramcore_refresher_next_state <= 1'd1;
 				end
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_sequencer_start0 <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
+			if (litedramcore_cmd_ready) begin
+				litedramcore_sequencer_start0 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4140,24 +4559,24 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_valid <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
+			litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
 				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
+					litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_valid <= 1'd0;
 			end
 		end
 		default: begin
@@ -4165,14 +4584,14 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_zqcs_executer_start <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
 				end
 			end
@@ -4184,148 +4603,148 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_last <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
+					litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_last <= 1'd1;
 			end
 		end
 		default: begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
-assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
-assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+	litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+		litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
 	end else begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
-assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
-assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+	litedramcore_bankmachine0_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+	litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine0_next_state <= 4'd0;
-	builder_bankmachine0_next_state <= builder_bankmachine0_state;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_next_state <= 4'd0;
+	litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd7;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine0_refresh_req)) begin
-				builder_bankmachine0_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine0_refresh_req)) begin
+				litedramcore_bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine0_next_state <= 3'd6;
+			litedramcore_bankmachine0_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine0_next_state <= 2'd3;
+			litedramcore_bankmachine0_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine0_next_state <= 4'd8;
+			litedramcore_bankmachine0_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine0_next_state <= 1'd0;
+			litedramcore_bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-				builder_bankmachine0_next_state <= 3'd4;
+			if (litedramcore_bankmachine0_refresh_req) begin
+				litedramcore_bankmachine0_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
-								builder_bankmachine0_next_state <= 2'd2;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+								litedramcore_bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine0_next_state <= 1'd1;
+							litedramcore_bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine0_next_state <= 2'd3;
+						litedramcore_bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4333,8 +4752,60 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_open <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_row_close <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd2: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4352,12 +4823,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4368,18 +4839,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4397,11 +4868,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4419,13 +4890,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4438,15 +4909,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4464,22 +4935,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4494,8 +4965,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4513,14 +4984,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -4532,8 +5003,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4551,13 +5022,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4570,8 +5041,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4589,13 +5060,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -4608,8 +5079,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4627,14 +5098,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+								litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -4646,8 +5117,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4655,8 +5126,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine0_twtpcon_ready) begin
+				litedramcore_bankmachine0_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -4672,18 +5143,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4697,12 +5168,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4712,45 +5183,146 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine0_row_open <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+		litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+always @(*) begin
+	litedramcore_bankmachine1_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine1_next_state <= 4'd0;
+	litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+	case (litedramcore_bankmachine1_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_open <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd7;
+				end
 			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine1_refresh_req)) begin
+				litedramcore_bankmachine1_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+				litedramcore_bankmachine1_next_state <= 3'd4;
+			end else begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+								litedramcore_bankmachine1_next_state <= 2'd2;
+							end
+						end else begin
+							litedramcore_bankmachine1_next_state <= 1'd1;
+						end
+					end else begin
+						litedramcore_bankmachine1_next_state <= 2'd3;
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_close <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_row_open <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4764,136 +5336,35 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
-assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
-assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
-assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine1_next_state <= 4'd0;
-	builder_bankmachine1_next_state <= builder_bankmachine1_state;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_close <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd5;
-				end
-			end
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				builder_bankmachine1_next_state <= 3'd5;
-			end
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine1_refresh_req)) begin
-				builder_bankmachine1_next_state <= 1'd0;
-			end
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
-			builder_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-				builder_bankmachine1_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
-								builder_bankmachine1_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine1_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine1_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4911,12 +5382,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4927,18 +5398,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4956,11 +5427,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4978,13 +5449,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4997,15 +5468,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5023,22 +5494,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5053,8 +5524,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5072,14 +5543,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5091,8 +5562,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5110,13 +5581,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5129,8 +5600,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5148,13 +5619,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5167,8 +5638,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5186,14 +5657,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+								litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -5205,8 +5676,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5214,8 +5685,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine1_twtpcon_ready) begin
+				litedramcore_bankmachine1_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -5231,18 +5702,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5256,12 +5727,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5271,45 +5742,146 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine1_row_open <= 1'd0;
-	case (builder_bankmachine1_state)
-		1'd1: begin
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+		litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+always @(*) begin
+	litedramcore_bankmachine2_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine2_next_state <= 4'd0;
+	litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd7;
+				end
 			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine2_refresh_req)) begin
+				litedramcore_bankmachine2_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+				litedramcore_bankmachine2_next_state <= 3'd4;
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+								litedramcore_bankmachine2_next_state <= 2'd2;
+							end
+						end else begin
+							litedramcore_bankmachine2_next_state <= 1'd1;
+						end
+					end else begin
+						litedramcore_bankmachine2_next_state <= 2'd3;
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_close <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_row_open <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5323,136 +5895,35 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
-assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
-assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine2_next_state <= 4'd0;
-	builder_bankmachine2_next_state <= builder_bankmachine2_state;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_close <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd5;
-				end
-			end
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				builder_bankmachine2_next_state <= 3'd5;
-			end
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine2_refresh_req)) begin
-				builder_bankmachine2_next_state <= 1'd0;
-			end
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
-			builder_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-				builder_bankmachine2_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
-								builder_bankmachine2_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine2_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine2_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5470,12 +5941,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5486,18 +5957,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5515,11 +5986,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5537,13 +6008,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5556,15 +6027,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5582,22 +6053,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5612,8 +6083,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5631,14 +6102,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5650,8 +6121,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5669,13 +6140,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5688,8 +6159,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5707,13 +6178,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5726,13 +6197,19 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -5745,15 +6222,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-							end
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5764,8 +6238,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5773,9 +6247,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5786,25 +6257,37 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (litedramcore_bankmachine2_twtpcon_ready) begin
+				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -5815,60 +6298,149 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+		litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+always @(*) begin
+	litedramcore_bankmachine3_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine2_row_open <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine3_next_state <= 4'd0;
+	litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_open <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd7;
+				end
 			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine3_refresh_req)) begin
+				litedramcore_bankmachine3_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+				litedramcore_bankmachine3_next_state <= 3'd4;
+			end else begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+								litedramcore_bankmachine3_next_state <= 2'd2;
+							end
+						end else begin
+							litedramcore_bankmachine3_next_state <= 1'd1;
+						end
+					end else begin
+						litedramcore_bankmachine3_next_state <= 2'd3;
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_close <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_row_open <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5882,136 +6454,35 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
-assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
-assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
-assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine3_next_state <= 4'd0;
-	builder_bankmachine3_next_state <= builder_bankmachine3_state;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_close <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd5;
-				end
-			end
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				builder_bankmachine3_next_state <= 3'd5;
-			end
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine3_refresh_req)) begin
-				builder_bankmachine3_next_state <= 1'd0;
-			end
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
-			builder_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-				builder_bankmachine3_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
-								builder_bankmachine3_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine3_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine3_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6029,12 +6500,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6045,18 +6516,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6074,11 +6545,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6096,13 +6567,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6115,15 +6586,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6141,22 +6612,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6171,8 +6642,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6190,14 +6661,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6209,8 +6680,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6228,13 +6699,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6247,8 +6718,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6266,13 +6737,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -6285,8 +6756,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6304,14 +6775,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+								litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -6323,8 +6794,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6332,8 +6803,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine3_twtpcon_ready) begin
+				litedramcore_bankmachine3_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -6349,18 +6820,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6374,12 +6845,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6389,45 +6860,146 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine3_row_open <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+		litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+always @(*) begin
+	litedramcore_bankmachine4_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine4_next_state <= 4'd0;
+	litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd7;
+				end
 			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine4_refresh_req)) begin
+				litedramcore_bankmachine4_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+				litedramcore_bankmachine4_next_state <= 3'd4;
+			end else begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+								litedramcore_bankmachine4_next_state <= 2'd2;
+							end
+						end else begin
+							litedramcore_bankmachine4_next_state <= 1'd1;
+						end
+					end else begin
+						litedramcore_bankmachine4_next_state <= 2'd3;
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_close <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_row_open <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6441,127 +7013,67 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
-assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
-assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
-assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
+	litedramcore_bankmachine4_row_close <= 1'd0;
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
-	end
+		2'd2: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine4_next_state <= 4'd0;
-	builder_bankmachine4_next_state <= builder_bankmachine4_state;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd5;
-				end
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				builder_bankmachine4_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd7;
-				end
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine4_refresh_req)) begin
-				builder_bankmachine4_next_state <= 1'd0;
-			end
 		end
 		3'd5: begin
-			builder_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-				builder_bankmachine4_next_state <= 3'd4;
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
-								builder_bankmachine4_next_state <= 2'd2;
-							end
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_valid <= 1'd1;
 						end else begin
-							builder_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6569,8 +7081,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6588,12 +7100,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6604,18 +7116,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6633,11 +7145,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6655,13 +7167,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6674,15 +7186,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6700,22 +7212,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6730,8 +7242,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6749,14 +7261,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6768,8 +7280,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6787,13 +7299,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6806,8 +7318,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6825,13 +7337,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -6844,8 +7356,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6863,14 +7375,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+								litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
 						end
@@ -6882,8 +7394,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6891,8 +7403,8 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			if (litedramcore_bankmachine4_twtpcon_ready) begin
+				litedramcore_bankmachine4_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
@@ -6907,41 +7419,127 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+		litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+	end else begin
+		litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+always @(*) begin
+	litedramcore_bankmachine5_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine5_next_state <= 4'd0;
+	litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd5;
+				end
 			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd7;
+				end
 			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine5_refresh_req)) begin
+				litedramcore_bankmachine5_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+				litedramcore_bankmachine5_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+								litedramcore_bankmachine5_next_state <= 2'd2;
+							end
 						end else begin
+							litedramcore_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6949,15 +7547,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine5_row_open <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6975,161 +7573,34 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
-		end
-		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
-assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
-assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
-	end else begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
-assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine5_next_state <= 4'd0;
-	builder_bankmachine5_next_state <= builder_bankmachine5_state;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_close <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd5;
-				end
-			end
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				builder_bankmachine5_next_state <= 3'd5;
-			end
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-				builder_bankmachine5_next_state <= 1'd0;
-			end
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
-			builder_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine5_next_state <= 4'd8;
-		end
-		4'd8: begin
-			builder_bankmachine5_next_state <= 1'd0;
-		end
-		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-				builder_bankmachine5_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-								builder_bankmachine5_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine5_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine5_next_state <= 2'd3;
-					end
-				end
-			end
+		end
+		4'd8: begin
+		end
+		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7147,12 +7618,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7163,18 +7634,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7192,11 +7663,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7214,13 +7685,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7233,15 +7704,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7259,22 +7730,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7289,13 +7760,19 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7308,15 +7785,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
-							end
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7327,8 +7801,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7346,14 +7820,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7365,8 +7839,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7384,13 +7858,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7403,8 +7877,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7422,14 +7896,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
 							end
 						end else begin
 						end
@@ -7441,45 +7915,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -7492,12 +7934,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -7508,44 +7953,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_open <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine5_row_close <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			if (litedramcore_bankmachine5_twtpcon_ready) begin
+				litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7559,127 +7978,127 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
-assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
-assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+	litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+		litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
 	end else begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
-assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
-assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
+	litedramcore_bankmachine6_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
 		end
 	end
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+	litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine6_next_state <= 4'd0;
-	builder_bankmachine6_next_state <= builder_bankmachine6_state;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_next_state <= 4'd0;
+	litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd5;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				builder_bankmachine6_next_state <= 3'd5;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd7;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine6_refresh_req)) begin
-				builder_bankmachine6_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine6_refresh_req)) begin
+				litedramcore_bankmachine6_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine6_next_state <= 3'd6;
+			litedramcore_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine6_next_state <= 2'd3;
+			litedramcore_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine6_next_state <= 4'd8;
+			litedramcore_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine6_next_state <= 1'd0;
+			litedramcore_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-				builder_bankmachine6_next_state <= 3'd4;
+			if (litedramcore_bankmachine6_refresh_req) begin
+				litedramcore_bankmachine6_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
-								builder_bankmachine6_next_state <= 2'd2;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+								litedramcore_bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine6_next_state <= 1'd1;
+							litedramcore_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine6_next_state <= 2'd3;
+						litedramcore_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7687,13 +8106,16 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_open <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7706,37 +8128,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_close <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-			end
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7751,12 +8158,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -7773,15 +8177,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7792,15 +8193,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7818,22 +8222,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7844,17 +8244,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7867,34 +8285,26 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7905,27 +8315,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7943,14 +8338,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7962,8 +8357,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7981,14 +8376,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
 							end
 						end else begin
 						end
@@ -8000,8 +8395,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8009,9 +8404,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8022,23 +8414,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -8051,12 +8452,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -8067,15 +8471,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8089,22 +8496,34 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			if (litedramcore_bankmachine6_twtpcon_ready) begin
+				litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -8118,127 +8537,127 @@ always @(*) begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
-assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
-assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
-	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+	litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+	if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+		litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
 	end else begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
-assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
-assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
-			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
+	litedramcore_bankmachine7_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
+			litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
 		end
 	end
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+	litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine7_next_state <= 4'd0;
-	builder_bankmachine7_next_state <= builder_bankmachine7_state;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_next_state <= 4'd0;
+	litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd5;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				builder_bankmachine7_next_state <= 3'd5;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd7;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine7_refresh_req)) begin
-				builder_bankmachine7_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine7_refresh_req)) begin
+				litedramcore_bankmachine7_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine7_next_state <= 3'd6;
+			litedramcore_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine7_next_state <= 2'd3;
+			litedramcore_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine7_next_state <= 4'd8;
+			litedramcore_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine7_next_state <= 1'd0;
+			litedramcore_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-				builder_bankmachine7_next_state <= 3'd4;
+			if (litedramcore_bankmachine7_refresh_req) begin
+				litedramcore_bankmachine7_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
-								builder_bankmachine7_next_state <= 2'd2;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+								litedramcore_bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine7_next_state <= 1'd1;
+							litedramcore_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine7_next_state <= 2'd3;
+						litedramcore_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8246,13 +8665,16 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_open <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8265,37 +8687,22 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_close <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-			end
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8310,12 +8717,9 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -8332,15 +8736,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8351,15 +8752,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8377,22 +8781,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8403,17 +8803,35 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8426,34 +8844,26 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8464,27 +8874,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8502,14 +8897,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8521,8 +8916,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8540,14 +8935,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -8559,8 +8954,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8568,9 +8963,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8581,23 +8973,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -8610,12 +9011,15 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -8626,18 +9030,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_open <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (litedramcore_bankmachine7_twtpcon_ready) begin
+				litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -8652,18 +9056,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_close <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8674,264 +9081,272 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
-assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
-assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
-assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
-assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
-assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
-assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
-assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
-assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
-assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
-assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
-assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
+assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
 always @(*) begin
-	main_litedramcore_choose_cmd_valids <= 8'd0;
-	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids <= 8'd0;
+	litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
 end
-assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
-assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
-assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
-assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
-assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
-assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
-assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
+	litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
+	litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
+	litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	litedramcore_bankmachine0_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	litedramcore_bankmachine1_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	litedramcore_bankmachine2_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	litedramcore_bankmachine3_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	litedramcore_bankmachine4_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	litedramcore_bankmachine5_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	litedramcore_bankmachine6_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	litedramcore_bankmachine7_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
 end
-assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-	main_litedramcore_choose_req_valids <= 8'd0;
-	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids <= 8'd0;
+	litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
 end
-assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
-assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
-assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
-assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
-assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
-assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
-assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
+	litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
+	litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
+	litedramcore_choose_req_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
 	end
 end
-assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
-assign main_litedramcore_dfi_p0_reset_n = 1'd1;
-assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}};
-assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}};
-assign main_litedramcore_dfi_p1_reset_n = 1'd1;
-assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}};
-assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}};
-assign main_litedramcore_dfi_p2_reset_n = 1'd1;
-assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}};
-assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}};
-assign main_litedramcore_dfi_p3_reset_n = 1'd1;
-assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
-assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
-assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
 always @(*) begin
-	builder_multiplexer_next_state <= 4'd0;
-	builder_multiplexer_next_state <= builder_multiplexer_state;
-	case (builder_multiplexer_state)
+	litedramcore_multiplexer_next_state <= 4'd0;
+	litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (main_litedramcore_read_available) begin
-				if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
-					builder_multiplexer_next_state <= 2'd3;
+			if (litedramcore_read_available) begin
+				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+					litedramcore_multiplexer_next_state <= 2'd3;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
-			if (main_litedramcore_cmd_last) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_cmd_last) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_twtrcon_ready) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_twtrcon_ready) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			builder_multiplexer_next_state <= 3'd5;
+			litedramcore_multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			builder_multiplexer_next_state <= 3'd6;
+			litedramcore_multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_multiplexer_next_state <= 3'd7;
+			litedramcore_multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			builder_multiplexer_next_state <= 4'd8;
+			litedramcore_multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_multiplexer_next_state <= 4'd9;
+			litedramcore_multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			builder_multiplexer_next_state <= 4'd10;
+			litedramcore_multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			builder_multiplexer_next_state <= 1'd1;
+			litedramcore_multiplexer_next_state <= 1'd1;
 		end
 		default: begin
-			if (main_litedramcore_write_available) begin
-				if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
-					builder_multiplexer_next_state <= 3'd4;
+			if (litedramcore_write_available) begin
+				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+					litedramcore_multiplexer_next_state <= 3'd4;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_writes <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -8952,19 +9367,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -8985,23 +9399,21 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel0 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en1 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
+			litedramcore_en1 <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -9020,23 +9432,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel0 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
+			litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -9055,22 +9467,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -9089,26 +9502,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel2 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel1 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
 			end
-			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
+			if ((litedramcore_wrcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9130,23 +9536,26 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
 			end
-			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
+			if ((litedramcore_rdcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel2 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9168,23 +9577,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_want_activates <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
 			end
 		end
 		2'd2: begin
@@ -9206,19 +9615,16 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en0 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9240,17 +9646,20 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			litedramcore_en0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel3 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9272,17 +9681,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -9303,15 +9719,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_reads <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9332,1987 +9750,2012 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 end
-assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
-assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12;
-assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13;
-assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14;
-assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
-assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15;
-assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16;
-assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17;
-assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
-assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18;
-assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19;
-assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20;
-assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
-assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21;
-assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22;
-assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23;
-assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
-assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24;
-assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25;
-assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26;
-assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
-assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27;
-assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28;
-assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29;
-assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
-assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30;
-assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31;
-assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32;
-assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
-assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33;
-assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34;
-assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
-assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
-assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
-assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
+assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
 always @(*) begin
-	main_litedramcore_interface_wdata <= 128'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata <= 128'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			litedramcore_interface_wdata <= user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 16'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata_we <= 16'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 end
-assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
-assign builder_roundrobin0_grant = 1'd0;
-assign builder_roundrobin1_grant = 1'd0;
-assign builder_roundrobin2_grant = 1'd0;
-assign builder_roundrobin3_grant = 1'd0;
-assign builder_roundrobin4_grant = 1'd0;
-assign builder_roundrobin5_grant = 1'd0;
-assign builder_roundrobin6_grant = 1'd0;
-assign builder_roundrobin7_grant = 1'd0;
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-	builder_next_state <= 2'd0;
-	builder_next_state <= builder_state;
-	case (builder_state)
+	litedramcore_next_state <= 2'd0;
+	litedramcore_next_state <= litedramcore_state;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_next_state <= 2'd2;
+			litedramcore_next_state <= 2'd2;
 		end
 		2'd2: begin
-			builder_next_state <= 1'd0;
+			litedramcore_next_state <= 1'd0;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_next_state <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value_ce2 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value_ce2 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_dat_r <= 32'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 32'd0;
-	case (builder_state)
+	litedramcore_adr_next_value1 <= 14'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
-	case (builder_state)
+	litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_dat_r <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value1 <= 14'd0;
-	case (builder_state)
+	litedramcore_we_next_value2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value1 <= 1'd0;
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
-	case (builder_state)
+	litedramcore_we_next_value_ce2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value2 <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_ack <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
-			end
 		end
 	endcase
 end
-assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
-assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
-assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r;
-assign builder_litedramcore_wishbone_sel = main_wb_bus_sel;
-assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc;
-assign builder_litedramcore_wishbone_stb = main_wb_bus_stb;
-assign main_wb_bus_ack = builder_litedramcore_wishbone_ack;
-assign builder_litedramcore_wishbone_we = main_wb_bus_we;
-assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
-assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
-assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
-assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_done0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_re <= interface0_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_done0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
 	end
 end
-assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_error0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_error0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
-assign builder_csrbank0_init_done0_w = main_init_done_storage;
-assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
-assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rst0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rst0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_dly_sel0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+	csrbank1_dly_sel0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+	csrbank1_half_sys8x_taps0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_half_sys8x_taps0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wlevel_en0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+	csrbank1_wlevel_en0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wlevel_strobe_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wlevel_strobe_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rdphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rdphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_wrphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wrphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
-assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
-assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
+assign csrbank1_rst0_w = a7ddrphy_rst_storage;
+assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
+assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
+assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
+assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
+assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_control0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_control0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_sel = main_litedramcore_storage[0];
-assign main_litedramcore_cke = main_litedramcore_storage[1];
-assign main_litedramcore_odt = main_litedramcore_storage[2];
-assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
-assign builder_csr_interconnect_adr = builder_litedramcore_adr;
-assign builder_csr_interconnect_we = builder_litedramcore_we;
-assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
-assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r;
-assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-always @(*) begin
-	builder_rhs_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+assign litedramcore_sel = litedramcore_storage[0];
+assign litedramcore_cke = litedramcore_storage[1];
+assign litedramcore_odt = litedramcore_storage[2];
+assign litedramcore_reset_n = litedramcore_storage[3];
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
+assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
+assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
+assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
+assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
+assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
+assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
+assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
+assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
+assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
+assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
+assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
+assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
+assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
+assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
+assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
+assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
+assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
+assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
+assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
+assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0];
+assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
+assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
+assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
+assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
+assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
+assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
+assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
+assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
+assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0];
+assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
+assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
+assign csr_interconnect_adr = litedramcore_adr;
+assign csr_interconnect_we = litedramcore_we;
+assign csr_interconnect_dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = csr_interconnect_dat_r;
+assign interface0_bank_bus_adr = csr_interconnect_adr;
+assign interface1_bank_bus_adr = csr_interconnect_adr;
+assign interface2_bank_bus_adr = csr_interconnect_adr;
+assign interface0_bank_bus_we = csr_interconnect_we;
+assign interface1_bank_bus_we = csr_interconnect_we;
+assign interface2_bank_bus_we = csr_interconnect_we;
+assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
+assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+always @(*) begin
+	rhs_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed1 <= 15'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed1 <= 15'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed2 <= 3'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed2 <= 3'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed1 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed1 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed2 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed2 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed6 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed6 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed7 <= 15'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed7 <= 15'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed8 <= 3'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed8 <= 3'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed9 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed9 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed10 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed10 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed11 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed11 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed12 <= 22'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed12 <= 22'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed13 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed13 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed13 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed14 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed14 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed15 <= 22'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed15 <= 22'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed16 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed16 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed16 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed17 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed17 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed18 <= 22'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed18 <= 22'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed19 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed19 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed19 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed20 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed20 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed21 <= 22'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed21 <= 22'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed22 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed22 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed22 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed23 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed23 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed24 <= 22'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed24 <= 22'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed25 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed25 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed25 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed26 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed26 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed27 <= 22'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed27 <= 22'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed28 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed28 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed28 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed29 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed29 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed30 <= 22'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed30 <= 22'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed31 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed31 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed31 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed32 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed32 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed33 <= 22'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed33 <= 22'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed34 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed34 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed34 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed35 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed35 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed0 <= 3'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed0 <= 3'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed0 <= main_litedramcore_nop_ba[2:0];
+			array_muxed0 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed1 <= 15'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed1 <= 15'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed1 <= main_litedramcore_nop_a;
+			array_muxed1 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
+			array_muxed1 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed2 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed2 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed2 <= 1'd0;
+			array_muxed2 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed3 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed3 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed3 <= 1'd0;
+			array_muxed3 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed4 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed4 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed4 <= 1'd0;
+			array_muxed4 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed5 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed5 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed5 <= 1'd0;
+			array_muxed5 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed6 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed6 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed6 <= 1'd0;
+			array_muxed6 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed7 <= 3'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed7 <= 3'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed7 <= main_litedramcore_nop_ba[2:0];
+			array_muxed7 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed8 <= 15'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed8 <= 15'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed8 <= main_litedramcore_nop_a;
+			array_muxed8 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
+			array_muxed8 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed9 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed9 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed9 <= 1'd0;
+			array_muxed9 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed10 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed10 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed10 <= 1'd0;
+			array_muxed10 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed11 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed11 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed11 <= 1'd0;
+			array_muxed11 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed12 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed12 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed12 <= 1'd0;
+			array_muxed12 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed13 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed13 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed13 <= 1'd0;
+			array_muxed13 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed14 <= 3'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed14 <= 3'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed14 <= main_litedramcore_nop_ba[2:0];
+			array_muxed14 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed15 <= 15'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed15 <= 15'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed15 <= main_litedramcore_nop_a;
+			array_muxed15 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
+			array_muxed15 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed16 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed16 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed16 <= 1'd0;
+			array_muxed16 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed17 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed17 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed17 <= 1'd0;
+			array_muxed17 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed18 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed18 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed18 <= 1'd0;
+			array_muxed18 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed19 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed19 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed19 <= 1'd0;
+			array_muxed19 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed20 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed20 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed20 <= 1'd0;
+			array_muxed20 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed21 <= 3'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed21 <= 3'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed21 <= main_litedramcore_nop_ba[2:0];
+			array_muxed21 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed22 <= 15'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed22 <= 15'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed22 <= main_litedramcore_nop_a;
+			array_muxed22 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
+			array_muxed22 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed23 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed23 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed23 <= 1'd0;
+			array_muxed23 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed24 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed24 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed24 <= 1'd0;
+			array_muxed24 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed25 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed25 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed25 <= 1'd0;
+			array_muxed25 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed26 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed26 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed26 <= 1'd0;
+			array_muxed26 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed27 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed27 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed27 <= 1'd0;
+			array_muxed27 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
+assign xilinxasyncresetsynchronizerimpl0 = (~locked);
+assign xilinxasyncresetsynchronizerimpl1 = (~locked);
+assign xilinxasyncresetsynchronizerimpl2 = (~locked);
+assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 
 
 //------------------------------------------------------------------------------
@@ -11320,1044 +11763,1044 @@ assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-	if ((main_reset_counter != 1'd0)) begin
-		main_reset_counter <= (main_reset_counter - 1'd1);
+	if ((reset_counter != 1'd0)) begin
+		reset_counter <= (reset_counter - 1'd1);
 	end else begin
-		main_ic_reset <= 1'd0;
+		ic_reset <= 1'd0;
 	end
 	if (iodelay_rst) begin
-		main_reset_counter <= 4'd15;
-		main_ic_reset <= 1'd1;
+		reset_counter <= 4'd15;
+		ic_reset <= 1'd1;
 	end
 end
 
 always @(posedge sys_clk) begin
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-	main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+	a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
+	a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
+	a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
+	a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
+	a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
+	a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
+	a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
+	a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
+	a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
+	a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
+	a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
+	a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
+	a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
+	a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
+	a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
+	a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
+	a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
+	a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
+	a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
+	a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
+	a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
+	a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
+	a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
+	a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
+	a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
+	a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
+	a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
+	a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
+	a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
+	a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
+	a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
+	a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
+	a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
+	a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
+	a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
+	a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
-	main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
-	main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
-	main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
-	main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
-	main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
-	main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
-	main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
-	main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
-	main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
-	main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
-	main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
-	if (main_litedramcore_inti_p0_rddata_valid) begin
-		main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata;
+	a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+	a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+	a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+	a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+	a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+	a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+	a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+	a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+	a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+	a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+	a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+	a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+	if (litedramcore_csr_dfi_p0_rddata_valid) begin
+		litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
 	end
-	if (main_litedramcore_inti_p1_rddata_valid) begin
-		main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata;
+	if (litedramcore_csr_dfi_p1_rddata_valid) begin
+		litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
 	end
-	if (main_litedramcore_inti_p2_rddata_valid) begin
-		main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata;
+	if (litedramcore_csr_dfi_p2_rddata_valid) begin
+		litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
 	end
-	if (main_litedramcore_inti_p3_rddata_valid) begin
-		main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata;
-	end
-	if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
-		main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
+	if (litedramcore_csr_dfi_p3_rddata_valid) begin
+		litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+	end
+	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_timer_count1 <= 10'd781;
+		litedramcore_timer_count1 <= 10'd781;
 	end
-	main_litedramcore_postponer_req_o <= 1'd0;
-	if (main_litedramcore_postponer_req_i) begin
-		main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
-		if ((main_litedramcore_postponer_count == 1'd0)) begin
-			main_litedramcore_postponer_count <= 1'd0;
-			main_litedramcore_postponer_req_o <= 1'd1;
-		end
+	litedramcore_postponer_req_o <= 1'd0;
+	if (litedramcore_postponer_req_i) begin
+		litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+		if ((litedramcore_postponer_count == 1'd0)) begin
+			litedramcore_postponer_count <= 1'd0;
+			litedramcore_postponer_req_o <= 1'd1;
+		end
 	end
-	if (main_litedramcore_sequencer_start0) begin
-		main_litedramcore_sequencer_count <= 1'd0;
-	end else begin
-		if (main_litedramcore_sequencer_done1) begin
-			if ((main_litedramcore_sequencer_count != 1'd0)) begin
-				main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
-			end
-		end
-	end
-	main_litedramcore_cmd_payload_a <= 1'd0;
-	main_litedramcore_cmd_payload_ba <= 1'd0;
-	main_litedramcore_cmd_payload_cas <= 1'd0;
-	main_litedramcore_cmd_payload_ras <= 1'd0;
-	main_litedramcore_cmd_payload_we <= 1'd0;
-	main_litedramcore_sequencer_done1 <= 1'd0;
-	if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd1;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd55)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd55)) begin
-		main_litedramcore_sequencer_counter <= 1'd0;
-	end else begin
-		if ((main_litedramcore_sequencer_counter != 1'd0)) begin
-			main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1);
+	if (litedramcore_sequencer_start0) begin
+		litedramcore_sequencer_count <= 1'd0;
+	end else begin
+		if (litedramcore_sequencer_done1) begin
+			if ((litedramcore_sequencer_count != 1'd0)) begin
+				litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+			end
+		end
+	end
+	litedramcore_cmd_payload_a <= 1'd0;
+	litedramcore_cmd_payload_ba <= 1'd0;
+	litedramcore_cmd_payload_cas <= 1'd0;
+	litedramcore_cmd_payload_ras <= 1'd0;
+	litedramcore_cmd_payload_we <= 1'd0;
+	litedramcore_sequencer_done1 <= 1'd0;
+	if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd1;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd0;
+	end
+	if ((litedramcore_sequencer_counter == 6'd55)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 6'd55)) begin
+		litedramcore_sequencer_counter <= 1'd0;
+	end else begin
+		if ((litedramcore_sequencer_counter != 1'd0)) begin
+			litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_sequencer_start1) begin
-				main_litedramcore_sequencer_counter <= 1'd1;
+			if (litedramcore_sequencer_start1) begin
+				litedramcore_sequencer_counter <= 1'd1;
 			end
 		end
 	end
-	if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
-		main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
+	if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+		litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
 	end
-	main_litedramcore_zqcs_executer_done <= 1'd0;
-	if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	litedramcore_zqcs_executer_done <= 1'd0;
+	if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_zqcs_executer_done <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_zqcs_executer_done <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_zqcs_executer_counter <= 1'd0;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_zqcs_executer_counter <= 1'd0;
 	end else begin
-		if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin
-			main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1);
+		if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+			litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_zqcs_executer_start) begin
-				main_litedramcore_zqcs_executer_counter <= 1'd1;
+			if (litedramcore_zqcs_executer_start) begin
+				litedramcore_zqcs_executer_counter <= 1'd1;
 			end
 		end
 	end
-	builder_refresher_state <= builder_refresher_next_state;
-	if (main_litedramcore_bankmachine0_row_close) begin
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
+	litedramcore_refresher_state <= litedramcore_refresher_next_state;
+	if (litedramcore_bankmachine0_row_close) begin
+		litedramcore_bankmachine0_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine0_row_open) begin
-			main_litedramcore_bankmachine0_row_opened <= 1'd1;
-			main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine0_row_open) begin
+			litedramcore_bankmachine0_row_opened <= 1'd1;
+			litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+		litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+		litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine0_twtpcon_valid) begin
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine0_twtpcon_valid) begin
+		litedramcore_bankmachine0_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
-			main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+			litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trccon_valid) begin
-		main_litedramcore_bankmachine0_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine0_trccon_valid) begin
+		litedramcore_bankmachine0_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+			litedramcore_bankmachine0_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+			litedramcore_bankmachine0_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
-			main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trccon_ready)) begin
+			litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trascon_valid) begin
-		main_litedramcore_bankmachine0_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine0_trascon_valid) begin
+		litedramcore_bankmachine0_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+			litedramcore_bankmachine0_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+			litedramcore_bankmachine0_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
-			main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trascon_ready)) begin
+			litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine0_state <= builder_bankmachine0_next_state;
-	if (main_litedramcore_bankmachine1_row_close) begin
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
+	litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+	if (litedramcore_bankmachine1_row_close) begin
+		litedramcore_bankmachine1_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine1_row_open) begin
-			main_litedramcore_bankmachine1_row_opened <= 1'd1;
-			main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine1_row_open) begin
+			litedramcore_bankmachine1_row_opened <= 1'd1;
+			litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+		litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+		litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine1_twtpcon_valid) begin
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine1_twtpcon_valid) begin
+		litedramcore_bankmachine1_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
-			main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+			litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trccon_valid) begin
-		main_litedramcore_bankmachine1_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine1_trccon_valid) begin
+		litedramcore_bankmachine1_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+			litedramcore_bankmachine1_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+			litedramcore_bankmachine1_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
-			main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trccon_ready)) begin
+			litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trascon_valid) begin
-		main_litedramcore_bankmachine1_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine1_trascon_valid) begin
+		litedramcore_bankmachine1_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+			litedramcore_bankmachine1_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+			litedramcore_bankmachine1_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
-			main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trascon_ready)) begin
+			litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine1_state <= builder_bankmachine1_next_state;
-	if (main_litedramcore_bankmachine2_row_close) begin
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
+	litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+	if (litedramcore_bankmachine2_row_close) begin
+		litedramcore_bankmachine2_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine2_row_open) begin
-			main_litedramcore_bankmachine2_row_opened <= 1'd1;
-			main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine2_row_open) begin
+			litedramcore_bankmachine2_row_opened <= 1'd1;
+			litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+		litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+		litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine2_twtpcon_valid) begin
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine2_twtpcon_valid) begin
+		litedramcore_bankmachine2_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
-			main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+			litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trccon_valid) begin
-		main_litedramcore_bankmachine2_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine2_trccon_valid) begin
+		litedramcore_bankmachine2_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+			litedramcore_bankmachine2_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+			litedramcore_bankmachine2_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
-			main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trccon_ready)) begin
+			litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trascon_valid) begin
-		main_litedramcore_bankmachine2_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine2_trascon_valid) begin
+		litedramcore_bankmachine2_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+			litedramcore_bankmachine2_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+			litedramcore_bankmachine2_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
-			main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trascon_ready)) begin
+			litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine2_state <= builder_bankmachine2_next_state;
-	if (main_litedramcore_bankmachine3_row_close) begin
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
+	litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+	if (litedramcore_bankmachine3_row_close) begin
+		litedramcore_bankmachine3_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine3_row_open) begin
-			main_litedramcore_bankmachine3_row_opened <= 1'd1;
-			main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine3_row_open) begin
+			litedramcore_bankmachine3_row_opened <= 1'd1;
+			litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+		litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+		litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine3_twtpcon_valid) begin
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine3_twtpcon_valid) begin
+		litedramcore_bankmachine3_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
-			main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+			litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trccon_valid) begin
-		main_litedramcore_bankmachine3_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine3_trccon_valid) begin
+		litedramcore_bankmachine3_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+			litedramcore_bankmachine3_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+			litedramcore_bankmachine3_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
-			main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trccon_ready)) begin
+			litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trascon_valid) begin
-		main_litedramcore_bankmachine3_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine3_trascon_valid) begin
+		litedramcore_bankmachine3_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+			litedramcore_bankmachine3_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+			litedramcore_bankmachine3_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
-			main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trascon_ready)) begin
+			litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine3_state <= builder_bankmachine3_next_state;
-	if (main_litedramcore_bankmachine4_row_close) begin
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
+	litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+	if (litedramcore_bankmachine4_row_close) begin
+		litedramcore_bankmachine4_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine4_row_open) begin
-			main_litedramcore_bankmachine4_row_opened <= 1'd1;
-			main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine4_row_open) begin
+			litedramcore_bankmachine4_row_opened <= 1'd1;
+			litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+		litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+		litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine4_twtpcon_valid) begin
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine4_twtpcon_valid) begin
+		litedramcore_bankmachine4_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
-			main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+			litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trccon_valid) begin
-		main_litedramcore_bankmachine4_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine4_trccon_valid) begin
+		litedramcore_bankmachine4_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+			litedramcore_bankmachine4_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+			litedramcore_bankmachine4_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
-			main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trccon_ready)) begin
+			litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trascon_valid) begin
-		main_litedramcore_bankmachine4_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine4_trascon_valid) begin
+		litedramcore_bankmachine4_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+			litedramcore_bankmachine4_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+			litedramcore_bankmachine4_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
-			main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trascon_ready)) begin
+			litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine4_state <= builder_bankmachine4_next_state;
-	if (main_litedramcore_bankmachine5_row_close) begin
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
+	litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+	if (litedramcore_bankmachine5_row_close) begin
+		litedramcore_bankmachine5_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine5_row_open) begin
-			main_litedramcore_bankmachine5_row_opened <= 1'd1;
-			main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine5_row_open) begin
+			litedramcore_bankmachine5_row_opened <= 1'd1;
+			litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+		litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+		litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine5_twtpcon_valid) begin
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine5_twtpcon_valid) begin
+		litedramcore_bankmachine5_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
-			main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+			litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trccon_valid) begin
-		main_litedramcore_bankmachine5_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine5_trccon_valid) begin
+		litedramcore_bankmachine5_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+			litedramcore_bankmachine5_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+			litedramcore_bankmachine5_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
-			main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trccon_ready)) begin
+			litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trascon_valid) begin
-		main_litedramcore_bankmachine5_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine5_trascon_valid) begin
+		litedramcore_bankmachine5_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+			litedramcore_bankmachine5_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+			litedramcore_bankmachine5_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
-			main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trascon_ready)) begin
+			litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine5_state <= builder_bankmachine5_next_state;
-	if (main_litedramcore_bankmachine6_row_close) begin
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
+	litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+	if (litedramcore_bankmachine6_row_close) begin
+		litedramcore_bankmachine6_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine6_row_open) begin
-			main_litedramcore_bankmachine6_row_opened <= 1'd1;
-			main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine6_row_open) begin
+			litedramcore_bankmachine6_row_opened <= 1'd1;
+			litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+		litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+		litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine6_twtpcon_valid) begin
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine6_twtpcon_valid) begin
+		litedramcore_bankmachine6_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
-			main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+			litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trccon_valid) begin
-		main_litedramcore_bankmachine6_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine6_trccon_valid) begin
+		litedramcore_bankmachine6_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+			litedramcore_bankmachine6_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+			litedramcore_bankmachine6_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
-			main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trccon_ready)) begin
+			litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trascon_valid) begin
-		main_litedramcore_bankmachine6_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine6_trascon_valid) begin
+		litedramcore_bankmachine6_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+			litedramcore_bankmachine6_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+			litedramcore_bankmachine6_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
-			main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trascon_ready)) begin
+			litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine6_state <= builder_bankmachine6_next_state;
-	if (main_litedramcore_bankmachine7_row_close) begin
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
+	litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+	if (litedramcore_bankmachine7_row_close) begin
+		litedramcore_bankmachine7_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine7_row_open) begin
-			main_litedramcore_bankmachine7_row_opened <= 1'd1;
-			main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+		if (litedramcore_bankmachine7_row_open) begin
+			litedramcore_bankmachine7_row_opened <= 1'd1;
+			litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+		litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+		litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine7_twtpcon_valid) begin
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine7_twtpcon_valid) begin
+		litedramcore_bankmachine7_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
-			main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+			litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trccon_valid) begin
-		main_litedramcore_bankmachine7_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine7_trccon_valid) begin
+		litedramcore_bankmachine7_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+			litedramcore_bankmachine7_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+			litedramcore_bankmachine7_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
-			main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trccon_ready)) begin
+			litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trascon_valid) begin
-		main_litedramcore_bankmachine7_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine7_trascon_valid) begin
+		litedramcore_bankmachine7_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+			litedramcore_bankmachine7_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+			litedramcore_bankmachine7_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
-			main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trascon_ready)) begin
+			litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine7_state <= builder_bankmachine7_next_state;
-	if ((~main_litedramcore_en0)) begin
-		main_litedramcore_time0 <= 5'd31;
+	litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+	if ((~litedramcore_en0)) begin
+		litedramcore_time0 <= 5'd31;
 	end else begin
-		if ((~main_litedramcore_max_time0)) begin
-			main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
+		if ((~litedramcore_max_time0)) begin
+			litedramcore_time0 <= (litedramcore_time0 - 1'd1);
 		end
 	end
-	if ((~main_litedramcore_en1)) begin
-		main_litedramcore_time1 <= 4'd15;
+	if ((~litedramcore_en1)) begin
+		litedramcore_time1 <= 4'd15;
 	end else begin
-		if ((~main_litedramcore_max_time1)) begin
-			main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
+		if ((~litedramcore_max_time1)) begin
+			litedramcore_time1 <= (litedramcore_time1 - 1'd1);
 		end
 	end
-	if (main_litedramcore_choose_cmd_ce) begin
-		case (main_litedramcore_choose_cmd_grant)
+	if (litedramcore_choose_cmd_ce) begin
+		case (litedramcore_choose_cmd_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_cmd_request[1]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd1;
+				if (litedramcore_choose_cmd_request[1]) begin
+					litedramcore_choose_cmd_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[2]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd2;
+					if (litedramcore_choose_cmd_request[2]) begin
+						litedramcore_choose_cmd_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[3]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd3;
+						if (litedramcore_choose_cmd_request[3]) begin
+							litedramcore_choose_cmd_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[4]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd4;
+							if (litedramcore_choose_cmd_request[4]) begin
+								litedramcore_choose_cmd_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[5]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd5;
+								if (litedramcore_choose_cmd_request[5]) begin
+									litedramcore_choose_cmd_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[6]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd6;
+									if (litedramcore_choose_cmd_request[6]) begin
+										litedramcore_choose_cmd_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[7]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd7;
+										if (litedramcore_choose_cmd_request[7]) begin
+											litedramcore_choose_cmd_grant <= 3'd7;
 										end
 									end
 								end
@@ -12367,26 +12810,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_cmd_request[2]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd2;
+				if (litedramcore_choose_cmd_request[2]) begin
+					litedramcore_choose_cmd_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[3]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd3;
+					if (litedramcore_choose_cmd_request[3]) begin
+						litedramcore_choose_cmd_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[4]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd4;
+						if (litedramcore_choose_cmd_request[4]) begin
+							litedramcore_choose_cmd_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[5]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd5;
+							if (litedramcore_choose_cmd_request[5]) begin
+								litedramcore_choose_cmd_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[6]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd6;
+								if (litedramcore_choose_cmd_request[6]) begin
+									litedramcore_choose_cmd_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[7]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd7;
+									if (litedramcore_choose_cmd_request[7]) begin
+										litedramcore_choose_cmd_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[0]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd0;
+										if (litedramcore_choose_cmd_request[0]) begin
+											litedramcore_choose_cmd_grant <= 1'd0;
 										end
 									end
 								end
@@ -12396,26 +12839,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_cmd_request[3]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd3;
+				if (litedramcore_choose_cmd_request[3]) begin
+					litedramcore_choose_cmd_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[4]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd4;
+					if (litedramcore_choose_cmd_request[4]) begin
+						litedramcore_choose_cmd_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[5]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd5;
+						if (litedramcore_choose_cmd_request[5]) begin
+							litedramcore_choose_cmd_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[6]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd6;
+							if (litedramcore_choose_cmd_request[6]) begin
+								litedramcore_choose_cmd_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[7]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd7;
+								if (litedramcore_choose_cmd_request[7]) begin
+									litedramcore_choose_cmd_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[0]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd0;
+									if (litedramcore_choose_cmd_request[0]) begin
+										litedramcore_choose_cmd_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[1]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd1;
+										if (litedramcore_choose_cmd_request[1]) begin
+											litedramcore_choose_cmd_grant <= 1'd1;
 										end
 									end
 								end
@@ -12425,26 +12868,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_cmd_request[4]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd4;
+				if (litedramcore_choose_cmd_request[4]) begin
+					litedramcore_choose_cmd_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[5]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd5;
+					if (litedramcore_choose_cmd_request[5]) begin
+						litedramcore_choose_cmd_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[6]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd6;
+						if (litedramcore_choose_cmd_request[6]) begin
+							litedramcore_choose_cmd_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[7]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd7;
+							if (litedramcore_choose_cmd_request[7]) begin
+								litedramcore_choose_cmd_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[0]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd0;
+								if (litedramcore_choose_cmd_request[0]) begin
+									litedramcore_choose_cmd_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[1]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd1;
+									if (litedramcore_choose_cmd_request[1]) begin
+										litedramcore_choose_cmd_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[2]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd2;
+										if (litedramcore_choose_cmd_request[2]) begin
+											litedramcore_choose_cmd_grant <= 2'd2;
 										end
 									end
 								end
@@ -12454,26 +12897,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_cmd_request[5]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd5;
+				if (litedramcore_choose_cmd_request[5]) begin
+					litedramcore_choose_cmd_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[6]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd6;
+					if (litedramcore_choose_cmd_request[6]) begin
+						litedramcore_choose_cmd_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[7]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd7;
+						if (litedramcore_choose_cmd_request[7]) begin
+							litedramcore_choose_cmd_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[0]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd0;
+							if (litedramcore_choose_cmd_request[0]) begin
+								litedramcore_choose_cmd_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[1]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd1;
+								if (litedramcore_choose_cmd_request[1]) begin
+									litedramcore_choose_cmd_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[2]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd2;
+									if (litedramcore_choose_cmd_request[2]) begin
+										litedramcore_choose_cmd_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[3]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd3;
+										if (litedramcore_choose_cmd_request[3]) begin
+											litedramcore_choose_cmd_grant <= 2'd3;
 										end
 									end
 								end
@@ -12483,26 +12926,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_cmd_request[6]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd6;
+				if (litedramcore_choose_cmd_request[6]) begin
+					litedramcore_choose_cmd_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[7]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd7;
+					if (litedramcore_choose_cmd_request[7]) begin
+						litedramcore_choose_cmd_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[0]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd0;
+						if (litedramcore_choose_cmd_request[0]) begin
+							litedramcore_choose_cmd_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[1]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd1;
+							if (litedramcore_choose_cmd_request[1]) begin
+								litedramcore_choose_cmd_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[2]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd2;
+								if (litedramcore_choose_cmd_request[2]) begin
+									litedramcore_choose_cmd_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[3]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd3;
+									if (litedramcore_choose_cmd_request[3]) begin
+										litedramcore_choose_cmd_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[4]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd4;
+										if (litedramcore_choose_cmd_request[4]) begin
+											litedramcore_choose_cmd_grant <= 3'd4;
 										end
 									end
 								end
@@ -12512,26 +12955,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_cmd_request[7]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd7;
+				if (litedramcore_choose_cmd_request[7]) begin
+					litedramcore_choose_cmd_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[0]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd0;
+					if (litedramcore_choose_cmd_request[0]) begin
+						litedramcore_choose_cmd_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[1]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd1;
+						if (litedramcore_choose_cmd_request[1]) begin
+							litedramcore_choose_cmd_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[2]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd2;
+							if (litedramcore_choose_cmd_request[2]) begin
+								litedramcore_choose_cmd_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[3]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd3;
+								if (litedramcore_choose_cmd_request[3]) begin
+									litedramcore_choose_cmd_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[4]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd4;
+									if (litedramcore_choose_cmd_request[4]) begin
+										litedramcore_choose_cmd_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[5]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd5;
+										if (litedramcore_choose_cmd_request[5]) begin
+											litedramcore_choose_cmd_grant <= 3'd5;
 										end
 									end
 								end
@@ -12541,26 +12984,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_cmd_request[0]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd0;
+				if (litedramcore_choose_cmd_request[0]) begin
+					litedramcore_choose_cmd_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[1]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd1;
+					if (litedramcore_choose_cmd_request[1]) begin
+						litedramcore_choose_cmd_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[2]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd2;
+						if (litedramcore_choose_cmd_request[2]) begin
+							litedramcore_choose_cmd_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[3]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd3;
+							if (litedramcore_choose_cmd_request[3]) begin
+								litedramcore_choose_cmd_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[4]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd4;
+								if (litedramcore_choose_cmd_request[4]) begin
+									litedramcore_choose_cmd_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[5]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd5;
+									if (litedramcore_choose_cmd_request[5]) begin
+										litedramcore_choose_cmd_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[6]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd6;
+										if (litedramcore_choose_cmd_request[6]) begin
+											litedramcore_choose_cmd_grant <= 3'd6;
 										end
 									end
 								end
@@ -12571,29 +13014,29 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	if (main_litedramcore_choose_req_ce) begin
-		case (main_litedramcore_choose_req_grant)
+	if (litedramcore_choose_req_ce) begin
+		case (litedramcore_choose_req_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_req_request[1]) begin
-					main_litedramcore_choose_req_grant <= 1'd1;
+				if (litedramcore_choose_req_request[1]) begin
+					litedramcore_choose_req_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_req_request[2]) begin
-						main_litedramcore_choose_req_grant <= 2'd2;
+					if (litedramcore_choose_req_request[2]) begin
+						litedramcore_choose_req_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_req_request[3]) begin
-							main_litedramcore_choose_req_grant <= 2'd3;
+						if (litedramcore_choose_req_request[3]) begin
+							litedramcore_choose_req_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_req_request[4]) begin
-								main_litedramcore_choose_req_grant <= 3'd4;
+							if (litedramcore_choose_req_request[4]) begin
+								litedramcore_choose_req_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_req_request[5]) begin
-									main_litedramcore_choose_req_grant <= 3'd5;
+								if (litedramcore_choose_req_request[5]) begin
+									litedramcore_choose_req_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_req_request[6]) begin
-										main_litedramcore_choose_req_grant <= 3'd6;
+									if (litedramcore_choose_req_request[6]) begin
+										litedramcore_choose_req_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_req_request[7]) begin
-											main_litedramcore_choose_req_grant <= 3'd7;
+										if (litedramcore_choose_req_request[7]) begin
+											litedramcore_choose_req_grant <= 3'd7;
 										end
 									end
 								end
@@ -12603,26 +13046,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_req_request[2]) begin
-					main_litedramcore_choose_req_grant <= 2'd2;
+				if (litedramcore_choose_req_request[2]) begin
+					litedramcore_choose_req_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_req_request[3]) begin
-						main_litedramcore_choose_req_grant <= 2'd3;
+					if (litedramcore_choose_req_request[3]) begin
+						litedramcore_choose_req_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_req_request[4]) begin
-							main_litedramcore_choose_req_grant <= 3'd4;
+						if (litedramcore_choose_req_request[4]) begin
+							litedramcore_choose_req_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_req_request[5]) begin
-								main_litedramcore_choose_req_grant <= 3'd5;
+							if (litedramcore_choose_req_request[5]) begin
+								litedramcore_choose_req_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_req_request[6]) begin
-									main_litedramcore_choose_req_grant <= 3'd6;
+								if (litedramcore_choose_req_request[6]) begin
+									litedramcore_choose_req_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_req_request[7]) begin
-										main_litedramcore_choose_req_grant <= 3'd7;
+									if (litedramcore_choose_req_request[7]) begin
+										litedramcore_choose_req_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_req_request[0]) begin
-											main_litedramcore_choose_req_grant <= 1'd0;
+										if (litedramcore_choose_req_request[0]) begin
+											litedramcore_choose_req_grant <= 1'd0;
 										end
 									end
 								end
@@ -12632,26 +13075,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_req_request[3]) begin
-					main_litedramcore_choose_req_grant <= 2'd3;
+				if (litedramcore_choose_req_request[3]) begin
+					litedramcore_choose_req_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_req_request[4]) begin
-						main_litedramcore_choose_req_grant <= 3'd4;
+					if (litedramcore_choose_req_request[4]) begin
+						litedramcore_choose_req_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_req_request[5]) begin
-							main_litedramcore_choose_req_grant <= 3'd5;
+						if (litedramcore_choose_req_request[5]) begin
+							litedramcore_choose_req_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_req_request[6]) begin
-								main_litedramcore_choose_req_grant <= 3'd6;
+							if (litedramcore_choose_req_request[6]) begin
+								litedramcore_choose_req_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_req_request[7]) begin
-									main_litedramcore_choose_req_grant <= 3'd7;
+								if (litedramcore_choose_req_request[7]) begin
+									litedramcore_choose_req_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_req_request[0]) begin
-										main_litedramcore_choose_req_grant <= 1'd0;
+									if (litedramcore_choose_req_request[0]) begin
+										litedramcore_choose_req_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_req_request[1]) begin
-											main_litedramcore_choose_req_grant <= 1'd1;
+										if (litedramcore_choose_req_request[1]) begin
+											litedramcore_choose_req_grant <= 1'd1;
 										end
 									end
 								end
@@ -12661,26 +13104,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_req_request[4]) begin
-					main_litedramcore_choose_req_grant <= 3'd4;
+				if (litedramcore_choose_req_request[4]) begin
+					litedramcore_choose_req_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_req_request[5]) begin
-						main_litedramcore_choose_req_grant <= 3'd5;
+					if (litedramcore_choose_req_request[5]) begin
+						litedramcore_choose_req_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_req_request[6]) begin
-							main_litedramcore_choose_req_grant <= 3'd6;
+						if (litedramcore_choose_req_request[6]) begin
+							litedramcore_choose_req_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_req_request[7]) begin
-								main_litedramcore_choose_req_grant <= 3'd7;
+							if (litedramcore_choose_req_request[7]) begin
+								litedramcore_choose_req_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_req_request[0]) begin
-									main_litedramcore_choose_req_grant <= 1'd0;
+								if (litedramcore_choose_req_request[0]) begin
+									litedramcore_choose_req_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_req_request[1]) begin
-										main_litedramcore_choose_req_grant <= 1'd1;
+									if (litedramcore_choose_req_request[1]) begin
+										litedramcore_choose_req_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_req_request[2]) begin
-											main_litedramcore_choose_req_grant <= 2'd2;
+										if (litedramcore_choose_req_request[2]) begin
+											litedramcore_choose_req_grant <= 2'd2;
 										end
 									end
 								end
@@ -12690,26 +13133,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_req_request[5]) begin
-					main_litedramcore_choose_req_grant <= 3'd5;
+				if (litedramcore_choose_req_request[5]) begin
+					litedramcore_choose_req_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_req_request[6]) begin
-						main_litedramcore_choose_req_grant <= 3'd6;
+					if (litedramcore_choose_req_request[6]) begin
+						litedramcore_choose_req_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_req_request[7]) begin
-							main_litedramcore_choose_req_grant <= 3'd7;
+						if (litedramcore_choose_req_request[7]) begin
+							litedramcore_choose_req_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_req_request[0]) begin
-								main_litedramcore_choose_req_grant <= 1'd0;
+							if (litedramcore_choose_req_request[0]) begin
+								litedramcore_choose_req_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_req_request[1]) begin
-									main_litedramcore_choose_req_grant <= 1'd1;
+								if (litedramcore_choose_req_request[1]) begin
+									litedramcore_choose_req_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_req_request[2]) begin
-										main_litedramcore_choose_req_grant <= 2'd2;
+									if (litedramcore_choose_req_request[2]) begin
+										litedramcore_choose_req_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_req_request[3]) begin
-											main_litedramcore_choose_req_grant <= 2'd3;
+										if (litedramcore_choose_req_request[3]) begin
+											litedramcore_choose_req_grant <= 2'd3;
 										end
 									end
 								end
@@ -12719,26 +13162,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_req_request[6]) begin
-					main_litedramcore_choose_req_grant <= 3'd6;
+				if (litedramcore_choose_req_request[6]) begin
+					litedramcore_choose_req_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_req_request[7]) begin
-						main_litedramcore_choose_req_grant <= 3'd7;
+					if (litedramcore_choose_req_request[7]) begin
+						litedramcore_choose_req_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_req_request[0]) begin
-							main_litedramcore_choose_req_grant <= 1'd0;
+						if (litedramcore_choose_req_request[0]) begin
+							litedramcore_choose_req_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_req_request[1]) begin
-								main_litedramcore_choose_req_grant <= 1'd1;
+							if (litedramcore_choose_req_request[1]) begin
+								litedramcore_choose_req_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_req_request[2]) begin
-									main_litedramcore_choose_req_grant <= 2'd2;
+								if (litedramcore_choose_req_request[2]) begin
+									litedramcore_choose_req_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_req_request[3]) begin
-										main_litedramcore_choose_req_grant <= 2'd3;
+									if (litedramcore_choose_req_request[3]) begin
+										litedramcore_choose_req_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_req_request[4]) begin
-											main_litedramcore_choose_req_grant <= 3'd4;
+										if (litedramcore_choose_req_request[4]) begin
+											litedramcore_choose_req_grant <= 3'd4;
 										end
 									end
 								end
@@ -12748,26 +13191,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_req_request[7]) begin
-					main_litedramcore_choose_req_grant <= 3'd7;
+				if (litedramcore_choose_req_request[7]) begin
+					litedramcore_choose_req_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_req_request[0]) begin
-						main_litedramcore_choose_req_grant <= 1'd0;
+					if (litedramcore_choose_req_request[0]) begin
+						litedramcore_choose_req_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_req_request[1]) begin
-							main_litedramcore_choose_req_grant <= 1'd1;
+						if (litedramcore_choose_req_request[1]) begin
+							litedramcore_choose_req_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_req_request[2]) begin
-								main_litedramcore_choose_req_grant <= 2'd2;
+							if (litedramcore_choose_req_request[2]) begin
+								litedramcore_choose_req_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_req_request[3]) begin
-									main_litedramcore_choose_req_grant <= 2'd3;
+								if (litedramcore_choose_req_request[3]) begin
+									litedramcore_choose_req_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_req_request[4]) begin
-										main_litedramcore_choose_req_grant <= 3'd4;
+									if (litedramcore_choose_req_request[4]) begin
+										litedramcore_choose_req_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_req_request[5]) begin
-											main_litedramcore_choose_req_grant <= 3'd5;
+										if (litedramcore_choose_req_request[5]) begin
+											litedramcore_choose_req_grant <= 3'd5;
 										end
 									end
 								end
@@ -12777,26 +13220,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_req_request[0]) begin
-					main_litedramcore_choose_req_grant <= 1'd0;
+				if (litedramcore_choose_req_request[0]) begin
+					litedramcore_choose_req_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_req_request[1]) begin
-						main_litedramcore_choose_req_grant <= 1'd1;
+					if (litedramcore_choose_req_request[1]) begin
+						litedramcore_choose_req_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_req_request[2]) begin
-							main_litedramcore_choose_req_grant <= 2'd2;
+						if (litedramcore_choose_req_request[2]) begin
+							litedramcore_choose_req_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_req_request[3]) begin
-								main_litedramcore_choose_req_grant <= 2'd3;
+							if (litedramcore_choose_req_request[3]) begin
+								litedramcore_choose_req_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_req_request[4]) begin
-									main_litedramcore_choose_req_grant <= 3'd4;
+								if (litedramcore_choose_req_request[4]) begin
+									litedramcore_choose_req_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_req_request[5]) begin
-										main_litedramcore_choose_req_grant <= 3'd5;
+									if (litedramcore_choose_req_request[5]) begin
+										litedramcore_choose_req_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_req_request[6]) begin
-											main_litedramcore_choose_req_grant <= 3'd6;
+										if (litedramcore_choose_req_request[6]) begin
+											litedramcore_choose_req_grant <= 3'd6;
 										end
 									end
 								end
@@ -12807,644 +13250,644 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	main_litedramcore_dfi_p0_cs_n <= 1'd0;
-	main_litedramcore_dfi_p0_bank <= builder_array_muxed0;
-	main_litedramcore_dfi_p0_address <= builder_array_muxed1;
-	main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2);
-	main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3);
-	main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4);
-	main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5;
-	main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6;
-	main_litedramcore_dfi_p1_cs_n <= 1'd0;
-	main_litedramcore_dfi_p1_bank <= builder_array_muxed7;
-	main_litedramcore_dfi_p1_address <= builder_array_muxed8;
-	main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9);
-	main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10);
-	main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11);
-	main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12;
-	main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13;
-	main_litedramcore_dfi_p2_cs_n <= 1'd0;
-	main_litedramcore_dfi_p2_bank <= builder_array_muxed14;
-	main_litedramcore_dfi_p2_address <= builder_array_muxed15;
-	main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16);
-	main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17);
-	main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18);
-	main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19;
-	main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20;
-	main_litedramcore_dfi_p3_cs_n <= 1'd0;
-	main_litedramcore_dfi_p3_bank <= builder_array_muxed21;
-	main_litedramcore_dfi_p3_address <= builder_array_muxed22;
-	main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23);
-	main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24);
-	main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25);
-	main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26;
-	main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27;
-	if (main_litedramcore_trrdcon_valid) begin
-		main_litedramcore_trrdcon_count <= 1'd1;
+	litedramcore_dfi_p0_cs_n <= 1'd0;
+	litedramcore_dfi_p0_bank <= array_muxed0;
+	litedramcore_dfi_p0_address <= array_muxed1;
+	litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+	litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+	litedramcore_dfi_p0_we_n <= (~array_muxed4);
+	litedramcore_dfi_p0_rddata_en <= array_muxed5;
+	litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+	litedramcore_dfi_p1_cs_n <= 1'd0;
+	litedramcore_dfi_p1_bank <= array_muxed7;
+	litedramcore_dfi_p1_address <= array_muxed8;
+	litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+	litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+	litedramcore_dfi_p1_we_n <= (~array_muxed11);
+	litedramcore_dfi_p1_rddata_en <= array_muxed12;
+	litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+	litedramcore_dfi_p2_cs_n <= 1'd0;
+	litedramcore_dfi_p2_bank <= array_muxed14;
+	litedramcore_dfi_p2_address <= array_muxed15;
+	litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+	litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+	litedramcore_dfi_p2_we_n <= (~array_muxed18);
+	litedramcore_dfi_p2_rddata_en <= array_muxed19;
+	litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+	litedramcore_dfi_p3_cs_n <= 1'd0;
+	litedramcore_dfi_p3_bank <= array_muxed21;
+	litedramcore_dfi_p3_address <= array_muxed22;
+	litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+	litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+	litedramcore_dfi_p3_we_n <= (~array_muxed25);
+	litedramcore_dfi_p3_rddata_en <= array_muxed26;
+	litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+	if (litedramcore_trrdcon_valid) begin
+		litedramcore_trrdcon_count <= 1'd1;
 		if (1'd0) begin
-			main_litedramcore_trrdcon_ready <= 1'd1;
+			litedramcore_trrdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_trrdcon_ready <= 1'd0;
+			litedramcore_trrdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_trrdcon_ready)) begin
-			main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
-			if ((main_litedramcore_trrdcon_count == 1'd1)) begin
-				main_litedramcore_trrdcon_ready <= 1'd1;
+		if ((~litedramcore_trrdcon_ready)) begin
+			litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+			if ((litedramcore_trrdcon_count == 1'd1)) begin
+				litedramcore_trrdcon_ready <= 1'd1;
 			end
 		end
 	end
-	main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
-	if ((main_litedramcore_tfawcon_count < 3'd4)) begin
-		if ((main_litedramcore_tfawcon_count == 2'd3)) begin
-			main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
+	litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+	if ((litedramcore_tfawcon_count < 3'd4)) begin
+		if ((litedramcore_tfawcon_count == 2'd3)) begin
+			litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
 		end else begin
-			main_litedramcore_tfawcon_ready <= 1'd1;
+			litedramcore_tfawcon_ready <= 1'd1;
 		end
 	end
-	if (main_litedramcore_tccdcon_valid) begin
-		main_litedramcore_tccdcon_count <= 1'd0;
+	if (litedramcore_tccdcon_valid) begin
+		litedramcore_tccdcon_count <= 1'd0;
 		if (1'd1) begin
-			main_litedramcore_tccdcon_ready <= 1'd1;
+			litedramcore_tccdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_tccdcon_ready <= 1'd0;
+			litedramcore_tccdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_tccdcon_ready)) begin
-			main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
-			if ((main_litedramcore_tccdcon_count == 1'd1)) begin
-				main_litedramcore_tccdcon_ready <= 1'd1;
+		if ((~litedramcore_tccdcon_ready)) begin
+			litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+			if ((litedramcore_tccdcon_count == 1'd1)) begin
+				litedramcore_tccdcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_twtrcon_valid) begin
-		main_litedramcore_twtrcon_count <= 3'd4;
+	if (litedramcore_twtrcon_valid) begin
+		litedramcore_twtrcon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_twtrcon_ready <= 1'd1;
+			litedramcore_twtrcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_twtrcon_ready <= 1'd0;
+			litedramcore_twtrcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_twtrcon_ready)) begin
-			main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
-			if ((main_litedramcore_twtrcon_count == 1'd1)) begin
-				main_litedramcore_twtrcon_ready <= 1'd1;
+		if ((~litedramcore_twtrcon_ready)) begin
+			litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+			if ((litedramcore_twtrcon_count == 1'd1)) begin
+				litedramcore_twtrcon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_multiplexer_state <= builder_multiplexer_next_state;
-	builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
-	builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
-	builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
-	builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
-	builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
-	builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
-	builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
-	builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
-	builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
-	builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
-	builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
-	builder_state <= builder_next_state;
-	if (builder_litedramcore_dat_w_next_value_ce0) begin
-		builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0;
+	litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+	litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+	litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+	litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+	litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+	litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+	litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+	litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+	litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+	litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+	litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+	litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+	litedramcore_state <= litedramcore_next_state;
+	if (litedramcore_dat_w_next_value_ce0) begin
+		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
 	end
-	if (builder_litedramcore_adr_next_value_ce1) begin
-		builder_litedramcore_adr <= builder_litedramcore_adr_next_value1;
+	if (litedramcore_adr_next_value_ce1) begin
+		litedramcore_adr <= litedramcore_adr_next_value1;
 	end
-	if (builder_litedramcore_we_next_value_ce2) begin
-		builder_litedramcore_we <= builder_litedramcore_we_next_value2;
+	if (litedramcore_we_next_value_ce2) begin
+		litedramcore_we <= litedramcore_we_next_value2;
 	end
-	builder_interface0_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank0_sel) begin
-		case (builder_interface0_bank_bus_adr[8:0])
+	interface0_bank_bus_dat_r <= 1'd0;
+	if (csrbank0_sel) begin
+		case (interface0_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
 			end
 			1'd1: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank0_init_done0_re) begin
-		main_init_done_storage <= builder_csrbank0_init_done0_r;
+	if (csrbank0_init_done0_re) begin
+		init_done_storage <= csrbank0_init_done0_r;
 	end
-	main_init_done_re <= builder_csrbank0_init_done0_re;
-	if (builder_csrbank0_init_error0_re) begin
-		main_init_error_storage <= builder_csrbank0_init_error0_r;
+	init_done_re <= csrbank0_init_done0_re;
+	if (csrbank0_init_error0_re) begin
+		init_error_storage <= csrbank0_init_error0_r;
 	end
-	main_init_error_re <= builder_csrbank0_init_error0_re;
-	builder_interface1_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank1_sel) begin
-		case (builder_interface1_bank_bus_adr[8:0])
+	init_error_re <= csrbank0_init_error0_re;
+	interface1_bank_bus_dat_r <= 1'd0;
+	if (csrbank1_sel) begin
+		case (interface1_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rst0_w;
 			end
 			1'd1: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
 			end
 			2'd2: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
+				interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
 			end
 			2'd3: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
+				interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
 			end
 			3'd4: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
 			end
 			3'd5: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
 			end
 			3'd6: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
 			end
 			3'd7: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
 			end
 			4'd8: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
 			end
 			4'd9: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
 			end
 			4'd10: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
 			end
 			4'd11: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
 			end
 			4'd12: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank1_rst0_re) begin
-		main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
+	if (csrbank1_rst0_re) begin
+		a7ddrphy_rst_storage <= csrbank1_rst0_r;
 	end
-	main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
-	if (builder_csrbank1_half_sys8x_taps0_re) begin
-		main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+	a7ddrphy_rst_re <= csrbank1_rst0_re;
+	if (csrbank1_dly_sel0_re) begin
+		a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
 	end
-	main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
-	if (builder_csrbank1_wlevel_en0_re) begin
-		main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
+	a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+	if (csrbank1_half_sys8x_taps0_re) begin
+		a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
 	end
-	main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
-	if (builder_csrbank1_dly_sel0_re) begin
-		main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+	a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+	if (csrbank1_wlevel_en0_re) begin
+		a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
 	end
-	main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
-	if (builder_csrbank1_rdphase0_re) begin
-		main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+	a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+	if (csrbank1_rdphase0_re) begin
+		a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
 	end
-	main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
-	if (builder_csrbank1_wrphase0_re) begin
-		main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+	a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+	if (csrbank1_wrphase0_re) begin
+		a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
 	end
-	main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
-	builder_interface2_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank2_sel) begin
-		case (builder_interface2_bank_bus_adr[8:0])
+	a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+	interface2_bank_bus_dat_r <= 1'd0;
+	if (csrbank2_sel) begin
+		case (interface2_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
 			end
 			1'd1: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
 			end
 			2'd2: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
 			end
 			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
 			end
 			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
 			end
 			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
 			end
 			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
 			end
 			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
-	if (builder_csrbank2_dfii_control0_re) begin
-		main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+	if (csrbank2_dfii_control0_re) begin
+		litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
 	end
-	main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
-	if (builder_csrbank2_dfii_pi0_command0_re) begin
-		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
+	litedramcore_re <= csrbank2_dfii_control0_re;
+	if (csrbank2_dfii_pi0_command0_re) begin
+		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
 	end
-	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
+	litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+	if (csrbank2_dfii_pi0_address0_re) begin
+		litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
 	end
-	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
-	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+	litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+	if (csrbank2_dfii_pi0_baddress0_re) begin
+		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
 	end
-	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+	litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+	if (csrbank2_dfii_pi0_wrdata0_re) begin
+		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
-	if (builder_csrbank2_dfii_pi1_command0_re) begin
-		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
+	litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+	litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+	if (csrbank2_dfii_pi1_command0_re) begin
+		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
 	end
-	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
+	litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+	if (csrbank2_dfii_pi1_address0_re) begin
+		litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
 	end
-	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
-	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+	litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+	if (csrbank2_dfii_pi1_baddress0_re) begin
+		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
 	end
-	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+	litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+	if (csrbank2_dfii_pi1_wrdata0_re) begin
+		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
-	if (builder_csrbank2_dfii_pi2_command0_re) begin
-		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
+	litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+	litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+	if (csrbank2_dfii_pi2_command0_re) begin
+		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
 	end
-	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
+	litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+	if (csrbank2_dfii_pi2_address0_re) begin
+		litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
 	end
-	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
-	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+	litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+	if (csrbank2_dfii_pi2_baddress0_re) begin
+		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
 	end
-	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+	litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+	if (csrbank2_dfii_pi2_wrdata0_re) begin
+		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
-	if (builder_csrbank2_dfii_pi3_command0_re) begin
-		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
+	litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+	litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+	if (csrbank2_dfii_pi3_command0_re) begin
+		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
 	end
-	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
+	litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+	if (csrbank2_dfii_pi3_address0_re) begin
+		litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
 	end
-	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
-	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+	litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+	if (csrbank2_dfii_pi3_baddress0_re) begin
+		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
 	end
-	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+	litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+	if (csrbank2_dfii_pi3_wrdata0_re) begin
+		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
+	litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+	litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
-		main_a7ddrphy_rst_storage <= 1'd0;
-		main_a7ddrphy_rst_re <= 1'd0;
-		main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-		main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
-		main_a7ddrphy_wlevel_en_storage <= 1'd0;
-		main_a7ddrphy_wlevel_en_re <= 1'd0;
-		main_a7ddrphy_dly_sel_storage <= 2'd0;
-		main_a7ddrphy_dly_sel_re <= 1'd0;
-		main_a7ddrphy_rdphase_storage <= 2'd2;
-		main_a7ddrphy_rdphase_re <= 1'd0;
-		main_a7ddrphy_wrphase_storage <= 2'd3;
-		main_a7ddrphy_wrphase_re <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_dqspattern_o1 <= 8'd0;
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
-		main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-		main_litedramcore_storage <= 4'd1;
-		main_litedramcore_re <= 1'd0;
-		main_litedramcore_phaseinjector0_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector0_command_re <= 1'd0;
-		main_litedramcore_phaseinjector0_address_re <= 1'd0;
-		main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector1_command_re <= 1'd0;
-		main_litedramcore_phaseinjector1_address_re <= 1'd0;
-		main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector2_command_re <= 1'd0;
-		main_litedramcore_phaseinjector2_address_re <= 1'd0;
-		main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector3_command_re <= 1'd0;
-		main_litedramcore_phaseinjector3_address_re <= 1'd0;
-		main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
-		main_litedramcore_dfi_p0_address <= 15'd0;
-		main_litedramcore_dfi_p0_bank <= 3'd0;
-		main_litedramcore_dfi_p0_cas_n <= 1'd1;
-		main_litedramcore_dfi_p0_cs_n <= 1'd1;
-		main_litedramcore_dfi_p0_ras_n <= 1'd1;
-		main_litedramcore_dfi_p0_we_n <= 1'd1;
-		main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p0_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p1_address <= 15'd0;
-		main_litedramcore_dfi_p1_bank <= 3'd0;
-		main_litedramcore_dfi_p1_cas_n <= 1'd1;
-		main_litedramcore_dfi_p1_cs_n <= 1'd1;
-		main_litedramcore_dfi_p1_ras_n <= 1'd1;
-		main_litedramcore_dfi_p1_we_n <= 1'd1;
-		main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p1_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p2_address <= 15'd0;
-		main_litedramcore_dfi_p2_bank <= 3'd0;
-		main_litedramcore_dfi_p2_cas_n <= 1'd1;
-		main_litedramcore_dfi_p2_cs_n <= 1'd1;
-		main_litedramcore_dfi_p2_ras_n <= 1'd1;
-		main_litedramcore_dfi_p2_we_n <= 1'd1;
-		main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p2_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p3_address <= 15'd0;
-		main_litedramcore_dfi_p3_bank <= 3'd0;
-		main_litedramcore_dfi_p3_cas_n <= 1'd1;
-		main_litedramcore_dfi_p3_cs_n <= 1'd1;
-		main_litedramcore_dfi_p3_ras_n <= 1'd1;
-		main_litedramcore_dfi_p3_we_n <= 1'd1;
-		main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p3_rddata_en <= 1'd0;
-		main_litedramcore_cmd_payload_a <= 15'd0;
-		main_litedramcore_cmd_payload_ba <= 3'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_timer_count1 <= 10'd781;
-		main_litedramcore_postponer_req_o <= 1'd0;
-		main_litedramcore_postponer_count <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd0;
-		main_litedramcore_sequencer_counter <= 6'd0;
-		main_litedramcore_sequencer_count <= 1'd0;
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
-		main_litedramcore_zqcs_executer_done <= 1'd0;
-		main_litedramcore_zqcs_executer_counter <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine0_row <= 15'd0;
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine1_row <= 15'd0;
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine2_row <= 15'd0;
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine3_row <= 15'd0;
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine4_row <= 15'd0;
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine5_row <= 15'd0;
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine6_row <= 15'd0;
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
-		main_litedramcore_bankmachine7_row <= 15'd0;
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trascon_count <= 3'd0;
-		main_litedramcore_choose_cmd_grant <= 3'd0;
-		main_litedramcore_choose_req_grant <= 3'd0;
-		main_litedramcore_trrdcon_ready <= 1'd0;
-		main_litedramcore_trrdcon_count <= 1'd0;
-		main_litedramcore_tfawcon_ready <= 1'd1;
-		main_litedramcore_tfawcon_window <= 5'd0;
-		main_litedramcore_tccdcon_ready <= 1'd0;
-		main_litedramcore_tccdcon_count <= 1'd0;
-		main_litedramcore_twtrcon_ready <= 1'd0;
-		main_litedramcore_twtrcon_count <= 3'd0;
-		main_litedramcore_time0 <= 5'd0;
-		main_litedramcore_time1 <= 4'd0;
-		main_init_done_storage <= 1'd0;
-		main_init_done_re <= 1'd0;
-		main_init_error_storage <= 1'd0;
-		main_init_error_re <= 1'd0;
-		builder_refresher_state <= 2'd0;
-		builder_bankmachine0_state <= 4'd0;
-		builder_bankmachine1_state <= 4'd0;
-		builder_bankmachine2_state <= 4'd0;
-		builder_bankmachine3_state <= 4'd0;
-		builder_bankmachine4_state <= 4'd0;
-		builder_bankmachine5_state <= 4'd0;
-		builder_bankmachine6_state <= 4'd0;
-		builder_bankmachine7_state <= 4'd0;
-		builder_multiplexer_state <= 4'd0;
-		builder_new_master_wdata_ready0 <= 1'd0;
-		builder_new_master_wdata_ready1 <= 1'd0;
-		builder_new_master_rdata_valid0 <= 1'd0;
-		builder_new_master_rdata_valid1 <= 1'd0;
-		builder_new_master_rdata_valid2 <= 1'd0;
-		builder_new_master_rdata_valid3 <= 1'd0;
-		builder_new_master_rdata_valid4 <= 1'd0;
-		builder_new_master_rdata_valid5 <= 1'd0;
-		builder_new_master_rdata_valid6 <= 1'd0;
-		builder_new_master_rdata_valid7 <= 1'd0;
-		builder_new_master_rdata_valid8 <= 1'd0;
-		builder_litedramcore_we <= 1'd0;
-		builder_state <= 2'd0;
+		a7ddrphy_rst_storage <= 1'd0;
+		a7ddrphy_rst_re <= 1'd0;
+		a7ddrphy_dly_sel_storage <= 2'd0;
+		a7ddrphy_dly_sel_re <= 1'd0;
+		a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+		a7ddrphy_half_sys8x_taps_re <= 1'd0;
+		a7ddrphy_wlevel_en_storage <= 1'd0;
+		a7ddrphy_wlevel_en_re <= 1'd0;
+		a7ddrphy_rdphase_storage <= 2'd2;
+		a7ddrphy_rdphase_re <= 1'd0;
+		a7ddrphy_wrphase_storage <= 2'd3;
+		a7ddrphy_wrphase_re <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_dqspattern_o1 <= 8'd0;
+		a7ddrphy_bitslip0_value0 <= 3'd7;
+		a7ddrphy_bitslip1_value0 <= 3'd7;
+		a7ddrphy_bitslip0_value1 <= 3'd7;
+		a7ddrphy_bitslip1_value1 <= 3'd7;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_bitslip0_value2 <= 3'd7;
+		a7ddrphy_bitslip0_value3 <= 3'd7;
+		a7ddrphy_bitslip1_value2 <= 3'd7;
+		a7ddrphy_bitslip1_value3 <= 3'd7;
+		a7ddrphy_bitslip2_value0 <= 3'd7;
+		a7ddrphy_bitslip2_value1 <= 3'd7;
+		a7ddrphy_bitslip3_value0 <= 3'd7;
+		a7ddrphy_bitslip3_value1 <= 3'd7;
+		a7ddrphy_bitslip4_value0 <= 3'd7;
+		a7ddrphy_bitslip4_value1 <= 3'd7;
+		a7ddrphy_bitslip5_value0 <= 3'd7;
+		a7ddrphy_bitslip5_value1 <= 3'd7;
+		a7ddrphy_bitslip6_value0 <= 3'd7;
+		a7ddrphy_bitslip6_value1 <= 3'd7;
+		a7ddrphy_bitslip7_value0 <= 3'd7;
+		a7ddrphy_bitslip7_value1 <= 3'd7;
+		a7ddrphy_bitslip8_value0 <= 3'd7;
+		a7ddrphy_bitslip8_value1 <= 3'd7;
+		a7ddrphy_bitslip9_value0 <= 3'd7;
+		a7ddrphy_bitslip9_value1 <= 3'd7;
+		a7ddrphy_bitslip10_value0 <= 3'd7;
+		a7ddrphy_bitslip10_value1 <= 3'd7;
+		a7ddrphy_bitslip11_value0 <= 3'd7;
+		a7ddrphy_bitslip11_value1 <= 3'd7;
+		a7ddrphy_bitslip12_value0 <= 3'd7;
+		a7ddrphy_bitslip12_value1 <= 3'd7;
+		a7ddrphy_bitslip13_value0 <= 3'd7;
+		a7ddrphy_bitslip13_value1 <= 3'd7;
+		a7ddrphy_bitslip14_value0 <= 3'd7;
+		a7ddrphy_bitslip14_value1 <= 3'd7;
+		a7ddrphy_bitslip15_value0 <= 3'd7;
+		a7ddrphy_bitslip15_value1 <= 3'd7;
+		a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+		litedramcore_storage <= 4'd1;
+		litedramcore_re <= 1'd0;
+		litedramcore_phaseinjector0_command_storage <= 6'd0;
+		litedramcore_phaseinjector0_command_re <= 1'd0;
+		litedramcore_phaseinjector0_address_re <= 1'd0;
+		litedramcore_phaseinjector0_baddress_re <= 1'd0;
+		litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector0_rddata_status <= 32'd0;
+		litedramcore_phaseinjector0_rddata_re <= 1'd0;
+		litedramcore_phaseinjector1_command_storage <= 6'd0;
+		litedramcore_phaseinjector1_command_re <= 1'd0;
+		litedramcore_phaseinjector1_address_re <= 1'd0;
+		litedramcore_phaseinjector1_baddress_re <= 1'd0;
+		litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector1_rddata_status <= 32'd0;
+		litedramcore_phaseinjector1_rddata_re <= 1'd0;
+		litedramcore_phaseinjector2_command_storage <= 6'd0;
+		litedramcore_phaseinjector2_command_re <= 1'd0;
+		litedramcore_phaseinjector2_address_re <= 1'd0;
+		litedramcore_phaseinjector2_baddress_re <= 1'd0;
+		litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector2_rddata_status <= 32'd0;
+		litedramcore_phaseinjector2_rddata_re <= 1'd0;
+		litedramcore_phaseinjector3_command_storage <= 6'd0;
+		litedramcore_phaseinjector3_command_re <= 1'd0;
+		litedramcore_phaseinjector3_address_re <= 1'd0;
+		litedramcore_phaseinjector3_baddress_re <= 1'd0;
+		litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector3_rddata_status <= 32'd0;
+		litedramcore_phaseinjector3_rddata_re <= 1'd0;
+		litedramcore_dfi_p0_address <= 15'd0;
+		litedramcore_dfi_p0_bank <= 3'd0;
+		litedramcore_dfi_p0_cas_n <= 1'd1;
+		litedramcore_dfi_p0_cs_n <= 1'd1;
+		litedramcore_dfi_p0_ras_n <= 1'd1;
+		litedramcore_dfi_p0_we_n <= 1'd1;
+		litedramcore_dfi_p0_wrdata_en <= 1'd0;
+		litedramcore_dfi_p0_rddata_en <= 1'd0;
+		litedramcore_dfi_p1_address <= 15'd0;
+		litedramcore_dfi_p1_bank <= 3'd0;
+		litedramcore_dfi_p1_cas_n <= 1'd1;
+		litedramcore_dfi_p1_cs_n <= 1'd1;
+		litedramcore_dfi_p1_ras_n <= 1'd1;
+		litedramcore_dfi_p1_we_n <= 1'd1;
+		litedramcore_dfi_p1_wrdata_en <= 1'd0;
+		litedramcore_dfi_p1_rddata_en <= 1'd0;
+		litedramcore_dfi_p2_address <= 15'd0;
+		litedramcore_dfi_p2_bank <= 3'd0;
+		litedramcore_dfi_p2_cas_n <= 1'd1;
+		litedramcore_dfi_p2_cs_n <= 1'd1;
+		litedramcore_dfi_p2_ras_n <= 1'd1;
+		litedramcore_dfi_p2_we_n <= 1'd1;
+		litedramcore_dfi_p2_wrdata_en <= 1'd0;
+		litedramcore_dfi_p2_rddata_en <= 1'd0;
+		litedramcore_dfi_p3_address <= 15'd0;
+		litedramcore_dfi_p3_bank <= 3'd0;
+		litedramcore_dfi_p3_cas_n <= 1'd1;
+		litedramcore_dfi_p3_cs_n <= 1'd1;
+		litedramcore_dfi_p3_ras_n <= 1'd1;
+		litedramcore_dfi_p3_we_n <= 1'd1;
+		litedramcore_dfi_p3_wrdata_en <= 1'd0;
+		litedramcore_dfi_p3_rddata_en <= 1'd0;
+		litedramcore_cmd_payload_a <= 15'd0;
+		litedramcore_cmd_payload_ba <= 3'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_timer_count1 <= 10'd781;
+		litedramcore_postponer_req_o <= 1'd0;
+		litedramcore_postponer_count <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd0;
+		litedramcore_sequencer_counter <= 6'd0;
+		litedramcore_sequencer_count <= 1'd0;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_executer_done <= 1'd0;
+		litedramcore_zqcs_executer_counter <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine0_row <= 15'd0;
+		litedramcore_bankmachine0_row_opened <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine0_trccon_ready <= 1'd0;
+		litedramcore_bankmachine0_trccon_count <= 3'd0;
+		litedramcore_bankmachine0_trascon_ready <= 1'd0;
+		litedramcore_bankmachine0_trascon_count <= 3'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine1_row <= 15'd0;
+		litedramcore_bankmachine1_row_opened <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine1_trccon_ready <= 1'd0;
+		litedramcore_bankmachine1_trccon_count <= 3'd0;
+		litedramcore_bankmachine1_trascon_ready <= 1'd0;
+		litedramcore_bankmachine1_trascon_count <= 3'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine2_row <= 15'd0;
+		litedramcore_bankmachine2_row_opened <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine2_trccon_ready <= 1'd0;
+		litedramcore_bankmachine2_trccon_count <= 3'd0;
+		litedramcore_bankmachine2_trascon_ready <= 1'd0;
+		litedramcore_bankmachine2_trascon_count <= 3'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine3_row <= 15'd0;
+		litedramcore_bankmachine3_row_opened <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine3_trccon_ready <= 1'd0;
+		litedramcore_bankmachine3_trccon_count <= 3'd0;
+		litedramcore_bankmachine3_trascon_ready <= 1'd0;
+		litedramcore_bankmachine3_trascon_count <= 3'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine4_row <= 15'd0;
+		litedramcore_bankmachine4_row_opened <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine4_trccon_ready <= 1'd0;
+		litedramcore_bankmachine4_trccon_count <= 3'd0;
+		litedramcore_bankmachine4_trascon_ready <= 1'd0;
+		litedramcore_bankmachine4_trascon_count <= 3'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine5_row <= 15'd0;
+		litedramcore_bankmachine5_row_opened <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine5_trccon_ready <= 1'd0;
+		litedramcore_bankmachine5_trccon_count <= 3'd0;
+		litedramcore_bankmachine5_trascon_ready <= 1'd0;
+		litedramcore_bankmachine5_trascon_count <= 3'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine6_row <= 15'd0;
+		litedramcore_bankmachine6_row_opened <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine6_trccon_ready <= 1'd0;
+		litedramcore_bankmachine6_trccon_count <= 3'd0;
+		litedramcore_bankmachine6_trascon_ready <= 1'd0;
+		litedramcore_bankmachine6_trascon_count <= 3'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
+		litedramcore_bankmachine7_row <= 15'd0;
+		litedramcore_bankmachine7_row_opened <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine7_trccon_ready <= 1'd0;
+		litedramcore_bankmachine7_trccon_count <= 3'd0;
+		litedramcore_bankmachine7_trascon_ready <= 1'd0;
+		litedramcore_bankmachine7_trascon_count <= 3'd0;
+		litedramcore_choose_cmd_grant <= 3'd0;
+		litedramcore_choose_req_grant <= 3'd0;
+		litedramcore_trrdcon_ready <= 1'd0;
+		litedramcore_trrdcon_count <= 1'd0;
+		litedramcore_tfawcon_ready <= 1'd1;
+		litedramcore_tfawcon_window <= 5'd0;
+		litedramcore_tccdcon_ready <= 1'd0;
+		litedramcore_tccdcon_count <= 1'd0;
+		litedramcore_twtrcon_ready <= 1'd0;
+		litedramcore_twtrcon_count <= 3'd0;
+		litedramcore_time0 <= 5'd0;
+		litedramcore_time1 <= 4'd0;
+		init_done_storage <= 1'd0;
+		init_done_re <= 1'd0;
+		init_error_storage <= 1'd0;
+		init_error_re <= 1'd0;
+		litedramcore_we <= 1'd0;
+		litedramcore_refresher_state <= 2'd0;
+		litedramcore_bankmachine0_state <= 4'd0;
+		litedramcore_bankmachine1_state <= 4'd0;
+		litedramcore_bankmachine2_state <= 4'd0;
+		litedramcore_bankmachine3_state <= 4'd0;
+		litedramcore_bankmachine4_state <= 4'd0;
+		litedramcore_bankmachine5_state <= 4'd0;
+		litedramcore_bankmachine6_state <= 4'd0;
+		litedramcore_bankmachine7_state <= 4'd0;
+		litedramcore_multiplexer_state <= 4'd0;
+		litedramcore_new_master_wdata_ready0 <= 1'd0;
+		litedramcore_new_master_wdata_ready1 <= 1'd0;
+		litedramcore_new_master_rdata_valid0 <= 1'd0;
+		litedramcore_new_master_rdata_valid1 <= 1'd0;
+		litedramcore_new_master_rdata_valid2 <= 1'd0;
+		litedramcore_new_master_rdata_valid3 <= 1'd0;
+		litedramcore_new_master_rdata_valid4 <= 1'd0;
+		litedramcore_new_master_rdata_valid5 <= 1'd0;
+		litedramcore_new_master_rdata_valid6 <= 1'd0;
+		litedramcore_new_master_rdata_valid7 <= 1'd0;
+		litedramcore_new_master_rdata_valid8 <= 1'd0;
+		litedramcore_state <= 2'd0;
 	end
 end
 
@@ -13454,28 +13897,28 @@ end
 //------------------------------------------------------------------------------
 
 BUFG BUFG(
-	.I(main_clkout0),
-	.O(main_clkout_buf0)
+	.I(clkout0),
+	.O(clkout_buf0)
 );
 
 BUFG BUFG_1(
-	.I(main_clkout1),
-	.O(main_clkout_buf1)
+	.I(clkout1),
+	.O(clkout_buf1)
 );
 
 BUFG BUFG_2(
-	.I(main_clkout2),
-	.O(main_clkout_buf2)
+	.I(clkout2),
+	.O(clkout_buf2)
 );
 
 BUFG BUFG_3(
-	.I(main_clkout3),
-	.O(main_clkout_buf3)
+	.I(clkout3),
+	.O(clkout_buf3)
 );
 
 IDELAYCTRL IDELAYCTRL(
 	.REFCLK(iodelay_clk),
-	.RST(main_ic_reset)
+	.RST(ic_reset)
 );
 
 OSERDESE2 #(
@@ -13496,12 +13939,12 @@ OSERDESE2 #(
 	.D7(1'd0),
 	.D8(1'd1),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(main_a7ddrphy_sd_clk_se_nodelay)
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_sd_clk_se_nodelay)
 );
 
 OBUFDS OBUFDS(
-	.I(main_a7ddrphy_sd_clk_se_nodelay),
+	.I(a7ddrphy_sd_clk_se_nodelay),
 	.O(ddram_clk_p),
 	.OB(ddram_clk_n)
 );
@@ -13515,16 +13958,16 @@ OSERDESE2 #(
 ) OSERDESE2_1 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_reset_n),
-	.D2(main_a7ddrphy_dfi_p0_reset_n),
-	.D3(main_a7ddrphy_dfi_p1_reset_n),
-	.D4(main_a7ddrphy_dfi_p1_reset_n),
-	.D5(main_a7ddrphy_dfi_p2_reset_n),
-	.D6(main_a7ddrphy_dfi_p2_reset_n),
-	.D7(main_a7ddrphy_dfi_p3_reset_n),
-	.D8(main_a7ddrphy_dfi_p3_reset_n),
+	.D1(a7ddrphy_dfi_p0_reset_n),
+	.D2(a7ddrphy_dfi_p0_reset_n),
+	.D3(a7ddrphy_dfi_p1_reset_n),
+	.D4(a7ddrphy_dfi_p1_reset_n),
+	.D5(a7ddrphy_dfi_p2_reset_n),
+	.D6(a7ddrphy_dfi_p2_reset_n),
+	.D7(a7ddrphy_dfi_p3_reset_n),
+	.D8(a7ddrphy_dfi_p3_reset_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_reset_n)
 );
 
@@ -13537,16 +13980,16 @@ OSERDESE2 #(
 ) OSERDESE2_2 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cs_n),
-	.D2(main_a7ddrphy_dfi_p0_cs_n),
-	.D3(main_a7ddrphy_dfi_p1_cs_n),
-	.D4(main_a7ddrphy_dfi_p1_cs_n),
-	.D5(main_a7ddrphy_dfi_p2_cs_n),
-	.D6(main_a7ddrphy_dfi_p2_cs_n),
-	.D7(main_a7ddrphy_dfi_p3_cs_n),
-	.D8(main_a7ddrphy_dfi_p3_cs_n),
+	.D1(a7ddrphy_dfi_p0_cs_n),
+	.D2(a7ddrphy_dfi_p0_cs_n),
+	.D3(a7ddrphy_dfi_p1_cs_n),
+	.D4(a7ddrphy_dfi_p1_cs_n),
+	.D5(a7ddrphy_dfi_p2_cs_n),
+	.D6(a7ddrphy_dfi_p2_cs_n),
+	.D7(a7ddrphy_dfi_p3_cs_n),
+	.D8(a7ddrphy_dfi_p3_cs_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cs_n)
 );
 
@@ -13559,16 +14002,16 @@ OSERDESE2 #(
 ) OSERDESE2_3 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[0]),
-	.D2(main_a7ddrphy_dfi_p0_address[0]),
-	.D3(main_a7ddrphy_dfi_p1_address[0]),
-	.D4(main_a7ddrphy_dfi_p1_address[0]),
-	.D5(main_a7ddrphy_dfi_p2_address[0]),
-	.D6(main_a7ddrphy_dfi_p2_address[0]),
-	.D7(main_a7ddrphy_dfi_p3_address[0]),
-	.D8(main_a7ddrphy_dfi_p3_address[0]),
+	.D1(a7ddrphy_dfi_p0_address[0]),
+	.D2(a7ddrphy_dfi_p0_address[0]),
+	.D3(a7ddrphy_dfi_p1_address[0]),
+	.D4(a7ddrphy_dfi_p1_address[0]),
+	.D5(a7ddrphy_dfi_p2_address[0]),
+	.D6(a7ddrphy_dfi_p2_address[0]),
+	.D7(a7ddrphy_dfi_p3_address[0]),
+	.D8(a7ddrphy_dfi_p3_address[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[0])
 );
 
@@ -13581,16 +14024,16 @@ OSERDESE2 #(
 ) OSERDESE2_4 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[1]),
-	.D2(main_a7ddrphy_dfi_p0_address[1]),
-	.D3(main_a7ddrphy_dfi_p1_address[1]),
-	.D4(main_a7ddrphy_dfi_p1_address[1]),
-	.D5(main_a7ddrphy_dfi_p2_address[1]),
-	.D6(main_a7ddrphy_dfi_p2_address[1]),
-	.D7(main_a7ddrphy_dfi_p3_address[1]),
-	.D8(main_a7ddrphy_dfi_p3_address[1]),
+	.D1(a7ddrphy_dfi_p0_address[1]),
+	.D2(a7ddrphy_dfi_p0_address[1]),
+	.D3(a7ddrphy_dfi_p1_address[1]),
+	.D4(a7ddrphy_dfi_p1_address[1]),
+	.D5(a7ddrphy_dfi_p2_address[1]),
+	.D6(a7ddrphy_dfi_p2_address[1]),
+	.D7(a7ddrphy_dfi_p3_address[1]),
+	.D8(a7ddrphy_dfi_p3_address[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[1])
 );
 
@@ -13603,16 +14046,16 @@ OSERDESE2 #(
 ) OSERDESE2_5 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[2]),
-	.D2(main_a7ddrphy_dfi_p0_address[2]),
-	.D3(main_a7ddrphy_dfi_p1_address[2]),
-	.D4(main_a7ddrphy_dfi_p1_address[2]),
-	.D5(main_a7ddrphy_dfi_p2_address[2]),
-	.D6(main_a7ddrphy_dfi_p2_address[2]),
-	.D7(main_a7ddrphy_dfi_p3_address[2]),
-	.D8(main_a7ddrphy_dfi_p3_address[2]),
+	.D1(a7ddrphy_dfi_p0_address[2]),
+	.D2(a7ddrphy_dfi_p0_address[2]),
+	.D3(a7ddrphy_dfi_p1_address[2]),
+	.D4(a7ddrphy_dfi_p1_address[2]),
+	.D5(a7ddrphy_dfi_p2_address[2]),
+	.D6(a7ddrphy_dfi_p2_address[2]),
+	.D7(a7ddrphy_dfi_p3_address[2]),
+	.D8(a7ddrphy_dfi_p3_address[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[2])
 );
 
@@ -13625,16 +14068,16 @@ OSERDESE2 #(
 ) OSERDESE2_6 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[3]),
-	.D2(main_a7ddrphy_dfi_p0_address[3]),
-	.D3(main_a7ddrphy_dfi_p1_address[3]),
-	.D4(main_a7ddrphy_dfi_p1_address[3]),
-	.D5(main_a7ddrphy_dfi_p2_address[3]),
-	.D6(main_a7ddrphy_dfi_p2_address[3]),
-	.D7(main_a7ddrphy_dfi_p3_address[3]),
-	.D8(main_a7ddrphy_dfi_p3_address[3]),
+	.D1(a7ddrphy_dfi_p0_address[3]),
+	.D2(a7ddrphy_dfi_p0_address[3]),
+	.D3(a7ddrphy_dfi_p1_address[3]),
+	.D4(a7ddrphy_dfi_p1_address[3]),
+	.D5(a7ddrphy_dfi_p2_address[3]),
+	.D6(a7ddrphy_dfi_p2_address[3]),
+	.D7(a7ddrphy_dfi_p3_address[3]),
+	.D8(a7ddrphy_dfi_p3_address[3]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[3])
 );
 
@@ -13647,16 +14090,16 @@ OSERDESE2 #(
 ) OSERDESE2_7 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[4]),
-	.D2(main_a7ddrphy_dfi_p0_address[4]),
-	.D3(main_a7ddrphy_dfi_p1_address[4]),
-	.D4(main_a7ddrphy_dfi_p1_address[4]),
-	.D5(main_a7ddrphy_dfi_p2_address[4]),
-	.D6(main_a7ddrphy_dfi_p2_address[4]),
-	.D7(main_a7ddrphy_dfi_p3_address[4]),
-	.D8(main_a7ddrphy_dfi_p3_address[4]),
+	.D1(a7ddrphy_dfi_p0_address[4]),
+	.D2(a7ddrphy_dfi_p0_address[4]),
+	.D3(a7ddrphy_dfi_p1_address[4]),
+	.D4(a7ddrphy_dfi_p1_address[4]),
+	.D5(a7ddrphy_dfi_p2_address[4]),
+	.D6(a7ddrphy_dfi_p2_address[4]),
+	.D7(a7ddrphy_dfi_p3_address[4]),
+	.D8(a7ddrphy_dfi_p3_address[4]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[4])
 );
 
@@ -13669,16 +14112,16 @@ OSERDESE2 #(
 ) OSERDESE2_8 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[5]),
-	.D2(main_a7ddrphy_dfi_p0_address[5]),
-	.D3(main_a7ddrphy_dfi_p1_address[5]),
-	.D4(main_a7ddrphy_dfi_p1_address[5]),
-	.D5(main_a7ddrphy_dfi_p2_address[5]),
-	.D6(main_a7ddrphy_dfi_p2_address[5]),
-	.D7(main_a7ddrphy_dfi_p3_address[5]),
-	.D8(main_a7ddrphy_dfi_p3_address[5]),
+	.D1(a7ddrphy_dfi_p0_address[5]),
+	.D2(a7ddrphy_dfi_p0_address[5]),
+	.D3(a7ddrphy_dfi_p1_address[5]),
+	.D4(a7ddrphy_dfi_p1_address[5]),
+	.D5(a7ddrphy_dfi_p2_address[5]),
+	.D6(a7ddrphy_dfi_p2_address[5]),
+	.D7(a7ddrphy_dfi_p3_address[5]),
+	.D8(a7ddrphy_dfi_p3_address[5]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[5])
 );
 
@@ -13691,16 +14134,16 @@ OSERDESE2 #(
 ) OSERDESE2_9 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[6]),
-	.D2(main_a7ddrphy_dfi_p0_address[6]),
-	.D3(main_a7ddrphy_dfi_p1_address[6]),
-	.D4(main_a7ddrphy_dfi_p1_address[6]),
-	.D5(main_a7ddrphy_dfi_p2_address[6]),
-	.D6(main_a7ddrphy_dfi_p2_address[6]),
-	.D7(main_a7ddrphy_dfi_p3_address[6]),
-	.D8(main_a7ddrphy_dfi_p3_address[6]),
+	.D1(a7ddrphy_dfi_p0_address[6]),
+	.D2(a7ddrphy_dfi_p0_address[6]),
+	.D3(a7ddrphy_dfi_p1_address[6]),
+	.D4(a7ddrphy_dfi_p1_address[6]),
+	.D5(a7ddrphy_dfi_p2_address[6]),
+	.D6(a7ddrphy_dfi_p2_address[6]),
+	.D7(a7ddrphy_dfi_p3_address[6]),
+	.D8(a7ddrphy_dfi_p3_address[6]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[6])
 );
 
@@ -13713,16 +14156,16 @@ OSERDESE2 #(
 ) OSERDESE2_10 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[7]),
-	.D2(main_a7ddrphy_dfi_p0_address[7]),
-	.D3(main_a7ddrphy_dfi_p1_address[7]),
-	.D4(main_a7ddrphy_dfi_p1_address[7]),
-	.D5(main_a7ddrphy_dfi_p2_address[7]),
-	.D6(main_a7ddrphy_dfi_p2_address[7]),
-	.D7(main_a7ddrphy_dfi_p3_address[7]),
-	.D8(main_a7ddrphy_dfi_p3_address[7]),
+	.D1(a7ddrphy_dfi_p0_address[7]),
+	.D2(a7ddrphy_dfi_p0_address[7]),
+	.D3(a7ddrphy_dfi_p1_address[7]),
+	.D4(a7ddrphy_dfi_p1_address[7]),
+	.D5(a7ddrphy_dfi_p2_address[7]),
+	.D6(a7ddrphy_dfi_p2_address[7]),
+	.D7(a7ddrphy_dfi_p3_address[7]),
+	.D8(a7ddrphy_dfi_p3_address[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[7])
 );
 
@@ -13735,16 +14178,16 @@ OSERDESE2 #(
 ) OSERDESE2_11 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[8]),
-	.D2(main_a7ddrphy_dfi_p0_address[8]),
-	.D3(main_a7ddrphy_dfi_p1_address[8]),
-	.D4(main_a7ddrphy_dfi_p1_address[8]),
-	.D5(main_a7ddrphy_dfi_p2_address[8]),
-	.D6(main_a7ddrphy_dfi_p2_address[8]),
-	.D7(main_a7ddrphy_dfi_p3_address[8]),
-	.D8(main_a7ddrphy_dfi_p3_address[8]),
+	.D1(a7ddrphy_dfi_p0_address[8]),
+	.D2(a7ddrphy_dfi_p0_address[8]),
+	.D3(a7ddrphy_dfi_p1_address[8]),
+	.D4(a7ddrphy_dfi_p1_address[8]),
+	.D5(a7ddrphy_dfi_p2_address[8]),
+	.D6(a7ddrphy_dfi_p2_address[8]),
+	.D7(a7ddrphy_dfi_p3_address[8]),
+	.D8(a7ddrphy_dfi_p3_address[8]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[8])
 );
 
@@ -13757,16 +14200,16 @@ OSERDESE2 #(
 ) OSERDESE2_12 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[9]),
-	.D2(main_a7ddrphy_dfi_p0_address[9]),
-	.D3(main_a7ddrphy_dfi_p1_address[9]),
-	.D4(main_a7ddrphy_dfi_p1_address[9]),
-	.D5(main_a7ddrphy_dfi_p2_address[9]),
-	.D6(main_a7ddrphy_dfi_p2_address[9]),
-	.D7(main_a7ddrphy_dfi_p3_address[9]),
-	.D8(main_a7ddrphy_dfi_p3_address[9]),
+	.D1(a7ddrphy_dfi_p0_address[9]),
+	.D2(a7ddrphy_dfi_p0_address[9]),
+	.D3(a7ddrphy_dfi_p1_address[9]),
+	.D4(a7ddrphy_dfi_p1_address[9]),
+	.D5(a7ddrphy_dfi_p2_address[9]),
+	.D6(a7ddrphy_dfi_p2_address[9]),
+	.D7(a7ddrphy_dfi_p3_address[9]),
+	.D8(a7ddrphy_dfi_p3_address[9]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[9])
 );
 
@@ -13779,16 +14222,16 @@ OSERDESE2 #(
 ) OSERDESE2_13 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[10]),
-	.D2(main_a7ddrphy_dfi_p0_address[10]),
-	.D3(main_a7ddrphy_dfi_p1_address[10]),
-	.D4(main_a7ddrphy_dfi_p1_address[10]),
-	.D5(main_a7ddrphy_dfi_p2_address[10]),
-	.D6(main_a7ddrphy_dfi_p2_address[10]),
-	.D7(main_a7ddrphy_dfi_p3_address[10]),
-	.D8(main_a7ddrphy_dfi_p3_address[10]),
+	.D1(a7ddrphy_dfi_p0_address[10]),
+	.D2(a7ddrphy_dfi_p0_address[10]),
+	.D3(a7ddrphy_dfi_p1_address[10]),
+	.D4(a7ddrphy_dfi_p1_address[10]),
+	.D5(a7ddrphy_dfi_p2_address[10]),
+	.D6(a7ddrphy_dfi_p2_address[10]),
+	.D7(a7ddrphy_dfi_p3_address[10]),
+	.D8(a7ddrphy_dfi_p3_address[10]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[10])
 );
 
@@ -13801,16 +14244,16 @@ OSERDESE2 #(
 ) OSERDESE2_14 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[11]),
-	.D2(main_a7ddrphy_dfi_p0_address[11]),
-	.D3(main_a7ddrphy_dfi_p1_address[11]),
-	.D4(main_a7ddrphy_dfi_p1_address[11]),
-	.D5(main_a7ddrphy_dfi_p2_address[11]),
-	.D6(main_a7ddrphy_dfi_p2_address[11]),
-	.D7(main_a7ddrphy_dfi_p3_address[11]),
-	.D8(main_a7ddrphy_dfi_p3_address[11]),
+	.D1(a7ddrphy_dfi_p0_address[11]),
+	.D2(a7ddrphy_dfi_p0_address[11]),
+	.D3(a7ddrphy_dfi_p1_address[11]),
+	.D4(a7ddrphy_dfi_p1_address[11]),
+	.D5(a7ddrphy_dfi_p2_address[11]),
+	.D6(a7ddrphy_dfi_p2_address[11]),
+	.D7(a7ddrphy_dfi_p3_address[11]),
+	.D8(a7ddrphy_dfi_p3_address[11]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[11])
 );
 
@@ -13823,16 +14266,16 @@ OSERDESE2 #(
 ) OSERDESE2_15 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[12]),
-	.D2(main_a7ddrphy_dfi_p0_address[12]),
-	.D3(main_a7ddrphy_dfi_p1_address[12]),
-	.D4(main_a7ddrphy_dfi_p1_address[12]),
-	.D5(main_a7ddrphy_dfi_p2_address[12]),
-	.D6(main_a7ddrphy_dfi_p2_address[12]),
-	.D7(main_a7ddrphy_dfi_p3_address[12]),
-	.D8(main_a7ddrphy_dfi_p3_address[12]),
+	.D1(a7ddrphy_dfi_p0_address[12]),
+	.D2(a7ddrphy_dfi_p0_address[12]),
+	.D3(a7ddrphy_dfi_p1_address[12]),
+	.D4(a7ddrphy_dfi_p1_address[12]),
+	.D5(a7ddrphy_dfi_p2_address[12]),
+	.D6(a7ddrphy_dfi_p2_address[12]),
+	.D7(a7ddrphy_dfi_p3_address[12]),
+	.D8(a7ddrphy_dfi_p3_address[12]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[12])
 );
 
@@ -13845,16 +14288,16 @@ OSERDESE2 #(
 ) OSERDESE2_16 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[13]),
-	.D2(main_a7ddrphy_dfi_p0_address[13]),
-	.D3(main_a7ddrphy_dfi_p1_address[13]),
-	.D4(main_a7ddrphy_dfi_p1_address[13]),
-	.D5(main_a7ddrphy_dfi_p2_address[13]),
-	.D6(main_a7ddrphy_dfi_p2_address[13]),
-	.D7(main_a7ddrphy_dfi_p3_address[13]),
-	.D8(main_a7ddrphy_dfi_p3_address[13]),
+	.D1(a7ddrphy_dfi_p0_address[13]),
+	.D2(a7ddrphy_dfi_p0_address[13]),
+	.D3(a7ddrphy_dfi_p1_address[13]),
+	.D4(a7ddrphy_dfi_p1_address[13]),
+	.D5(a7ddrphy_dfi_p2_address[13]),
+	.D6(a7ddrphy_dfi_p2_address[13]),
+	.D7(a7ddrphy_dfi_p3_address[13]),
+	.D8(a7ddrphy_dfi_p3_address[13]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[13])
 );
 
@@ -13867,16 +14310,16 @@ OSERDESE2 #(
 ) OSERDESE2_17 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[14]),
-	.D2(main_a7ddrphy_dfi_p0_address[14]),
-	.D3(main_a7ddrphy_dfi_p1_address[14]),
-	.D4(main_a7ddrphy_dfi_p1_address[14]),
-	.D5(main_a7ddrphy_dfi_p2_address[14]),
-	.D6(main_a7ddrphy_dfi_p2_address[14]),
-	.D7(main_a7ddrphy_dfi_p3_address[14]),
-	.D8(main_a7ddrphy_dfi_p3_address[14]),
+	.D1(a7ddrphy_dfi_p0_address[14]),
+	.D2(a7ddrphy_dfi_p0_address[14]),
+	.D3(a7ddrphy_dfi_p1_address[14]),
+	.D4(a7ddrphy_dfi_p1_address[14]),
+	.D5(a7ddrphy_dfi_p2_address[14]),
+	.D6(a7ddrphy_dfi_p2_address[14]),
+	.D7(a7ddrphy_dfi_p3_address[14]),
+	.D8(a7ddrphy_dfi_p3_address[14]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[14])
 );
 
@@ -13889,17 +14332,17 @@ OSERDESE2 #(
 ) OSERDESE2_18 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[0]),
-	.D2(main_a7ddrphy_dfi_p0_bank[0]),
-	.D3(main_a7ddrphy_dfi_p1_bank[0]),
-	.D4(main_a7ddrphy_dfi_p1_bank[0]),
-	.D5(main_a7ddrphy_dfi_p2_bank[0]),
-	.D6(main_a7ddrphy_dfi_p2_bank[0]),
-	.D7(main_a7ddrphy_dfi_p3_bank[0]),
-	.D8(main_a7ddrphy_dfi_p3_bank[0]),
+	.D1(a7ddrphy_dfi_p0_bank[0]),
+	.D2(a7ddrphy_dfi_p0_bank[0]),
+	.D3(a7ddrphy_dfi_p1_bank[0]),
+	.D4(a7ddrphy_dfi_p1_bank[0]),
+	.D5(a7ddrphy_dfi_p2_bank[0]),
+	.D6(a7ddrphy_dfi_p2_bank[0]),
+	.D7(a7ddrphy_dfi_p3_bank[0]),
+	.D8(a7ddrphy_dfi_p3_bank[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[0])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[0])
 );
 
 OSERDESE2 #(
@@ -13911,17 +14354,17 @@ OSERDESE2 #(
 ) OSERDESE2_19 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[1]),
-	.D2(main_a7ddrphy_dfi_p0_bank[1]),
-	.D3(main_a7ddrphy_dfi_p1_bank[1]),
-	.D4(main_a7ddrphy_dfi_p1_bank[1]),
-	.D5(main_a7ddrphy_dfi_p2_bank[1]),
-	.D6(main_a7ddrphy_dfi_p2_bank[1]),
-	.D7(main_a7ddrphy_dfi_p3_bank[1]),
-	.D8(main_a7ddrphy_dfi_p3_bank[1]),
+	.D1(a7ddrphy_dfi_p0_bank[1]),
+	.D2(a7ddrphy_dfi_p0_bank[1]),
+	.D3(a7ddrphy_dfi_p1_bank[1]),
+	.D4(a7ddrphy_dfi_p1_bank[1]),
+	.D5(a7ddrphy_dfi_p2_bank[1]),
+	.D6(a7ddrphy_dfi_p2_bank[1]),
+	.D7(a7ddrphy_dfi_p3_bank[1]),
+	.D8(a7ddrphy_dfi_p3_bank[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[1])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[1])
 );
 
 OSERDESE2 #(
@@ -13933,17 +14376,17 @@ OSERDESE2 #(
 ) OSERDESE2_20 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[2]),
-	.D2(main_a7ddrphy_dfi_p0_bank[2]),
-	.D3(main_a7ddrphy_dfi_p1_bank[2]),
-	.D4(main_a7ddrphy_dfi_p1_bank[2]),
-	.D5(main_a7ddrphy_dfi_p2_bank[2]),
-	.D6(main_a7ddrphy_dfi_p2_bank[2]),
-	.D7(main_a7ddrphy_dfi_p3_bank[2]),
-	.D8(main_a7ddrphy_dfi_p3_bank[2]),
+	.D1(a7ddrphy_dfi_p0_bank[2]),
+	.D2(a7ddrphy_dfi_p0_bank[2]),
+	.D3(a7ddrphy_dfi_p1_bank[2]),
+	.D4(a7ddrphy_dfi_p1_bank[2]),
+	.D5(a7ddrphy_dfi_p2_bank[2]),
+	.D6(a7ddrphy_dfi_p2_bank[2]),
+	.D7(a7ddrphy_dfi_p3_bank[2]),
+	.D8(a7ddrphy_dfi_p3_bank[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[2])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[2])
 );
 
 OSERDESE2 #(
@@ -13955,16 +14398,16 @@ OSERDESE2 #(
 ) OSERDESE2_21 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_ras_n),
-	.D2(main_a7ddrphy_dfi_p0_ras_n),
-	.D3(main_a7ddrphy_dfi_p1_ras_n),
-	.D4(main_a7ddrphy_dfi_p1_ras_n),
-	.D5(main_a7ddrphy_dfi_p2_ras_n),
-	.D6(main_a7ddrphy_dfi_p2_ras_n),
-	.D7(main_a7ddrphy_dfi_p3_ras_n),
-	.D8(main_a7ddrphy_dfi_p3_ras_n),
+	.D1(a7ddrphy_dfi_p0_ras_n),
+	.D2(a7ddrphy_dfi_p0_ras_n),
+	.D3(a7ddrphy_dfi_p1_ras_n),
+	.D4(a7ddrphy_dfi_p1_ras_n),
+	.D5(a7ddrphy_dfi_p2_ras_n),
+	.D6(a7ddrphy_dfi_p2_ras_n),
+	.D7(a7ddrphy_dfi_p3_ras_n),
+	.D8(a7ddrphy_dfi_p3_ras_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_ras_n)
 );
 
@@ -13977,16 +14420,16 @@ OSERDESE2 #(
 ) OSERDESE2_22 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cas_n),
-	.D2(main_a7ddrphy_dfi_p0_cas_n),
-	.D3(main_a7ddrphy_dfi_p1_cas_n),
-	.D4(main_a7ddrphy_dfi_p1_cas_n),
-	.D5(main_a7ddrphy_dfi_p2_cas_n),
-	.D6(main_a7ddrphy_dfi_p2_cas_n),
-	.D7(main_a7ddrphy_dfi_p3_cas_n),
-	.D8(main_a7ddrphy_dfi_p3_cas_n),
+	.D1(a7ddrphy_dfi_p0_cas_n),
+	.D2(a7ddrphy_dfi_p0_cas_n),
+	.D3(a7ddrphy_dfi_p1_cas_n),
+	.D4(a7ddrphy_dfi_p1_cas_n),
+	.D5(a7ddrphy_dfi_p2_cas_n),
+	.D6(a7ddrphy_dfi_p2_cas_n),
+	.D7(a7ddrphy_dfi_p3_cas_n),
+	.D8(a7ddrphy_dfi_p3_cas_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cas_n)
 );
 
@@ -13999,16 +14442,16 @@ OSERDESE2 #(
 ) OSERDESE2_23 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_we_n),
-	.D2(main_a7ddrphy_dfi_p0_we_n),
-	.D3(main_a7ddrphy_dfi_p1_we_n),
-	.D4(main_a7ddrphy_dfi_p1_we_n),
-	.D5(main_a7ddrphy_dfi_p2_we_n),
-	.D6(main_a7ddrphy_dfi_p2_we_n),
-	.D7(main_a7ddrphy_dfi_p3_we_n),
-	.D8(main_a7ddrphy_dfi_p3_we_n),
+	.D1(a7ddrphy_dfi_p0_we_n),
+	.D2(a7ddrphy_dfi_p0_we_n),
+	.D3(a7ddrphy_dfi_p1_we_n),
+	.D4(a7ddrphy_dfi_p1_we_n),
+	.D5(a7ddrphy_dfi_p2_we_n),
+	.D6(a7ddrphy_dfi_p2_we_n),
+	.D7(a7ddrphy_dfi_p3_we_n),
+	.D8(a7ddrphy_dfi_p3_we_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_we_n)
 );
 
@@ -14021,16 +14464,16 @@ OSERDESE2 #(
 ) OSERDESE2_24 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cke),
-	.D2(main_a7ddrphy_dfi_p0_cke),
-	.D3(main_a7ddrphy_dfi_p1_cke),
-	.D4(main_a7ddrphy_dfi_p1_cke),
-	.D5(main_a7ddrphy_dfi_p2_cke),
-	.D6(main_a7ddrphy_dfi_p2_cke),
-	.D7(main_a7ddrphy_dfi_p3_cke),
-	.D8(main_a7ddrphy_dfi_p3_cke),
+	.D1(a7ddrphy_dfi_p0_cke),
+	.D2(a7ddrphy_dfi_p0_cke),
+	.D3(a7ddrphy_dfi_p1_cke),
+	.D4(a7ddrphy_dfi_p1_cke),
+	.D5(a7ddrphy_dfi_p2_cke),
+	.D6(a7ddrphy_dfi_p2_cke),
+	.D7(a7ddrphy_dfi_p3_cke),
+	.D8(a7ddrphy_dfi_p3_cke),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cke)
 );
 
@@ -14043,16 +14486,16 @@ OSERDESE2 #(
 ) OSERDESE2_25 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_odt),
-	.D2(main_a7ddrphy_dfi_p0_odt),
-	.D3(main_a7ddrphy_dfi_p1_odt),
-	.D4(main_a7ddrphy_dfi_p1_odt),
-	.D5(main_a7ddrphy_dfi_p2_odt),
-	.D6(main_a7ddrphy_dfi_p2_odt),
-	.D7(main_a7ddrphy_dfi_p3_odt),
-	.D8(main_a7ddrphy_dfi_p3_odt),
+	.D1(a7ddrphy_dfi_p0_odt),
+	.D2(a7ddrphy_dfi_p0_odt),
+	.D3(a7ddrphy_dfi_p1_odt),
+	.D4(a7ddrphy_dfi_p1_odt),
+	.D5(a7ddrphy_dfi_p2_odt),
+	.D6(a7ddrphy_dfi_p2_odt),
+	.D7(a7ddrphy_dfi_p3_odt),
+	.D8(a7ddrphy_dfi_p3_odt),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_odt)
 );
 
@@ -14065,26 +14508,26 @@ OSERDESE2 #(
 ) OSERDESE2_26 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip00[0]),
-	.D2(main_a7ddrphy_bitslip00[1]),
-	.D3(main_a7ddrphy_bitslip00[2]),
-	.D4(main_a7ddrphy_bitslip00[3]),
-	.D5(main_a7ddrphy_bitslip00[4]),
-	.D6(main_a7ddrphy_bitslip00[5]),
-	.D7(main_a7ddrphy_bitslip00[6]),
-	.D8(main_a7ddrphy_bitslip00[7]),
+	.D1(a7ddrphy_bitslip00[0]),
+	.D2(a7ddrphy_bitslip00[1]),
+	.D3(a7ddrphy_bitslip00[2]),
+	.D4(a7ddrphy_bitslip00[3]),
+	.D5(a7ddrphy_bitslip00[4]),
+	.D6(a7ddrphy_bitslip00[5]),
+	.D7(a7ddrphy_bitslip00[6]),
+	.D8(a7ddrphy_bitslip00[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy0),
-	.OQ(main_a7ddrphy_dqs_o_no_delay0),
-	.TQ(main_a7ddrphy_dqs_t0)
+	.OFB(a7ddrphy0),
+	.OQ(a7ddrphy_dqs_o_no_delay0),
+	.TQ(a7ddrphy_dqs_t0)
 );
 
 IOBUFDS IOBUFDS(
-	.I(main_a7ddrphy_dqs_o_no_delay0),
-	.T(main_a7ddrphy_dqs_t0),
+	.I(a7ddrphy_dqs_o_no_delay0),
+	.T(a7ddrphy_dqs_t0),
 	.IO(ddram_dqs_p[0]),
 	.IOB(ddram_dqs_n[0])
 );
@@ -14098,26 +14541,26 @@ OSERDESE2 #(
 ) OSERDESE2_27 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip10[0]),
-	.D2(main_a7ddrphy_bitslip10[1]),
-	.D3(main_a7ddrphy_bitslip10[2]),
-	.D4(main_a7ddrphy_bitslip10[3]),
-	.D5(main_a7ddrphy_bitslip10[4]),
-	.D6(main_a7ddrphy_bitslip10[5]),
-	.D7(main_a7ddrphy_bitslip10[6]),
-	.D8(main_a7ddrphy_bitslip10[7]),
+	.D1(a7ddrphy_bitslip10[0]),
+	.D2(a7ddrphy_bitslip10[1]),
+	.D3(a7ddrphy_bitslip10[2]),
+	.D4(a7ddrphy_bitslip10[3]),
+	.D5(a7ddrphy_bitslip10[4]),
+	.D6(a7ddrphy_bitslip10[5]),
+	.D7(a7ddrphy_bitslip10[6]),
+	.D8(a7ddrphy_bitslip10[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy1),
-	.OQ(main_a7ddrphy_dqs_o_no_delay1),
-	.TQ(main_a7ddrphy_dqs_t1)
+	.OFB(a7ddrphy1),
+	.OQ(a7ddrphy_dqs_o_no_delay1),
+	.TQ(a7ddrphy_dqs_t1)
 );
 
 IOBUFDS IOBUFDS_1(
-	.I(main_a7ddrphy_dqs_o_no_delay1),
-	.T(main_a7ddrphy_dqs_t1),
+	.I(a7ddrphy_dqs_o_no_delay1),
+	.T(a7ddrphy_dqs_t1),
 	.IO(ddram_dqs_p[1]),
 	.IOB(ddram_dqs_n[1])
 );
@@ -14131,16 +14574,16 @@ OSERDESE2 #(
 ) OSERDESE2_28 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip01[0]),
-	.D2(main_a7ddrphy_bitslip01[1]),
-	.D3(main_a7ddrphy_bitslip01[2]),
-	.D4(main_a7ddrphy_bitslip01[3]),
-	.D5(main_a7ddrphy_bitslip01[4]),
-	.D6(main_a7ddrphy_bitslip01[5]),
-	.D7(main_a7ddrphy_bitslip01[6]),
-	.D8(main_a7ddrphy_bitslip01[7]),
+	.D1(a7ddrphy_bitslip01[0]),
+	.D2(a7ddrphy_bitslip01[1]),
+	.D3(a7ddrphy_bitslip01[2]),
+	.D4(a7ddrphy_bitslip01[3]),
+	.D5(a7ddrphy_bitslip01[4]),
+	.D6(a7ddrphy_bitslip01[5]),
+	.D7(a7ddrphy_bitslip01[6]),
+	.D8(a7ddrphy_bitslip01[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[0])
 );
 
@@ -14153,16 +14596,16 @@ OSERDESE2 #(
 ) OSERDESE2_29 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip11[0]),
-	.D2(main_a7ddrphy_bitslip11[1]),
-	.D3(main_a7ddrphy_bitslip11[2]),
-	.D4(main_a7ddrphy_bitslip11[3]),
-	.D5(main_a7ddrphy_bitslip11[4]),
-	.D6(main_a7ddrphy_bitslip11[5]),
-	.D7(main_a7ddrphy_bitslip11[6]),
-	.D8(main_a7ddrphy_bitslip11[7]),
+	.D1(a7ddrphy_bitslip11[0]),
+	.D2(a7ddrphy_bitslip11[1]),
+	.D3(a7ddrphy_bitslip11[2]),
+	.D4(a7ddrphy_bitslip11[3]),
+	.D5(a7ddrphy_bitslip11[4]),
+	.D6(a7ddrphy_bitslip11[5]),
+	.D7(a7ddrphy_bitslip11[6]),
+	.D8(a7ddrphy_bitslip11[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[1])
 );
 
@@ -14175,20 +14618,20 @@ OSERDESE2 #(
 ) OSERDESE2_30 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip02[0]),
-	.D2(main_a7ddrphy_bitslip02[1]),
-	.D3(main_a7ddrphy_bitslip02[2]),
-	.D4(main_a7ddrphy_bitslip02[3]),
-	.D5(main_a7ddrphy_bitslip02[4]),
-	.D6(main_a7ddrphy_bitslip02[5]),
-	.D7(main_a7ddrphy_bitslip02[6]),
-	.D8(main_a7ddrphy_bitslip02[7]),
+	.D1(a7ddrphy_bitslip02[0]),
+	.D2(a7ddrphy_bitslip02[1]),
+	.D3(a7ddrphy_bitslip02[2]),
+	.D4(a7ddrphy_bitslip02[3]),
+	.D5(a7ddrphy_bitslip02[4]),
+	.D6(a7ddrphy_bitslip02[5]),
+	.D7(a7ddrphy_bitslip02[6]),
+	.D8(a7ddrphy_bitslip02[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay0),
-	.TQ(main_a7ddrphy_dq_t0)
+	.OQ(a7ddrphy_dq_o_nodelay0),
+	.TQ(a7ddrphy_dq_t0)
 );
 
 ISERDESE2 #(
@@ -14204,16 +14647,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip03[7]),
-	.Q2(main_a7ddrphy_bitslip03[6]),
-	.Q3(main_a7ddrphy_bitslip03[5]),
-	.Q4(main_a7ddrphy_bitslip03[4]),
-	.Q5(main_a7ddrphy_bitslip03[3]),
-	.Q6(main_a7ddrphy_bitslip03[2]),
-	.Q7(main_a7ddrphy_bitslip03[1]),
-	.Q8(main_a7ddrphy_bitslip03[0])
+	.DDLY(a7ddrphy_dq_i_delayed0),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip03[7]),
+	.Q2(a7ddrphy_bitslip03[6]),
+	.Q3(a7ddrphy_bitslip03[5]),
+	.Q4(a7ddrphy_bitslip03[4]),
+	.Q5(a7ddrphy_bitslip03[3]),
+	.Q6(a7ddrphy_bitslip03[2]),
+	.Q7(a7ddrphy_bitslip03[1]),
+	.Q8(a7ddrphy_bitslip03[0])
 );
 
 IDELAYE2 #(
@@ -14227,19 +14670,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay0),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay0),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed0)
+	.DATAOUT(a7ddrphy_dq_i_delayed0)
 );
 
 IOBUF IOBUF(
-	.I(main_a7ddrphy_dq_o_nodelay0),
-	.T(main_a7ddrphy_dq_t0),
+	.I(a7ddrphy_dq_o_nodelay0),
+	.T(a7ddrphy_dq_t0),
 	.IO(ddram_dq[0]),
-	.O(main_a7ddrphy_dq_i_nodelay0)
+	.O(a7ddrphy_dq_i_nodelay0)
 );
 
 OSERDESE2 #(
@@ -14251,20 +14694,20 @@ OSERDESE2 #(
 ) OSERDESE2_31 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip12[0]),
-	.D2(main_a7ddrphy_bitslip12[1]),
-	.D3(main_a7ddrphy_bitslip12[2]),
-	.D4(main_a7ddrphy_bitslip12[3]),
-	.D5(main_a7ddrphy_bitslip12[4]),
-	.D6(main_a7ddrphy_bitslip12[5]),
-	.D7(main_a7ddrphy_bitslip12[6]),
-	.D8(main_a7ddrphy_bitslip12[7]),
+	.D1(a7ddrphy_bitslip12[0]),
+	.D2(a7ddrphy_bitslip12[1]),
+	.D3(a7ddrphy_bitslip12[2]),
+	.D4(a7ddrphy_bitslip12[3]),
+	.D5(a7ddrphy_bitslip12[4]),
+	.D6(a7ddrphy_bitslip12[5]),
+	.D7(a7ddrphy_bitslip12[6]),
+	.D8(a7ddrphy_bitslip12[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay1),
-	.TQ(main_a7ddrphy_dq_t1)
+	.OQ(a7ddrphy_dq_o_nodelay1),
+	.TQ(a7ddrphy_dq_t1)
 );
 
 ISERDESE2 #(
@@ -14280,16 +14723,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip13[7]),
-	.Q2(main_a7ddrphy_bitslip13[6]),
-	.Q3(main_a7ddrphy_bitslip13[5]),
-	.Q4(main_a7ddrphy_bitslip13[4]),
-	.Q5(main_a7ddrphy_bitslip13[3]),
-	.Q6(main_a7ddrphy_bitslip13[2]),
-	.Q7(main_a7ddrphy_bitslip13[1]),
-	.Q8(main_a7ddrphy_bitslip13[0])
+	.DDLY(a7ddrphy_dq_i_delayed1),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip13[7]),
+	.Q2(a7ddrphy_bitslip13[6]),
+	.Q3(a7ddrphy_bitslip13[5]),
+	.Q4(a7ddrphy_bitslip13[4]),
+	.Q5(a7ddrphy_bitslip13[3]),
+	.Q6(a7ddrphy_bitslip13[2]),
+	.Q7(a7ddrphy_bitslip13[1]),
+	.Q8(a7ddrphy_bitslip13[0])
 );
 
 IDELAYE2 #(
@@ -14303,19 +14746,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_1 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay1),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay1),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed1)
+	.DATAOUT(a7ddrphy_dq_i_delayed1)
 );
 
 IOBUF IOBUF_1(
-	.I(main_a7ddrphy_dq_o_nodelay1),
-	.T(main_a7ddrphy_dq_t1),
+	.I(a7ddrphy_dq_o_nodelay1),
+	.T(a7ddrphy_dq_t1),
 	.IO(ddram_dq[1]),
-	.O(main_a7ddrphy_dq_i_nodelay1)
+	.O(a7ddrphy_dq_i_nodelay1)
 );
 
 OSERDESE2 #(
@@ -14327,20 +14770,20 @@ OSERDESE2 #(
 ) OSERDESE2_32 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip20[0]),
-	.D2(main_a7ddrphy_bitslip20[1]),
-	.D3(main_a7ddrphy_bitslip20[2]),
-	.D4(main_a7ddrphy_bitslip20[3]),
-	.D5(main_a7ddrphy_bitslip20[4]),
-	.D6(main_a7ddrphy_bitslip20[5]),
-	.D7(main_a7ddrphy_bitslip20[6]),
-	.D8(main_a7ddrphy_bitslip20[7]),
+	.D1(a7ddrphy_bitslip20[0]),
+	.D2(a7ddrphy_bitslip20[1]),
+	.D3(a7ddrphy_bitslip20[2]),
+	.D4(a7ddrphy_bitslip20[3]),
+	.D5(a7ddrphy_bitslip20[4]),
+	.D6(a7ddrphy_bitslip20[5]),
+	.D7(a7ddrphy_bitslip20[6]),
+	.D8(a7ddrphy_bitslip20[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay2),
-	.TQ(main_a7ddrphy_dq_t2)
+	.OQ(a7ddrphy_dq_o_nodelay2),
+	.TQ(a7ddrphy_dq_t2)
 );
 
 ISERDESE2 #(
@@ -14356,16 +14799,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip21[7]),
-	.Q2(main_a7ddrphy_bitslip21[6]),
-	.Q3(main_a7ddrphy_bitslip21[5]),
-	.Q4(main_a7ddrphy_bitslip21[4]),
-	.Q5(main_a7ddrphy_bitslip21[3]),
-	.Q6(main_a7ddrphy_bitslip21[2]),
-	.Q7(main_a7ddrphy_bitslip21[1]),
-	.Q8(main_a7ddrphy_bitslip21[0])
+	.DDLY(a7ddrphy_dq_i_delayed2),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip21[7]),
+	.Q2(a7ddrphy_bitslip21[6]),
+	.Q3(a7ddrphy_bitslip21[5]),
+	.Q4(a7ddrphy_bitslip21[4]),
+	.Q5(a7ddrphy_bitslip21[3]),
+	.Q6(a7ddrphy_bitslip21[2]),
+	.Q7(a7ddrphy_bitslip21[1]),
+	.Q8(a7ddrphy_bitslip21[0])
 );
 
 IDELAYE2 #(
@@ -14379,19 +14822,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay2),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay2),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed2)
+	.DATAOUT(a7ddrphy_dq_i_delayed2)
 );
 
 IOBUF IOBUF_2(
-	.I(main_a7ddrphy_dq_o_nodelay2),
-	.T(main_a7ddrphy_dq_t2),
+	.I(a7ddrphy_dq_o_nodelay2),
+	.T(a7ddrphy_dq_t2),
 	.IO(ddram_dq[2]),
-	.O(main_a7ddrphy_dq_i_nodelay2)
+	.O(a7ddrphy_dq_i_nodelay2)
 );
 
 OSERDESE2 #(
@@ -14403,20 +14846,20 @@ OSERDESE2 #(
 ) OSERDESE2_33 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip30[0]),
-	.D2(main_a7ddrphy_bitslip30[1]),
-	.D3(main_a7ddrphy_bitslip30[2]),
-	.D4(main_a7ddrphy_bitslip30[3]),
-	.D5(main_a7ddrphy_bitslip30[4]),
-	.D6(main_a7ddrphy_bitslip30[5]),
-	.D7(main_a7ddrphy_bitslip30[6]),
-	.D8(main_a7ddrphy_bitslip30[7]),
+	.D1(a7ddrphy_bitslip30[0]),
+	.D2(a7ddrphy_bitslip30[1]),
+	.D3(a7ddrphy_bitslip30[2]),
+	.D4(a7ddrphy_bitslip30[3]),
+	.D5(a7ddrphy_bitslip30[4]),
+	.D6(a7ddrphy_bitslip30[5]),
+	.D7(a7ddrphy_bitslip30[6]),
+	.D8(a7ddrphy_bitslip30[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay3),
-	.TQ(main_a7ddrphy_dq_t3)
+	.OQ(a7ddrphy_dq_o_nodelay3),
+	.TQ(a7ddrphy_dq_t3)
 );
 
 ISERDESE2 #(
@@ -14432,16 +14875,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip31[7]),
-	.Q2(main_a7ddrphy_bitslip31[6]),
-	.Q3(main_a7ddrphy_bitslip31[5]),
-	.Q4(main_a7ddrphy_bitslip31[4]),
-	.Q5(main_a7ddrphy_bitslip31[3]),
-	.Q6(main_a7ddrphy_bitslip31[2]),
-	.Q7(main_a7ddrphy_bitslip31[1]),
-	.Q8(main_a7ddrphy_bitslip31[0])
+	.DDLY(a7ddrphy_dq_i_delayed3),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip31[7]),
+	.Q2(a7ddrphy_bitslip31[6]),
+	.Q3(a7ddrphy_bitslip31[5]),
+	.Q4(a7ddrphy_bitslip31[4]),
+	.Q5(a7ddrphy_bitslip31[3]),
+	.Q6(a7ddrphy_bitslip31[2]),
+	.Q7(a7ddrphy_bitslip31[1]),
+	.Q8(a7ddrphy_bitslip31[0])
 );
 
 IDELAYE2 #(
@@ -14455,19 +14898,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_3 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay3),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay3),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed3)
+	.DATAOUT(a7ddrphy_dq_i_delayed3)
 );
 
 IOBUF IOBUF_3(
-	.I(main_a7ddrphy_dq_o_nodelay3),
-	.T(main_a7ddrphy_dq_t3),
+	.I(a7ddrphy_dq_o_nodelay3),
+	.T(a7ddrphy_dq_t3),
 	.IO(ddram_dq[3]),
-	.O(main_a7ddrphy_dq_i_nodelay3)
+	.O(a7ddrphy_dq_i_nodelay3)
 );
 
 OSERDESE2 #(
@@ -14479,20 +14922,20 @@ OSERDESE2 #(
 ) OSERDESE2_34 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip40[0]),
-	.D2(main_a7ddrphy_bitslip40[1]),
-	.D3(main_a7ddrphy_bitslip40[2]),
-	.D4(main_a7ddrphy_bitslip40[3]),
-	.D5(main_a7ddrphy_bitslip40[4]),
-	.D6(main_a7ddrphy_bitslip40[5]),
-	.D7(main_a7ddrphy_bitslip40[6]),
-	.D8(main_a7ddrphy_bitslip40[7]),
+	.D1(a7ddrphy_bitslip40[0]),
+	.D2(a7ddrphy_bitslip40[1]),
+	.D3(a7ddrphy_bitslip40[2]),
+	.D4(a7ddrphy_bitslip40[3]),
+	.D5(a7ddrphy_bitslip40[4]),
+	.D6(a7ddrphy_bitslip40[5]),
+	.D7(a7ddrphy_bitslip40[6]),
+	.D8(a7ddrphy_bitslip40[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay4),
-	.TQ(main_a7ddrphy_dq_t4)
+	.OQ(a7ddrphy_dq_o_nodelay4),
+	.TQ(a7ddrphy_dq_t4)
 );
 
 ISERDESE2 #(
@@ -14508,16 +14951,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip41[7]),
-	.Q2(main_a7ddrphy_bitslip41[6]),
-	.Q3(main_a7ddrphy_bitslip41[5]),
-	.Q4(main_a7ddrphy_bitslip41[4]),
-	.Q5(main_a7ddrphy_bitslip41[3]),
-	.Q6(main_a7ddrphy_bitslip41[2]),
-	.Q7(main_a7ddrphy_bitslip41[1]),
-	.Q8(main_a7ddrphy_bitslip41[0])
+	.DDLY(a7ddrphy_dq_i_delayed4),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip41[7]),
+	.Q2(a7ddrphy_bitslip41[6]),
+	.Q3(a7ddrphy_bitslip41[5]),
+	.Q4(a7ddrphy_bitslip41[4]),
+	.Q5(a7ddrphy_bitslip41[3]),
+	.Q6(a7ddrphy_bitslip41[2]),
+	.Q7(a7ddrphy_bitslip41[1]),
+	.Q8(a7ddrphy_bitslip41[0])
 );
 
 IDELAYE2 #(
@@ -14531,19 +14974,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_4 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay4),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay4),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed4)
+	.DATAOUT(a7ddrphy_dq_i_delayed4)
 );
 
 IOBUF IOBUF_4(
-	.I(main_a7ddrphy_dq_o_nodelay4),
-	.T(main_a7ddrphy_dq_t4),
+	.I(a7ddrphy_dq_o_nodelay4),
+	.T(a7ddrphy_dq_t4),
 	.IO(ddram_dq[4]),
-	.O(main_a7ddrphy_dq_i_nodelay4)
+	.O(a7ddrphy_dq_i_nodelay4)
 );
 
 OSERDESE2 #(
@@ -14555,20 +14998,20 @@ OSERDESE2 #(
 ) OSERDESE2_35 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip50[0]),
-	.D2(main_a7ddrphy_bitslip50[1]),
-	.D3(main_a7ddrphy_bitslip50[2]),
-	.D4(main_a7ddrphy_bitslip50[3]),
-	.D5(main_a7ddrphy_bitslip50[4]),
-	.D6(main_a7ddrphy_bitslip50[5]),
-	.D7(main_a7ddrphy_bitslip50[6]),
-	.D8(main_a7ddrphy_bitslip50[7]),
+	.D1(a7ddrphy_bitslip50[0]),
+	.D2(a7ddrphy_bitslip50[1]),
+	.D3(a7ddrphy_bitslip50[2]),
+	.D4(a7ddrphy_bitslip50[3]),
+	.D5(a7ddrphy_bitslip50[4]),
+	.D6(a7ddrphy_bitslip50[5]),
+	.D7(a7ddrphy_bitslip50[6]),
+	.D8(a7ddrphy_bitslip50[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay5),
-	.TQ(main_a7ddrphy_dq_t5)
+	.OQ(a7ddrphy_dq_o_nodelay5),
+	.TQ(a7ddrphy_dq_t5)
 );
 
 ISERDESE2 #(
@@ -14584,16 +15027,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip51[7]),
-	.Q2(main_a7ddrphy_bitslip51[6]),
-	.Q3(main_a7ddrphy_bitslip51[5]),
-	.Q4(main_a7ddrphy_bitslip51[4]),
-	.Q5(main_a7ddrphy_bitslip51[3]),
-	.Q6(main_a7ddrphy_bitslip51[2]),
-	.Q7(main_a7ddrphy_bitslip51[1]),
-	.Q8(main_a7ddrphy_bitslip51[0])
+	.DDLY(a7ddrphy_dq_i_delayed5),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip51[7]),
+	.Q2(a7ddrphy_bitslip51[6]),
+	.Q3(a7ddrphy_bitslip51[5]),
+	.Q4(a7ddrphy_bitslip51[4]),
+	.Q5(a7ddrphy_bitslip51[3]),
+	.Q6(a7ddrphy_bitslip51[2]),
+	.Q7(a7ddrphy_bitslip51[1]),
+	.Q8(a7ddrphy_bitslip51[0])
 );
 
 IDELAYE2 #(
@@ -14607,19 +15050,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_5 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay5),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay5),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed5)
+	.DATAOUT(a7ddrphy_dq_i_delayed5)
 );
 
 IOBUF IOBUF_5(
-	.I(main_a7ddrphy_dq_o_nodelay5),
-	.T(main_a7ddrphy_dq_t5),
+	.I(a7ddrphy_dq_o_nodelay5),
+	.T(a7ddrphy_dq_t5),
 	.IO(ddram_dq[5]),
-	.O(main_a7ddrphy_dq_i_nodelay5)
+	.O(a7ddrphy_dq_i_nodelay5)
 );
 
 OSERDESE2 #(
@@ -14631,20 +15074,20 @@ OSERDESE2 #(
 ) OSERDESE2_36 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip60[0]),
-	.D2(main_a7ddrphy_bitslip60[1]),
-	.D3(main_a7ddrphy_bitslip60[2]),
-	.D4(main_a7ddrphy_bitslip60[3]),
-	.D5(main_a7ddrphy_bitslip60[4]),
-	.D6(main_a7ddrphy_bitslip60[5]),
-	.D7(main_a7ddrphy_bitslip60[6]),
-	.D8(main_a7ddrphy_bitslip60[7]),
+	.D1(a7ddrphy_bitslip60[0]),
+	.D2(a7ddrphy_bitslip60[1]),
+	.D3(a7ddrphy_bitslip60[2]),
+	.D4(a7ddrphy_bitslip60[3]),
+	.D5(a7ddrphy_bitslip60[4]),
+	.D6(a7ddrphy_bitslip60[5]),
+	.D7(a7ddrphy_bitslip60[6]),
+	.D8(a7ddrphy_bitslip60[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay6),
-	.TQ(main_a7ddrphy_dq_t6)
+	.OQ(a7ddrphy_dq_o_nodelay6),
+	.TQ(a7ddrphy_dq_t6)
 );
 
 ISERDESE2 #(
@@ -14660,16 +15103,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip61[7]),
-	.Q2(main_a7ddrphy_bitslip61[6]),
-	.Q3(main_a7ddrphy_bitslip61[5]),
-	.Q4(main_a7ddrphy_bitslip61[4]),
-	.Q5(main_a7ddrphy_bitslip61[3]),
-	.Q6(main_a7ddrphy_bitslip61[2]),
-	.Q7(main_a7ddrphy_bitslip61[1]),
-	.Q8(main_a7ddrphy_bitslip61[0])
+	.DDLY(a7ddrphy_dq_i_delayed6),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip61[7]),
+	.Q2(a7ddrphy_bitslip61[6]),
+	.Q3(a7ddrphy_bitslip61[5]),
+	.Q4(a7ddrphy_bitslip61[4]),
+	.Q5(a7ddrphy_bitslip61[3]),
+	.Q6(a7ddrphy_bitslip61[2]),
+	.Q7(a7ddrphy_bitslip61[1]),
+	.Q8(a7ddrphy_bitslip61[0])
 );
 
 IDELAYE2 #(
@@ -14683,19 +15126,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_6 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay6),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay6),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed6)
+	.DATAOUT(a7ddrphy_dq_i_delayed6)
 );
 
 IOBUF IOBUF_6(
-	.I(main_a7ddrphy_dq_o_nodelay6),
-	.T(main_a7ddrphy_dq_t6),
+	.I(a7ddrphy_dq_o_nodelay6),
+	.T(a7ddrphy_dq_t6),
 	.IO(ddram_dq[6]),
-	.O(main_a7ddrphy_dq_i_nodelay6)
+	.O(a7ddrphy_dq_i_nodelay6)
 );
 
 OSERDESE2 #(
@@ -14707,20 +15150,20 @@ OSERDESE2 #(
 ) OSERDESE2_37 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip70[0]),
-	.D2(main_a7ddrphy_bitslip70[1]),
-	.D3(main_a7ddrphy_bitslip70[2]),
-	.D4(main_a7ddrphy_bitslip70[3]),
-	.D5(main_a7ddrphy_bitslip70[4]),
-	.D6(main_a7ddrphy_bitslip70[5]),
-	.D7(main_a7ddrphy_bitslip70[6]),
-	.D8(main_a7ddrphy_bitslip70[7]),
+	.D1(a7ddrphy_bitslip70[0]),
+	.D2(a7ddrphy_bitslip70[1]),
+	.D3(a7ddrphy_bitslip70[2]),
+	.D4(a7ddrphy_bitslip70[3]),
+	.D5(a7ddrphy_bitslip70[4]),
+	.D6(a7ddrphy_bitslip70[5]),
+	.D7(a7ddrphy_bitslip70[6]),
+	.D8(a7ddrphy_bitslip70[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay7),
-	.TQ(main_a7ddrphy_dq_t7)
+	.OQ(a7ddrphy_dq_o_nodelay7),
+	.TQ(a7ddrphy_dq_t7)
 );
 
 ISERDESE2 #(
@@ -14736,16 +15179,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip71[7]),
-	.Q2(main_a7ddrphy_bitslip71[6]),
-	.Q3(main_a7ddrphy_bitslip71[5]),
-	.Q4(main_a7ddrphy_bitslip71[4]),
-	.Q5(main_a7ddrphy_bitslip71[3]),
-	.Q6(main_a7ddrphy_bitslip71[2]),
-	.Q7(main_a7ddrphy_bitslip71[1]),
-	.Q8(main_a7ddrphy_bitslip71[0])
+	.DDLY(a7ddrphy_dq_i_delayed7),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip71[7]),
+	.Q2(a7ddrphy_bitslip71[6]),
+	.Q3(a7ddrphy_bitslip71[5]),
+	.Q4(a7ddrphy_bitslip71[4]),
+	.Q5(a7ddrphy_bitslip71[3]),
+	.Q6(a7ddrphy_bitslip71[2]),
+	.Q7(a7ddrphy_bitslip71[1]),
+	.Q8(a7ddrphy_bitslip71[0])
 );
 
 IDELAYE2 #(
@@ -14759,19 +15202,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_7 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay7),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay7),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed7)
+	.DATAOUT(a7ddrphy_dq_i_delayed7)
 );
 
 IOBUF IOBUF_7(
-	.I(main_a7ddrphy_dq_o_nodelay7),
-	.T(main_a7ddrphy_dq_t7),
+	.I(a7ddrphy_dq_o_nodelay7),
+	.T(a7ddrphy_dq_t7),
 	.IO(ddram_dq[7]),
-	.O(main_a7ddrphy_dq_i_nodelay7)
+	.O(a7ddrphy_dq_i_nodelay7)
 );
 
 OSERDESE2 #(
@@ -14783,20 +15226,20 @@ OSERDESE2 #(
 ) OSERDESE2_38 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip80[0]),
-	.D2(main_a7ddrphy_bitslip80[1]),
-	.D3(main_a7ddrphy_bitslip80[2]),
-	.D4(main_a7ddrphy_bitslip80[3]),
-	.D5(main_a7ddrphy_bitslip80[4]),
-	.D6(main_a7ddrphy_bitslip80[5]),
-	.D7(main_a7ddrphy_bitslip80[6]),
-	.D8(main_a7ddrphy_bitslip80[7]),
+	.D1(a7ddrphy_bitslip80[0]),
+	.D2(a7ddrphy_bitslip80[1]),
+	.D3(a7ddrphy_bitslip80[2]),
+	.D4(a7ddrphy_bitslip80[3]),
+	.D5(a7ddrphy_bitslip80[4]),
+	.D6(a7ddrphy_bitslip80[5]),
+	.D7(a7ddrphy_bitslip80[6]),
+	.D8(a7ddrphy_bitslip80[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay8),
-	.TQ(main_a7ddrphy_dq_t8)
+	.OQ(a7ddrphy_dq_o_nodelay8),
+	.TQ(a7ddrphy_dq_t8)
 );
 
 ISERDESE2 #(
@@ -14812,16 +15255,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip81[7]),
-	.Q2(main_a7ddrphy_bitslip81[6]),
-	.Q3(main_a7ddrphy_bitslip81[5]),
-	.Q4(main_a7ddrphy_bitslip81[4]),
-	.Q5(main_a7ddrphy_bitslip81[3]),
-	.Q6(main_a7ddrphy_bitslip81[2]),
-	.Q7(main_a7ddrphy_bitslip81[1]),
-	.Q8(main_a7ddrphy_bitslip81[0])
+	.DDLY(a7ddrphy_dq_i_delayed8),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip81[7]),
+	.Q2(a7ddrphy_bitslip81[6]),
+	.Q3(a7ddrphy_bitslip81[5]),
+	.Q4(a7ddrphy_bitslip81[4]),
+	.Q5(a7ddrphy_bitslip81[3]),
+	.Q6(a7ddrphy_bitslip81[2]),
+	.Q7(a7ddrphy_bitslip81[1]),
+	.Q8(a7ddrphy_bitslip81[0])
 );
 
 IDELAYE2 #(
@@ -14835,19 +15278,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_8 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay8),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay8),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed8)
+	.DATAOUT(a7ddrphy_dq_i_delayed8)
 );
 
 IOBUF IOBUF_8(
-	.I(main_a7ddrphy_dq_o_nodelay8),
-	.T(main_a7ddrphy_dq_t8),
+	.I(a7ddrphy_dq_o_nodelay8),
+	.T(a7ddrphy_dq_t8),
 	.IO(ddram_dq[8]),
-	.O(main_a7ddrphy_dq_i_nodelay8)
+	.O(a7ddrphy_dq_i_nodelay8)
 );
 
 OSERDESE2 #(
@@ -14859,20 +15302,20 @@ OSERDESE2 #(
 ) OSERDESE2_39 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip90[0]),
-	.D2(main_a7ddrphy_bitslip90[1]),
-	.D3(main_a7ddrphy_bitslip90[2]),
-	.D4(main_a7ddrphy_bitslip90[3]),
-	.D5(main_a7ddrphy_bitslip90[4]),
-	.D6(main_a7ddrphy_bitslip90[5]),
-	.D7(main_a7ddrphy_bitslip90[6]),
-	.D8(main_a7ddrphy_bitslip90[7]),
+	.D1(a7ddrphy_bitslip90[0]),
+	.D2(a7ddrphy_bitslip90[1]),
+	.D3(a7ddrphy_bitslip90[2]),
+	.D4(a7ddrphy_bitslip90[3]),
+	.D5(a7ddrphy_bitslip90[4]),
+	.D6(a7ddrphy_bitslip90[5]),
+	.D7(a7ddrphy_bitslip90[6]),
+	.D8(a7ddrphy_bitslip90[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay9),
-	.TQ(main_a7ddrphy_dq_t9)
+	.OQ(a7ddrphy_dq_o_nodelay9),
+	.TQ(a7ddrphy_dq_t9)
 );
 
 ISERDESE2 #(
@@ -14888,16 +15331,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip91[7]),
-	.Q2(main_a7ddrphy_bitslip91[6]),
-	.Q3(main_a7ddrphy_bitslip91[5]),
-	.Q4(main_a7ddrphy_bitslip91[4]),
-	.Q5(main_a7ddrphy_bitslip91[3]),
-	.Q6(main_a7ddrphy_bitslip91[2]),
-	.Q7(main_a7ddrphy_bitslip91[1]),
-	.Q8(main_a7ddrphy_bitslip91[0])
+	.DDLY(a7ddrphy_dq_i_delayed9),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip91[7]),
+	.Q2(a7ddrphy_bitslip91[6]),
+	.Q3(a7ddrphy_bitslip91[5]),
+	.Q4(a7ddrphy_bitslip91[4]),
+	.Q5(a7ddrphy_bitslip91[3]),
+	.Q6(a7ddrphy_bitslip91[2]),
+	.Q7(a7ddrphy_bitslip91[1]),
+	.Q8(a7ddrphy_bitslip91[0])
 );
 
 IDELAYE2 #(
@@ -14911,19 +15354,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_9 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay9),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay9),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed9)
+	.DATAOUT(a7ddrphy_dq_i_delayed9)
 );
 
 IOBUF IOBUF_9(
-	.I(main_a7ddrphy_dq_o_nodelay9),
-	.T(main_a7ddrphy_dq_t9),
+	.I(a7ddrphy_dq_o_nodelay9),
+	.T(a7ddrphy_dq_t9),
 	.IO(ddram_dq[9]),
-	.O(main_a7ddrphy_dq_i_nodelay9)
+	.O(a7ddrphy_dq_i_nodelay9)
 );
 
 OSERDESE2 #(
@@ -14935,20 +15378,20 @@ OSERDESE2 #(
 ) OSERDESE2_40 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip100[0]),
-	.D2(main_a7ddrphy_bitslip100[1]),
-	.D3(main_a7ddrphy_bitslip100[2]),
-	.D4(main_a7ddrphy_bitslip100[3]),
-	.D5(main_a7ddrphy_bitslip100[4]),
-	.D6(main_a7ddrphy_bitslip100[5]),
-	.D7(main_a7ddrphy_bitslip100[6]),
-	.D8(main_a7ddrphy_bitslip100[7]),
+	.D1(a7ddrphy_bitslip100[0]),
+	.D2(a7ddrphy_bitslip100[1]),
+	.D3(a7ddrphy_bitslip100[2]),
+	.D4(a7ddrphy_bitslip100[3]),
+	.D5(a7ddrphy_bitslip100[4]),
+	.D6(a7ddrphy_bitslip100[5]),
+	.D7(a7ddrphy_bitslip100[6]),
+	.D8(a7ddrphy_bitslip100[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay10),
-	.TQ(main_a7ddrphy_dq_t10)
+	.OQ(a7ddrphy_dq_o_nodelay10),
+	.TQ(a7ddrphy_dq_t10)
 );
 
 ISERDESE2 #(
@@ -14964,16 +15407,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip101[7]),
-	.Q2(main_a7ddrphy_bitslip101[6]),
-	.Q3(main_a7ddrphy_bitslip101[5]),
-	.Q4(main_a7ddrphy_bitslip101[4]),
-	.Q5(main_a7ddrphy_bitslip101[3]),
-	.Q6(main_a7ddrphy_bitslip101[2]),
-	.Q7(main_a7ddrphy_bitslip101[1]),
-	.Q8(main_a7ddrphy_bitslip101[0])
+	.DDLY(a7ddrphy_dq_i_delayed10),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip101[7]),
+	.Q2(a7ddrphy_bitslip101[6]),
+	.Q3(a7ddrphy_bitslip101[5]),
+	.Q4(a7ddrphy_bitslip101[4]),
+	.Q5(a7ddrphy_bitslip101[3]),
+	.Q6(a7ddrphy_bitslip101[2]),
+	.Q7(a7ddrphy_bitslip101[1]),
+	.Q8(a7ddrphy_bitslip101[0])
 );
 
 IDELAYE2 #(
@@ -14987,19 +15430,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_10 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay10),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay10),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed10)
+	.DATAOUT(a7ddrphy_dq_i_delayed10)
 );
 
 IOBUF IOBUF_10(
-	.I(main_a7ddrphy_dq_o_nodelay10),
-	.T(main_a7ddrphy_dq_t10),
+	.I(a7ddrphy_dq_o_nodelay10),
+	.T(a7ddrphy_dq_t10),
 	.IO(ddram_dq[10]),
-	.O(main_a7ddrphy_dq_i_nodelay10)
+	.O(a7ddrphy_dq_i_nodelay10)
 );
 
 OSERDESE2 #(
@@ -15011,20 +15454,20 @@ OSERDESE2 #(
 ) OSERDESE2_41 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip110[0]),
-	.D2(main_a7ddrphy_bitslip110[1]),
-	.D3(main_a7ddrphy_bitslip110[2]),
-	.D4(main_a7ddrphy_bitslip110[3]),
-	.D5(main_a7ddrphy_bitslip110[4]),
-	.D6(main_a7ddrphy_bitslip110[5]),
-	.D7(main_a7ddrphy_bitslip110[6]),
-	.D8(main_a7ddrphy_bitslip110[7]),
+	.D1(a7ddrphy_bitslip110[0]),
+	.D2(a7ddrphy_bitslip110[1]),
+	.D3(a7ddrphy_bitslip110[2]),
+	.D4(a7ddrphy_bitslip110[3]),
+	.D5(a7ddrphy_bitslip110[4]),
+	.D6(a7ddrphy_bitslip110[5]),
+	.D7(a7ddrphy_bitslip110[6]),
+	.D8(a7ddrphy_bitslip110[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay11),
-	.TQ(main_a7ddrphy_dq_t11)
+	.OQ(a7ddrphy_dq_o_nodelay11),
+	.TQ(a7ddrphy_dq_t11)
 );
 
 ISERDESE2 #(
@@ -15040,16 +15483,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip111[7]),
-	.Q2(main_a7ddrphy_bitslip111[6]),
-	.Q3(main_a7ddrphy_bitslip111[5]),
-	.Q4(main_a7ddrphy_bitslip111[4]),
-	.Q5(main_a7ddrphy_bitslip111[3]),
-	.Q6(main_a7ddrphy_bitslip111[2]),
-	.Q7(main_a7ddrphy_bitslip111[1]),
-	.Q8(main_a7ddrphy_bitslip111[0])
+	.DDLY(a7ddrphy_dq_i_delayed11),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip111[7]),
+	.Q2(a7ddrphy_bitslip111[6]),
+	.Q3(a7ddrphy_bitslip111[5]),
+	.Q4(a7ddrphy_bitslip111[4]),
+	.Q5(a7ddrphy_bitslip111[3]),
+	.Q6(a7ddrphy_bitslip111[2]),
+	.Q7(a7ddrphy_bitslip111[1]),
+	.Q8(a7ddrphy_bitslip111[0])
 );
 
 IDELAYE2 #(
@@ -15063,19 +15506,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_11 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay11),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay11),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed11)
+	.DATAOUT(a7ddrphy_dq_i_delayed11)
 );
 
 IOBUF IOBUF_11(
-	.I(main_a7ddrphy_dq_o_nodelay11),
-	.T(main_a7ddrphy_dq_t11),
+	.I(a7ddrphy_dq_o_nodelay11),
+	.T(a7ddrphy_dq_t11),
 	.IO(ddram_dq[11]),
-	.O(main_a7ddrphy_dq_i_nodelay11)
+	.O(a7ddrphy_dq_i_nodelay11)
 );
 
 OSERDESE2 #(
@@ -15087,20 +15530,20 @@ OSERDESE2 #(
 ) OSERDESE2_42 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip120[0]),
-	.D2(main_a7ddrphy_bitslip120[1]),
-	.D3(main_a7ddrphy_bitslip120[2]),
-	.D4(main_a7ddrphy_bitslip120[3]),
-	.D5(main_a7ddrphy_bitslip120[4]),
-	.D6(main_a7ddrphy_bitslip120[5]),
-	.D7(main_a7ddrphy_bitslip120[6]),
-	.D8(main_a7ddrphy_bitslip120[7]),
+	.D1(a7ddrphy_bitslip120[0]),
+	.D2(a7ddrphy_bitslip120[1]),
+	.D3(a7ddrphy_bitslip120[2]),
+	.D4(a7ddrphy_bitslip120[3]),
+	.D5(a7ddrphy_bitslip120[4]),
+	.D6(a7ddrphy_bitslip120[5]),
+	.D7(a7ddrphy_bitslip120[6]),
+	.D8(a7ddrphy_bitslip120[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay12),
-	.TQ(main_a7ddrphy_dq_t12)
+	.OQ(a7ddrphy_dq_o_nodelay12),
+	.TQ(a7ddrphy_dq_t12)
 );
 
 ISERDESE2 #(
@@ -15116,16 +15559,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip121[7]),
-	.Q2(main_a7ddrphy_bitslip121[6]),
-	.Q3(main_a7ddrphy_bitslip121[5]),
-	.Q4(main_a7ddrphy_bitslip121[4]),
-	.Q5(main_a7ddrphy_bitslip121[3]),
-	.Q6(main_a7ddrphy_bitslip121[2]),
-	.Q7(main_a7ddrphy_bitslip121[1]),
-	.Q8(main_a7ddrphy_bitslip121[0])
+	.DDLY(a7ddrphy_dq_i_delayed12),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip121[7]),
+	.Q2(a7ddrphy_bitslip121[6]),
+	.Q3(a7ddrphy_bitslip121[5]),
+	.Q4(a7ddrphy_bitslip121[4]),
+	.Q5(a7ddrphy_bitslip121[3]),
+	.Q6(a7ddrphy_bitslip121[2]),
+	.Q7(a7ddrphy_bitslip121[1]),
+	.Q8(a7ddrphy_bitslip121[0])
 );
 
 IDELAYE2 #(
@@ -15139,19 +15582,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_12 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay12),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay12),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed12)
+	.DATAOUT(a7ddrphy_dq_i_delayed12)
 );
 
 IOBUF IOBUF_12(
-	.I(main_a7ddrphy_dq_o_nodelay12),
-	.T(main_a7ddrphy_dq_t12),
+	.I(a7ddrphy_dq_o_nodelay12),
+	.T(a7ddrphy_dq_t12),
 	.IO(ddram_dq[12]),
-	.O(main_a7ddrphy_dq_i_nodelay12)
+	.O(a7ddrphy_dq_i_nodelay12)
 );
 
 OSERDESE2 #(
@@ -15163,20 +15606,20 @@ OSERDESE2 #(
 ) OSERDESE2_43 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip130[0]),
-	.D2(main_a7ddrphy_bitslip130[1]),
-	.D3(main_a7ddrphy_bitslip130[2]),
-	.D4(main_a7ddrphy_bitslip130[3]),
-	.D5(main_a7ddrphy_bitslip130[4]),
-	.D6(main_a7ddrphy_bitslip130[5]),
-	.D7(main_a7ddrphy_bitslip130[6]),
-	.D8(main_a7ddrphy_bitslip130[7]),
+	.D1(a7ddrphy_bitslip130[0]),
+	.D2(a7ddrphy_bitslip130[1]),
+	.D3(a7ddrphy_bitslip130[2]),
+	.D4(a7ddrphy_bitslip130[3]),
+	.D5(a7ddrphy_bitslip130[4]),
+	.D6(a7ddrphy_bitslip130[5]),
+	.D7(a7ddrphy_bitslip130[6]),
+	.D8(a7ddrphy_bitslip130[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay13),
-	.TQ(main_a7ddrphy_dq_t13)
+	.OQ(a7ddrphy_dq_o_nodelay13),
+	.TQ(a7ddrphy_dq_t13)
 );
 
 ISERDESE2 #(
@@ -15192,16 +15635,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip131[7]),
-	.Q2(main_a7ddrphy_bitslip131[6]),
-	.Q3(main_a7ddrphy_bitslip131[5]),
-	.Q4(main_a7ddrphy_bitslip131[4]),
-	.Q5(main_a7ddrphy_bitslip131[3]),
-	.Q6(main_a7ddrphy_bitslip131[2]),
-	.Q7(main_a7ddrphy_bitslip131[1]),
-	.Q8(main_a7ddrphy_bitslip131[0])
+	.DDLY(a7ddrphy_dq_i_delayed13),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip131[7]),
+	.Q2(a7ddrphy_bitslip131[6]),
+	.Q3(a7ddrphy_bitslip131[5]),
+	.Q4(a7ddrphy_bitslip131[4]),
+	.Q5(a7ddrphy_bitslip131[3]),
+	.Q6(a7ddrphy_bitslip131[2]),
+	.Q7(a7ddrphy_bitslip131[1]),
+	.Q8(a7ddrphy_bitslip131[0])
 );
 
 IDELAYE2 #(
@@ -15215,19 +15658,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_13 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay13),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay13),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed13)
+	.DATAOUT(a7ddrphy_dq_i_delayed13)
 );
 
 IOBUF IOBUF_13(
-	.I(main_a7ddrphy_dq_o_nodelay13),
-	.T(main_a7ddrphy_dq_t13),
+	.I(a7ddrphy_dq_o_nodelay13),
+	.T(a7ddrphy_dq_t13),
 	.IO(ddram_dq[13]),
-	.O(main_a7ddrphy_dq_i_nodelay13)
+	.O(a7ddrphy_dq_i_nodelay13)
 );
 
 OSERDESE2 #(
@@ -15239,20 +15682,20 @@ OSERDESE2 #(
 ) OSERDESE2_44 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip140[0]),
-	.D2(main_a7ddrphy_bitslip140[1]),
-	.D3(main_a7ddrphy_bitslip140[2]),
-	.D4(main_a7ddrphy_bitslip140[3]),
-	.D5(main_a7ddrphy_bitslip140[4]),
-	.D6(main_a7ddrphy_bitslip140[5]),
-	.D7(main_a7ddrphy_bitslip140[6]),
-	.D8(main_a7ddrphy_bitslip140[7]),
+	.D1(a7ddrphy_bitslip140[0]),
+	.D2(a7ddrphy_bitslip140[1]),
+	.D3(a7ddrphy_bitslip140[2]),
+	.D4(a7ddrphy_bitslip140[3]),
+	.D5(a7ddrphy_bitslip140[4]),
+	.D6(a7ddrphy_bitslip140[5]),
+	.D7(a7ddrphy_bitslip140[6]),
+	.D8(a7ddrphy_bitslip140[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay14),
-	.TQ(main_a7ddrphy_dq_t14)
+	.OQ(a7ddrphy_dq_o_nodelay14),
+	.TQ(a7ddrphy_dq_t14)
 );
 
 ISERDESE2 #(
@@ -15268,16 +15711,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip141[7]),
-	.Q2(main_a7ddrphy_bitslip141[6]),
-	.Q3(main_a7ddrphy_bitslip141[5]),
-	.Q4(main_a7ddrphy_bitslip141[4]),
-	.Q5(main_a7ddrphy_bitslip141[3]),
-	.Q6(main_a7ddrphy_bitslip141[2]),
-	.Q7(main_a7ddrphy_bitslip141[1]),
-	.Q8(main_a7ddrphy_bitslip141[0])
+	.DDLY(a7ddrphy_dq_i_delayed14),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip141[7]),
+	.Q2(a7ddrphy_bitslip141[6]),
+	.Q3(a7ddrphy_bitslip141[5]),
+	.Q4(a7ddrphy_bitslip141[4]),
+	.Q5(a7ddrphy_bitslip141[3]),
+	.Q6(a7ddrphy_bitslip141[2]),
+	.Q7(a7ddrphy_bitslip141[1]),
+	.Q8(a7ddrphy_bitslip141[0])
 );
 
 IDELAYE2 #(
@@ -15291,19 +15734,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_14 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay14),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay14),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed14)
+	.DATAOUT(a7ddrphy_dq_i_delayed14)
 );
 
 IOBUF IOBUF_14(
-	.I(main_a7ddrphy_dq_o_nodelay14),
-	.T(main_a7ddrphy_dq_t14),
+	.I(a7ddrphy_dq_o_nodelay14),
+	.T(a7ddrphy_dq_t14),
 	.IO(ddram_dq[14]),
-	.O(main_a7ddrphy_dq_i_nodelay14)
+	.O(a7ddrphy_dq_i_nodelay14)
 );
 
 OSERDESE2 #(
@@ -15315,20 +15758,20 @@ OSERDESE2 #(
 ) OSERDESE2_45 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip150[0]),
-	.D2(main_a7ddrphy_bitslip150[1]),
-	.D3(main_a7ddrphy_bitslip150[2]),
-	.D4(main_a7ddrphy_bitslip150[3]),
-	.D5(main_a7ddrphy_bitslip150[4]),
-	.D6(main_a7ddrphy_bitslip150[5]),
-	.D7(main_a7ddrphy_bitslip150[6]),
-	.D8(main_a7ddrphy_bitslip150[7]),
+	.D1(a7ddrphy_bitslip150[0]),
+	.D2(a7ddrphy_bitslip150[1]),
+	.D3(a7ddrphy_bitslip150[2]),
+	.D4(a7ddrphy_bitslip150[3]),
+	.D5(a7ddrphy_bitslip150[4]),
+	.D6(a7ddrphy_bitslip150[5]),
+	.D7(a7ddrphy_bitslip150[6]),
+	.D8(a7ddrphy_bitslip150[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay15),
-	.TQ(main_a7ddrphy_dq_t15)
+	.OQ(a7ddrphy_dq_o_nodelay15),
+	.TQ(a7ddrphy_dq_t15)
 );
 
 ISERDESE2 #(
@@ -15344,16 +15787,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip151[7]),
-	.Q2(main_a7ddrphy_bitslip151[6]),
-	.Q3(main_a7ddrphy_bitslip151[5]),
-	.Q4(main_a7ddrphy_bitslip151[4]),
-	.Q5(main_a7ddrphy_bitslip151[3]),
-	.Q6(main_a7ddrphy_bitslip151[2]),
-	.Q7(main_a7ddrphy_bitslip151[1]),
-	.Q8(main_a7ddrphy_bitslip151[0])
+	.DDLY(a7ddrphy_dq_i_delayed15),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip151[7]),
+	.Q2(a7ddrphy_bitslip151[6]),
+	.Q3(a7ddrphy_bitslip151[5]),
+	.Q4(a7ddrphy_bitslip151[4]),
+	.Q5(a7ddrphy_bitslip151[3]),
+	.Q6(a7ddrphy_bitslip151[2]),
+	.Q7(a7ddrphy_bitslip151[1]),
+	.Q8(a7ddrphy_bitslip151[0])
 );
 
 IDELAYE2 #(
@@ -15367,19 +15810,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_15 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay15),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay15),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed15)
+	.DATAOUT(a7ddrphy_dq_i_delayed15)
 );
 
 IOBUF IOBUF_15(
-	.I(main_a7ddrphy_dq_o_nodelay15),
-	.T(main_a7ddrphy_dq_t15),
+	.I(a7ddrphy_dq_o_nodelay15),
+	.T(a7ddrphy_dq_t15),
 	.IO(ddram_dq[15]),
-	.O(main_a7ddrphy_dq_i_nodelay15)
+	.O(a7ddrphy_dq_i_nodelay15)
 );
 
 //------------------------------------------------------------------------------
@@ -15390,14 +15833,14 @@ IOBUF IOBUF_15(
 reg [24:0] storage[0:15];
 reg [24:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
-		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+		storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+	storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15408,14 +15851,14 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_1[0:15];
 reg [24:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
-		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+		storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15426,14 +15869,14 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_2[0:15];
 reg [24:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
-		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+		storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15444,14 +15887,14 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_3[0:15];
 reg [24:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
-		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+		storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15462,14 +15905,14 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_4[0:15];
 reg [24:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
-		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+		storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15480,14 +15923,14 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_5[0:15];
 reg [24:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
-		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+		storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15498,14 +15941,14 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_6[0:15];
 reg [24:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
-		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+		storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15516,62 +15959,78 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [24:0] storage_7[0:15];
 reg [24:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
-		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+		storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
 
-FD FD(
-	.C(main_clkin),
-	.D(main_reset),
-	.Q(builder_reset0)
+FDCE FDCE(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(reset),
+	.Q(litedramcore_reset0)
 );
 
-FD FD_1(
-	.C(main_clkin),
-	.D(builder_reset0),
-	.Q(builder_reset1)
+FDCE FDCE_1(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset0),
+	.Q(litedramcore_reset1)
 );
 
-FD FD_2(
-	.C(main_clkin),
-	.D(builder_reset1),
-	.Q(builder_reset2)
+FDCE FDCE_2(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset1),
+	.Q(litedramcore_reset2)
 );
 
-FD FD_3(
-	.C(main_clkin),
-	.D(builder_reset2),
-	.Q(builder_reset3)
+FDCE FDCE_3(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset2),
+	.Q(litedramcore_reset3)
 );
 
-FD FD_4(
-	.C(main_clkin),
-	.D(builder_reset3),
-	.Q(builder_reset4)
+FDCE FDCE_4(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset3),
+	.Q(litedramcore_reset4)
 );
 
-FD FD_5(
-	.C(main_clkin),
-	.D(builder_reset4),
-	.Q(builder_reset5)
+FDCE FDCE_5(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset4),
+	.Q(litedramcore_reset5)
 );
 
-FD FD_6(
-	.C(main_clkin),
-	.D(builder_reset5),
-	.Q(builder_reset6)
+FDCE FDCE_6(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset5),
+	.Q(litedramcore_reset6)
 );
 
-FD FD_7(
-	.C(main_clkin),
-	.D(builder_reset6),
-	.Q(builder_reset7)
+FDCE FDCE_7(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset6),
+	.Q(litedramcore_reset7)
 );
 
 PLLE2_ADV #(
@@ -15589,16 +16048,16 @@ PLLE2_ADV #(
 	.REF_JITTER1(0.01),
 	.STARTUP_WAIT("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(builder_pll_fb),
-	.CLKIN1(main_clkin),
-	.PWRDWN(main_power_down),
-	.RST(builder_reset7),
-	.CLKFBOUT(builder_pll_fb),
-	.CLKOUT0(main_clkout0),
-	.CLKOUT1(main_clkout1),
-	.CLKOUT2(main_clkout2),
-	.CLKOUT3(main_clkout3),
-	.LOCKED(main_locked)
+	.CLKFBIN(litedramcore_pll_fb),
+	.CLKIN1(clkin),
+	.PWRDWN(power_down),
+	.RST(litedramcore_reset7),
+	.CLKFBOUT(litedramcore_pll_fb),
+	.CLKOUT0(clkout0),
+	.CLKOUT1(clkout1),
+	.CLKOUT2(clkout2),
+	.CLKOUT3(clkout3),
+	.LOCKED(locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15607,8 +16066,8 @@ PLLE2_ADV #(
 	.C(iodelay_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
-	.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl0),
+	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15616,8 +16075,8 @@ PLLE2_ADV #(
 ) FDPE_1 (
 	.C(iodelay_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
+	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl0),
 	.Q(iodelay_rst)
 );
 
@@ -15627,8 +16086,8 @@ PLLE2_ADV #(
 	.C(sys_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
-	.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl1),
+	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15636,8 +16095,8 @@ PLLE2_ADV #(
 ) FDPE_3 (
 	.C(sys_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
+	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl1),
 	.Q(sys_rst)
 );
 
@@ -15647,8 +16106,8 @@ PLLE2_ADV #(
 	.C(sys4x_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15656,9 +16115,9 @@ PLLE2_ADV #(
 ) FDPE_5 (
 	.C(sys4x_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_expr)
+	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15667,8 +16126,8 @@ PLLE2_ADV #(
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15676,13 +16135,13 @@ PLLE2_ADV #(
 ) FDPE_7 (
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_expr)
+	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-01-14 08:32:10.
+//  Auto-Generated by LiteX on 2022-08-04 21:06:57.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.init b/litedram/generated/orangecrab-85-0.2/litedram_core.init
index 54fd98a..cb505da 100644
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.init
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10e0658cff00
+618c10d8658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -519,213 +519,215 @@ a64b5a7d14004a39
 0000000000000000
 3c4c000100000000
 7c0802a63842acc4
-fbe1fff8fbc1fff0
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 7fe3fb78382100b0
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-0000028001000000
+0000000048002754
+0000018001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842ac203c4c0001
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 3c62ffff60000000
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 4182001073e90010
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 0000000000000000
diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.v b/litedram/generated/orangecrab-85-0.2/litedram_core.v
index e0e68fd..cdebb1b 100644
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.v
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : LFE5U-85F-8MG285C
-// LiteX sha1 : --------
-// Date       : 2022-01-14 09:35:04
+// LiteX sha1 : 6932fc51
+// Date       : 2022-08-04 21:07:03
 //------------------------------------------------------------------------------
 
 
@@ -200,7 +200,7 @@ wire ddrphy_dqsw2700;
 wire ddrphy_dqsw0;
 wire [2:0] ddrphy_rdpntr0;
 wire [2:0] ddrphy_wrpntr0;
-reg  [6:0] ddrphy_rdly0 = 7'd0;
+reg  [2:0] ddrphy_rdly0 = 3'd0;
 wire ddrphy_burstdet0;
 reg  ddrphy_burstdet_d0 = 1'd0;
 wire ddrphy_dqs0;
@@ -318,7 +318,7 @@ wire ddrphy_dqsw2701;
 wire ddrphy_dqsw1;
 wire [2:0] ddrphy_rdpntr1;
 wire [2:0] ddrphy_wrpntr1;
-reg  [6:0] ddrphy_rdly1 = 7'd0;
+reg  [2:0] ddrphy_rdly1 = 3'd0;
 wire ddrphy_burstdet1;
 reg  ddrphy_burstdet_d1 = 1'd0;
 wire ddrphy_dqs1;
@@ -450,38 +450,6 @@ reg  ddrphy_wrdata_en_tappeddelayline3 = 1'd0;
 reg  ddrphy_wrdata_en_tappeddelayline4 = 1'd0;
 reg  ddrphy_wrdata_en_tappeddelayline5 = 1'd0;
 reg  ddrphy_wrdata_en_tappeddelayline6 = 1'd0;
-wire [14:0] litedramcore_inti_p0_address;
-wire [2:0] litedramcore_inti_p0_bank;
-reg  litedramcore_inti_p0_cas_n = 1'd1;
-reg  litedramcore_inti_p0_cs_n = 1'd1;
-reg  litedramcore_inti_p0_ras_n = 1'd1;
-reg  litedramcore_inti_p0_we_n = 1'd1;
-wire litedramcore_inti_p0_cke;
-wire litedramcore_inti_p0_odt;
-wire litedramcore_inti_p0_reset_n;
-reg  litedramcore_inti_p0_act_n = 1'd1;
-wire [63:0] litedramcore_inti_p0_wrdata;
-wire litedramcore_inti_p0_wrdata_en;
-wire [7:0] litedramcore_inti_p0_wrdata_mask;
-wire litedramcore_inti_p0_rddata_en;
-reg  [63:0] litedramcore_inti_p0_rddata = 64'd0;
-reg  litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_inti_p1_address;
-wire [2:0] litedramcore_inti_p1_bank;
-reg  litedramcore_inti_p1_cas_n = 1'd1;
-reg  litedramcore_inti_p1_cs_n = 1'd1;
-reg  litedramcore_inti_p1_ras_n = 1'd1;
-reg  litedramcore_inti_p1_we_n = 1'd1;
-wire litedramcore_inti_p1_cke;
-wire litedramcore_inti_p1_odt;
-wire litedramcore_inti_p1_reset_n;
-reg  litedramcore_inti_p1_act_n = 1'd1;
-wire [63:0] litedramcore_inti_p1_wrdata;
-wire litedramcore_inti_p1_wrdata_en;
-wire [7:0] litedramcore_inti_p1_wrdata_mask;
-wire litedramcore_inti_p1_rddata_en;
-reg  [63:0] litedramcore_inti_p1_rddata = 64'd0;
-reg  litedramcore_inti_p1_rddata_valid = 1'd0;
 wire [14:0] litedramcore_slave_p0_address;
 wire [2:0] litedramcore_slave_p0_bank;
 wire litedramcore_slave_p0_cas_n;
@@ -546,12 +514,83 @@ reg  [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
 reg  litedramcore_master_p1_rddata_en = 1'd0;
 wire [63:0] litedramcore_master_p1_rddata;
 wire litedramcore_master_p1_rddata_valid;
+wire [14:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg  litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg  litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg  [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
+reg  litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg  litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg  litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg  [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
+reg  litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg  litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cke = 1'd0;
+reg  litedramcore_ext_dfi_p0_odt = 1'd0;
+reg  litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg  [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
+reg  litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
+reg  litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg  [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
+reg  litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg  [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
+reg  [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg  litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cke = 1'd0;
+reg  litedramcore_ext_dfi_p1_odt = 1'd0;
+reg  litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg  [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
+reg  litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg  [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
+reg  litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg  [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
+reg  litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg  litedramcore_ext_dfi_sel = 1'd0;
 wire litedramcore_sel;
 wire litedramcore_cke;
 wire litedramcore_odt;
 wire litedramcore_reset_n;
 reg  [3:0] litedramcore_storage = 4'd1;
 reg  litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
 reg  [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
 reg  litedramcore_phaseinjector0_command_re = 1'd0;
 reg  litedramcore_phaseinjector0_command_issue_re = 1'd0;
@@ -567,6 +606,12 @@ reg  litedramcore_phaseinjector0_wrdata_re = 1'd0;
 reg  [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
 wire litedramcore_phaseinjector0_rddata_we;
 reg  litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
 reg  [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
 reg  litedramcore_phaseinjector1_command_re = 1'd0;
 reg  litedramcore_phaseinjector1_command_issue_re = 1'd0;
@@ -1474,78 +1519,6 @@ wire [15:0] user_port_wdata_payload_we;
 wire user_port_rdata_valid;
 wire user_port_rdata_ready;
 wire [127:0] user_port_rdata_payload_data;
-wire litedramecp5ddrphycrg_ecp5pll;
-wire litedramecp5ddrphycrg_locked;
-reg  [1:0] litedramcore_refresher_state = 2'd0;
-reg  [1:0] litedramcore_refresher_next_state = 2'd0;
-reg  [2:0] litedramcore_bankmachine0_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine0_next_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine1_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine1_next_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine2_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine2_next_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine3_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine3_next_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine4_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine4_next_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine5_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine5_next_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine6_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine6_next_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine7_state = 3'd0;
-reg  [2:0] litedramcore_bankmachine7_next_state = 3'd0;
-reg  [3:0] litedramcore_multiplexer_state = 4'd0;
-reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_roundrobin0_request;
-wire litedramcore_roundrobin0_grant;
-wire litedramcore_roundrobin0_ce;
-wire litedramcore_roundrobin1_request;
-wire litedramcore_roundrobin1_grant;
-wire litedramcore_roundrobin1_ce;
-wire litedramcore_roundrobin2_request;
-wire litedramcore_roundrobin2_grant;
-wire litedramcore_roundrobin2_ce;
-wire litedramcore_roundrobin3_request;
-wire litedramcore_roundrobin3_grant;
-wire litedramcore_roundrobin3_ce;
-wire litedramcore_roundrobin4_request;
-wire litedramcore_roundrobin4_grant;
-wire litedramcore_roundrobin4_ce;
-wire litedramcore_roundrobin5_request;
-wire litedramcore_roundrobin5_grant;
-wire litedramcore_roundrobin5_ce;
-wire litedramcore_roundrobin6_request;
-wire litedramcore_roundrobin6_grant;
-wire litedramcore_roundrobin6_ce;
-wire litedramcore_roundrobin7_request;
-wire litedramcore_roundrobin7_grant;
-wire litedramcore_roundrobin7_ce;
-reg  litedramcore_locked0 = 1'd0;
-reg  litedramcore_locked1 = 1'd0;
-reg  litedramcore_locked2 = 1'd0;
-reg  litedramcore_locked3 = 1'd0;
-reg  litedramcore_locked4 = 1'd0;
-reg  litedramcore_locked5 = 1'd0;
-reg  litedramcore_locked6 = 1'd0;
-reg  litedramcore_locked7 = 1'd0;
-reg  litedramcore_new_master_wdata_ready0 = 1'd0;
-reg  litedramcore_new_master_wdata_ready1 = 1'd0;
-reg  litedramcore_new_master_wdata_ready2 = 1'd0;
-reg  litedramcore_new_master_wdata_ready3 = 1'd0;
-reg  litedramcore_new_master_rdata_valid0 = 1'd0;
-reg  litedramcore_new_master_rdata_valid1 = 1'd0;
-reg  litedramcore_new_master_rdata_valid2 = 1'd0;
-reg  litedramcore_new_master_rdata_valid3 = 1'd0;
-reg  litedramcore_new_master_rdata_valid4 = 1'd0;
-reg  litedramcore_new_master_rdata_valid5 = 1'd0;
-reg  litedramcore_new_master_rdata_valid6 = 1'd0;
-reg  litedramcore_new_master_rdata_valid7 = 1'd0;
-reg  litedramcore_new_master_rdata_valid8 = 1'd0;
-reg  litedramcore_new_master_rdata_valid9 = 1'd0;
-reg  litedramcore_new_master_rdata_valid10 = 1'd0;
-reg  litedramcore_new_master_rdata_valid11 = 1'd0;
-reg  litedramcore_new_master_rdata_valid12 = 1'd0;
-reg  litedramcore_new_master_rdata_valid13 = 1'd0;
 reg  [13:0] litedramcore_adr = 14'd0;
 reg  litedramcore_we = 1'd0;
 reg  [31:0] litedramcore_dat_w = 32'd0;
@@ -1656,8 +1629,80 @@ wire [13:0] csr_interconnect_adr;
 wire csr_interconnect_we;
 wire [31:0] csr_interconnect_dat_w;
 wire [31:0] csr_interconnect_dat_r;
-reg  [1:0] state = 2'd0;
-reg  [1:0] next_state = 2'd0;
+wire litedramcore_litedramecp5ddrphycrg_ecp5pll;
+wire litedramcore_litedramecp5ddrphycrg_locked;
+reg  [1:0] litedramcore_litedramcore_refresher_state = 2'd0;
+reg  [1:0] litedramcore_litedramcore_refresher_next_state = 2'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine0_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine0_next_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine1_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine1_next_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine2_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine2_next_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine3_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine3_next_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine4_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine4_next_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine5_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine5_next_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine6_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine6_next_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine7_state = 3'd0;
+reg  [2:0] litedramcore_litedramcore_bankmachine7_next_state = 3'd0;
+reg  [3:0] litedramcore_litedramcore_multiplexer_state = 4'd0;
+reg  [3:0] litedramcore_litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_litedramcore_roundrobin0_request;
+wire litedramcore_litedramcore_roundrobin0_grant;
+wire litedramcore_litedramcore_roundrobin0_ce;
+wire litedramcore_litedramcore_roundrobin1_request;
+wire litedramcore_litedramcore_roundrobin1_grant;
+wire litedramcore_litedramcore_roundrobin1_ce;
+wire litedramcore_litedramcore_roundrobin2_request;
+wire litedramcore_litedramcore_roundrobin2_grant;
+wire litedramcore_litedramcore_roundrobin2_ce;
+wire litedramcore_litedramcore_roundrobin3_request;
+wire litedramcore_litedramcore_roundrobin3_grant;
+wire litedramcore_litedramcore_roundrobin3_ce;
+wire litedramcore_litedramcore_roundrobin4_request;
+wire litedramcore_litedramcore_roundrobin4_grant;
+wire litedramcore_litedramcore_roundrobin4_ce;
+wire litedramcore_litedramcore_roundrobin5_request;
+wire litedramcore_litedramcore_roundrobin5_grant;
+wire litedramcore_litedramcore_roundrobin5_ce;
+wire litedramcore_litedramcore_roundrobin6_request;
+wire litedramcore_litedramcore_roundrobin6_grant;
+wire litedramcore_litedramcore_roundrobin6_ce;
+wire litedramcore_litedramcore_roundrobin7_request;
+wire litedramcore_litedramcore_roundrobin7_grant;
+wire litedramcore_litedramcore_roundrobin7_ce;
+reg  litedramcore_litedramcore_locked0 = 1'd0;
+reg  litedramcore_litedramcore_locked1 = 1'd0;
+reg  litedramcore_litedramcore_locked2 = 1'd0;
+reg  litedramcore_litedramcore_locked3 = 1'd0;
+reg  litedramcore_litedramcore_locked4 = 1'd0;
+reg  litedramcore_litedramcore_locked5 = 1'd0;
+reg  litedramcore_litedramcore_locked6 = 1'd0;
+reg  litedramcore_litedramcore_locked7 = 1'd0;
+reg  litedramcore_litedramcore_new_master_wdata_ready0 = 1'd0;
+reg  litedramcore_litedramcore_new_master_wdata_ready1 = 1'd0;
+reg  litedramcore_litedramcore_new_master_wdata_ready2 = 1'd0;
+reg  litedramcore_litedramcore_new_master_wdata_ready3 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid0 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid1 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid2 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid3 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid4 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid5 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid6 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid7 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid8 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid9 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid10 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid11 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid12 = 1'd0;
+reg  litedramcore_litedramcore_new_master_rdata_valid13 = 1'd0;
+reg  [1:0] litedramcore_state = 2'd0;
+reg  [1:0] litedramcore_next_state = 2'd0;
 reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
 reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
 reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
@@ -1768,7 +1813,7 @@ assign pll_locked = crg_locked;
 assign crg_clkin = clk;
 assign sys2x_i_clk = crg_clkout0;
 assign init_clk = crg_clkout1;
-assign crg_locked = (litedramecp5ddrphycrg_locked & (~crg_reset1));
+assign crg_locked = (litedramcore_litedramecp5ddrphycrg_locked & (~crg_reset1));
 always @(*) begin
 	ddrphy_dm_o_data0 <= 8'd0;
 	ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1];
@@ -2467,367 +2512,531 @@ assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
 assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
 assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
 always @(*) begin
-	litedramcore_slave_p0_rddata <= 64'd0;
+	litedramcore_master_p0_cs_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+		end else begin
+			litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+		end
 	end else begin
+		litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
 	end
 end
 always @(*) begin
-	litedramcore_slave_p0_rddata_valid <= 1'd0;
+	litedramcore_csr_dfi_p1_rddata <= 64'd0;
 	if (litedramcore_sel) begin
-		litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
 	end else begin
+		litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
 	end
 end
 always @(*) begin
-	litedramcore_slave_p1_rddata <= 64'd0;
+	litedramcore_master_p0_ras_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+		end else begin
+			litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+		end
 	end else begin
+		litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
 	end
 end
 always @(*) begin
-	litedramcore_slave_p1_rddata_valid <= 1'd0;
+	litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
 	end else begin
+		litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_address <= 15'd0;
+	litedramcore_master_p0_we_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+		end else begin
+			litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+		end
 	end else begin
-		litedramcore_master_p0_address <= litedramcore_inti_p0_address;
+		litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_bank <= 3'd0;
+	litedramcore_master_p0_cke <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+		end else begin
+			litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+		end
 	end else begin
-		litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+		litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_cas_n <= 1'd1;
+	litedramcore_master_p0_odt <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+		end else begin
+			litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+		end
 	end else begin
-		litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
+		litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_cs_n <= 1'd1;
+	litedramcore_master_p0_reset_n <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+		end else begin
+			litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+		end
 	end else begin
-		litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+		litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_ras_n <= 1'd1;
+	litedramcore_master_p0_act_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+		end else begin
+			litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+		end
 	end else begin
-		litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+		litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p0_rddata <= 64'd0;
+	litedramcore_master_p0_wrdata <= 64'd0;
 	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+		end else begin
+			litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+		end
 	end else begin
-		litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
+		litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_we_n <= 1'd1;
+	litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+		end else begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+		end
 	end else begin
-		litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+		litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p0_rddata_valid <= 1'd0;
+	litedramcore_master_p0_wrdata_mask <= 8'd0;
 	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+		end else begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+		end
 	end else begin
-		litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_cke <= 1'd0;
+	litedramcore_master_p0_rddata_en <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+		end else begin
+			litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+		end
 	end else begin
-		litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+		litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_odt <= 1'd0;
+	litedramcore_master_p1_address <= 15'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+		end else begin
+			litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+		end
 	end else begin
-		litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
+		litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_reset_n <= 1'd0;
+	litedramcore_master_p1_bank <= 3'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+		end else begin
+			litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+		end
 	end else begin
-		litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+		litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_act_n <= 1'd1;
+	litedramcore_master_p1_cas_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+		end else begin
+			litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+		end
 	end else begin
-		litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
+		litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_wrdata <= 64'd0;
+	litedramcore_master_p1_cs_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+		end else begin
+			litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+		end
 	end else begin
-		litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+		litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_wrdata_en <= 1'd0;
+	litedramcore_master_p1_ras_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+		end else begin
+			litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+		end
 	end else begin
-		litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
+		litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_wrdata_mask <= 8'd0;
+	litedramcore_master_p1_we_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+		end else begin
+			litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+		end
 	end else begin
-		litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
+		litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p0_rddata_en <= 1'd0;
+	litedramcore_master_p1_cke <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+		end else begin
+			litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+		end
 	end else begin
-		litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
+		litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_address <= 15'd0;
+	litedramcore_master_p1_odt <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+		end else begin
+			litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+		end
 	end else begin
-		litedramcore_master_p1_address <= litedramcore_inti_p1_address;
+		litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_bank <= 3'd0;
+	litedramcore_ext_dfi_p0_rddata <= 64'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+		end else begin
+		end
 	end else begin
-		litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_cas_n <= 1'd1;
+	litedramcore_master_p1_reset_n <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+		end else begin
+			litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+		end
 	end else begin
-		litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
+		litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_cs_n <= 1'd1;
+	litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end else begin
+		end
 	end else begin
-		litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_ras_n <= 1'd1;
+	litedramcore_master_p1_act_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+		end else begin
+			litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+		end
 	end else begin
-		litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
+		litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p1_rddata <= 64'd0;
+	litedramcore_master_p1_wrdata <= 64'd0;
 	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+		end else begin
+			litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+		end
 	end else begin
-		litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
+		litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_we_n <= 1'd1;
+	litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+		end else begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+		end
 	end else begin
-		litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
+		litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p1_rddata_valid <= 1'd0;
+	litedramcore_master_p1_wrdata_mask <= 8'd0;
 	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+		end else begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+		end
 	end else begin
-		litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_cke <= 1'd0;
+	litedramcore_master_p1_rddata_en <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+		end else begin
+			litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+		end
 	end else begin
-		litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
+		litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_odt <= 1'd0;
+	litedramcore_ext_dfi_p1_rddata <= 64'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+		end else begin
+		end
 	end else begin
-		litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_reset_n <= 1'd0;
+	litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end else begin
+		end
 	end else begin
-		litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_act_n <= 1'd1;
+	litedramcore_slave_p0_rddata <= 64'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+		end
 	end else begin
-		litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_wrdata <= 64'd0;
+	litedramcore_slave_p0_rddata_valid <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end
 	end else begin
-		litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_wrdata_en <= 1'd0;
+	litedramcore_csr_dfi_p0_rddata <= 64'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
 	end else begin
-		litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+		litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_wrdata_mask <= 8'd0;
+	litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
 	end else begin
-		litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+		litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
 	end
 end
 always @(*) begin
-	litedramcore_master_p1_rddata_en <= 1'd0;
+	litedramcore_slave_p1_rddata <= 64'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+		end
+	end else begin
+	end
+end
+always @(*) begin
+	litedramcore_slave_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end
+	end else begin
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_address <= 15'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+		end else begin
+			litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+		end
+	end else begin
+		litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+		end else begin
+			litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+		end
+	end else begin
+		litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_cas_n <= 1'd1;
 	if (litedramcore_sel) begin
-		litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+		end else begin
+			litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+		end
 	end else begin
-		litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
+		litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
 	end
 end
-assign litedramcore_inti_p0_cke = litedramcore_cke;
-assign litedramcore_inti_p1_cke = litedramcore_cke;
-assign litedramcore_inti_p0_odt = litedramcore_odt;
-assign litedramcore_inti_p1_odt = litedramcore_odt;
-assign litedramcore_inti_p0_reset_n = litedramcore_reset_n;
-assign litedramcore_inti_p1_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
 always @(*) begin
-	litedramcore_inti_p0_ras_n <= 1'd1;
+	litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	if (litedramcore_phaseinjector0_command_issue_re) begin
-		litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
+		litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
 	end else begin
-		litedramcore_inti_p0_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p0_we_n <= 1'd1;
+	litedramcore_csr_dfi_p0_cs_n <= 1'd1;
 	if (litedramcore_phaseinjector0_command_issue_re) begin
-		litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
+		litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
 	end else begin
-		litedramcore_inti_p0_we_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	litedramcore_inti_p0_cas_n <= 1'd1;
+	litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	if (litedramcore_phaseinjector0_command_issue_re) begin
-		litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
+		litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
 	end else begin
-		litedramcore_inti_p0_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p0_cs_n <= 1'd1;
+	litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	if (litedramcore_phaseinjector0_command_issue_re) begin
-		litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+		litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
 	end else begin
-		litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	end
 end
-assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
-assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
-assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
+assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
+assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	litedramcore_inti_p1_ras_n <= 1'd1;
+	litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	if (litedramcore_phaseinjector1_command_issue_re) begin
-		litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
+		litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
 	end else begin
-		litedramcore_inti_p1_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p1_we_n <= 1'd1;
+	litedramcore_csr_dfi_p1_cs_n <= 1'd1;
 	if (litedramcore_phaseinjector1_command_issue_re) begin
-		litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
+		litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
 	end else begin
-		litedramcore_inti_p1_we_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	litedramcore_inti_p1_cas_n <= 1'd1;
+	litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	if (litedramcore_phaseinjector1_command_issue_re) begin
-		litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
+		litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
 	end else begin
-		litedramcore_inti_p1_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	litedramcore_inti_p1_cs_n <= 1'd1;
+	litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	if (litedramcore_phaseinjector1_command_issue_re) begin
-		litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+		litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
 	end else begin
-		litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	end
 end
-assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
-assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
-assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
+assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
+assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
 assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
 assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
@@ -2898,32 +3107,32 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
 assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
 assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
 always @(*) begin
-	litedramcore_refresher_next_state <= 2'd0;
-	litedramcore_refresher_next_state <= litedramcore_refresher_state;
-	case (litedramcore_refresher_state)
+	litedramcore_litedramcore_refresher_next_state <= 2'd0;
+	litedramcore_litedramcore_refresher_next_state <= litedramcore_litedramcore_refresher_state;
+	case (litedramcore_litedramcore_refresher_state)
 		1'd1: begin
 			if (litedramcore_cmd_ready) begin
-				litedramcore_refresher_next_state <= 2'd2;
+				litedramcore_litedramcore_refresher_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
 			if (litedramcore_sequencer_done0) begin
 				if (litedramcore_wants_zqcs) begin
-					litedramcore_refresher_next_state <= 2'd3;
+					litedramcore_litedramcore_refresher_next_state <= 2'd3;
 				end else begin
-					litedramcore_refresher_next_state <= 1'd0;
+					litedramcore_litedramcore_refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
 			if (litedramcore_zqcs_executer_done) begin
-				litedramcore_refresher_next_state <= 1'd0;
+				litedramcore_litedramcore_refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
 				if (litedramcore_wants_refresh) begin
-					litedramcore_refresher_next_state <= 1'd1;
+					litedramcore_litedramcore_refresher_next_state <= 1'd1;
 				end
 			end
 		end
@@ -2931,7 +3140,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_sequencer_start0 <= 1'd0;
-	case (litedramcore_refresher_state)
+	case (litedramcore_litedramcore_refresher_state)
 		1'd1: begin
 			if (litedramcore_cmd_ready) begin
 				litedramcore_sequencer_start0 <= 1'd1;
@@ -2947,7 +3156,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_cmd_valid <= 1'd0;
-	case (litedramcore_refresher_state)
+	case (litedramcore_litedramcore_refresher_state)
 		1'd1: begin
 			litedramcore_cmd_valid <= 1'd1;
 		end
@@ -2972,7 +3181,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_zqcs_executer_start <= 1'd0;
-	case (litedramcore_refresher_state)
+	case (litedramcore_litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -2991,7 +3200,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_cmd_last <= 1'd0;
-	case (litedramcore_refresher_state)
+	case (litedramcore_litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3078,63 +3287,85 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (lite
 assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine0_next_state <= 3'd0;
-	litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
-	case (litedramcore_bankmachine0_state)
+	litedramcore_litedramcore_bankmachine0_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine0_next_state <= litedramcore_litedramcore_bankmachine0_state;
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
 				if (litedramcore_bankmachine0_cmd_ready) begin
-					litedramcore_bankmachine0_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-				litedramcore_bankmachine0_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine0_trccon_ready) begin
 				if (litedramcore_bankmachine0_cmd_ready) begin
-					litedramcore_bankmachine0_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine0_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine0_refresh_req)) begin
-				litedramcore_bankmachine0_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine0_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine0_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine0_refresh_req) begin
-				litedramcore_bankmachine0_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine0_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine0_row_opened) begin
 						if (litedramcore_bankmachine0_row_hit) begin
 							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
-								litedramcore_bankmachine0_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine0_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine0_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_bankmachine0_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_bankmachine0_row_close <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 			litedramcore_bankmachine0_row_close <= 1'd1;
 		end
@@ -3156,7 +3387,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3187,7 +3418,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
 				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
@@ -3212,7 +3443,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
 				litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
@@ -3249,7 +3480,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3271,7 +3502,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
 				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
@@ -3297,7 +3528,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3331,7 +3562,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3365,7 +3596,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3399,7 +3630,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3433,7 +3664,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3455,7 +3686,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine0_state)
+	case (litedramcore_litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
 				litedramcore_bankmachine0_cmd_valid <= 1'd1;
@@ -3490,28 +3721,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine0_row_open <= 1'd0;
-	case (litedramcore_bankmachine0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine0_trccon_ready) begin
-				litedramcore_bankmachine0_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
 assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
 assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
@@ -3579,63 +3788,85 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (lite
 assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine1_next_state <= 3'd0;
-	litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
-	case (litedramcore_bankmachine1_state)
+	litedramcore_litedramcore_bankmachine1_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine1_next_state <= litedramcore_litedramcore_bankmachine1_state;
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
 				if (litedramcore_bankmachine1_cmd_ready) begin
-					litedramcore_bankmachine1_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-				litedramcore_bankmachine1_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine1_trccon_ready) begin
 				if (litedramcore_bankmachine1_cmd_ready) begin
-					litedramcore_bankmachine1_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine1_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine1_refresh_req)) begin
-				litedramcore_bankmachine1_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine1_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine1_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine1_refresh_req) begin
-				litedramcore_bankmachine1_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine1_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine1_row_opened) begin
 						if (litedramcore_bankmachine1_row_hit) begin
 							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
-								litedramcore_bankmachine1_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine1_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine1_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine1_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_bankmachine1_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_bankmachine1_row_close <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
@@ -3657,7 +3888,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3688,7 +3919,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
 				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
@@ -3713,7 +3944,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
 				litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
@@ -3750,7 +3981,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3772,7 +4003,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
 				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
@@ -3798,7 +4029,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3832,7 +4063,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3866,7 +4097,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3900,7 +4131,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3934,7 +4165,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -3956,7 +4187,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine1_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine1_state)
+	case (litedramcore_litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
 				litedramcore_bankmachine1_cmd_valid <= 1'd1;
@@ -3991,28 +4222,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine1_row_open <= 1'd0;
-	case (litedramcore_bankmachine1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine1_trccon_ready) begin
-				litedramcore_bankmachine1_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
 assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
 assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
@@ -4080,54 +4289,54 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (lite
 assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine2_next_state <= 3'd0;
-	litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
-	case (litedramcore_bankmachine2_state)
+	litedramcore_litedramcore_bankmachine2_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine2_next_state <= litedramcore_litedramcore_bankmachine2_state;
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
 				if (litedramcore_bankmachine2_cmd_ready) begin
-					litedramcore_bankmachine2_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-				litedramcore_bankmachine2_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine2_trccon_ready) begin
 				if (litedramcore_bankmachine2_cmd_ready) begin
-					litedramcore_bankmachine2_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine2_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine2_refresh_req)) begin
-				litedramcore_bankmachine2_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine2_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine2_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine2_refresh_req) begin
-				litedramcore_bankmachine2_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine2_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine2_row_opened) begin
 						if (litedramcore_bankmachine2_row_hit) begin
 							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
-								litedramcore_bankmachine2_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine2_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine2_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine2_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4135,18 +4344,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine2_row_close <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	litedramcore_bankmachine2_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
-			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
-			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4157,24 +4366,46 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	litedramcore_bankmachine2_row_close <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
 		3'd6: begin
 		end
 		default: begin
-			if (litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine2_row_opened) begin
 						if (litedramcore_bankmachine2_row_hit) begin
 							litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
@@ -4189,7 +4420,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
 				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
@@ -4214,7 +4445,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
 				litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
@@ -4251,7 +4482,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4273,7 +4504,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
 				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
@@ -4297,9 +4528,31 @@ always @(*) begin
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (litedramcore_bankmachine2_twtpcon_ready) begin
+				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4333,7 +4586,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4367,7 +4620,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4401,7 +4654,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4433,31 +4686,9 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine2_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (litedramcore_bankmachine2_twtpcon_ready) begin
-				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 always @(*) begin
 	litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine2_state)
+	case (litedramcore_litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
 				litedramcore_bankmachine2_cmd_valid <= 1'd1;
@@ -4492,28 +4723,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine2_row_open <= 1'd0;
-	case (litedramcore_bankmachine2_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine2_trccon_ready) begin
-				litedramcore_bankmachine2_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
 assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
 assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
@@ -4581,63 +4790,85 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (lite
 assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine3_next_state <= 3'd0;
-	litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
-	case (litedramcore_bankmachine3_state)
+	litedramcore_litedramcore_bankmachine3_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine3_next_state <= litedramcore_litedramcore_bankmachine3_state;
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
 				if (litedramcore_bankmachine3_cmd_ready) begin
-					litedramcore_bankmachine3_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-				litedramcore_bankmachine3_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine3_trccon_ready) begin
 				if (litedramcore_bankmachine3_cmd_ready) begin
-					litedramcore_bankmachine3_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine3_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine3_refresh_req)) begin
-				litedramcore_bankmachine3_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine3_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine3_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine3_refresh_req) begin
-				litedramcore_bankmachine3_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine3_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine3_row_opened) begin
 						if (litedramcore_bankmachine3_row_hit) begin
 							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
-								litedramcore_bankmachine3_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine3_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine3_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine3_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_bankmachine3_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_bankmachine3_row_close <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
@@ -4659,7 +4890,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4690,7 +4921,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
 				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
@@ -4715,7 +4946,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
 				litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
@@ -4752,7 +4983,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4774,7 +5005,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
 				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
@@ -4800,7 +5031,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4834,7 +5065,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4868,7 +5099,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4902,7 +5133,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4936,7 +5167,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4958,7 +5189,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine3_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine3_state)
+	case (litedramcore_litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
 				litedramcore_bankmachine3_cmd_valid <= 1'd1;
@@ -4993,28 +5224,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine3_row_open <= 1'd0;
-	case (litedramcore_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine3_trccon_ready) begin
-				litedramcore_bankmachine3_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
 assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
 assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
@@ -5082,63 +5291,85 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (lite
 assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine4_next_state <= 3'd0;
-	litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
-	case (litedramcore_bankmachine4_state)
+	litedramcore_litedramcore_bankmachine4_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine4_next_state <= litedramcore_litedramcore_bankmachine4_state;
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
 				if (litedramcore_bankmachine4_cmd_ready) begin
-					litedramcore_bankmachine4_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-				litedramcore_bankmachine4_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine4_trccon_ready) begin
 				if (litedramcore_bankmachine4_cmd_ready) begin
-					litedramcore_bankmachine4_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine4_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine4_refresh_req)) begin
-				litedramcore_bankmachine4_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine4_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine4_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine4_refresh_req) begin
-				litedramcore_bankmachine4_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine4_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine4_row_opened) begin
 						if (litedramcore_bankmachine4_row_hit) begin
 							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
-								litedramcore_bankmachine4_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine4_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine4_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine4_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_bankmachine4_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_bankmachine4_row_close <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
@@ -5160,7 +5391,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5191,7 +5422,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
 				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
@@ -5216,7 +5447,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
 				litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
@@ -5253,7 +5484,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5275,7 +5506,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
 				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
@@ -5301,7 +5532,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5335,7 +5566,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5369,7 +5600,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5403,7 +5634,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5437,7 +5668,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5459,7 +5690,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine4_state)
+	case (litedramcore_litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
 				litedramcore_bankmachine4_cmd_valid <= 1'd1;
@@ -5494,28 +5725,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine4_row_open <= 1'd0;
-	case (litedramcore_bankmachine4_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine4_trccon_ready) begin
-				litedramcore_bankmachine4_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
 assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
 assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
@@ -5583,63 +5792,85 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (lite
 assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine5_next_state <= 3'd0;
-	litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
-	case (litedramcore_bankmachine5_state)
+	litedramcore_litedramcore_bankmachine5_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine5_next_state <= litedramcore_litedramcore_bankmachine5_state;
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
 				if (litedramcore_bankmachine5_cmd_ready) begin
-					litedramcore_bankmachine5_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-				litedramcore_bankmachine5_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine5_trccon_ready) begin
 				if (litedramcore_bankmachine5_cmd_ready) begin
-					litedramcore_bankmachine5_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine5_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine5_refresh_req)) begin
-				litedramcore_bankmachine5_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine5_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine5_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine5_refresh_req) begin
-				litedramcore_bankmachine5_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine5_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine5_row_opened) begin
 						if (litedramcore_bankmachine5_row_hit) begin
 							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
-								litedramcore_bankmachine5_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine5_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine5_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine5_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_bankmachine5_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_bankmachine5_row_close <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
@@ -5661,7 +5892,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5692,7 +5923,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
 				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
@@ -5717,7 +5948,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
 				litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
@@ -5754,7 +5985,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5776,7 +6007,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
 				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
@@ -5802,7 +6033,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5836,7 +6067,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5870,7 +6101,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5904,7 +6135,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5938,7 +6169,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5960,7 +6191,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine5_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine5_state)
+	case (litedramcore_litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
 				litedramcore_bankmachine5_cmd_valid <= 1'd1;
@@ -5995,28 +6226,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine5_row_open <= 1'd0;
-	case (litedramcore_bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine5_trccon_ready) begin
-				litedramcore_bankmachine5_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
 assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
 assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
@@ -6084,63 +6293,85 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (lite
 assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine6_next_state <= 3'd0;
-	litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
-	case (litedramcore_bankmachine6_state)
+	litedramcore_litedramcore_bankmachine6_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine6_next_state <= litedramcore_litedramcore_bankmachine6_state;
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
 				if (litedramcore_bankmachine6_cmd_ready) begin
-					litedramcore_bankmachine6_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-				litedramcore_bankmachine6_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine6_trccon_ready) begin
 				if (litedramcore_bankmachine6_cmd_ready) begin
-					litedramcore_bankmachine6_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine6_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine6_refresh_req)) begin
-				litedramcore_bankmachine6_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine6_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine6_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine6_refresh_req) begin
-				litedramcore_bankmachine6_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine6_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine6_row_opened) begin
 						if (litedramcore_bankmachine6_row_hit) begin
 							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
-								litedramcore_bankmachine6_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine6_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine6_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_bankmachine6_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_bankmachine6_row_close <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
@@ -6162,7 +6393,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6193,7 +6424,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
 				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
@@ -6218,7 +6449,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
 				litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
@@ -6255,7 +6486,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6277,7 +6508,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
 				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
@@ -6303,7 +6534,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6337,7 +6568,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6371,7 +6602,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6405,7 +6636,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6439,7 +6670,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6461,7 +6692,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine6_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine6_state)
+	case (litedramcore_litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
 				litedramcore_bankmachine6_cmd_valid <= 1'd1;
@@ -6496,28 +6727,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine6_row_open <= 1'd0;
-	case (litedramcore_bankmachine6_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine6_trccon_ready) begin
-				litedramcore_bankmachine6_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
 assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
 assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
@@ -6585,54 +6794,54 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (lite
 assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
 always @(*) begin
-	litedramcore_bankmachine7_next_state <= 3'd0;
-	litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
-	case (litedramcore_bankmachine7_state)
+	litedramcore_litedramcore_bankmachine7_next_state <= 3'd0;
+	litedramcore_litedramcore_bankmachine7_next_state <= litedramcore_litedramcore_bankmachine7_state;
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
 				if (litedramcore_bankmachine7_cmd_ready) begin
-					litedramcore_bankmachine7_next_state <= 3'd5;
+					litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-				litedramcore_bankmachine7_next_state <= 3'd5;
+				litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_bankmachine7_trccon_ready) begin
 				if (litedramcore_bankmachine7_cmd_ready) begin
-					litedramcore_bankmachine7_next_state <= 3'd6;
+					litedramcore_litedramcore_bankmachine7_next_state <= 3'd6;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~litedramcore_bankmachine7_refresh_req)) begin
-				litedramcore_bankmachine7_next_state <= 1'd0;
+				litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			litedramcore_bankmachine7_next_state <= 2'd3;
+			litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
 		end
 		3'd6: begin
-			litedramcore_bankmachine7_next_state <= 1'd0;
+			litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
 			if (litedramcore_bankmachine7_refresh_req) begin
-				litedramcore_bankmachine7_next_state <= 3'd4;
+				litedramcore_litedramcore_bankmachine7_next_state <= 3'd4;
 			end else begin
 				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
 					if (litedramcore_bankmachine7_row_opened) begin
 						if (litedramcore_bankmachine7_row_hit) begin
 							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
-								litedramcore_bankmachine7_next_state <= 2'd2;
+								litedramcore_litedramcore_bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
-							litedramcore_bankmachine7_next_state <= 1'd1;
+							litedramcore_litedramcore_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
-						litedramcore_bankmachine7_next_state <= 2'd3;
+						litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6640,13 +6849,35 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine7_row_close <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	litedramcore_bankmachine7_row_open <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
-			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
-			litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine7_row_close <= 1'd0;
+	case (litedramcore_litedramcore_bankmachine7_state)
+		1'd1: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		2'd2: begin
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -6663,7 +6894,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6694,7 +6925,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
 				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
@@ -6719,7 +6950,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
 				litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
@@ -6756,7 +6987,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6778,7 +7009,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
 				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
@@ -6804,7 +7035,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6838,7 +7069,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6872,7 +7103,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6906,7 +7137,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6940,7 +7171,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6962,7 +7193,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (litedramcore_bankmachine7_state)
+	case (litedramcore_litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
 				litedramcore_bankmachine7_cmd_valid <= 1'd1;
@@ -6997,28 +7228,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_bankmachine7_row_open <= 1'd0;
-	case (litedramcore_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (litedramcore_bankmachine7_trccon_ready) begin
-				litedramcore_bankmachine7_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
 assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
 assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
@@ -7197,80 +7406,127 @@ assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
 assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
 assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]);
 always @(*) begin
-	litedramcore_multiplexer_next_state <= 4'd0;
-	litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
-	case (litedramcore_multiplexer_state)
+	litedramcore_litedramcore_multiplexer_next_state <= 4'd0;
+	litedramcore_litedramcore_multiplexer_next_state <= litedramcore_litedramcore_multiplexer_state;
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 			if (litedramcore_read_available) begin
 				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
-					litedramcore_multiplexer_next_state <= 2'd3;
+					litedramcore_litedramcore_multiplexer_next_state <= 2'd3;
 				end
 			end
 			if (litedramcore_go_to_refresh) begin
-				litedramcore_multiplexer_next_state <= 2'd2;
+				litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
 			if (litedramcore_cmd_last) begin
-				litedramcore_multiplexer_next_state <= 1'd0;
+				litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
 			if (litedramcore_twtrcon_ready) begin
-				litedramcore_multiplexer_next_state <= 1'd0;
+				litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			litedramcore_multiplexer_next_state <= 3'd5;
+			litedramcore_litedramcore_multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			litedramcore_multiplexer_next_state <= 3'd6;
+			litedramcore_litedramcore_multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			litedramcore_multiplexer_next_state <= 3'd7;
+			litedramcore_litedramcore_multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			litedramcore_multiplexer_next_state <= 4'd8;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			litedramcore_multiplexer_next_state <= 4'd9;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			litedramcore_multiplexer_next_state <= 4'd10;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			litedramcore_multiplexer_next_state <= 4'd11;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd11;
 		end
 		4'd11: begin
-			litedramcore_multiplexer_next_state <= 4'd12;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd12;
 		end
 		4'd12: begin
-			litedramcore_multiplexer_next_state <= 4'd13;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd13;
 		end
 		4'd13: begin
-			litedramcore_multiplexer_next_state <= 4'd14;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd14;
 		end
 		4'd14: begin
-			litedramcore_multiplexer_next_state <= 4'd15;
+			litedramcore_litedramcore_multiplexer_next_state <= 4'd15;
 		end
 		4'd15: begin
-			litedramcore_multiplexer_next_state <= 1'd1;
+			litedramcore_litedramcore_multiplexer_next_state <= 1'd1;
 		end
 		default: begin
 			if (litedramcore_write_available) begin
 				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
-					litedramcore_multiplexer_next_state <= 3'd4;
+					litedramcore_litedramcore_multiplexer_next_state <= 3'd4;
 				end
 			end
 			if (litedramcore_go_to_refresh) begin
-				litedramcore_multiplexer_next_state <= 2'd2;
+				litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
+			end
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (litedramcore_litedramcore_multiplexer_state)
+		1'd1: begin
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		4'd11: begin
+		end
+		4'd12: begin
+		end
+		4'd13: begin
+		end
+		4'd14: begin
+		end
+		4'd15: begin
+		end
+		default: begin
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
 			end
 		end
 	endcase
 end
 always @(*) begin
 	litedramcore_en1 <= 1'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 			litedramcore_en1 <= 1'd1;
 		end
@@ -7308,7 +7564,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_steerer_sel0 <= 2'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 			litedramcore_steerer_sel0 <= 1'd0;
 			if (1'd0) begin
@@ -7360,7 +7616,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_steerer_sel1 <= 2'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 			litedramcore_steerer_sel1 <= 1'd0;
 			if (1'd1) begin
@@ -7411,7 +7667,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 			if (1'd0) begin
 			end else begin
@@ -7456,7 +7712,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_cmd_ready <= 1'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7494,7 +7750,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_choose_cmd_cmd_ready <= 1'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 			if (1'd0) begin
 			end else begin
@@ -7539,7 +7795,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_choose_req_want_reads <= 1'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7577,7 +7833,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_choose_req_want_writes <= 1'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 			litedramcore_choose_req_want_writes <= 1'd1;
 		end
@@ -7615,7 +7871,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_en0 <= 1'd0;
-	case (litedramcore_multiplexer_state)
+	case (litedramcore_litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7651,99 +7907,52 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_choose_req_cmd_ready <= 1'd0;
-	case (litedramcore_multiplexer_state)
-		1'd1: begin
-			if (1'd0) begin
-				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-			end else begin
-				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		4'd11: begin
-		end
-		4'd12: begin
-		end
-		4'd13: begin
-		end
-		4'd14: begin
-		end
-		4'd15: begin
-		end
-		default: begin
-			if (1'd0) begin
-				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-			end else begin
-				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-			end
-		end
-	endcase
-end
-assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
 assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
 assign litedramcore_interface_bank0_we = rhs_array_muxed13;
 assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
 assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
 assign litedramcore_interface_bank1_we = rhs_array_muxed16;
 assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
 assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
 assign litedramcore_interface_bank2_we = rhs_array_muxed19;
 assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
 assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
 assign litedramcore_interface_bank3_we = rhs_array_muxed22;
 assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
 assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
 assign litedramcore_interface_bank4_we = rhs_array_muxed25;
 assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
 assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
 assign litedramcore_interface_bank5_we = rhs_array_muxed28;
 assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
 assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
 assign litedramcore_interface_bank6_we = rhs_array_muxed31;
 assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
 assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
 assign litedramcore_interface_bank7_we = rhs_array_muxed34;
 assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = litedramcore_new_master_wdata_ready3;
-assign user_port_rdata_valid = litedramcore_new_master_rdata_valid13;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_litedramcore_new_master_wdata_ready3;
+assign user_port_rdata_valid = litedramcore_litedramcore_new_master_rdata_valid13;
 always @(*) begin
 	litedramcore_interface_wdata <= 128'd0;
-	case ({litedramcore_new_master_wdata_ready3})
+	case ({litedramcore_litedramcore_new_master_wdata_ready3})
 		1'd1: begin
 			litedramcore_interface_wdata <= user_port_wdata_payload_data;
 		end
@@ -7754,7 +7963,7 @@ always @(*) begin
 end
 always @(*) begin
 	litedramcore_interface_wdata_we <= 16'd0;
-	case ({litedramcore_new_master_wdata_ready3})
+	case ({litedramcore_litedramcore_new_master_wdata_ready3})
 		1'd1: begin
 			litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
 		end
@@ -7764,136 +7973,136 @@ always @(*) begin
 	endcase
 end
 assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_roundrobin7_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-	next_state <= 2'd0;
-	next_state <= state;
-	case (state)
+	litedramcore_next_state <= 2'd0;
+	litedramcore_next_state <= litedramcore_state;
+	case (litedramcore_state)
 		1'd1: begin
-			next_state <= 2'd2;
+			litedramcore_next_state <= 2'd2;
 		end
 		2'd2: begin
-			next_state <= 1'd0;
+			litedramcore_next_state <= 1'd0;
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				next_state <= 1'd1;
+				litedramcore_next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value2 <= 1'd0;
-	case (state)
+	litedramcore_adr_next_value1 <= 14'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_we_next_value2 <= 1'd0;
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_wishbone_dat_r <= 32'd0;
-	case (state)
+	litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
-			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value_ce2 <= 1'd0;
-	case (state)
+	litedramcore_we_next_value2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_we_next_value_ce2 <= 1'd1;
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value_ce2 <= 1'd1;
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_wishbone_ack <= 1'd0;
-	case (state)
+	litedramcore_we_next_value_ce2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
-			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_dat_w_next_value0 <= 32'd0;
-	case (state)
+	litedramcore_wishbone_dat_r <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_dat_w_next_value_ce0 <= 1'd0;
-	case (state)
+	litedramcore_wishbone_ack <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value1 <= 14'd0;
-	case (state)
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-			end
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value_ce1 <= 1'd0;
-	case (state)
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value_ce1 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
@@ -7911,28 +8120,28 @@ assign wb_bus_err = litedramcore_wishbone_err;
 assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank0_init_done0_re <= 1'd0;
+	csrbank0_init_done0_we <= 1'd0;
 	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank0_init_done0_re <= interface0_bank_bus_we;
+		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank0_init_done0_we <= 1'd0;
+	csrbank0_init_done0_re <= 1'd0;
 	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+		csrbank0_init_done0_re <= interface0_bank_bus_we;
 	end
 end
 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank0_init_error0_we <= 1'd0;
+	csrbank0_init_error0_re <= 1'd0;
 	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank0_init_error0_re <= 1'd0;
+	csrbank0_init_error0_we <= 1'd0;
 	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank0_init_error0_re <= interface0_bank_bus_we;
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
 assign csrbank0_init_done0_w = init_done_storage;
@@ -7940,15 +8149,15 @@ assign csrbank0_init_error0_w = init_error_storage;
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	csrbank1_dly_sel0_we <= 1'd0;
+	csrbank1_dly_sel0_re <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dly_sel0_re <= 1'd0;
+	csrbank1_dly_sel0_we <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
 	end
 end
 assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
@@ -8018,15 +8227,15 @@ always @(*) begin
 end
 assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	csrbank1_burstdet_seen_re <= 1'd0;
+	csrbank1_burstdet_seen_we <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
+		csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_burstdet_seen_we <= 1'd0;
+	csrbank1_burstdet_seen_re <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
+		csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0];
@@ -8035,132 +8244,132 @@ assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we;
 assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
 assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-	csrbank2_dfii_control0_re <= 1'd0;
+	csrbank2_dfii_control0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_control0_we <= 1'd0;
+	csrbank2_dfii_control0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_control0_re <= interface2_bank_bus_we;
 	end
 end
 assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank2_dfii_pi0_command0_we <= 1'd0;
+	csrbank2_dfii_pi0_command0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_command0_re <= 1'd0;
+	csrbank2_dfii_pi0_command0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	litedramcore_phaseinjector0_command_issue_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+		litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	litedramcore_phaseinjector0_command_issue_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+		litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	csrbank2_dfii_pi0_address0_re <= 1'd0;
+	csrbank2_dfii_pi0_address0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_address0_we <= 1'd0;
+	csrbank2_dfii_pi0_address0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
 	end
 end
 assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	csrbank2_dfii_pi0_baddress0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	csrbank2_dfii_pi0_baddress0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+	csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+	csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+	csrbank2_dfii_pi0_rddata1_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+	csrbank2_dfii_pi0_rddata1_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+	csrbank2_dfii_pi0_rddata0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+	csrbank2_dfii_pi0_rddata0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank2_dfii_pi1_command0_re <= 1'd0;
+	csrbank2_dfii_pi1_command0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_command0_we <= 1'd0;
+	csrbank2_dfii_pi1_command0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
 	end
 end
 assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
@@ -8178,80 +8387,80 @@ always @(*) begin
 end
 assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-	csrbank2_dfii_pi1_address0_re <= 1'd0;
+	csrbank2_dfii_pi1_address0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_address0_we <= 1'd0;
+	csrbank2_dfii_pi1_address0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
 	end
 end
 assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+	csrbank2_dfii_pi1_baddress0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+	csrbank2_dfii_pi1_baddress0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+	csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+	csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
 	end
 end
 assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+	csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+	csrbank2_dfii_pi1_rddata1_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+	csrbank2_dfii_pi1_rddata1_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+	csrbank2_dfii_pi1_rddata0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+	csrbank2_dfii_pi1_rddata0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
 	end
 end
 assign litedramcore_sel = litedramcore_storage[0];
@@ -8259,6 +8468,12 @@ assign litedramcore_cke = litedramcore_storage[1];
 assign litedramcore_odt = litedramcore_storage[2];
 assign litedramcore_reset_n = litedramcore_storage[3];
 assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
+assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
+assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
+assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
+assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
+assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
 assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
 assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
 assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
@@ -8267,6 +8482,12 @@ assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[
 assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32];
 assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0];
 assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we;
+assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
+assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
+assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
+assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
+assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
+assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
 assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
 assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
 assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
@@ -8813,7 +9034,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed12 <= 22'd0;
-	case (litedramcore_roundrobin0_grant)
+	case (litedramcore_litedramcore_roundrobin0_grant)
 		default: begin
 			rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8821,7 +9042,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed13 <= 1'd0;
-	case (litedramcore_roundrobin0_grant)
+	case (litedramcore_litedramcore_roundrobin0_grant)
 		default: begin
 			rhs_array_muxed13 <= user_port_cmd_payload_we;
 		end
@@ -8829,15 +9050,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed14 <= 1'd0;
-	case (litedramcore_roundrobin0_grant)
+	case (litedramcore_litedramcore_roundrobin0_grant)
 		default: begin
-			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed15 <= 22'd0;
-	case (litedramcore_roundrobin1_grant)
+	case (litedramcore_litedramcore_roundrobin1_grant)
 		default: begin
 			rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8845,7 +9066,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed16 <= 1'd0;
-	case (litedramcore_roundrobin1_grant)
+	case (litedramcore_litedramcore_roundrobin1_grant)
 		default: begin
 			rhs_array_muxed16 <= user_port_cmd_payload_we;
 		end
@@ -8853,15 +9074,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed17 <= 1'd0;
-	case (litedramcore_roundrobin1_grant)
+	case (litedramcore_litedramcore_roundrobin1_grant)
 		default: begin
-			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed18 <= 22'd0;
-	case (litedramcore_roundrobin2_grant)
+	case (litedramcore_litedramcore_roundrobin2_grant)
 		default: begin
 			rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8869,7 +9090,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed19 <= 1'd0;
-	case (litedramcore_roundrobin2_grant)
+	case (litedramcore_litedramcore_roundrobin2_grant)
 		default: begin
 			rhs_array_muxed19 <= user_port_cmd_payload_we;
 		end
@@ -8877,15 +9098,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed20 <= 1'd0;
-	case (litedramcore_roundrobin2_grant)
+	case (litedramcore_litedramcore_roundrobin2_grant)
 		default: begin
-			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed21 <= 22'd0;
-	case (litedramcore_roundrobin3_grant)
+	case (litedramcore_litedramcore_roundrobin3_grant)
 		default: begin
 			rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8893,7 +9114,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed22 <= 1'd0;
-	case (litedramcore_roundrobin3_grant)
+	case (litedramcore_litedramcore_roundrobin3_grant)
 		default: begin
 			rhs_array_muxed22 <= user_port_cmd_payload_we;
 		end
@@ -8901,15 +9122,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed23 <= 1'd0;
-	case (litedramcore_roundrobin3_grant)
+	case (litedramcore_litedramcore_roundrobin3_grant)
 		default: begin
-			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed24 <= 22'd0;
-	case (litedramcore_roundrobin4_grant)
+	case (litedramcore_litedramcore_roundrobin4_grant)
 		default: begin
 			rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8917,7 +9138,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed25 <= 1'd0;
-	case (litedramcore_roundrobin4_grant)
+	case (litedramcore_litedramcore_roundrobin4_grant)
 		default: begin
 			rhs_array_muxed25 <= user_port_cmd_payload_we;
 		end
@@ -8925,15 +9146,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed26 <= 1'd0;
-	case (litedramcore_roundrobin4_grant)
+	case (litedramcore_litedramcore_roundrobin4_grant)
 		default: begin
-			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed27 <= 22'd0;
-	case (litedramcore_roundrobin5_grant)
+	case (litedramcore_litedramcore_roundrobin5_grant)
 		default: begin
 			rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8941,7 +9162,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed28 <= 1'd0;
-	case (litedramcore_roundrobin5_grant)
+	case (litedramcore_litedramcore_roundrobin5_grant)
 		default: begin
 			rhs_array_muxed28 <= user_port_cmd_payload_we;
 		end
@@ -8949,15 +9170,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed29 <= 1'd0;
-	case (litedramcore_roundrobin5_grant)
+	case (litedramcore_litedramcore_roundrobin5_grant)
 		default: begin
-			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed30 <= 22'd0;
-	case (litedramcore_roundrobin6_grant)
+	case (litedramcore_litedramcore_roundrobin6_grant)
 		default: begin
 			rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8965,7 +9186,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed31 <= 1'd0;
-	case (litedramcore_roundrobin6_grant)
+	case (litedramcore_litedramcore_roundrobin6_grant)
 		default: begin
 			rhs_array_muxed31 <= user_port_cmd_payload_we;
 		end
@@ -8973,15 +9194,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed32 <= 1'd0;
-	case (litedramcore_roundrobin6_grant)
+	case (litedramcore_litedramcore_roundrobin6_grant)
 		default: begin
-			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed33 <= 22'd0;
-	case (litedramcore_roundrobin7_grant)
+	case (litedramcore_litedramcore_roundrobin7_grant)
 		default: begin
 			rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
 		end
@@ -8989,7 +9210,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed34 <= 1'd0;
-	case (litedramcore_roundrobin7_grant)
+	case (litedramcore_litedramcore_roundrobin7_grant)
 		default: begin
 			rhs_array_muxed34 <= user_port_cmd_payload_we;
 		end
@@ -8997,9 +9218,9 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed35 <= 1'd0;
-	case (litedramcore_roundrobin7_grant)
+	case (litedramcore_litedramcore_roundrobin7_grant)
 		default: begin
-			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
@@ -9647,11 +9868,11 @@ always @(posedge sys_clk) begin
 	ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3;
 	ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4;
 	ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5;
-	if (litedramcore_inti_p0_rddata_valid) begin
-		litedramcore_phaseinjector0_rddata_status <= litedramcore_inti_p0_rddata;
+	if (litedramcore_csr_dfi_p0_rddata_valid) begin
+		litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
 	end
-	if (litedramcore_inti_p1_rddata_valid) begin
-		litedramcore_phaseinjector1_rddata_status <= litedramcore_inti_p1_rddata;
+	if (litedramcore_csr_dfi_p1_rddata_valid) begin
+		litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
 	end
 	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
 		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
@@ -9753,7 +9974,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_refresher_state <= litedramcore_refresher_next_state;
+	litedramcore_litedramcore_refresher_state <= litedramcore_litedramcore_refresher_next_state;
 	if (litedramcore_bankmachine0_row_close) begin
 		litedramcore_bankmachine0_row_opened <= 1'd0;
 	end else begin
@@ -9829,7 +10050,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+	litedramcore_litedramcore_bankmachine0_state <= litedramcore_litedramcore_bankmachine0_next_state;
 	if (litedramcore_bankmachine1_row_close) begin
 		litedramcore_bankmachine1_row_opened <= 1'd0;
 	end else begin
@@ -9905,7 +10126,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+	litedramcore_litedramcore_bankmachine1_state <= litedramcore_litedramcore_bankmachine1_next_state;
 	if (litedramcore_bankmachine2_row_close) begin
 		litedramcore_bankmachine2_row_opened <= 1'd0;
 	end else begin
@@ -9981,7 +10202,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+	litedramcore_litedramcore_bankmachine2_state <= litedramcore_litedramcore_bankmachine2_next_state;
 	if (litedramcore_bankmachine3_row_close) begin
 		litedramcore_bankmachine3_row_opened <= 1'd0;
 	end else begin
@@ -10057,7 +10278,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+	litedramcore_litedramcore_bankmachine3_state <= litedramcore_litedramcore_bankmachine3_next_state;
 	if (litedramcore_bankmachine4_row_close) begin
 		litedramcore_bankmachine4_row_opened <= 1'd0;
 	end else begin
@@ -10133,7 +10354,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+	litedramcore_litedramcore_bankmachine4_state <= litedramcore_litedramcore_bankmachine4_next_state;
 	if (litedramcore_bankmachine5_row_close) begin
 		litedramcore_bankmachine5_row_opened <= 1'd0;
 	end else begin
@@ -10209,7 +10430,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+	litedramcore_litedramcore_bankmachine5_state <= litedramcore_litedramcore_bankmachine5_next_state;
 	if (litedramcore_bankmachine6_row_close) begin
 		litedramcore_bankmachine6_row_opened <= 1'd0;
 	end else begin
@@ -10285,7 +10506,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+	litedramcore_litedramcore_bankmachine6_state <= litedramcore_litedramcore_bankmachine6_next_state;
 	if (litedramcore_bankmachine7_row_close) begin
 		litedramcore_bankmachine7_row_opened <= 1'd0;
 	end else begin
@@ -10361,7 +10582,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+	litedramcore_litedramcore_bankmachine7_state <= litedramcore_litedramcore_bankmachine7_next_state;
 	if ((~litedramcore_en0)) begin
 		litedramcore_time0 <= 5'd31;
 	end else begin
@@ -10917,26 +11138,26 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
-	litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
-	litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
-	litedramcore_new_master_wdata_ready2 <= litedramcore_new_master_wdata_ready1;
-	litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2;
-	litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
-	litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
-	litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
-	litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
-	litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
-	litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
-	litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
-	litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
-	litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
-	litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8;
-	litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9;
-	litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10;
-	litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11;
-	litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12;
-	state <= next_state;
+	litedramcore_litedramcore_multiplexer_state <= litedramcore_litedramcore_multiplexer_next_state;
+	litedramcore_litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+	litedramcore_litedramcore_new_master_wdata_ready1 <= litedramcore_litedramcore_new_master_wdata_ready0;
+	litedramcore_litedramcore_new_master_wdata_ready2 <= litedramcore_litedramcore_new_master_wdata_ready1;
+	litedramcore_litedramcore_new_master_wdata_ready3 <= litedramcore_litedramcore_new_master_wdata_ready2;
+	litedramcore_litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+	litedramcore_litedramcore_new_master_rdata_valid1 <= litedramcore_litedramcore_new_master_rdata_valid0;
+	litedramcore_litedramcore_new_master_rdata_valid2 <= litedramcore_litedramcore_new_master_rdata_valid1;
+	litedramcore_litedramcore_new_master_rdata_valid3 <= litedramcore_litedramcore_new_master_rdata_valid2;
+	litedramcore_litedramcore_new_master_rdata_valid4 <= litedramcore_litedramcore_new_master_rdata_valid3;
+	litedramcore_litedramcore_new_master_rdata_valid5 <= litedramcore_litedramcore_new_master_rdata_valid4;
+	litedramcore_litedramcore_new_master_rdata_valid6 <= litedramcore_litedramcore_new_master_rdata_valid5;
+	litedramcore_litedramcore_new_master_rdata_valid7 <= litedramcore_litedramcore_new_master_rdata_valid6;
+	litedramcore_litedramcore_new_master_rdata_valid8 <= litedramcore_litedramcore_new_master_rdata_valid7;
+	litedramcore_litedramcore_new_master_rdata_valid9 <= litedramcore_litedramcore_new_master_rdata_valid8;
+	litedramcore_litedramcore_new_master_rdata_valid10 <= litedramcore_litedramcore_new_master_rdata_valid9;
+	litedramcore_litedramcore_new_master_rdata_valid11 <= litedramcore_litedramcore_new_master_rdata_valid10;
+	litedramcore_litedramcore_new_master_rdata_valid12 <= litedramcore_litedramcore_new_master_rdata_valid11;
+	litedramcore_litedramcore_new_master_rdata_valid13 <= litedramcore_litedramcore_new_master_rdata_valid12;
+	litedramcore_state <= litedramcore_next_state;
 	if (litedramcore_dat_w_next_value_ce0) begin
 		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
 	end
@@ -11101,7 +11322,7 @@ always @(posedge sys_clk) begin
 		ddrphy_dly_sel_re <= 1'd0;
 		ddrphy_burstdet_seen_status <= 2'd0;
 		ddrphy_burstdet_seen_re <= 1'd0;
-		ddrphy_rdly0 <= 7'd0;
+		ddrphy_rdly0 <= 3'd0;
 		ddrphy_burstdet_d0 <= 1'd0;
 		ddrphy_dm_o_data_d0 <= 8'd0;
 		ddrphy_dm_o_data_muxed0 <= 4'd0;
@@ -11137,7 +11358,7 @@ always @(posedge sys_clk) begin
 		ddrphy_dq_o_data_muxed7 <= 4'd0;
 		ddrphy_bitslip7_value <= 2'd0;
 		ddrphy_dq_i_bitslip_o_d7 <= 4'd0;
-		ddrphy_rdly1 <= 7'd0;
+		ddrphy_rdly1 <= 3'd0;
 		ddrphy_burstdet_d1 <= 1'd0;
 		ddrphy_dm_o_data_d1 <= 8'd0;
 		ddrphy_dm_o_data_muxed1 <= 4'd0;
@@ -11367,36 +11588,36 @@ always @(posedge sys_clk) begin
 		init_done_re <= 1'd0;
 		init_error_storage <= 1'd0;
 		init_error_re <= 1'd0;
-		litedramcore_refresher_state <= 2'd0;
-		litedramcore_bankmachine0_state <= 3'd0;
-		litedramcore_bankmachine1_state <= 3'd0;
-		litedramcore_bankmachine2_state <= 3'd0;
-		litedramcore_bankmachine3_state <= 3'd0;
-		litedramcore_bankmachine4_state <= 3'd0;
-		litedramcore_bankmachine5_state <= 3'd0;
-		litedramcore_bankmachine6_state <= 3'd0;
-		litedramcore_bankmachine7_state <= 3'd0;
-		litedramcore_multiplexer_state <= 4'd0;
-		litedramcore_new_master_wdata_ready0 <= 1'd0;
-		litedramcore_new_master_wdata_ready1 <= 1'd0;
-		litedramcore_new_master_wdata_ready2 <= 1'd0;
-		litedramcore_new_master_wdata_ready3 <= 1'd0;
-		litedramcore_new_master_rdata_valid0 <= 1'd0;
-		litedramcore_new_master_rdata_valid1 <= 1'd0;
-		litedramcore_new_master_rdata_valid2 <= 1'd0;
-		litedramcore_new_master_rdata_valid3 <= 1'd0;
-		litedramcore_new_master_rdata_valid4 <= 1'd0;
-		litedramcore_new_master_rdata_valid5 <= 1'd0;
-		litedramcore_new_master_rdata_valid6 <= 1'd0;
-		litedramcore_new_master_rdata_valid7 <= 1'd0;
-		litedramcore_new_master_rdata_valid8 <= 1'd0;
-		litedramcore_new_master_rdata_valid9 <= 1'd0;
-		litedramcore_new_master_rdata_valid10 <= 1'd0;
-		litedramcore_new_master_rdata_valid11 <= 1'd0;
-		litedramcore_new_master_rdata_valid12 <= 1'd0;
-		litedramcore_new_master_rdata_valid13 <= 1'd0;
 		litedramcore_we <= 1'd0;
-		state <= 2'd0;
+		litedramcore_litedramcore_refresher_state <= 2'd0;
+		litedramcore_litedramcore_bankmachine0_state <= 3'd0;
+		litedramcore_litedramcore_bankmachine1_state <= 3'd0;
+		litedramcore_litedramcore_bankmachine2_state <= 3'd0;
+		litedramcore_litedramcore_bankmachine3_state <= 3'd0;
+		litedramcore_litedramcore_bankmachine4_state <= 3'd0;
+		litedramcore_litedramcore_bankmachine5_state <= 3'd0;
+		litedramcore_litedramcore_bankmachine6_state <= 3'd0;
+		litedramcore_litedramcore_bankmachine7_state <= 3'd0;
+		litedramcore_litedramcore_multiplexer_state <= 4'd0;
+		litedramcore_litedramcore_new_master_wdata_ready0 <= 1'd0;
+		litedramcore_litedramcore_new_master_wdata_ready1 <= 1'd0;
+		litedramcore_litedramcore_new_master_wdata_ready2 <= 1'd0;
+		litedramcore_litedramcore_new_master_wdata_ready3 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid0 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid1 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid2 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid3 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid4 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid5 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid6 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid7 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid8 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid9 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid10 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid11 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid12 <= 1'd0;
+		litedramcore_litedramcore_new_master_rdata_valid13 <= 1'd0;
+		litedramcore_state <= 2'd0;
 	end
 end
 
@@ -12961,8 +13182,8 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[l
 	.STDBY(crg_stdby),
 	.CLKOP(crg_clkout0),
 	.CLKOS(crg_clkout1),
-	.CLKOS2(litedramecp5ddrphycrg_ecp5pll),
-	.LOCK(litedramecp5ddrphycrg_locked)
+	.CLKOS2(litedramcore_litedramecp5ddrphycrg_ecp5pll),
+	.LOCK(litedramcore_litedramecp5ddrphycrg_locked)
 );
 
 FD1S3BX FD1S3BX(
@@ -13186,5 +13407,5 @@ TRELLIS_IO #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-01-14 09:35:05.
+//  Auto-Generated by LiteX on 2022-08-04 21:07:03.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init
index e0b2512..c3dd752 100644
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10e0658cff00
+618c10d8658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -519,213 +519,215 @@ a64b5a7d14004a39
 0000000000000000
 3c4c000100000000
 7c0802a63842a3c4
-fbe1fff8fbc1fff0
-f821ff51f8010010
-f88100d83bc10020
+f8010010fbe1fff8
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 38800080f8a100e0
 f8c100e87c651b78
-38c100d87fc3f378
+38c100d838610020
 f90100f8f8e100f0
 f9410108f9210100
-60000000480017fd
-7fc3f3787c7f1b78
-6000000048001221
+6000000048001781
+386100207c7f1b78
+6000000048001199
 7fe3fb78382100b0
-0000000048001e78
-0000028001000000
+0000000048001e88
+0000018001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842a3203c4c0001
-7d8000267c0802a6
-9181000848001db5
-4800121df821fed1
+3842a3283c4c0001
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+9161000848001dc1
+48001195f821fed1
 3c62ffff60000000
-4bffff3938637b38
+4bffff4138637b38
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
 63ff000838637b58
-3c62ffff4bffff15
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 38637b787bff0020
-7c0004ac4bffff05
+7c0004ac4bffff0d
 73e900017fe0feea
 3c62ffff41820010
-4bfffee938637b90
-4e00000073e90002
+4bfffef138637b90
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 3c62ffff41820010
-4bfffed138637b98
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+4e00000073e90004
 3c62ffff41820010
-4bfffeb938637ba0
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 4d00000073e90008
 3c62ffff41820010
-4bfffea138637ba8
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 4182001073e90010
 38637bb83c62ffff
-73ff01004bfffe8d
+73ff01004bfffe95
 3c62ffff41820010
-4bfffe7938637bc8
+4bfffe8138637bc8
 3b7b7bd03f62ffff
-4bfffe697f63db78
-3c80c000418e0028
+4bfffe717f63db78
+3c80c00041920028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4138637bd8
-3c80c0004192004c
+4bfffe4938637bd8
+3c80c000418e004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe1938637bf0
+4bfffe2138637bf0
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
 38637c087884b282
-3d20c0004bfffdf5
+3d20c0004bfffdfd
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
 38637c207c892392
-418a025c4bfffdc5
-639c00383f80c000
-7c0004ac7b9c0020
-3d40c0007f80e6ea
+418a02604bfffdcd
+63de00383fc0c000
+7c0004ac7bde0020
+3d40c0007fc0f6ea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
 63ff60003920ff9f
 7c0004ac7bff0020
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+7f03c3787c6f1b78
+600000004bfff6bd
+408100647c2f1840
+7f5ac8507d0ef850
+7c6378507d08ca14
+7c6e1a142c280000
+38e0002039400000
+408200083b5a0001
+2c3a00013b400001
+408200143b5affff
+41820024714a0001
+4800001cf9c10060
+39ce000198ee0000
+7c23704039400001
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+4bfff8a57c84c850
+893600014bfffdd0
+2c09006c3aa00008
+7cf63b784082fdc0
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+2c0900683aa00002
+7cf63b784082fda8
+4bfffd9c3aa00001
+554a063e3949ffd0
+4181fd8c280a0009
+3af700017aea0020
+992a00207d415214
+3aa000084bfffd78
+3a6000204bfffd70
+4bfffba43ac10041
+3bff0001993f0000
+fbe100607d054378
+000000004bfffaf4
+0000128001000000
+f9e1ff78f9c1ff70
+fa21ff88fa01ff80
+fa61ff98fa41ff90
+faa1ffa8fa81ffa0
+fae1ffb8fac1ffb0
+fb21ffc8fb01ffc0
+fb61ffd8fb41ffd0
+fba1ffe8fb81ffe0
+fbe1fff8fbc1fff0
+4e800020f8010010
+e9e1ff78e9c1ff70
+ea21ff88ea01ff80
+ea61ff98ea41ff90
+eaa1ffa8ea81ffa0
+eae1ffb8eac1ffb0
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+e8010010eb81ffe0
+7c0803a6eba1ffe8
+ebe1fff8ebc1fff0
+ebc1fff04e800020
+ebe1fff8e8010010
+4e8000207c0803a6
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -1559,17 +1559,15 @@ e8010010ebc1fff0
 203a46464f204853
 7479622078257830
 00000000000a7365
-2d2d2d2d2d2d2d2d
-0000000000000000
-4d4152446574694c
-6620746c69756220
-6567694d206d6f72
-646e61207325206e
-2520586574694c20
-0000000000000a73
 20676e69746f6f42
 415242206d6f7266
 0000000a2e2e2e4d
+3135636632333936
+0000000000000000
+4d4152446574694c
+6620746c69756220
+6574694c206d6f72
+0000000a73252058
 6620676e69797254
 0a2e2e2e6873616c
 0000000000000000
diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v
index 1d6e21d..f7462d1 100644
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-01-14 08:32:16
+// LiteX sha1 : 6932fc51
+// Date       : 2022-08-04 21:07:04
 //------------------------------------------------------------------------------
 
 
@@ -379,70 +379,6 @@ reg  soc_ddrphy_new_banks_read6 = 1'd0;
 reg  [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
 reg  soc_ddrphy_new_banks_read7 = 1'd0;
 reg  [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
-wire [13:0] soc_litedramcore_inti_p0_address;
-wire [2:0] soc_litedramcore_inti_p0_bank;
-reg  soc_litedramcore_inti_p0_cas_n = 1'd1;
-reg  soc_litedramcore_inti_p0_cs_n = 1'd1;
-reg  soc_litedramcore_inti_p0_ras_n = 1'd1;
-reg  soc_litedramcore_inti_p0_we_n = 1'd1;
-wire soc_litedramcore_inti_p0_cke;
-wire soc_litedramcore_inti_p0_odt;
-wire soc_litedramcore_inti_p0_reset_n;
-reg  soc_litedramcore_inti_p0_act_n = 1'd1;
-wire [31:0] soc_litedramcore_inti_p0_wrdata;
-wire soc_litedramcore_inti_p0_wrdata_en;
-wire [3:0] soc_litedramcore_inti_p0_wrdata_mask;
-wire soc_litedramcore_inti_p0_rddata_en;
-reg  [31:0] soc_litedramcore_inti_p0_rddata = 32'd0;
-reg  soc_litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_inti_p1_address;
-wire [2:0] soc_litedramcore_inti_p1_bank;
-reg  soc_litedramcore_inti_p1_cas_n = 1'd1;
-reg  soc_litedramcore_inti_p1_cs_n = 1'd1;
-reg  soc_litedramcore_inti_p1_ras_n = 1'd1;
-reg  soc_litedramcore_inti_p1_we_n = 1'd1;
-wire soc_litedramcore_inti_p1_cke;
-wire soc_litedramcore_inti_p1_odt;
-wire soc_litedramcore_inti_p1_reset_n;
-reg  soc_litedramcore_inti_p1_act_n = 1'd1;
-wire [31:0] soc_litedramcore_inti_p1_wrdata;
-wire soc_litedramcore_inti_p1_wrdata_en;
-wire [3:0] soc_litedramcore_inti_p1_wrdata_mask;
-wire soc_litedramcore_inti_p1_rddata_en;
-reg  [31:0] soc_litedramcore_inti_p1_rddata = 32'd0;
-reg  soc_litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_inti_p2_address;
-wire [2:0] soc_litedramcore_inti_p2_bank;
-reg  soc_litedramcore_inti_p2_cas_n = 1'd1;
-reg  soc_litedramcore_inti_p2_cs_n = 1'd1;
-reg  soc_litedramcore_inti_p2_ras_n = 1'd1;
-reg  soc_litedramcore_inti_p2_we_n = 1'd1;
-wire soc_litedramcore_inti_p2_cke;
-wire soc_litedramcore_inti_p2_odt;
-wire soc_litedramcore_inti_p2_reset_n;
-reg  soc_litedramcore_inti_p2_act_n = 1'd1;
-wire [31:0] soc_litedramcore_inti_p2_wrdata;
-wire soc_litedramcore_inti_p2_wrdata_en;
-wire [3:0] soc_litedramcore_inti_p2_wrdata_mask;
-wire soc_litedramcore_inti_p2_rddata_en;
-reg  [31:0] soc_litedramcore_inti_p2_rddata = 32'd0;
-reg  soc_litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_inti_p3_address;
-wire [2:0] soc_litedramcore_inti_p3_bank;
-reg  soc_litedramcore_inti_p3_cas_n = 1'd1;
-reg  soc_litedramcore_inti_p3_cs_n = 1'd1;
-reg  soc_litedramcore_inti_p3_ras_n = 1'd1;
-reg  soc_litedramcore_inti_p3_we_n = 1'd1;
-wire soc_litedramcore_inti_p3_cke;
-wire soc_litedramcore_inti_p3_odt;
-wire soc_litedramcore_inti_p3_reset_n;
-reg  soc_litedramcore_inti_p3_act_n = 1'd1;
-wire [31:0] soc_litedramcore_inti_p3_wrdata;
-wire soc_litedramcore_inti_p3_wrdata_en;
-wire [3:0] soc_litedramcore_inti_p3_wrdata_mask;
-wire soc_litedramcore_inti_p3_rddata_en;
-reg  [31:0] soc_litedramcore_inti_p3_rddata = 32'd0;
-reg  soc_litedramcore_inti_p3_rddata_valid = 1'd0;
 wire [13:0] soc_litedramcore_slave_p0_address;
 wire [2:0] soc_litedramcore_slave_p0_bank;
 wire soc_litedramcore_slave_p0_cas_n;
@@ -571,12 +507,147 @@ reg  [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
 reg  soc_litedramcore_master_p3_rddata_en = 1'd0;
 wire [31:0] soc_litedramcore_master_p3_rddata;
 wire soc_litedramcore_master_p3_rddata_valid;
+wire [13:0] soc_litedramcore_csr_dfi_p0_address;
+wire [2:0] soc_litedramcore_csr_dfi_p0_bank;
+reg  soc_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p0_cke;
+wire soc_litedramcore_csr_dfi_p0_odt;
+wire soc_litedramcore_csr_dfi_p0_reset_n;
+reg  soc_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata;
+wire soc_litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p0_rddata_en;
+reg  [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg  soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_csr_dfi_p1_address;
+wire [2:0] soc_litedramcore_csr_dfi_p1_bank;
+reg  soc_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p1_cke;
+wire soc_litedramcore_csr_dfi_p1_odt;
+wire soc_litedramcore_csr_dfi_p1_reset_n;
+reg  soc_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata;
+wire soc_litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p1_rddata_en;
+reg  [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg  soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_csr_dfi_p2_address;
+wire [2:0] soc_litedramcore_csr_dfi_p2_bank;
+reg  soc_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p2_cke;
+wire soc_litedramcore_csr_dfi_p2_odt;
+wire soc_litedramcore_csr_dfi_p2_reset_n;
+reg  soc_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata;
+wire soc_litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p2_rddata_en;
+reg  [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg  soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_csr_dfi_p3_address;
+wire [2:0] soc_litedramcore_csr_dfi_p3_bank;
+reg  soc_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg  soc_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p3_cke;
+wire soc_litedramcore_csr_dfi_p3_odt;
+wire soc_litedramcore_csr_dfi_p3_reset_n;
+reg  soc_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata;
+wire soc_litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p3_rddata_en;
+reg  [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg  soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg  [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0;
+reg  [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg  soc_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg  soc_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg  soc_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg  soc_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg  soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg  [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg  [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0;
+reg  [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg  soc_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg  soc_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg  soc_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg  soc_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg  soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg  [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg  [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0;
+reg  [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg  soc_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg  soc_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg  soc_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg  soc_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg  soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg  [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg  [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0;
+reg  [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg  soc_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg  soc_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg  soc_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg  soc_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg  soc_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg  [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg  [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg  soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg  [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg  soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg  soc_litedramcore_ext_dfi_sel = 1'd0;
 wire soc_litedramcore_sel;
 wire soc_litedramcore_cke;
 wire soc_litedramcore_odt;
 wire soc_litedramcore_reset_n;
 reg  [3:0] soc_litedramcore_storage = 4'd1;
 reg  soc_litedramcore_re = 1'd0;
+wire soc_litedramcore_phaseinjector0_csrfield_cs;
+wire soc_litedramcore_phaseinjector0_csrfield_we;
+wire soc_litedramcore_phaseinjector0_csrfield_cas;
+wire soc_litedramcore_phaseinjector0_csrfield_ras;
+wire soc_litedramcore_phaseinjector0_csrfield_wren;
+wire soc_litedramcore_phaseinjector0_csrfield_rden;
 reg  [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
 reg  soc_litedramcore_phaseinjector0_command_re = 1'd0;
 reg  soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
@@ -592,6 +663,12 @@ reg  soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
 reg  [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
 wire soc_litedramcore_phaseinjector0_rddata_we;
 reg  soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire soc_litedramcore_phaseinjector1_csrfield_cs;
+wire soc_litedramcore_phaseinjector1_csrfield_we;
+wire soc_litedramcore_phaseinjector1_csrfield_cas;
+wire soc_litedramcore_phaseinjector1_csrfield_ras;
+wire soc_litedramcore_phaseinjector1_csrfield_wren;
+wire soc_litedramcore_phaseinjector1_csrfield_rden;
 reg  [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
 reg  soc_litedramcore_phaseinjector1_command_re = 1'd0;
 reg  soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
@@ -607,6 +684,12 @@ reg  soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
 reg  [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
 wire soc_litedramcore_phaseinjector1_rddata_we;
 reg  soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire soc_litedramcore_phaseinjector2_csrfield_cs;
+wire soc_litedramcore_phaseinjector2_csrfield_we;
+wire soc_litedramcore_phaseinjector2_csrfield_cas;
+wire soc_litedramcore_phaseinjector2_csrfield_ras;
+wire soc_litedramcore_phaseinjector2_csrfield_wren;
+wire soc_litedramcore_phaseinjector2_csrfield_rden;
 reg  [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
 reg  soc_litedramcore_phaseinjector2_command_re = 1'd0;
 reg  soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
@@ -622,6 +705,12 @@ reg  soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
 reg  [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
 wire soc_litedramcore_phaseinjector2_rddata_we;
 reg  soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire soc_litedramcore_phaseinjector3_csrfield_cs;
+wire soc_litedramcore_phaseinjector3_csrfield_we;
+wire soc_litedramcore_phaseinjector3_csrfield_cas;
+wire soc_litedramcore_phaseinjector3_csrfield_ras;
+wire soc_litedramcore_phaseinjector3_csrfield_wren;
+wire soc_litedramcore_phaseinjector3_csrfield_rden;
 reg  [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
 reg  soc_litedramcore_phaseinjector3_command_re = 1'd0;
 reg  soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
@@ -1567,69 +1656,6 @@ wire [15:0] soc_user_port_wdata_payload_we;
 wire soc_user_port_rdata_valid;
 wire soc_user_port_rdata_ready;
 wire [127:0] soc_user_port_rdata_payload_data;
-reg  [1:0] refresher_state = 2'd0;
-reg  [1:0] refresher_next_state = 2'd0;
-reg  [3:0] bankmachine0_state = 4'd0;
-reg  [3:0] bankmachine0_next_state = 4'd0;
-reg  [3:0] bankmachine1_state = 4'd0;
-reg  [3:0] bankmachine1_next_state = 4'd0;
-reg  [3:0] bankmachine2_state = 4'd0;
-reg  [3:0] bankmachine2_next_state = 4'd0;
-reg  [3:0] bankmachine3_state = 4'd0;
-reg  [3:0] bankmachine3_next_state = 4'd0;
-reg  [3:0] bankmachine4_state = 4'd0;
-reg  [3:0] bankmachine4_next_state = 4'd0;
-reg  [3:0] bankmachine5_state = 4'd0;
-reg  [3:0] bankmachine5_next_state = 4'd0;
-reg  [3:0] bankmachine6_state = 4'd0;
-reg  [3:0] bankmachine6_next_state = 4'd0;
-reg  [3:0] bankmachine7_state = 4'd0;
-reg  [3:0] bankmachine7_next_state = 4'd0;
-reg  [3:0] multiplexer_state = 4'd0;
-reg  [3:0] multiplexer_next_state = 4'd0;
-wire roundrobin0_request;
-wire roundrobin0_grant;
-wire roundrobin0_ce;
-wire roundrobin1_request;
-wire roundrobin1_grant;
-wire roundrobin1_ce;
-wire roundrobin2_request;
-wire roundrobin2_grant;
-wire roundrobin2_ce;
-wire roundrobin3_request;
-wire roundrobin3_grant;
-wire roundrobin3_ce;
-wire roundrobin4_request;
-wire roundrobin4_grant;
-wire roundrobin4_ce;
-wire roundrobin5_request;
-wire roundrobin5_grant;
-wire roundrobin5_ce;
-wire roundrobin6_request;
-wire roundrobin6_grant;
-wire roundrobin6_ce;
-wire roundrobin7_request;
-wire roundrobin7_grant;
-wire roundrobin7_ce;
-reg  locked0 = 1'd0;
-reg  locked1 = 1'd0;
-reg  locked2 = 1'd0;
-reg  locked3 = 1'd0;
-reg  locked4 = 1'd0;
-reg  locked5 = 1'd0;
-reg  locked6 = 1'd0;
-reg  locked7 = 1'd0;
-reg  new_master_wdata_ready0 = 1'd0;
-reg  new_master_wdata_ready1 = 1'd0;
-reg  new_master_rdata_valid0 = 1'd0;
-reg  new_master_rdata_valid1 = 1'd0;
-reg  new_master_rdata_valid2 = 1'd0;
-reg  new_master_rdata_valid3 = 1'd0;
-reg  new_master_rdata_valid4 = 1'd0;
-reg  new_master_rdata_valid5 = 1'd0;
-reg  new_master_rdata_valid6 = 1'd0;
-reg  new_master_rdata_valid7 = 1'd0;
-reg  new_master_rdata_valid8 = 1'd0;
 reg  [13:0] litedramcore_adr = 14'd0;
 reg  litedramcore_we = 1'd0;
 reg  [31:0] litedramcore_dat_w = 32'd0;
@@ -1751,8 +1777,71 @@ wire [13:0] csr_interconnect_adr;
 wire csr_interconnect_we;
 wire [31:0] csr_interconnect_dat_w;
 wire [31:0] csr_interconnect_dat_r;
-reg  [1:0] state = 2'd0;
-reg  [1:0] next_state = 2'd0;
+reg  [1:0] litedramcore_refresher_state = 2'd0;
+reg  [1:0] litedramcore_refresher_next_state = 2'd0;
+reg  [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg  litedramcore_locked0 = 1'd0;
+reg  litedramcore_locked1 = 1'd0;
+reg  litedramcore_locked2 = 1'd0;
+reg  litedramcore_locked3 = 1'd0;
+reg  litedramcore_locked4 = 1'd0;
+reg  litedramcore_locked5 = 1'd0;
+reg  litedramcore_locked6 = 1'd0;
+reg  litedramcore_locked7 = 1'd0;
+reg  litedramcore_new_master_wdata_ready0 = 1'd0;
+reg  litedramcore_new_master_wdata_ready1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid0 = 1'd0;
+reg  litedramcore_new_master_rdata_valid1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid2 = 1'd0;
+reg  litedramcore_new_master_rdata_valid3 = 1'd0;
+reg  litedramcore_new_master_rdata_valid4 = 1'd0;
+reg  litedramcore_new_master_rdata_valid5 = 1'd0;
+reg  litedramcore_new_master_rdata_valid6 = 1'd0;
+reg  litedramcore_new_master_rdata_valid7 = 1'd0;
+reg  litedramcore_new_master_rdata_valid8 = 1'd0;
+reg  [1:0] litedramcore_state = 2'd0;
+reg  [1:0] litedramcore_next_state = 2'd0;
 reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
 reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
 reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
@@ -3643,729 +3732,1057 @@ assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en;
 assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata;
 assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid;
 always @(*) begin
-	soc_litedramcore_master_p0_cs_n <= 1'd1;
+	soc_litedramcore_ext_dfi_p3_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
+		end else begin
+		end
 	end else begin
-		soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_ras_n <= 1'd1;
+	soc_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+		end else begin
+		end
 	end else begin
-		soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p0_rddata <= 32'd0;
+	soc_litedramcore_slave_p1_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_we_n <= 1'd1;
+	soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+		end
 	end else begin
-		soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
+	soc_litedramcore_slave_p2_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_cke <= 1'd0;
+	soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+		end
 	end else begin
-		soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_odt <= 1'd0;
+	soc_litedramcore_slave_p3_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
+		end
 	end else begin
-		soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_reset_n <= 1'd0;
+	soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+		end
 	end else begin
-		soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_act_n <= 1'd1;
+	soc_litedramcore_master_p0_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_address <= soc_litedramcore_ext_dfi_p0_address;
+		end else begin
+			soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
+		end
 	end else begin
-		soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n;
+		soc_litedramcore_master_p0_address <= soc_litedramcore_csr_dfi_p0_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_wrdata <= 32'd0;
+	soc_litedramcore_master_p0_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_bank <= soc_litedramcore_ext_dfi_p0_bank;
+		end else begin
+			soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
+		end
 	end else begin
-		soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata;
+		soc_litedramcore_master_p0_bank <= soc_litedramcore_csr_dfi_p0_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_rddata <= 32'd0;
+	soc_litedramcore_master_p0_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_cas_n <= soc_litedramcore_ext_dfi_p0_cas_n;
+		end else begin
+			soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
+		end
 	end else begin
-		soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata;
+		soc_litedramcore_master_p0_cas_n <= soc_litedramcore_csr_dfi_p0_cas_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_wrdata_en <= 1'd0;
+	soc_litedramcore_master_p0_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n;
+		end else begin
+			soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
+		end
 	end else begin
-		soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en;
+		soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_rddata_valid <= 1'd0;
+	soc_litedramcore_master_p0_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_ras_n <= soc_litedramcore_ext_dfi_p0_ras_n;
+		end else begin
+			soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
+		end
 	end else begin
-		soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+		soc_litedramcore_master_p0_ras_n <= soc_litedramcore_csr_dfi_p0_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
+	soc_litedramcore_master_p0_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_we_n <= soc_litedramcore_ext_dfi_p0_we_n;
+		end else begin
+			soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
+		end
 	end else begin
-		soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask;
+		soc_litedramcore_master_p0_we_n <= soc_litedramcore_csr_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_rddata_en <= 1'd0;
+	soc_litedramcore_master_p0_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_cke <= soc_litedramcore_ext_dfi_p0_cke;
+		end else begin
+			soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
+		end
 	end else begin
-		soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en;
+		soc_litedramcore_master_p0_cke <= soc_litedramcore_csr_dfi_p0_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_address <= 14'd0;
+	soc_litedramcore_master_p0_odt <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_odt <= soc_litedramcore_ext_dfi_p0_odt;
+		end else begin
+			soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
+		end
 	end else begin
-		soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address;
+		soc_litedramcore_master_p0_odt <= soc_litedramcore_csr_dfi_p0_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_bank <= 3'd0;
+	soc_litedramcore_master_p0_reset_n <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_reset_n <= soc_litedramcore_ext_dfi_p0_reset_n;
+		end else begin
+			soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
+		end
 	end else begin
-		soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank;
+		soc_litedramcore_master_p0_reset_n <= soc_litedramcore_csr_dfi_p0_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_cas_n <= 1'd1;
+	soc_litedramcore_master_p0_act_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_act_n <= soc_litedramcore_ext_dfi_p0_act_n;
+		end else begin
+			soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
+		end
 	end else begin
-		soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n;
+		soc_litedramcore_master_p0_act_n <= soc_litedramcore_csr_dfi_p0_act_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_cs_n <= 1'd1;
+	soc_litedramcore_master_p0_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_wrdata <= soc_litedramcore_ext_dfi_p0_wrdata;
+		end else begin
+			soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
+		end
 	end else begin
-		soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n;
+		soc_litedramcore_master_p0_wrdata <= soc_litedramcore_csr_dfi_p0_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_ras_n <= 1'd1;
+	soc_litedramcore_master_p0_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_ext_dfi_p0_wrdata_en;
+		end else begin
+			soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
+		end
 	end else begin
-		soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n;
+		soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_csr_dfi_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p1_rddata <= 32'd0;
+	soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_ext_dfi_p0_wrdata_mask;
+		end else begin
+			soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
+		end
 	end else begin
+		soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_csr_dfi_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_we_n <= 1'd1;
+	soc_litedramcore_master_p0_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_ext_dfi_p0_rddata_en;
+		end else begin
+			soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
+		end
 	end else begin
-		soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n;
+		soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_csr_dfi_p0_rddata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
+	soc_litedramcore_master_p1_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_address <= soc_litedramcore_ext_dfi_p1_address;
+		end else begin
+			soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
+		end
 	end else begin
+		soc_litedramcore_master_p1_address <= soc_litedramcore_csr_dfi_p1_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_cke <= 1'd0;
+	soc_litedramcore_master_p1_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_bank <= soc_litedramcore_ext_dfi_p1_bank;
+		end else begin
+			soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
+		end
 	end else begin
-		soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke;
+		soc_litedramcore_master_p1_bank <= soc_litedramcore_csr_dfi_p1_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_odt <= 1'd0;
+	soc_litedramcore_master_p1_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_cas_n <= soc_litedramcore_ext_dfi_p1_cas_n;
+		end else begin
+			soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
+		end
 	end else begin
-		soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt;
+		soc_litedramcore_master_p1_cas_n <= soc_litedramcore_csr_dfi_p1_cas_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_reset_n <= 1'd0;
+	soc_litedramcore_master_p1_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n;
+		end else begin
+			soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
+		end
 	end else begin
-		soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n;
+		soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_act_n <= 1'd1;
+	soc_litedramcore_master_p1_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_ras_n <= soc_litedramcore_ext_dfi_p1_ras_n;
+		end else begin
+			soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
+		end
 	end else begin
-		soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n;
+		soc_litedramcore_master_p1_ras_n <= soc_litedramcore_csr_dfi_p1_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_wrdata <= 32'd0;
+	soc_litedramcore_master_p1_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_we_n <= soc_litedramcore_ext_dfi_p1_we_n;
+		end else begin
+			soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
+		end
 	end else begin
-		soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata;
+		soc_litedramcore_master_p1_we_n <= soc_litedramcore_csr_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_rddata <= 32'd0;
+	soc_litedramcore_master_p1_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_cke <= soc_litedramcore_ext_dfi_p1_cke;
+		end else begin
+			soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
+		end
 	end else begin
-		soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata;
+		soc_litedramcore_master_p1_cke <= soc_litedramcore_csr_dfi_p1_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p1_wrdata_en <= 1'd0;
+	soc_litedramcore_master_p1_odt <= 1'd0;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_odt <= soc_litedramcore_ext_dfi_p1_odt;
+		end else begin
+			soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
+		end
+	end else begin
+		soc_litedramcore_master_p1_odt <= soc_litedramcore_csr_dfi_p1_odt;
+	end
+end
+always @(*) begin
+	soc_litedramcore_master_p1_reset_n <= 1'd0;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_reset_n <= soc_litedramcore_ext_dfi_p1_reset_n;
+		end else begin
+			soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
+		end
+	end else begin
+		soc_litedramcore_master_p1_reset_n <= soc_litedramcore_csr_dfi_p1_reset_n;
+	end
+end
+always @(*) begin
+	soc_litedramcore_master_p1_act_n <= 1'd1;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_act_n <= soc_litedramcore_ext_dfi_p1_act_n;
+		end else begin
+			soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
+		end
+	end else begin
+		soc_litedramcore_master_p1_act_n <= soc_litedramcore_csr_dfi_p1_act_n;
+	end
+end
+always @(*) begin
+	soc_litedramcore_master_p1_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_wrdata <= soc_litedramcore_ext_dfi_p1_wrdata;
+		end else begin
+			soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
+		end
 	end else begin
-		soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en;
+		soc_litedramcore_master_p1_wrdata <= soc_litedramcore_csr_dfi_p1_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_rddata_valid <= 1'd0;
+	soc_litedramcore_master_p1_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_ext_dfi_p1_wrdata_en;
+		end else begin
+			soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
+		end
 	end else begin
-		soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+		soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_csr_dfi_p1_wrdata_en;
 	end
 end
 always @(*) begin
 	soc_litedramcore_master_p1_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_ext_dfi_p1_wrdata_mask;
+		end else begin
+			soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
+		end
 	end else begin
-		soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask;
+		soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_csr_dfi_p1_wrdata_mask;
 	end
 end
 always @(*) begin
 	soc_litedramcore_master_p1_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_ext_dfi_p1_rddata_en;
+		end else begin
+			soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
+		end
 	end else begin
-		soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en;
+		soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_csr_dfi_p1_rddata_en;
 	end
 end
 always @(*) begin
 	soc_litedramcore_master_p2_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_address <= soc_litedramcore_ext_dfi_p2_address;
+		end else begin
+			soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
+		end
 	end else begin
-		soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address;
+		soc_litedramcore_master_p2_address <= soc_litedramcore_csr_dfi_p2_address;
 	end
 end
 always @(*) begin
 	soc_litedramcore_master_p2_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_bank <= soc_litedramcore_ext_dfi_p2_bank;
+		end else begin
+			soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
+		end
 	end else begin
-		soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank;
+		soc_litedramcore_master_p2_bank <= soc_litedramcore_csr_dfi_p2_bank;
 	end
 end
 always @(*) begin
 	soc_litedramcore_master_p2_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_cas_n <= soc_litedramcore_ext_dfi_p2_cas_n;
+		end else begin
+			soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
+		end
 	end else begin
-		soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n;
+		soc_litedramcore_master_p2_cas_n <= soc_litedramcore_csr_dfi_p2_cas_n;
 	end
 end
 always @(*) begin
 	soc_litedramcore_master_p2_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n;
+		end else begin
+			soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
+		end
 	end else begin
-		soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n;
+		soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n;
 	end
 end
 always @(*) begin
 	soc_litedramcore_master_p2_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_ras_n <= soc_litedramcore_ext_dfi_p2_ras_n;
+		end else begin
+			soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
+		end
 	end else begin
-		soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n;
+		soc_litedramcore_master_p2_ras_n <= soc_litedramcore_csr_dfi_p2_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p2_rddata <= 32'd0;
+	soc_litedramcore_master_p2_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_we_n <= soc_litedramcore_ext_dfi_p2_we_n;
+		end else begin
+			soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
+		end
 	end else begin
+		soc_litedramcore_master_p2_we_n <= soc_litedramcore_csr_dfi_p2_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_we_n <= 1'd1;
+	soc_litedramcore_master_p2_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_cke <= soc_litedramcore_ext_dfi_p2_cke;
+		end else begin
+			soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
+		end
 	end else begin
-		soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n;
+		soc_litedramcore_master_p2_cke <= soc_litedramcore_csr_dfi_p2_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
+	soc_litedramcore_master_p2_odt <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_odt <= soc_litedramcore_ext_dfi_p2_odt;
+		end else begin
+			soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
+		end
 	end else begin
+		soc_litedramcore_master_p2_odt <= soc_litedramcore_csr_dfi_p2_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_cke <= 1'd0;
+	soc_litedramcore_master_p2_reset_n <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_reset_n <= soc_litedramcore_ext_dfi_p2_reset_n;
+		end else begin
+			soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
+		end
 	end else begin
-		soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke;
+		soc_litedramcore_master_p2_reset_n <= soc_litedramcore_csr_dfi_p2_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_odt <= 1'd0;
+	soc_litedramcore_master_p2_act_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_act_n <= soc_litedramcore_ext_dfi_p2_act_n;
+		end else begin
+			soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
+		end
 	end else begin
-		soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt;
+		soc_litedramcore_master_p2_act_n <= soc_litedramcore_csr_dfi_p2_act_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_reset_n <= 1'd0;
+	soc_litedramcore_master_p2_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_wrdata <= soc_litedramcore_ext_dfi_p2_wrdata;
+		end else begin
+			soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
+		end
 	end else begin
-		soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n;
+		soc_litedramcore_master_p2_wrdata <= soc_litedramcore_csr_dfi_p2_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_act_n <= 1'd1;
+	soc_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_ext_dfi_p2_wrdata_en;
+		end else begin
+			soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
+		end
 	end else begin
-		soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n;
+		soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_csr_dfi_p2_wrdata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_wrdata <= 32'd0;
+	soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_ext_dfi_p2_wrdata_mask;
+		end else begin
+			soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
+		end
 	end else begin
-		soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata;
+		soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_csr_dfi_p2_wrdata_mask;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_rddata <= 32'd0;
+	soc_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_ext_dfi_p2_rddata_en;
+		end else begin
+			soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
+		end
 	end else begin
-		soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata;
+		soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_csr_dfi_p2_rddata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_wrdata_en <= 1'd0;
+	soc_litedramcore_master_p3_address <= 14'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_address <= soc_litedramcore_ext_dfi_p3_address;
+		end else begin
+			soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
+		end
 	end else begin
-		soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en;
+		soc_litedramcore_master_p3_address <= soc_litedramcore_csr_dfi_p3_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	soc_litedramcore_master_p3_bank <= 3'd0;
 	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_bank <= soc_litedramcore_ext_dfi_p3_bank;
+		end else begin
+			soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
+		end
 	end else begin
-		soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+		soc_litedramcore_master_p3_bank <= soc_litedramcore_csr_dfi_p3_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
+	soc_litedramcore_master_p3_cas_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_cas_n <= soc_litedramcore_ext_dfi_p3_cas_n;
+		end else begin
+			soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
+		end
 	end else begin
-		soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask;
+		soc_litedramcore_master_p3_cas_n <= soc_litedramcore_csr_dfi_p3_cas_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p2_rddata_en <= 1'd0;
+	soc_litedramcore_master_p3_cs_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n;
+		end else begin
+			soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
+		end
 	end else begin
-		soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en;
+		soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_address <= 14'd0;
+	soc_litedramcore_master_p3_ras_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_ras_n <= soc_litedramcore_ext_dfi_p3_ras_n;
+		end else begin
+			soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
+		end
 	end else begin
-		soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address;
+		soc_litedramcore_master_p3_ras_n <= soc_litedramcore_csr_dfi_p3_ras_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_bank <= 3'd0;
+	soc_litedramcore_master_p3_we_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_we_n <= soc_litedramcore_ext_dfi_p3_we_n;
+		end else begin
+			soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
+		end
 	end else begin
-		soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank;
+		soc_litedramcore_master_p3_we_n <= soc_litedramcore_csr_dfi_p3_we_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_cas_n <= 1'd1;
+	soc_litedramcore_master_p3_cke <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_cke <= soc_litedramcore_ext_dfi_p3_cke;
+		end else begin
+			soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
+		end
 	end else begin
-		soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n;
+		soc_litedramcore_master_p3_cke <= soc_litedramcore_csr_dfi_p3_cke;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_cs_n <= 1'd1;
+	soc_litedramcore_master_p3_odt <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_odt <= soc_litedramcore_ext_dfi_p3_odt;
+		end else begin
+			soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
+		end
 	end else begin
-		soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n;
+		soc_litedramcore_master_p3_odt <= soc_litedramcore_csr_dfi_p3_odt;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_ras_n <= 1'd1;
+	soc_litedramcore_master_p3_reset_n <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_reset_n <= soc_litedramcore_ext_dfi_p3_reset_n;
+		end else begin
+			soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
+		end
 	end else begin
-		soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n;
+		soc_litedramcore_master_p3_reset_n <= soc_litedramcore_csr_dfi_p3_reset_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p3_rddata <= 32'd0;
+	soc_litedramcore_master_p3_act_n <= 1'd1;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_act_n <= soc_litedramcore_ext_dfi_p3_act_n;
+		end else begin
+			soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
+		end
 	end else begin
+		soc_litedramcore_master_p3_act_n <= soc_litedramcore_csr_dfi_p3_act_n;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_we_n <= 1'd1;
+	soc_litedramcore_master_p3_wrdata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_wrdata <= soc_litedramcore_ext_dfi_p3_wrdata;
+		end else begin
+			soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
+		end
 	end else begin
-		soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n;
+		soc_litedramcore_master_p3_wrdata <= soc_litedramcore_csr_dfi_p3_wrdata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
+	soc_litedramcore_master_p3_wrdata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_ext_dfi_p3_wrdata_en;
+		end else begin
+			soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
+		end
 	end else begin
+		soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_csr_dfi_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_cke <= 1'd0;
+	soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_ext_dfi_p3_wrdata_mask;
+		end else begin
+			soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
+		end
 	end else begin
-		soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke;
+		soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_csr_dfi_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_odt <= 1'd0;
+	soc_litedramcore_master_p3_rddata_en <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_ext_dfi_p3_rddata_en;
+		end else begin
+			soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
+		end
 	end else begin
-		soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt;
+		soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_csr_dfi_p3_rddata_en;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_reset_n <= 1'd0;
+	soc_litedramcore_csr_dfi_p0_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
 	end else begin
-		soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n;
+		soc_litedramcore_csr_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_act_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
 	end else begin
-		soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n;
+		soc_litedramcore_csr_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_wrdata <= 32'd0;
+	soc_litedramcore_csr_dfi_p1_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
 	end else begin
-		soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata;
+		soc_litedramcore_csr_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_rddata <= 32'd0;
+	soc_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
 	end else begin
-		soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata;
+		soc_litedramcore_csr_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_wrdata_en <= 1'd0;
+	soc_litedramcore_csr_dfi_p2_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
 	end else begin
-		soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en;
+		soc_litedramcore_csr_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_rddata_valid <= 1'd0;
+	soc_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
 	end else begin
-		soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+		soc_litedramcore_csr_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
+	soc_litedramcore_csr_dfi_p3_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
 	end else begin
-		soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask;
+		soc_litedramcore_csr_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p3_rddata_en <= 1'd0;
+	soc_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
 	end else begin
-		soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en;
+		soc_litedramcore_csr_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_address <= 14'd0;
+	soc_litedramcore_ext_dfi_p0_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
+		end else begin
+		end
 	end else begin
-		soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_bank <= 3'd0;
+	soc_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+		end else begin
+		end
 	end else begin
-		soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank;
 	end
 end
 always @(*) begin
-	soc_litedramcore_master_p0_cas_n <= 1'd1;
+	soc_litedramcore_ext_dfi_p1_rddata <= 32'd0;
 	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
+		end else begin
+		end
+	end else begin
+	end
+end
+always @(*) begin
+	soc_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+		end else begin
+		end
+	end else begin
+	end
+end
+always @(*) begin
+	soc_litedramcore_ext_dfi_p2_rddata <= 32'd0;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
+		end else begin
+		end
+	end else begin
+	end
+end
+always @(*) begin
+	soc_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+			soc_litedramcore_ext_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+		end else begin
+		end
+	end else begin
+	end
+end
+always @(*) begin
+	soc_litedramcore_slave_p0_rddata <= 32'd0;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
+		end
+	end else begin
+	end
+end
+always @(*) begin
+	soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
+	if (soc_litedramcore_sel) begin
+		if (soc_litedramcore_ext_dfi_sel) begin
+		end else begin
+			soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+		end
 	end else begin
-		soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n;
 	end
 end
-assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke;
-assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke;
-assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke;
-assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke;
-assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt;
-assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt;
-assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt;
-assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt;
-assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n;
-assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n;
-assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n;
-assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p2_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p3_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p0_odt = soc_litedramcore_odt;
+assign soc_litedramcore_csr_dfi_p1_odt = soc_litedramcore_odt;
+assign soc_litedramcore_csr_dfi_p2_odt = soc_litedramcore_odt;
+assign soc_litedramcore_csr_dfi_p3_odt = soc_litedramcore_odt;
+assign soc_litedramcore_csr_dfi_p0_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n;
 always @(*) begin
-	soc_litedramcore_inti_p0_cs_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
+		soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}};
 	end else begin
-		soc_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_ras_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]);
+		soc_litedramcore_csr_dfi_p0_ras_n <= (~soc_litedramcore_phaseinjector0_csrfield_ras);
 	end else begin
-		soc_litedramcore_inti_p0_ras_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_we_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]);
+		soc_litedramcore_csr_dfi_p0_we_n <= (~soc_litedramcore_phaseinjector0_csrfield_we);
 	end else begin
-		soc_litedramcore_inti_p0_we_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p0_cas_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-		soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]);
+		soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas);
 	end else begin
-		soc_litedramcore_inti_p0_cas_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	end
 end
-assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage;
-assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
-assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]);
-assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]);
-assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
-assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign soc_litedramcore_csr_dfi_p0_address = soc_litedramcore_phaseinjector0_address_storage;
+assign soc_litedramcore_csr_dfi_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
+assign soc_litedramcore_csr_dfi_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_wren);
+assign soc_litedramcore_csr_dfi_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_rden);
+assign soc_litedramcore_csr_dfi_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
+assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	soc_litedramcore_inti_p1_cs_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
+		soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}};
 	end else begin
-		soc_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_ras_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]);
+		soc_litedramcore_csr_dfi_p1_ras_n <= (~soc_litedramcore_phaseinjector1_csrfield_ras);
 	end else begin
-		soc_litedramcore_inti_p1_ras_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_we_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]);
+		soc_litedramcore_csr_dfi_p1_we_n <= (~soc_litedramcore_phaseinjector1_csrfield_we);
 	end else begin
-		soc_litedramcore_inti_p1_we_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p1_cas_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-		soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]);
+		soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas);
 	end else begin
-		soc_litedramcore_inti_p1_cas_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	end
 end
-assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage;
-assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
-assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]);
-assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]);
-assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
-assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign soc_litedramcore_csr_dfi_p1_address = soc_litedramcore_phaseinjector1_address_storage;
+assign soc_litedramcore_csr_dfi_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
+assign soc_litedramcore_csr_dfi_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_wren);
+assign soc_litedramcore_csr_dfi_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_rden);
+assign soc_litedramcore_csr_dfi_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
+assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-	soc_litedramcore_inti_p2_cs_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
+		soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}};
 	end else begin
-		soc_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_ras_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]);
+		soc_litedramcore_csr_dfi_p2_ras_n <= (~soc_litedramcore_phaseinjector2_csrfield_ras);
 	end else begin
-		soc_litedramcore_inti_p2_ras_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_we_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]);
+		soc_litedramcore_csr_dfi_p2_we_n <= (~soc_litedramcore_phaseinjector2_csrfield_we);
 	end else begin
-		soc_litedramcore_inti_p2_we_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p2_cas_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-		soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]);
+		soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas);
 	end else begin
-		soc_litedramcore_inti_p2_cas_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
 	end
 end
-assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage;
-assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
-assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]);
-assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]);
-assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
-assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign soc_litedramcore_csr_dfi_p2_address = soc_litedramcore_phaseinjector2_address_storage;
+assign soc_litedramcore_csr_dfi_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
+assign soc_litedramcore_csr_dfi_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_wren);
+assign soc_litedramcore_csr_dfi_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_rden);
+assign soc_litedramcore_csr_dfi_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
+assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-	soc_litedramcore_inti_p3_cs_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
+		soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}};
 	end else begin
-		soc_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_ras_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]);
+		soc_litedramcore_csr_dfi_p3_ras_n <= (~soc_litedramcore_phaseinjector3_csrfield_ras);
 	end else begin
-		soc_litedramcore_inti_p3_ras_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_we_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]);
+		soc_litedramcore_csr_dfi_p3_we_n <= (~soc_litedramcore_phaseinjector3_csrfield_we);
 	end else begin
-		soc_litedramcore_inti_p3_we_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	soc_litedramcore_inti_p3_cas_n <= 1'd1;
+	soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
 	if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-		soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]);
+		soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas);
 	end else begin
-		soc_litedramcore_inti_p3_cas_n <= 1'd1;
+		soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
 	end
 end
-assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage;
-assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
-assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]);
-assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]);
-assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage;
-assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0;
+assign soc_litedramcore_csr_dfi_p3_address = soc_litedramcore_phaseinjector3_address_storage;
+assign soc_litedramcore_csr_dfi_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
+assign soc_litedramcore_csr_dfi_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_csrfield_wren);
+assign soc_litedramcore_csr_dfi_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_csrfield_rden);
+assign soc_litedramcore_csr_dfi_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage;
+assign soc_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
 assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid;
 assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready;
 assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we;
@@ -4436,32 +4853,32 @@ assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 =
 assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
 assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
 always @(*) begin
-	refresher_next_state <= 2'd0;
-	refresher_next_state <= refresher_state;
-	case (refresher_state)
+	litedramcore_refresher_next_state <= 2'd0;
+	litedramcore_refresher_next_state <= litedramcore_refresher_state;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 			if (soc_litedramcore_cmd_ready) begin
-				refresher_next_state <= 2'd2;
+				litedramcore_refresher_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
 			if (soc_litedramcore_sequencer_done0) begin
 				if (soc_litedramcore_wants_zqcs) begin
-					refresher_next_state <= 2'd3;
+					litedramcore_refresher_next_state <= 2'd3;
 				end else begin
-					refresher_next_state <= 1'd0;
+					litedramcore_refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_zqcs_executer_done) begin
-				refresher_next_state <= 1'd0;
+				litedramcore_refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
 				if (soc_litedramcore_wants_refresh) begin
-					refresher_next_state <= 1'd1;
+					litedramcore_refresher_next_state <= 1'd1;
 				end
 			end
 		end
@@ -4469,7 +4886,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_sequencer_start0 <= 1'd0;
-	case (refresher_state)
+	case (litedramcore_refresher_state)
 		1'd1: begin
 			if (soc_litedramcore_cmd_ready) begin
 				soc_litedramcore_sequencer_start0 <= 1'd1;
@@ -4485,7 +4902,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_cmd_valid <= 1'd0;
-	case (refresher_state)
+	case (litedramcore_refresher_state)
 		1'd1: begin
 			soc_litedramcore_cmd_valid <= 1'd1;
 		end
@@ -4510,7 +4927,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_zqcs_executer_start <= 1'd0;
-	case (refresher_state)
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4529,7 +4946,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_cmd_last <= 1'd0;
-	case (refresher_state)
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4616,69 +5033,121 @@ assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (
 assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine0_next_state <= 4'd0;
-	bankmachine0_next_state <= bankmachine0_state;
-	case (bankmachine0_state)
+	litedramcore_bankmachine0_next_state <= 4'd0;
+	litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine0_cmd_ready) begin
-					bankmachine0_next_state <= 3'd5;
+					litedramcore_bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-				bankmachine0_next_state <= 3'd5;
+				litedramcore_bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine0_trccon_ready) begin
 				if (soc_litedramcore_bankmachine0_cmd_ready) begin
-					bankmachine0_next_state <= 3'd7;
+					litedramcore_bankmachine0_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
-				bankmachine0_next_state <= 1'd0;
+				litedramcore_bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine0_next_state <= 3'd6;
+			litedramcore_bankmachine0_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine0_next_state <= 2'd3;
+			litedramcore_bankmachine0_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine0_next_state <= 4'd8;
+			litedramcore_bankmachine0_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine0_next_state <= 1'd0;
+			litedramcore_bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine0_refresh_req) begin
-				bankmachine0_next_state <= 3'd4;
+				litedramcore_bankmachine0_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine0_row_opened) begin
 						if (soc_litedramcore_bankmachine0_row_hit) begin
 							if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
-								bankmachine0_next_state <= 2'd2;
+								litedramcore_bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine0_next_state <= 1'd1;
+							litedramcore_bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine0_next_state <= 2'd3;
+						litedramcore_bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine0_row_open <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine0_trccon_ready) begin
+				soc_litedramcore_bankmachine0_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine0_row_close <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4713,7 +5182,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
 				soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
@@ -4742,7 +5211,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
 				soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
@@ -4783,7 +5252,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4809,7 +5278,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
 				soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
@@ -4839,7 +5308,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4877,7 +5346,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4915,7 +5384,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-	case (bankmachine0_state)
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4953,82 +5422,12 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-	case (bankmachine0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine0_row_opened) begin
-						if (soc_litedramcore_bankmachine0_row_hit) begin
-							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (bankmachine0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
-				soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (bankmachine0_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-				soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine0_trccon_ready) begin
-				soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -5046,7 +5445,10 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine0_row_opened) begin
 						if (soc_litedramcore_bankmachine0_row_hit) begin
-							soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+							if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -5057,18 +5459,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_row_open <= 1'd0;
-	case (bankmachine0_state)
+	soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine0_trccon_ready) begin
-				soc_litedramcore_bankmachine0_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
+				soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -5083,18 +5485,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine0_row_close <= 1'd0;
-	case (bankmachine0_state)
+	soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine0_row_close <= 1'd1;
+			if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+				soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine0_trccon_ready) begin
+				soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5105,6 +5510,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine0_row_opened) begin
+						if (soc_litedramcore_bankmachine0_row_hit) begin
+							soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
@@ -5175,69 +5592,121 @@ assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (
 assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine1_next_state <= 4'd0;
-	bankmachine1_next_state <= bankmachine1_state;
-	case (bankmachine1_state)
+	litedramcore_bankmachine1_next_state <= 4'd0;
+	litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine1_cmd_ready) begin
-					bankmachine1_next_state <= 3'd5;
+					litedramcore_bankmachine1_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-				bankmachine1_next_state <= 3'd5;
+				litedramcore_bankmachine1_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine1_trccon_ready) begin
 				if (soc_litedramcore_bankmachine1_cmd_ready) begin
-					bankmachine1_next_state <= 3'd7;
+					litedramcore_bankmachine1_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
-				bankmachine1_next_state <= 1'd0;
+				litedramcore_bankmachine1_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine1_next_state <= 3'd6;
+			litedramcore_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine1_next_state <= 2'd3;
+			litedramcore_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine1_next_state <= 4'd8;
+			litedramcore_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine1_next_state <= 1'd0;
+			litedramcore_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine1_refresh_req) begin
-				bankmachine1_next_state <= 3'd4;
+				litedramcore_bankmachine1_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine1_row_opened) begin
 						if (soc_litedramcore_bankmachine1_row_hit) begin
 							if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
-								bankmachine1_next_state <= 2'd2;
+								litedramcore_bankmachine1_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine1_next_state <= 1'd1;
+							litedramcore_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine1_next_state <= 2'd3;
+						litedramcore_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine1_row_open <= 1'd0;
+	case (litedramcore_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine1_trccon_ready) begin
+				soc_litedramcore_bankmachine1_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine1_row_close <= 1'd0;
+	case (litedramcore_bankmachine1_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine1_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine1_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine1_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5272,7 +5741,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
 				soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
@@ -5301,7 +5770,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
 				soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
@@ -5342,7 +5811,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5368,7 +5837,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
 				soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
@@ -5398,7 +5867,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5436,7 +5905,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5474,7 +5943,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5512,7 +5981,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5550,7 +6019,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5576,7 +6045,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-	case (bankmachine1_state)
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
 				soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
@@ -5615,58 +6084,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	soc_litedramcore_bankmachine1_row_open <= 1'd0;
-	case (bankmachine1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine1_trccon_ready) begin
-				soc_litedramcore_bankmachine1_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine1_row_close <= 1'd0;
-	case (bankmachine1_state)
-		1'd1: begin
-			soc_litedramcore_bankmachine1_row_close <= 1'd1;
-		end
-		2'd2: begin
-			soc_litedramcore_bankmachine1_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			soc_litedramcore_bankmachine1_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid;
 assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
@@ -5734,69 +6151,121 @@ assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (
 assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine2_next_state <= 4'd0;
-	bankmachine2_next_state <= bankmachine2_state;
-	case (bankmachine2_state)
+	litedramcore_bankmachine2_next_state <= 4'd0;
+	litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine2_cmd_ready) begin
-					bankmachine2_next_state <= 3'd5;
+					litedramcore_bankmachine2_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-				bankmachine2_next_state <= 3'd5;
+				litedramcore_bankmachine2_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine2_trccon_ready) begin
 				if (soc_litedramcore_bankmachine2_cmd_ready) begin
-					bankmachine2_next_state <= 3'd7;
+					litedramcore_bankmachine2_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
-				bankmachine2_next_state <= 1'd0;
+				litedramcore_bankmachine2_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine2_next_state <= 3'd6;
+			litedramcore_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine2_next_state <= 2'd3;
+			litedramcore_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine2_next_state <= 4'd8;
+			litedramcore_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine2_next_state <= 1'd0;
+			litedramcore_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine2_refresh_req) begin
-				bankmachine2_next_state <= 3'd4;
+				litedramcore_bankmachine2_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine2_row_opened) begin
 						if (soc_litedramcore_bankmachine2_row_hit) begin
 							if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
-								bankmachine2_next_state <= 2'd2;
+								litedramcore_bankmachine2_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine2_next_state <= 1'd1;
+							litedramcore_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine2_next_state <= 2'd3;
+						litedramcore_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine2_row_open <= 1'd0;
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine2_trccon_ready) begin
+				soc_litedramcore_bankmachine2_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine2_row_close <= 1'd0;
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine2_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine2_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine2_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5831,7 +6300,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
 				soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
@@ -5860,7 +6329,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
 				soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
@@ -5901,7 +6370,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5927,7 +6396,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
 				soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
@@ -5957,7 +6426,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5995,7 +6464,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6033,7 +6502,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-	case (bankmachine2_state)
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6071,82 +6540,12 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-	case (bankmachine2_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine2_row_opened) begin
-						if (soc_litedramcore_bankmachine2_row_hit) begin
-							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-	case (bankmachine2_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
-				soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (bankmachine2_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-				soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine2_trccon_ready) begin
-				soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -6164,7 +6563,10 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine2_row_opened) begin
 						if (soc_litedramcore_bankmachine2_row_hit) begin
-							soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+							if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -6175,18 +6577,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_row_open <= 1'd0;
-	case (bankmachine2_state)
+	soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine2_trccon_ready) begin
-				soc_litedramcore_bankmachine2_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
+				soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -6201,18 +6603,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine2_row_close <= 1'd0;
-	case (bankmachine2_state)
+	soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine2_row_close <= 1'd1;
+			if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+				soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine2_trccon_ready) begin
+				soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6223,6 +6628,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine2_row_opened) begin
+						if (soc_litedramcore_bankmachine2_row_hit) begin
+							soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
@@ -6293,69 +6710,121 @@ assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (
 assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine3_next_state <= 4'd0;
-	bankmachine3_next_state <= bankmachine3_state;
-	case (bankmachine3_state)
+	litedramcore_bankmachine3_next_state <= 4'd0;
+	litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine3_cmd_ready) begin
-					bankmachine3_next_state <= 3'd5;
+					litedramcore_bankmachine3_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-				bankmachine3_next_state <= 3'd5;
+				litedramcore_bankmachine3_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine3_trccon_ready) begin
 				if (soc_litedramcore_bankmachine3_cmd_ready) begin
-					bankmachine3_next_state <= 3'd7;
+					litedramcore_bankmachine3_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
-				bankmachine3_next_state <= 1'd0;
+				litedramcore_bankmachine3_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine3_next_state <= 3'd6;
+			litedramcore_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine3_next_state <= 2'd3;
+			litedramcore_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine3_next_state <= 4'd8;
+			litedramcore_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine3_next_state <= 1'd0;
+			litedramcore_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine3_refresh_req) begin
-				bankmachine3_next_state <= 3'd4;
+				litedramcore_bankmachine3_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine3_row_opened) begin
 						if (soc_litedramcore_bankmachine3_row_hit) begin
 							if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
-								bankmachine3_next_state <= 2'd2;
+								litedramcore_bankmachine3_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine3_next_state <= 1'd1;
+							litedramcore_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine3_next_state <= 2'd3;
+						litedramcore_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine3_row_open <= 1'd0;
+	case (litedramcore_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine3_trccon_ready) begin
+				soc_litedramcore_bankmachine3_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine3_row_close <= 1'd0;
+	case (litedramcore_bankmachine3_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine3_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine3_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine3_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6390,7 +6859,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
 				soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
@@ -6419,7 +6888,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
 				soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
@@ -6460,7 +6929,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6486,7 +6955,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
 				soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
@@ -6516,7 +6985,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6554,7 +7023,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6592,7 +7061,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6630,7 +7099,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6668,7 +7137,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6694,7 +7163,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
-	case (bankmachine3_state)
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
 				soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
@@ -6733,58 +7202,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	soc_litedramcore_bankmachine3_row_open <= 1'd0;
-	case (bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine3_trccon_ready) begin
-				soc_litedramcore_bankmachine3_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine3_row_close <= 1'd0;
-	case (bankmachine3_state)
-		1'd1: begin
-			soc_litedramcore_bankmachine3_row_close <= 1'd1;
-		end
-		2'd2: begin
-			soc_litedramcore_bankmachine3_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			soc_litedramcore_bankmachine3_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid;
 assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
@@ -6852,69 +7269,121 @@ assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (
 assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine4_next_state <= 4'd0;
-	bankmachine4_next_state <= bankmachine4_state;
-	case (bankmachine4_state)
+	litedramcore_bankmachine4_next_state <= 4'd0;
+	litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine4_cmd_ready) begin
-					bankmachine4_next_state <= 3'd5;
+					litedramcore_bankmachine4_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-				bankmachine4_next_state <= 3'd5;
+				litedramcore_bankmachine4_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine4_trccon_ready) begin
 				if (soc_litedramcore_bankmachine4_cmd_ready) begin
-					bankmachine4_next_state <= 3'd7;
+					litedramcore_bankmachine4_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
-				bankmachine4_next_state <= 1'd0;
+				litedramcore_bankmachine4_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine4_next_state <= 3'd6;
+			litedramcore_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine4_next_state <= 2'd3;
+			litedramcore_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine4_next_state <= 4'd8;
+			litedramcore_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine4_next_state <= 1'd0;
+			litedramcore_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine4_refresh_req) begin
-				bankmachine4_next_state <= 3'd4;
+				litedramcore_bankmachine4_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine4_row_opened) begin
 						if (soc_litedramcore_bankmachine4_row_hit) begin
 							if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
-								bankmachine4_next_state <= 2'd2;
+								litedramcore_bankmachine4_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine4_next_state <= 1'd1;
+							litedramcore_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine4_next_state <= 2'd3;
+						litedramcore_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine4_row_open <= 1'd0;
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine4_trccon_ready) begin
+				soc_litedramcore_bankmachine4_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine4_row_close <= 1'd0;
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6949,7 +7418,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
 				soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
@@ -6978,7 +7447,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
 				soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
@@ -7019,7 +7488,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7045,7 +7514,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
 				soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
@@ -7075,7 +7544,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7113,7 +7582,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7151,7 +7620,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-	case (bankmachine4_state)
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7189,82 +7658,12 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-	case (bankmachine4_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine4_row_opened) begin
-						if (soc_litedramcore_bankmachine4_row_hit) begin
-							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-	case (bankmachine4_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
-				soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (bankmachine4_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-				soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine4_trccon_ready) begin
-				soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -7282,7 +7681,10 @@ always @(*) begin
 				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine4_row_opened) begin
 						if (soc_litedramcore_bankmachine4_row_hit) begin
-							soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+							if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -7293,18 +7695,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_row_open <= 1'd0;
-	case (bankmachine4_state)
+	soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (soc_litedramcore_bankmachine4_trccon_ready) begin
-				soc_litedramcore_bankmachine4_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
+				soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -7319,18 +7721,21 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_bankmachine4_row_close <= 1'd0;
-	case (bankmachine4_state)
+	soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine4_row_close <= 1'd1;
+			if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+				soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine4_trccon_ready) begin
+				soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7341,6 +7746,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine4_row_opened) begin
+						if (soc_litedramcore_bankmachine4_row_hit) begin
+							soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
@@ -7411,69 +7828,121 @@ assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (
 assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine5_next_state <= 4'd0;
-	bankmachine5_next_state <= bankmachine5_state;
-	case (bankmachine5_state)
+	litedramcore_bankmachine5_next_state <= 4'd0;
+	litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine5_cmd_ready) begin
-					bankmachine5_next_state <= 3'd5;
+					litedramcore_bankmachine5_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-				bankmachine5_next_state <= 3'd5;
+				litedramcore_bankmachine5_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine5_trccon_ready) begin
 				if (soc_litedramcore_bankmachine5_cmd_ready) begin
-					bankmachine5_next_state <= 3'd7;
+					litedramcore_bankmachine5_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
-				bankmachine5_next_state <= 1'd0;
+				litedramcore_bankmachine5_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine5_next_state <= 3'd6;
+			litedramcore_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine5_next_state <= 2'd3;
+			litedramcore_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine5_next_state <= 4'd8;
+			litedramcore_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine5_next_state <= 1'd0;
+			litedramcore_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine5_refresh_req) begin
-				bankmachine5_next_state <= 3'd4;
+				litedramcore_bankmachine5_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine5_row_opened) begin
 						if (soc_litedramcore_bankmachine5_row_hit) begin
 							if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
-								bankmachine5_next_state <= 2'd2;
+								litedramcore_bankmachine5_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine5_next_state <= 1'd1;
+							litedramcore_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine5_next_state <= 2'd3;
+						litedramcore_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine5_row_open <= 1'd0;
+	case (litedramcore_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine5_trccon_ready) begin
+				soc_litedramcore_bankmachine5_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine5_row_close <= 1'd0;
+	case (litedramcore_bankmachine5_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine5_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine5_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine5_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7508,7 +7977,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
 				soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
@@ -7537,7 +8006,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
 				soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
@@ -7578,7 +8047,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7604,7 +8073,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
 				soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
@@ -7634,7 +8103,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7672,7 +8141,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7710,7 +8179,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7748,7 +8217,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7786,7 +8255,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7812,7 +8281,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-	case (bankmachine5_state)
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
 				soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
@@ -7851,58 +8320,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	soc_litedramcore_bankmachine5_row_open <= 1'd0;
-	case (bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine5_trccon_ready) begin
-				soc_litedramcore_bankmachine5_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine5_row_close <= 1'd0;
-	case (bankmachine5_state)
-		1'd1: begin
-			soc_litedramcore_bankmachine5_row_close <= 1'd1;
-		end
-		2'd2: begin
-			soc_litedramcore_bankmachine5_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			soc_litedramcore_bankmachine5_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid;
 assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
@@ -7970,69 +8387,121 @@ assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (
 assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine6_next_state <= 4'd0;
-	bankmachine6_next_state <= bankmachine6_state;
-	case (bankmachine6_state)
+	litedramcore_bankmachine6_next_state <= 4'd0;
+	litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine6_cmd_ready) begin
-					bankmachine6_next_state <= 3'd5;
+					litedramcore_bankmachine6_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-				bankmachine6_next_state <= 3'd5;
+				litedramcore_bankmachine6_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine6_trccon_ready) begin
 				if (soc_litedramcore_bankmachine6_cmd_ready) begin
-					bankmachine6_next_state <= 3'd7;
+					litedramcore_bankmachine6_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
-				bankmachine6_next_state <= 1'd0;
+				litedramcore_bankmachine6_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine6_next_state <= 3'd6;
+			litedramcore_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine6_next_state <= 2'd3;
+			litedramcore_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine6_next_state <= 4'd8;
+			litedramcore_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine6_next_state <= 1'd0;
+			litedramcore_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine6_refresh_req) begin
-				bankmachine6_next_state <= 3'd4;
+				litedramcore_bankmachine6_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine6_row_opened) begin
 						if (soc_litedramcore_bankmachine6_row_hit) begin
 							if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
-								bankmachine6_next_state <= 2'd2;
+								litedramcore_bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine6_next_state <= 1'd1;
+							litedramcore_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine6_next_state <= 2'd3;
+						litedramcore_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine6_row_open <= 1'd0;
+	case (litedramcore_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine6_trccon_ready) begin
+				soc_litedramcore_bankmachine6_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine6_row_close <= 1'd0;
+	case (litedramcore_bankmachine6_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine6_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine6_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine6_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8067,7 +8536,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
 				soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
@@ -8096,7 +8565,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
 				soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
@@ -8137,7 +8606,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8163,7 +8632,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
 				soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
@@ -8193,7 +8662,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8231,7 +8700,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8269,7 +8738,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8307,7 +8776,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8345,7 +8814,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8371,84 +8840,20 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
-	case (bankmachine6_state)
-		1'd1: begin
-			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-				soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine6_trccon_ready) begin
-				soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (soc_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (soc_litedramcore_bankmachine6_row_opened) begin
-						if (soc_litedramcore_bankmachine6_row_hit) begin
-							soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine6_row_open <= 1'd0;
-	case (bankmachine6_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine6_trccon_ready) begin
-				soc_litedramcore_bankmachine6_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine6_row_close <= 1'd0;
-	case (bankmachine6_state)
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			soc_litedramcore_bankmachine6_row_close <= 1'd1;
+			if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+				soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
-			soc_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (soc_litedramcore_bankmachine6_trccon_ready) begin
+				soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
-			soc_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8459,6 +8864,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (soc_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (soc_litedramcore_bankmachine6_row_opened) begin
+						if (soc_litedramcore_bankmachine6_row_hit) begin
+							soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
@@ -8529,69 +8946,121 @@ assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (
 assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
 assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready);
 always @(*) begin
-	bankmachine7_next_state <= 4'd0;
-	bankmachine7_next_state <= bankmachine7_state;
-	case (bankmachine7_state)
+	litedramcore_bankmachine7_next_state <= 4'd0;
+	litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
 				if (soc_litedramcore_bankmachine7_cmd_ready) begin
-					bankmachine7_next_state <= 3'd5;
+					litedramcore_bankmachine7_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-				bankmachine7_next_state <= 3'd5;
+				litedramcore_bankmachine7_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_bankmachine7_trccon_ready) begin
 				if (soc_litedramcore_bankmachine7_cmd_ready) begin
-					bankmachine7_next_state <= 3'd7;
+					litedramcore_bankmachine7_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
 			if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
-				bankmachine7_next_state <= 1'd0;
+				litedramcore_bankmachine7_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			bankmachine7_next_state <= 3'd6;
+			litedramcore_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
-			bankmachine7_next_state <= 2'd3;
+			litedramcore_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
-			bankmachine7_next_state <= 4'd8;
+			litedramcore_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
-			bankmachine7_next_state <= 1'd0;
+			litedramcore_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
 			if (soc_litedramcore_bankmachine7_refresh_req) begin
-				bankmachine7_next_state <= 3'd4;
+				litedramcore_bankmachine7_next_state <= 3'd4;
 			end else begin
 				if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
 					if (soc_litedramcore_bankmachine7_row_opened) begin
 						if (soc_litedramcore_bankmachine7_row_hit) begin
 							if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
-								bankmachine7_next_state <= 2'd2;
+								litedramcore_bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
-							bankmachine7_next_state <= 1'd1;
+							litedramcore_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
-						bankmachine7_next_state <= 2'd3;
+						litedramcore_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
 		end
 	endcase
 end
+always @(*) begin
+	soc_litedramcore_bankmachine7_row_open <= 1'd0;
+	case (litedramcore_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (soc_litedramcore_bankmachine7_trccon_ready) begin
+				soc_litedramcore_bankmachine7_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_bankmachine7_row_close <= 1'd0;
+	case (litedramcore_bankmachine7_state)
+		1'd1: begin
+			soc_litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		2'd2: begin
+			soc_litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			soc_litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
 always @(*) begin
 	soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8626,7 +9095,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
 				soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
@@ -8655,7 +9124,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
 				soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
@@ -8696,7 +9165,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8722,7 +9191,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
 				soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
@@ -8752,7 +9221,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8790,7 +9259,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8828,7 +9297,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8866,7 +9335,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8904,7 +9373,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8930,7 +9399,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (bankmachine7_state)
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 			if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
 				soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
@@ -8969,58 +9438,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	soc_litedramcore_bankmachine7_row_open <= 1'd0;
-	case (bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (soc_litedramcore_bankmachine7_trccon_ready) begin
-				soc_litedramcore_bankmachine7_row_open <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	soc_litedramcore_bankmachine7_row_close <= 1'd0;
-	case (bankmachine7_state)
-		1'd1: begin
-			soc_litedramcore_bankmachine7_row_close <= 1'd1;
-		end
-		2'd2: begin
-			soc_litedramcore_bankmachine7_row_close <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			soc_litedramcore_bankmachine7_row_close <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
 assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
 assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
 assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready);
@@ -9209,65 +9626,102 @@ assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}};
 assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}};
 assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
 always @(*) begin
-	multiplexer_next_state <= 4'd0;
-	multiplexer_next_state <= multiplexer_state;
-	case (multiplexer_state)
+	litedramcore_multiplexer_next_state <= 4'd0;
+	litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			if (soc_litedramcore_read_available) begin
 				if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
-					multiplexer_next_state <= 2'd3;
+					litedramcore_multiplexer_next_state <= 2'd3;
 				end
 			end
 			if (soc_litedramcore_go_to_refresh) begin
-				multiplexer_next_state <= 2'd2;
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
 			if (soc_litedramcore_cmd_last) begin
-				multiplexer_next_state <= 1'd0;
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
 			if (soc_litedramcore_twtrcon_ready) begin
-				multiplexer_next_state <= 1'd0;
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			multiplexer_next_state <= 3'd5;
+			litedramcore_multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			multiplexer_next_state <= 3'd6;
+			litedramcore_multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			multiplexer_next_state <= 3'd7;
+			litedramcore_multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			multiplexer_next_state <= 4'd8;
+			litedramcore_multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			multiplexer_next_state <= 4'd9;
+			litedramcore_multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			multiplexer_next_state <= 4'd10;
+			litedramcore_multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			multiplexer_next_state <= 1'd1;
+			litedramcore_multiplexer_next_state <= 1'd1;
 		end
 		default: begin
 			if (soc_litedramcore_write_available) begin
 				if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
-					multiplexer_next_state <= 3'd4;
+					litedramcore_multiplexer_next_state <= 3'd4;
 				end
 			end
 			if (soc_litedramcore_go_to_refresh) begin
-				multiplexer_next_state <= 2'd2;
+				litedramcore_multiplexer_next_state <= 2'd2;
+			end
+		end
+	endcase
+end
+always @(*) begin
+	soc_litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
+		1'd1: begin
+			if (1'd0) begin
+				soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+			end else begin
+				soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			if (1'd0) begin
+				soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+			end else begin
+				soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
 			end
 		end
 	endcase
 end
 always @(*) begin
 	soc_litedramcore_en1 <= 1'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			soc_litedramcore_en1 <= 1'd1;
 		end
@@ -9295,7 +9749,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_steerer_sel0 <= 2'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			soc_litedramcore_steerer_sel0 <= 1'd0;
 			if (1'd0) begin
@@ -9337,7 +9791,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_steerer_sel1 <= 2'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			soc_litedramcore_steerer_sel1 <= 1'd0;
 			if (1'd0) begin
@@ -9378,7 +9832,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_steerer_sel2 <= 2'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			soc_litedramcore_steerer_sel2 <= 1'd0;
 			if (1'd0) begin
@@ -9419,7 +9873,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			if (1'd0) begin
 			end else begin
@@ -9454,7 +9908,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_steerer_sel3 <= 2'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			soc_litedramcore_steerer_sel3 <= 1'd0;
 			if (1'd1) begin
@@ -9495,7 +9949,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_en0 <= 1'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9523,7 +9977,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_cmd_ready <= 1'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9551,7 +10005,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			if (1'd0) begin
 			end else begin
@@ -9586,7 +10040,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_choose_req_want_reads <= 1'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -9614,7 +10068,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_choose_req_want_writes <= 1'd0;
-	case (multiplexer_state)
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
 			soc_litedramcore_choose_req_want_writes <= 1'd1;
 		end
@@ -9640,89 +10094,52 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	soc_litedramcore_choose_req_cmd_ready <= 1'd0;
-	case (multiplexer_state)
-		1'd1: begin
-			if (1'd0) begin
-				soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
-			end else begin
-				soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			if (1'd0) begin
-				soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
-			end else begin
-				soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
-			end
-		end
-	endcase
-end
-assign roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
+assign litedramcore_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
 assign soc_litedramcore_interface_bank0_addr = rhs_array_muxed12;
 assign soc_litedramcore_interface_bank0_we = rhs_array_muxed13;
 assign soc_litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
+assign litedramcore_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
 assign soc_litedramcore_interface_bank1_addr = rhs_array_muxed15;
 assign soc_litedramcore_interface_bank1_we = rhs_array_muxed16;
 assign soc_litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
+assign litedramcore_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
 assign soc_litedramcore_interface_bank2_addr = rhs_array_muxed18;
 assign soc_litedramcore_interface_bank2_we = rhs_array_muxed19;
 assign soc_litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
+assign litedramcore_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
 assign soc_litedramcore_interface_bank3_addr = rhs_array_muxed21;
 assign soc_litedramcore_interface_bank3_we = rhs_array_muxed22;
 assign soc_litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
+assign litedramcore_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
 assign soc_litedramcore_interface_bank4_addr = rhs_array_muxed24;
 assign soc_litedramcore_interface_bank4_we = rhs_array_muxed25;
 assign soc_litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
+assign litedramcore_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
 assign soc_litedramcore_interface_bank5_addr = rhs_array_muxed27;
 assign soc_litedramcore_interface_bank5_we = rhs_array_muxed28;
 assign soc_litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
+assign litedramcore_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
 assign soc_litedramcore_interface_bank6_addr = rhs_array_muxed30;
 assign soc_litedramcore_interface_bank6_we = rhs_array_muxed31;
 assign soc_litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
+assign litedramcore_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
 assign soc_litedramcore_interface_bank7_addr = rhs_array_muxed33;
 assign soc_litedramcore_interface_bank7_we = rhs_array_muxed34;
 assign soc_litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
-assign soc_user_port_wdata_ready = new_master_wdata_ready1;
-assign soc_user_port_rdata_valid = new_master_rdata_valid8;
+assign soc_user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
+assign soc_user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
+assign soc_user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
 always @(*) begin
 	soc_litedramcore_interface_wdata <= 128'd0;
-	case ({new_master_wdata_ready1})
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
 			soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
 		end
@@ -9733,7 +10150,7 @@ always @(*) begin
 end
 always @(*) begin
 	soc_litedramcore_interface_wdata_we <= 16'd0;
-	case ({new_master_wdata_ready1})
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
 			soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
 		end
@@ -9743,136 +10160,136 @@ always @(*) begin
 	endcase
 end
 assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata;
-assign roundrobin0_grant = 1'd0;
-assign roundrobin1_grant = 1'd0;
-assign roundrobin2_grant = 1'd0;
-assign roundrobin3_grant = 1'd0;
-assign roundrobin4_grant = 1'd0;
-assign roundrobin5_grant = 1'd0;
-assign roundrobin6_grant = 1'd0;
-assign roundrobin7_grant = 1'd0;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-	next_state <= 2'd0;
-	next_state <= state;
-	case (state)
+	litedramcore_next_state <= 2'd0;
+	litedramcore_next_state <= litedramcore_state;
+	case (litedramcore_state)
 		1'd1: begin
-			next_state <= 2'd2;
+			litedramcore_next_state <= 2'd2;
 		end
 		2'd2: begin
-			next_state <= 1'd0;
+			litedramcore_next_state <= 1'd0;
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				next_state <= 1'd1;
+				litedramcore_next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value1 <= 14'd0;
-	case (state)
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-			end
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value_ce1 <= 1'd0;
-	case (state)
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value_ce1 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_wishbone_dat_r <= 32'd0;
-	case (state)
+	litedramcore_wishbone_ack <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value2 <= 1'd0;
-	case (state)
+	litedramcore_adr_next_value1 <= 14'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_we_next_value2 <= 1'd0;
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value_ce2 <= 1'd0;
-	case (state)
+	litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			litedramcore_we_next_value_ce2 <= 1'd1;
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value_ce2 <= 1'd1;
+				litedramcore_adr_next_value_ce1 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_wishbone_ack <= 1'd0;
-	case (state)
+	litedramcore_we_next_value2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
-			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_dat_w_next_value0 <= 32'd0;
-	case (state)
+	litedramcore_we_next_value_ce2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_dat_w_next_value_ce0 <= 1'd0;
-	case (state)
+	litedramcore_wishbone_dat_r <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
@@ -10023,15 +10440,15 @@ always @(*) begin
 end
 assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
+		soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
+		soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
@@ -10179,15 +10596,15 @@ always @(*) begin
 end
 assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
-		soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we;
+		soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
-		soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we);
+		soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
@@ -10247,24 +10664,48 @@ assign soc_litedramcore_cke = soc_litedramcore_storage[1];
 assign soc_litedramcore_odt = soc_litedramcore_storage[2];
 assign soc_litedramcore_reset_n = soc_litedramcore_storage[3];
 assign csrbank1_dfii_control0_w = soc_litedramcore_storage[3:0];
+assign soc_litedramcore_phaseinjector0_csrfield_cs = soc_litedramcore_phaseinjector0_command_storage[0];
+assign soc_litedramcore_phaseinjector0_csrfield_we = soc_litedramcore_phaseinjector0_command_storage[1];
+assign soc_litedramcore_phaseinjector0_csrfield_cas = soc_litedramcore_phaseinjector0_command_storage[2];
+assign soc_litedramcore_phaseinjector0_csrfield_ras = soc_litedramcore_phaseinjector0_command_storage[3];
+assign soc_litedramcore_phaseinjector0_csrfield_wren = soc_litedramcore_phaseinjector0_command_storage[4];
+assign soc_litedramcore_phaseinjector0_csrfield_rden = soc_litedramcore_phaseinjector0_command_storage[5];
 assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0];
 assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0];
 assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0];
 assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0];
 assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status[31:0];
 assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata_we;
+assign soc_litedramcore_phaseinjector1_csrfield_cs = soc_litedramcore_phaseinjector1_command_storage[0];
+assign soc_litedramcore_phaseinjector1_csrfield_we = soc_litedramcore_phaseinjector1_command_storage[1];
+assign soc_litedramcore_phaseinjector1_csrfield_cas = soc_litedramcore_phaseinjector1_command_storage[2];
+assign soc_litedramcore_phaseinjector1_csrfield_ras = soc_litedramcore_phaseinjector1_command_storage[3];
+assign soc_litedramcore_phaseinjector1_csrfield_wren = soc_litedramcore_phaseinjector1_command_storage[4];
+assign soc_litedramcore_phaseinjector1_csrfield_rden = soc_litedramcore_phaseinjector1_command_storage[5];
 assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0];
 assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0];
 assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0];
 assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0];
 assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status[31:0];
 assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata_we;
+assign soc_litedramcore_phaseinjector2_csrfield_cs = soc_litedramcore_phaseinjector2_command_storage[0];
+assign soc_litedramcore_phaseinjector2_csrfield_we = soc_litedramcore_phaseinjector2_command_storage[1];
+assign soc_litedramcore_phaseinjector2_csrfield_cas = soc_litedramcore_phaseinjector2_command_storage[2];
+assign soc_litedramcore_phaseinjector2_csrfield_ras = soc_litedramcore_phaseinjector2_command_storage[3];
+assign soc_litedramcore_phaseinjector2_csrfield_wren = soc_litedramcore_phaseinjector2_command_storage[4];
+assign soc_litedramcore_phaseinjector2_csrfield_rden = soc_litedramcore_phaseinjector2_command_storage[5];
 assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0];
 assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0];
 assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0];
 assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0];
 assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status[31:0];
 assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata_we;
+assign soc_litedramcore_phaseinjector3_csrfield_cs = soc_litedramcore_phaseinjector3_command_storage[0];
+assign soc_litedramcore_phaseinjector3_csrfield_we = soc_litedramcore_phaseinjector3_command_storage[1];
+assign soc_litedramcore_phaseinjector3_csrfield_cas = soc_litedramcore_phaseinjector3_command_storage[2];
+assign soc_litedramcore_phaseinjector3_csrfield_ras = soc_litedramcore_phaseinjector3_command_storage[3];
+assign soc_litedramcore_phaseinjector3_csrfield_wren = soc_litedramcore_phaseinjector3_command_storage[4];
+assign soc_litedramcore_phaseinjector3_csrfield_rden = soc_litedramcore_phaseinjector3_command_storage[5];
 assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0];
 assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0];
 assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0];
@@ -10822,7 +11263,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed12 <= 21'd0;
-	case (roundrobin0_grant)
+	case (litedramcore_roundrobin0_grant)
 		default: begin
 			rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10830,7 +11271,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed13 <= 1'd0;
-	case (roundrobin0_grant)
+	case (litedramcore_roundrobin0_grant)
 		default: begin
 			rhs_array_muxed13 <= soc_user_port_cmd_payload_we;
 		end
@@ -10838,15 +11279,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed14 <= 1'd0;
-	case (roundrobin0_grant)
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed15 <= 21'd0;
-	case (roundrobin1_grant)
+	case (litedramcore_roundrobin1_grant)
 		default: begin
 			rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10854,7 +11295,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed16 <= 1'd0;
-	case (roundrobin1_grant)
+	case (litedramcore_roundrobin1_grant)
 		default: begin
 			rhs_array_muxed16 <= soc_user_port_cmd_payload_we;
 		end
@@ -10862,15 +11303,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed17 <= 1'd0;
-	case (roundrobin1_grant)
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed18 <= 21'd0;
-	case (roundrobin2_grant)
+	case (litedramcore_roundrobin2_grant)
 		default: begin
 			rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10878,7 +11319,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed19 <= 1'd0;
-	case (roundrobin2_grant)
+	case (litedramcore_roundrobin2_grant)
 		default: begin
 			rhs_array_muxed19 <= soc_user_port_cmd_payload_we;
 		end
@@ -10886,15 +11327,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed20 <= 1'd0;
-	case (roundrobin2_grant)
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed21 <= 21'd0;
-	case (roundrobin3_grant)
+	case (litedramcore_roundrobin3_grant)
 		default: begin
 			rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10902,7 +11343,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed22 <= 1'd0;
-	case (roundrobin3_grant)
+	case (litedramcore_roundrobin3_grant)
 		default: begin
 			rhs_array_muxed22 <= soc_user_port_cmd_payload_we;
 		end
@@ -10910,15 +11351,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed23 <= 1'd0;
-	case (roundrobin3_grant)
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed24 <= 21'd0;
-	case (roundrobin4_grant)
+	case (litedramcore_roundrobin4_grant)
 		default: begin
 			rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10926,7 +11367,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed25 <= 1'd0;
-	case (roundrobin4_grant)
+	case (litedramcore_roundrobin4_grant)
 		default: begin
 			rhs_array_muxed25 <= soc_user_port_cmd_payload_we;
 		end
@@ -10934,15 +11375,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed26 <= 1'd0;
-	case (roundrobin4_grant)
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed27 <= 21'd0;
-	case (roundrobin5_grant)
+	case (litedramcore_roundrobin5_grant)
 		default: begin
 			rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10950,7 +11391,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed28 <= 1'd0;
-	case (roundrobin5_grant)
+	case (litedramcore_roundrobin5_grant)
 		default: begin
 			rhs_array_muxed28 <= soc_user_port_cmd_payload_we;
 		end
@@ -10958,15 +11399,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed29 <= 1'd0;
-	case (roundrobin5_grant)
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed30 <= 21'd0;
-	case (roundrobin6_grant)
+	case (litedramcore_roundrobin6_grant)
 		default: begin
 			rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10974,7 +11415,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed31 <= 1'd0;
-	case (roundrobin6_grant)
+	case (litedramcore_roundrobin6_grant)
 		default: begin
 			rhs_array_muxed31 <= soc_user_port_cmd_payload_we;
 		end
@@ -10982,15 +11423,15 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed32 <= 1'd0;
-	case (roundrobin6_grant)
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
 	rhs_array_muxed33 <= 21'd0;
-	case (roundrobin7_grant)
+	case (litedramcore_roundrobin7_grant)
 		default: begin
 			rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
 		end
@@ -10998,7 +11439,7 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed34 <= 1'd0;
-	case (roundrobin7_grant)
+	case (litedramcore_roundrobin7_grant)
 		default: begin
 			rhs_array_muxed34 <= soc_user_port_cmd_payload_we;
 		end
@@ -11006,9 +11447,9 @@ always @(*) begin
 end
 always @(*) begin
 	rhs_array_muxed35 <= 1'd0;
-	case (roundrobin7_grant)
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
+			rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
 		end
 	endcase
 end
@@ -11595,17 +12036,17 @@ always @(posedge sys_clk) begin
 			soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row;
 		end
 	end
-	if (soc_litedramcore_inti_p0_rddata_valid) begin
-		soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_inti_p0_rddata;
+	if (soc_litedramcore_csr_dfi_p0_rddata_valid) begin
+		soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_csr_dfi_p0_rddata;
 	end
-	if (soc_litedramcore_inti_p1_rddata_valid) begin
-		soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_inti_p1_rddata;
+	if (soc_litedramcore_csr_dfi_p1_rddata_valid) begin
+		soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_csr_dfi_p1_rddata;
 	end
-	if (soc_litedramcore_inti_p2_rddata_valid) begin
-		soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_inti_p2_rddata;
+	if (soc_litedramcore_csr_dfi_p2_rddata_valid) begin
+		soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_csr_dfi_p2_rddata;
 	end
-	if (soc_litedramcore_inti_p3_rddata_valid) begin
-		soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_inti_p3_rddata;
+	if (soc_litedramcore_csr_dfi_p3_rddata_valid) begin
+		soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_csr_dfi_p3_rddata;
 	end
 	if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin
 		soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1);
@@ -11707,7 +12148,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	refresher_state <= refresher_next_state;
+	litedramcore_refresher_state <= litedramcore_refresher_next_state;
 	if (soc_litedramcore_bankmachine0_row_close) begin
 		soc_litedramcore_bankmachine0_row_opened <= 1'd0;
 	end else begin
@@ -11783,7 +12224,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine0_state <= bankmachine0_next_state;
+	litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
 	if (soc_litedramcore_bankmachine1_row_close) begin
 		soc_litedramcore_bankmachine1_row_opened <= 1'd0;
 	end else begin
@@ -11859,7 +12300,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine1_state <= bankmachine1_next_state;
+	litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
 	if (soc_litedramcore_bankmachine2_row_close) begin
 		soc_litedramcore_bankmachine2_row_opened <= 1'd0;
 	end else begin
@@ -11935,7 +12376,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine2_state <= bankmachine2_next_state;
+	litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
 	if (soc_litedramcore_bankmachine3_row_close) begin
 		soc_litedramcore_bankmachine3_row_opened <= 1'd0;
 	end else begin
@@ -12011,7 +12452,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine3_state <= bankmachine3_next_state;
+	litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
 	if (soc_litedramcore_bankmachine4_row_close) begin
 		soc_litedramcore_bankmachine4_row_opened <= 1'd0;
 	end else begin
@@ -12087,7 +12528,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine4_state <= bankmachine4_next_state;
+	litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
 	if (soc_litedramcore_bankmachine5_row_close) begin
 		soc_litedramcore_bankmachine5_row_opened <= 1'd0;
 	end else begin
@@ -12163,7 +12604,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine5_state <= bankmachine5_next_state;
+	litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
 	if (soc_litedramcore_bankmachine6_row_close) begin
 		soc_litedramcore_bankmachine6_row_opened <= 1'd0;
 	end else begin
@@ -12239,7 +12680,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine6_state <= bankmachine6_next_state;
+	litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
 	if (soc_litedramcore_bankmachine7_row_close) begin
 		soc_litedramcore_bankmachine7_row_opened <= 1'd0;
 	end else begin
@@ -12315,7 +12756,7 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	bankmachine7_state <= bankmachine7_next_state;
+	litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
 	if ((~soc_litedramcore_en0)) begin
 		soc_litedramcore_time0 <= 5'd31;
 	end else begin
@@ -12887,19 +13328,19 @@ always @(posedge sys_clk) begin
 			end
 		end
 	end
-	multiplexer_state <= multiplexer_next_state;
-	new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
-	new_master_wdata_ready1 <= new_master_wdata_ready0;
-	new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
-	new_master_rdata_valid1 <= new_master_rdata_valid0;
-	new_master_rdata_valid2 <= new_master_rdata_valid1;
-	new_master_rdata_valid3 <= new_master_rdata_valid2;
-	new_master_rdata_valid4 <= new_master_rdata_valid3;
-	new_master_rdata_valid5 <= new_master_rdata_valid4;
-	new_master_rdata_valid6 <= new_master_rdata_valid5;
-	new_master_rdata_valid7 <= new_master_rdata_valid6;
-	new_master_rdata_valid8 <= new_master_rdata_valid7;
-	state <= next_state;
+	litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+	litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
+	litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+	litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
+	litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+	litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+	litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+	litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+	litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+	litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+	litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+	litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+	litedramcore_state <= litedramcore_next_state;
 	if (litedramcore_dat_w_next_value_ce0) begin
 		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
 	end
@@ -13333,29 +13774,29 @@ always @(posedge sys_clk) begin
 		soc_init_done_re <= 1'd0;
 		soc_init_error_storage <= 1'd0;
 		soc_init_error_re <= 1'd0;
-		refresher_state <= 2'd0;
-		bankmachine0_state <= 4'd0;
-		bankmachine1_state <= 4'd0;
-		bankmachine2_state <= 4'd0;
-		bankmachine3_state <= 4'd0;
-		bankmachine4_state <= 4'd0;
-		bankmachine5_state <= 4'd0;
-		bankmachine6_state <= 4'd0;
-		bankmachine7_state <= 4'd0;
-		multiplexer_state <= 4'd0;
-		new_master_wdata_ready0 <= 1'd0;
-		new_master_wdata_ready1 <= 1'd0;
-		new_master_rdata_valid0 <= 1'd0;
-		new_master_rdata_valid1 <= 1'd0;
-		new_master_rdata_valid2 <= 1'd0;
-		new_master_rdata_valid3 <= 1'd0;
-		new_master_rdata_valid4 <= 1'd0;
-		new_master_rdata_valid5 <= 1'd0;
-		new_master_rdata_valid6 <= 1'd0;
-		new_master_rdata_valid7 <= 1'd0;
-		new_master_rdata_valid8 <= 1'd0;
 		litedramcore_we <= 1'd0;
-		state <= 2'd0;
+		litedramcore_refresher_state <= 2'd0;
+		litedramcore_bankmachine0_state <= 4'd0;
+		litedramcore_bankmachine1_state <= 4'd0;
+		litedramcore_bankmachine2_state <= 4'd0;
+		litedramcore_bankmachine3_state <= 4'd0;
+		litedramcore_bankmachine4_state <= 4'd0;
+		litedramcore_bankmachine5_state <= 4'd0;
+		litedramcore_bankmachine6_state <= 4'd0;
+		litedramcore_bankmachine7_state <= 4'd0;
+		litedramcore_multiplexer_state <= 4'd0;
+		litedramcore_new_master_wdata_ready0 <= 1'd0;
+		litedramcore_new_master_wdata_ready1 <= 1'd0;
+		litedramcore_new_master_rdata_valid0 <= 1'd0;
+		litedramcore_new_master_rdata_valid1 <= 1'd0;
+		litedramcore_new_master_rdata_valid2 <= 1'd0;
+		litedramcore_new_master_rdata_valid3 <= 1'd0;
+		litedramcore_new_master_rdata_valid4 <= 1'd0;
+		litedramcore_new_master_rdata_valid5 <= 1'd0;
+		litedramcore_new_master_rdata_valid6 <= 1'd0;
+		litedramcore_new_master_rdata_valid7 <= 1'd0;
+		litedramcore_new_master_rdata_valid8 <= 1'd0;
+		litedramcore_state <= 2'd0;
 	end
 end
 
@@ -13895,5 +14336,5 @@ assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-01-14 08:32:16.
+//  Auto-Generated by LiteX on 2022-08-04 21:07:04.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init
index 1b6e88e..9006b18 100644
--- a/litedram/generated/wukong-v2/litedram_core.init
+++ b/litedram/generated/wukong-v2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
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@@ -519,213 +519,215 @@ a64b5a7d14004a39
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@@ -735,7 +737,7 @@ ebc100b8eb8100c0
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@@ -757,7 +759,7 @@ ebc100b8eb8100c0
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@@ -767,7 +769,7 @@ ebc100b8eb8100c0
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+3aa0000889360001
+4082fdc02c09006c
+4bfffdb87cf63b78
+3aa0000289360001
+4082fda82c090068
+3aa000017cf63b78
+3949ffd04bfffd9c
+280a0009554a063e
+7aea00204181fd8c
+7d4152143af70001
+4bfffd78992a0020
+4bfffd703aa00008
+3ac100413a600020
+993f00004bfffba4
+7d0543783bff0001
+4bfffaf4fbe10060
+0100000000000000
+f9c1ff7000001280
+fa01ff80f9e1ff78
+fa41ff90fa21ff88
+fa81ffa0fa61ff98
+fac1ffb0faa1ffa8
+fb01ffc0fae1ffb8
+fb41ffd0fb21ffc8
+fb81ffe0fb61ffd8
+fbc1fff0fba1ffe8
+f8010010fbe1fff8
+e9c1ff704e800020
+ea01ff80e9e1ff78
+ea41ff90ea21ff88
+ea81ffa0ea61ff98
+eac1ffb0eaa1ffa8
+eb01ffc0eae1ffb8
+eb41ffd0eb21ffc8
+eb81ffe0eb61ffd8
+eba1ffe8e8010010
+ebc1fff07c0803a6
+4e800020ebe1fff8
+e8010010ebc1fff0
+7c0803a6ebe1fff8
+600000004e800020
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -1858,17 +1870,15 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
-2d2d2d2d2d2d2d2d
-0000000000000000
-4d4152446574694c
-6620746c69756220
-6567694d206d6f72
-646e61207325206e
-2520586574694c20
-0000000000000a73
 20676e69746f6f42
 415242206d6f7266
 0000000a2e2e2e4d
+3135636632333936
+0000000000000000
+4d4152446574694c
+6620746c69756220
+6574694c206d6f72
+0000000a73252058
 6620676e69797254
 0a2e2e2e6873616c
 0000000000000000
diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v
index 233a914..d4db3de 100644
--- a/litedram/generated/wukong-v2/litedram_core.v
+++ b/litedram/generated/wukong-v2/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-01-14 08:32:15
+// LiteX sha1 : 6932fc51
+// Date       : 2022-08-04 21:07:01
 //------------------------------------------------------------------------------
 
 
@@ -69,4263 +69,4682 @@ module litedram_core (
 // Signals
 //------------------------------------------------------------------------------
 
-reg  main_rst = 1'd0;
+reg  rst_1 = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
 wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
-wire main_reset;
-reg  main_power_down = 1'd0;
-wire main_locked;
-wire main_clkin;
-wire main_clkout0;
-wire main_clkout_buf0;
-wire main_clkout1;
-wire main_clkout_buf1;
-wire main_clkout2;
-wire main_clkout_buf2;
-wire main_clkout3;
-wire main_clkout_buf3;
-reg  [3:0] main_reset_counter = 4'd15;
-reg  main_ic_reset = 1'd1;
-reg  main_a7ddrphy_rst_storage = 1'd0;
-reg  main_a7ddrphy_rst_re = 1'd0;
-reg  [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg  main_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg  main_a7ddrphy_wlevel_en_storage = 1'd0;
-reg  main_a7ddrphy_wlevel_en_re = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_re = 1'd0;
-wire main_a7ddrphy_wlevel_strobe_r;
-reg  main_a7ddrphy_wlevel_strobe_we = 1'd0;
-reg  main_a7ddrphy_wlevel_strobe_w = 1'd0;
-reg  [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
-reg  main_a7ddrphy_dly_sel_re = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_rst_r;
-reg  main_a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_inc_r;
-reg  main_a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_rdly_dq_bitslip_r;
-reg  main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire main_a7ddrphy_wdly_dq_bitslip_r;
-reg  main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg  main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg  [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
-reg  main_a7ddrphy_rdphase_re = 1'd0;
-reg  [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
-reg  main_a7ddrphy_wrphase_re = 1'd0;
-wire [13:0] main_a7ddrphy_dfi_p0_address;
-wire [2:0] main_a7ddrphy_dfi_p0_bank;
-wire main_a7ddrphy_dfi_p0_cas_n;
-wire main_a7ddrphy_dfi_p0_cs_n;
-wire main_a7ddrphy_dfi_p0_ras_n;
-wire main_a7ddrphy_dfi_p0_we_n;
-wire main_a7ddrphy_dfi_p0_cke;
-wire main_a7ddrphy_dfi_p0_odt;
-wire main_a7ddrphy_dfi_p0_reset_n;
-wire main_a7ddrphy_dfi_p0_act_n;
-wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
-wire main_a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
-wire main_a7ddrphy_dfi_p0_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p0_rddata_valid;
-wire [13:0] main_a7ddrphy_dfi_p1_address;
-wire [2:0] main_a7ddrphy_dfi_p1_bank;
-wire main_a7ddrphy_dfi_p1_cas_n;
-wire main_a7ddrphy_dfi_p1_cs_n;
-wire main_a7ddrphy_dfi_p1_ras_n;
-wire main_a7ddrphy_dfi_p1_we_n;
-wire main_a7ddrphy_dfi_p1_cke;
-wire main_a7ddrphy_dfi_p1_odt;
-wire main_a7ddrphy_dfi_p1_reset_n;
-wire main_a7ddrphy_dfi_p1_act_n;
-wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
-wire main_a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
-wire main_a7ddrphy_dfi_p1_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p1_rddata_valid;
-wire [13:0] main_a7ddrphy_dfi_p2_address;
-wire [2:0] main_a7ddrphy_dfi_p2_bank;
-wire main_a7ddrphy_dfi_p2_cas_n;
-wire main_a7ddrphy_dfi_p2_cs_n;
-wire main_a7ddrphy_dfi_p2_ras_n;
-wire main_a7ddrphy_dfi_p2_we_n;
-wire main_a7ddrphy_dfi_p2_cke;
-wire main_a7ddrphy_dfi_p2_odt;
-wire main_a7ddrphy_dfi_p2_reset_n;
-wire main_a7ddrphy_dfi_p2_act_n;
-wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
-wire main_a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
-wire main_a7ddrphy_dfi_p2_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p2_rddata_valid;
-wire [13:0] main_a7ddrphy_dfi_p3_address;
-wire [2:0] main_a7ddrphy_dfi_p3_bank;
-wire main_a7ddrphy_dfi_p3_cas_n;
-wire main_a7ddrphy_dfi_p3_cs_n;
-wire main_a7ddrphy_dfi_p3_ras_n;
-wire main_a7ddrphy_dfi_p3_we_n;
-wire main_a7ddrphy_dfi_p3_cke;
-wire main_a7ddrphy_dfi_p3_odt;
-wire main_a7ddrphy_dfi_p3_reset_n;
-wire main_a7ddrphy_dfi_p3_act_n;
-wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
-wire main_a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
-wire main_a7ddrphy_dfi_p3_rddata_en;
-reg  [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
-wire main_a7ddrphy_dfi_p3_rddata_valid;
-wire main_a7ddrphy_sd_clk_se_nodelay;
-reg  main_a7ddrphy_dqs_oe = 1'd0;
-wire main_a7ddrphy_dqs_preamble;
-wire main_a7ddrphy_dqs_postamble;
-wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_dqspattern0 = 1'd0;
-reg  main_a7ddrphy_dqspattern1 = 1'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
-reg  [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
-wire main_a7ddrphy_dqs_o_no_delay0;
-wire main_a7ddrphy_dqs_t0;
-reg  [7:0] main_a7ddrphy_bitslip00 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
-wire main_a7ddrphy0;
-wire main_a7ddrphy_dqs_o_no_delay1;
-wire main_a7ddrphy_dqs_t1;
-reg  [7:0] main_a7ddrphy_bitslip10 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
-wire main_a7ddrphy1;
-reg  [7:0] main_a7ddrphy_bitslip01 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
-reg  [7:0] main_a7ddrphy_bitslip11 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
-wire main_a7ddrphy_dq_oe;
-wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire main_a7ddrphy_dq_o_nodelay0;
-wire main_a7ddrphy_dq_i_nodelay0;
-wire main_a7ddrphy_dq_i_delayed0;
-wire main_a7ddrphy_dq_t0;
-reg  [7:0] main_a7ddrphy_bitslip02 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip03;
-reg  [7:0] main_a7ddrphy_bitslip04 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay1;
-wire main_a7ddrphy_dq_i_nodelay1;
-wire main_a7ddrphy_dq_i_delayed1;
-wire main_a7ddrphy_dq_t1;
-reg  [7:0] main_a7ddrphy_bitslip12 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip13;
-reg  [7:0] main_a7ddrphy_bitslip14 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay2;
-wire main_a7ddrphy_dq_i_nodelay2;
-wire main_a7ddrphy_dq_i_delayed2;
-wire main_a7ddrphy_dq_t2;
-reg  [7:0] main_a7ddrphy_bitslip20 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip21;
-reg  [7:0] main_a7ddrphy_bitslip22 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay3;
-wire main_a7ddrphy_dq_i_nodelay3;
-wire main_a7ddrphy_dq_i_delayed3;
-wire main_a7ddrphy_dq_t3;
-reg  [7:0] main_a7ddrphy_bitslip30 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip31;
-reg  [7:0] main_a7ddrphy_bitslip32 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay4;
-wire main_a7ddrphy_dq_i_nodelay4;
-wire main_a7ddrphy_dq_i_delayed4;
-wire main_a7ddrphy_dq_t4;
-reg  [7:0] main_a7ddrphy_bitslip40 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip41;
-reg  [7:0] main_a7ddrphy_bitslip42 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay5;
-wire main_a7ddrphy_dq_i_nodelay5;
-wire main_a7ddrphy_dq_i_delayed5;
-wire main_a7ddrphy_dq_t5;
-reg  [7:0] main_a7ddrphy_bitslip50 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip51;
-reg  [7:0] main_a7ddrphy_bitslip52 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay6;
-wire main_a7ddrphy_dq_i_nodelay6;
-wire main_a7ddrphy_dq_i_delayed6;
-wire main_a7ddrphy_dq_t6;
-reg  [7:0] main_a7ddrphy_bitslip60 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip61;
-reg  [7:0] main_a7ddrphy_bitslip62 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay7;
-wire main_a7ddrphy_dq_i_nodelay7;
-wire main_a7ddrphy_dq_i_delayed7;
-wire main_a7ddrphy_dq_t7;
-reg  [7:0] main_a7ddrphy_bitslip70 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip71;
-reg  [7:0] main_a7ddrphy_bitslip72 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay8;
-wire main_a7ddrphy_dq_i_nodelay8;
-wire main_a7ddrphy_dq_i_delayed8;
-wire main_a7ddrphy_dq_t8;
-reg  [7:0] main_a7ddrphy_bitslip80 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip81;
-reg  [7:0] main_a7ddrphy_bitslip82 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay9;
-wire main_a7ddrphy_dq_i_nodelay9;
-wire main_a7ddrphy_dq_i_delayed9;
-wire main_a7ddrphy_dq_t9;
-reg  [7:0] main_a7ddrphy_bitslip90 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip91;
-reg  [7:0] main_a7ddrphy_bitslip92 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay10;
-wire main_a7ddrphy_dq_i_nodelay10;
-wire main_a7ddrphy_dq_i_delayed10;
-wire main_a7ddrphy_dq_t10;
-reg  [7:0] main_a7ddrphy_bitslip100 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip101;
-reg  [7:0] main_a7ddrphy_bitslip102 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay11;
-wire main_a7ddrphy_dq_i_nodelay11;
-wire main_a7ddrphy_dq_i_delayed11;
-wire main_a7ddrphy_dq_t11;
-reg  [7:0] main_a7ddrphy_bitslip110 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip111;
-reg  [7:0] main_a7ddrphy_bitslip112 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay12;
-wire main_a7ddrphy_dq_i_nodelay12;
-wire main_a7ddrphy_dq_i_delayed12;
-wire main_a7ddrphy_dq_t12;
-reg  [7:0] main_a7ddrphy_bitslip120 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip121;
-reg  [7:0] main_a7ddrphy_bitslip122 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay13;
-wire main_a7ddrphy_dq_i_nodelay13;
-wire main_a7ddrphy_dq_i_delayed13;
-wire main_a7ddrphy_dq_t13;
-reg  [7:0] main_a7ddrphy_bitslip130 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip131;
-reg  [7:0] main_a7ddrphy_bitslip132 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay14;
-wire main_a7ddrphy_dq_i_nodelay14;
-wire main_a7ddrphy_dq_i_delayed14;
-wire main_a7ddrphy_dq_t14;
-reg  [7:0] main_a7ddrphy_bitslip140 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip141;
-reg  [7:0] main_a7ddrphy_bitslip142 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
-wire main_a7ddrphy_dq_o_nodelay15;
-wire main_a7ddrphy_dq_i_nodelay15;
-wire main_a7ddrphy_dq_i_delayed15;
-wire main_a7ddrphy_dq_t15;
-reg  [7:0] main_a7ddrphy_bitslip150 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] main_a7ddrphy_bitslip151;
-reg  [7:0] main_a7ddrphy_bitslip152 = 8'd0;
-reg  [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
-reg  [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg  main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg  main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [13:0] main_litedramcore_inti_p0_address;
-wire [2:0] main_litedramcore_inti_p0_bank;
-reg  main_litedramcore_inti_p0_cas_n = 1'd1;
-reg  main_litedramcore_inti_p0_cs_n = 1'd1;
-reg  main_litedramcore_inti_p0_ras_n = 1'd1;
-reg  main_litedramcore_inti_p0_we_n = 1'd1;
-wire main_litedramcore_inti_p0_cke;
-wire main_litedramcore_inti_p0_odt;
-wire main_litedramcore_inti_p0_reset_n;
-reg  main_litedramcore_inti_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p0_wrdata;
-wire main_litedramcore_inti_p0_wrdata_en;
-wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
-wire main_litedramcore_inti_p0_rddata_en;
-reg  [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
-reg  main_litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_inti_p1_address;
-wire [2:0] main_litedramcore_inti_p1_bank;
-reg  main_litedramcore_inti_p1_cas_n = 1'd1;
-reg  main_litedramcore_inti_p1_cs_n = 1'd1;
-reg  main_litedramcore_inti_p1_ras_n = 1'd1;
-reg  main_litedramcore_inti_p1_we_n = 1'd1;
-wire main_litedramcore_inti_p1_cke;
-wire main_litedramcore_inti_p1_odt;
-wire main_litedramcore_inti_p1_reset_n;
-reg  main_litedramcore_inti_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p1_wrdata;
-wire main_litedramcore_inti_p1_wrdata_en;
-wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
-wire main_litedramcore_inti_p1_rddata_en;
-reg  [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
-reg  main_litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_inti_p2_address;
-wire [2:0] main_litedramcore_inti_p2_bank;
-reg  main_litedramcore_inti_p2_cas_n = 1'd1;
-reg  main_litedramcore_inti_p2_cs_n = 1'd1;
-reg  main_litedramcore_inti_p2_ras_n = 1'd1;
-reg  main_litedramcore_inti_p2_we_n = 1'd1;
-wire main_litedramcore_inti_p2_cke;
-wire main_litedramcore_inti_p2_odt;
-wire main_litedramcore_inti_p2_reset_n;
-reg  main_litedramcore_inti_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p2_wrdata;
-wire main_litedramcore_inti_p2_wrdata_en;
-wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
-wire main_litedramcore_inti_p2_rddata_en;
-reg  [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
-reg  main_litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_inti_p3_address;
-wire [2:0] main_litedramcore_inti_p3_bank;
-reg  main_litedramcore_inti_p3_cas_n = 1'd1;
-reg  main_litedramcore_inti_p3_cs_n = 1'd1;
-reg  main_litedramcore_inti_p3_ras_n = 1'd1;
-reg  main_litedramcore_inti_p3_we_n = 1'd1;
-wire main_litedramcore_inti_p3_cke;
-wire main_litedramcore_inti_p3_odt;
-wire main_litedramcore_inti_p3_reset_n;
-reg  main_litedramcore_inti_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_inti_p3_wrdata;
-wire main_litedramcore_inti_p3_wrdata_en;
-wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
-wire main_litedramcore_inti_p3_rddata_en;
-reg  [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
-reg  main_litedramcore_inti_p3_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p0_address;
-wire [2:0] main_litedramcore_slave_p0_bank;
-wire main_litedramcore_slave_p0_cas_n;
-wire main_litedramcore_slave_p0_cs_n;
-wire main_litedramcore_slave_p0_ras_n;
-wire main_litedramcore_slave_p0_we_n;
-wire main_litedramcore_slave_p0_cke;
-wire main_litedramcore_slave_p0_odt;
-wire main_litedramcore_slave_p0_reset_n;
-wire main_litedramcore_slave_p0_act_n;
-wire [31:0] main_litedramcore_slave_p0_wrdata;
-wire main_litedramcore_slave_p0_wrdata_en;
-wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
-wire main_litedramcore_slave_p0_rddata_en;
-reg  [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
-reg  main_litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p1_address;
-wire [2:0] main_litedramcore_slave_p1_bank;
-wire main_litedramcore_slave_p1_cas_n;
-wire main_litedramcore_slave_p1_cs_n;
-wire main_litedramcore_slave_p1_ras_n;
-wire main_litedramcore_slave_p1_we_n;
-wire main_litedramcore_slave_p1_cke;
-wire main_litedramcore_slave_p1_odt;
-wire main_litedramcore_slave_p1_reset_n;
-wire main_litedramcore_slave_p1_act_n;
-wire [31:0] main_litedramcore_slave_p1_wrdata;
-wire main_litedramcore_slave_p1_wrdata_en;
-wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
-wire main_litedramcore_slave_p1_rddata_en;
-reg  [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
-reg  main_litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p2_address;
-wire [2:0] main_litedramcore_slave_p2_bank;
-wire main_litedramcore_slave_p2_cas_n;
-wire main_litedramcore_slave_p2_cs_n;
-wire main_litedramcore_slave_p2_ras_n;
-wire main_litedramcore_slave_p2_we_n;
-wire main_litedramcore_slave_p2_cke;
-wire main_litedramcore_slave_p2_odt;
-wire main_litedramcore_slave_p2_reset_n;
-wire main_litedramcore_slave_p2_act_n;
-wire [31:0] main_litedramcore_slave_p2_wrdata;
-wire main_litedramcore_slave_p2_wrdata_en;
-wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
-wire main_litedramcore_slave_p2_rddata_en;
-reg  [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
-reg  main_litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [13:0] main_litedramcore_slave_p3_address;
-wire [2:0] main_litedramcore_slave_p3_bank;
-wire main_litedramcore_slave_p3_cas_n;
-wire main_litedramcore_slave_p3_cs_n;
-wire main_litedramcore_slave_p3_ras_n;
-wire main_litedramcore_slave_p3_we_n;
-wire main_litedramcore_slave_p3_cke;
-wire main_litedramcore_slave_p3_odt;
-wire main_litedramcore_slave_p3_reset_n;
-wire main_litedramcore_slave_p3_act_n;
-wire [31:0] main_litedramcore_slave_p3_wrdata;
-wire main_litedramcore_slave_p3_wrdata_en;
-wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
-wire main_litedramcore_slave_p3_rddata_en;
-reg  [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
-reg  main_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg  [13:0] main_litedramcore_master_p0_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p0_bank = 3'd0;
-reg  main_litedramcore_master_p0_cas_n = 1'd1;
-reg  main_litedramcore_master_p0_cs_n = 1'd1;
-reg  main_litedramcore_master_p0_ras_n = 1'd1;
-reg  main_litedramcore_master_p0_we_n = 1'd1;
-reg  main_litedramcore_master_p0_cke = 1'd0;
-reg  main_litedramcore_master_p0_odt = 1'd0;
-reg  main_litedramcore_master_p0_reset_n = 1'd0;
-reg  main_litedramcore_master_p0_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
-reg  main_litedramcore_master_p0_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p0_rddata;
-wire main_litedramcore_master_p0_rddata_valid;
-reg  [13:0] main_litedramcore_master_p1_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p1_bank = 3'd0;
-reg  main_litedramcore_master_p1_cas_n = 1'd1;
-reg  main_litedramcore_master_p1_cs_n = 1'd1;
-reg  main_litedramcore_master_p1_ras_n = 1'd1;
-reg  main_litedramcore_master_p1_we_n = 1'd1;
-reg  main_litedramcore_master_p1_cke = 1'd0;
-reg  main_litedramcore_master_p1_odt = 1'd0;
-reg  main_litedramcore_master_p1_reset_n = 1'd0;
-reg  main_litedramcore_master_p1_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
-reg  main_litedramcore_master_p1_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p1_rddata;
-wire main_litedramcore_master_p1_rddata_valid;
-reg  [13:0] main_litedramcore_master_p2_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p2_bank = 3'd0;
-reg  main_litedramcore_master_p2_cas_n = 1'd1;
-reg  main_litedramcore_master_p2_cs_n = 1'd1;
-reg  main_litedramcore_master_p2_ras_n = 1'd1;
-reg  main_litedramcore_master_p2_we_n = 1'd1;
-reg  main_litedramcore_master_p2_cke = 1'd0;
-reg  main_litedramcore_master_p2_odt = 1'd0;
-reg  main_litedramcore_master_p2_reset_n = 1'd0;
-reg  main_litedramcore_master_p2_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
-reg  main_litedramcore_master_p2_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p2_rddata;
-wire main_litedramcore_master_p2_rddata_valid;
-reg  [13:0] main_litedramcore_master_p3_address = 14'd0;
-reg  [2:0] main_litedramcore_master_p3_bank = 3'd0;
-reg  main_litedramcore_master_p3_cas_n = 1'd1;
-reg  main_litedramcore_master_p3_cs_n = 1'd1;
-reg  main_litedramcore_master_p3_ras_n = 1'd1;
-reg  main_litedramcore_master_p3_we_n = 1'd1;
-reg  main_litedramcore_master_p3_cke = 1'd0;
-reg  main_litedramcore_master_p3_odt = 1'd0;
-reg  main_litedramcore_master_p3_reset_n = 1'd0;
-reg  main_litedramcore_master_p3_act_n = 1'd1;
-reg  [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
-reg  main_litedramcore_master_p3_wrdata_en = 1'd0;
-reg  [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg  main_litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_master_p3_rddata;
-wire main_litedramcore_master_p3_rddata_valid;
-wire main_litedramcore_sel;
-wire main_litedramcore_cke;
-wire main_litedramcore_odt;
-wire main_litedramcore_reset_n;
-reg  [3:0] main_litedramcore_storage = 4'd1;
-reg  main_litedramcore_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector0_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector0_command_issue_r;
-reg  main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector0_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector0_rddata_we;
-reg  main_litedramcore_phaseinjector0_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector1_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector1_command_issue_r;
-reg  main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector1_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector1_rddata_we;
-reg  main_litedramcore_phaseinjector1_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector2_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector2_command_issue_r;
-reg  main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector2_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector2_rddata_we;
-reg  main_litedramcore_phaseinjector2_rddata_re = 1'd0;
-reg  [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg  main_litedramcore_phaseinjector3_command_re = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire main_litedramcore_phaseinjector3_command_issue_r;
-reg  main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg  main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg  [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
-reg  main_litedramcore_phaseinjector3_address_re = 1'd0;
-reg  [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg  main_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg  main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg  [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire main_litedramcore_phaseinjector3_rddata_we;
-reg  main_litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire main_litedramcore_interface_bank0_valid;
-wire main_litedramcore_interface_bank0_ready;
-wire main_litedramcore_interface_bank0_we;
-wire [20:0] main_litedramcore_interface_bank0_addr;
-wire main_litedramcore_interface_bank0_lock;
-wire main_litedramcore_interface_bank0_wdata_ready;
-wire main_litedramcore_interface_bank0_rdata_valid;
-wire main_litedramcore_interface_bank1_valid;
-wire main_litedramcore_interface_bank1_ready;
-wire main_litedramcore_interface_bank1_we;
-wire [20:0] main_litedramcore_interface_bank1_addr;
-wire main_litedramcore_interface_bank1_lock;
-wire main_litedramcore_interface_bank1_wdata_ready;
-wire main_litedramcore_interface_bank1_rdata_valid;
-wire main_litedramcore_interface_bank2_valid;
-wire main_litedramcore_interface_bank2_ready;
-wire main_litedramcore_interface_bank2_we;
-wire [20:0] main_litedramcore_interface_bank2_addr;
-wire main_litedramcore_interface_bank2_lock;
-wire main_litedramcore_interface_bank2_wdata_ready;
-wire main_litedramcore_interface_bank2_rdata_valid;
-wire main_litedramcore_interface_bank3_valid;
-wire main_litedramcore_interface_bank3_ready;
-wire main_litedramcore_interface_bank3_we;
-wire [20:0] main_litedramcore_interface_bank3_addr;
-wire main_litedramcore_interface_bank3_lock;
-wire main_litedramcore_interface_bank3_wdata_ready;
-wire main_litedramcore_interface_bank3_rdata_valid;
-wire main_litedramcore_interface_bank4_valid;
-wire main_litedramcore_interface_bank4_ready;
-wire main_litedramcore_interface_bank4_we;
-wire [20:0] main_litedramcore_interface_bank4_addr;
-wire main_litedramcore_interface_bank4_lock;
-wire main_litedramcore_interface_bank4_wdata_ready;
-wire main_litedramcore_interface_bank4_rdata_valid;
-wire main_litedramcore_interface_bank5_valid;
-wire main_litedramcore_interface_bank5_ready;
-wire main_litedramcore_interface_bank5_we;
-wire [20:0] main_litedramcore_interface_bank5_addr;
-wire main_litedramcore_interface_bank5_lock;
-wire main_litedramcore_interface_bank5_wdata_ready;
-wire main_litedramcore_interface_bank5_rdata_valid;
-wire main_litedramcore_interface_bank6_valid;
-wire main_litedramcore_interface_bank6_ready;
-wire main_litedramcore_interface_bank6_we;
-wire [20:0] main_litedramcore_interface_bank6_addr;
-wire main_litedramcore_interface_bank6_lock;
-wire main_litedramcore_interface_bank6_wdata_ready;
-wire main_litedramcore_interface_bank6_rdata_valid;
-wire main_litedramcore_interface_bank7_valid;
-wire main_litedramcore_interface_bank7_ready;
-wire main_litedramcore_interface_bank7_we;
-wire [20:0] main_litedramcore_interface_bank7_addr;
-wire main_litedramcore_interface_bank7_lock;
-wire main_litedramcore_interface_bank7_wdata_ready;
-wire main_litedramcore_interface_bank7_rdata_valid;
-reg  [127:0] main_litedramcore_interface_wdata = 128'd0;
-reg  [15:0] main_litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] main_litedramcore_interface_rdata;
-reg  [13:0] main_litedramcore_dfi_p0_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
-reg  main_litedramcore_dfi_p0_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p0_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p0_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p0_we_n = 1'd1;
-wire main_litedramcore_dfi_p0_cke;
-wire main_litedramcore_dfi_p0_odt;
-wire main_litedramcore_dfi_p0_reset_n;
-reg  main_litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p0_wrdata;
-reg  main_litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
-reg  main_litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p0_rddata;
-wire main_litedramcore_dfi_p0_rddata_valid;
-reg  [13:0] main_litedramcore_dfi_p1_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
-reg  main_litedramcore_dfi_p1_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p1_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p1_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p1_we_n = 1'd1;
-wire main_litedramcore_dfi_p1_cke;
-wire main_litedramcore_dfi_p1_odt;
-wire main_litedramcore_dfi_p1_reset_n;
-reg  main_litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p1_wrdata;
-reg  main_litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
-reg  main_litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p1_rddata;
-wire main_litedramcore_dfi_p1_rddata_valid;
-reg  [13:0] main_litedramcore_dfi_p2_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
-reg  main_litedramcore_dfi_p2_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p2_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p2_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p2_we_n = 1'd1;
-wire main_litedramcore_dfi_p2_cke;
-wire main_litedramcore_dfi_p2_odt;
-wire main_litedramcore_dfi_p2_reset_n;
-reg  main_litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p2_wrdata;
-reg  main_litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
-reg  main_litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p2_rddata;
-wire main_litedramcore_dfi_p2_rddata_valid;
-reg  [13:0] main_litedramcore_dfi_p3_address = 14'd0;
-reg  [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
-reg  main_litedramcore_dfi_p3_cas_n = 1'd1;
-reg  main_litedramcore_dfi_p3_cs_n = 1'd1;
-reg  main_litedramcore_dfi_p3_ras_n = 1'd1;
-reg  main_litedramcore_dfi_p3_we_n = 1'd1;
-wire main_litedramcore_dfi_p3_cke;
-wire main_litedramcore_dfi_p3_odt;
-wire main_litedramcore_dfi_p3_reset_n;
-reg  main_litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] main_litedramcore_dfi_p3_wrdata;
-reg  main_litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
-reg  main_litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] main_litedramcore_dfi_p3_rddata;
-wire main_litedramcore_dfi_p3_rddata_valid;
-reg  main_litedramcore_cmd_valid = 1'd0;
-reg  main_litedramcore_cmd_ready = 1'd0;
-reg  main_litedramcore_cmd_last = 1'd0;
-reg  [13:0] main_litedramcore_cmd_payload_a = 14'd0;
-reg  [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
-reg  main_litedramcore_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_cmd_payload_we = 1'd0;
-reg  main_litedramcore_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_cmd_payload_is_write = 1'd0;
-wire main_litedramcore_wants_refresh;
-wire main_litedramcore_wants_zqcs;
-wire main_litedramcore_timer_wait;
-wire main_litedramcore_timer_done0;
-wire [9:0] main_litedramcore_timer_count0;
-wire main_litedramcore_timer_done1;
-reg  [9:0] main_litedramcore_timer_count1 = 10'd781;
-wire main_litedramcore_postponer_req_i;
-reg  main_litedramcore_postponer_req_o = 1'd0;
-reg  main_litedramcore_postponer_count = 1'd0;
-reg  main_litedramcore_sequencer_start0 = 1'd0;
-wire main_litedramcore_sequencer_done0;
-wire main_litedramcore_sequencer_start1;
-reg  main_litedramcore_sequencer_done1 = 1'd0;
-reg  [5:0] main_litedramcore_sequencer_counter = 6'd0;
-reg  main_litedramcore_sequencer_count = 1'd0;
-wire main_litedramcore_zqcs_timer_wait;
-wire main_litedramcore_zqcs_timer_done0;
-wire [26:0] main_litedramcore_zqcs_timer_count0;
-wire main_litedramcore_zqcs_timer_done1;
-reg  [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg  main_litedramcore_zqcs_executer_start = 1'd0;
-reg  main_litedramcore_zqcs_executer_done = 1'd0;
-reg  [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
-wire main_litedramcore_bankmachine0_req_valid;
-wire main_litedramcore_bankmachine0_req_ready;
-wire main_litedramcore_bankmachine0_req_we;
-wire [20:0] main_litedramcore_bankmachine0_req_addr;
-wire main_litedramcore_bankmachine0_req_lock;
-reg  main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine0_refresh_req;
-reg  main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
-reg  main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg  [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine0_row = 14'd0;
-reg  main_litedramcore_bankmachine0_row_opened = 1'd0;
-wire main_litedramcore_bankmachine0_row_hit;
-reg  main_litedramcore_bankmachine0_row_open = 1'd0;
-reg  main_litedramcore_bankmachine0_row_close = 1'd0;
-reg  main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine1_req_valid;
-wire main_litedramcore_bankmachine1_req_ready;
-wire main_litedramcore_bankmachine1_req_we;
-wire [20:0] main_litedramcore_bankmachine1_req_addr;
-wire main_litedramcore_bankmachine1_req_lock;
-reg  main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine1_refresh_req;
-reg  main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
-reg  main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg  [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine1_row = 14'd0;
-reg  main_litedramcore_bankmachine1_row_opened = 1'd0;
-wire main_litedramcore_bankmachine1_row_hit;
-reg  main_litedramcore_bankmachine1_row_open = 1'd0;
-reg  main_litedramcore_bankmachine1_row_close = 1'd0;
-reg  main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine2_req_valid;
-wire main_litedramcore_bankmachine2_req_ready;
-wire main_litedramcore_bankmachine2_req_we;
-wire [20:0] main_litedramcore_bankmachine2_req_addr;
-wire main_litedramcore_bankmachine2_req_lock;
-reg  main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine2_refresh_req;
-reg  main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
-reg  main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg  [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine2_row = 14'd0;
-reg  main_litedramcore_bankmachine2_row_opened = 1'd0;
-wire main_litedramcore_bankmachine2_row_hit;
-reg  main_litedramcore_bankmachine2_row_open = 1'd0;
-reg  main_litedramcore_bankmachine2_row_close = 1'd0;
-reg  main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine3_req_valid;
-wire main_litedramcore_bankmachine3_req_ready;
-wire main_litedramcore_bankmachine3_req_we;
-wire [20:0] main_litedramcore_bankmachine3_req_addr;
-wire main_litedramcore_bankmachine3_req_lock;
-reg  main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine3_refresh_req;
-reg  main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
-reg  main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg  [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine3_row = 14'd0;
-reg  main_litedramcore_bankmachine3_row_opened = 1'd0;
-wire main_litedramcore_bankmachine3_row_hit;
-reg  main_litedramcore_bankmachine3_row_open = 1'd0;
-reg  main_litedramcore_bankmachine3_row_close = 1'd0;
-reg  main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine4_req_valid;
-wire main_litedramcore_bankmachine4_req_ready;
-wire main_litedramcore_bankmachine4_req_we;
-wire [20:0] main_litedramcore_bankmachine4_req_addr;
-wire main_litedramcore_bankmachine4_req_lock;
-reg  main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine4_refresh_req;
-reg  main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
-reg  main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg  [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine4_row = 14'd0;
-reg  main_litedramcore_bankmachine4_row_opened = 1'd0;
-wire main_litedramcore_bankmachine4_row_hit;
-reg  main_litedramcore_bankmachine4_row_open = 1'd0;
-reg  main_litedramcore_bankmachine4_row_close = 1'd0;
-reg  main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine5_req_valid;
-wire main_litedramcore_bankmachine5_req_ready;
-wire main_litedramcore_bankmachine5_req_we;
-wire [20:0] main_litedramcore_bankmachine5_req_addr;
-wire main_litedramcore_bankmachine5_req_lock;
-reg  main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine5_refresh_req;
-reg  main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
-reg  main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg  [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine5_row = 14'd0;
-reg  main_litedramcore_bankmachine5_row_opened = 1'd0;
-wire main_litedramcore_bankmachine5_row_hit;
-reg  main_litedramcore_bankmachine5_row_open = 1'd0;
-reg  main_litedramcore_bankmachine5_row_close = 1'd0;
-reg  main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine6_req_valid;
-wire main_litedramcore_bankmachine6_req_ready;
-wire main_litedramcore_bankmachine6_req_we;
-wire [20:0] main_litedramcore_bankmachine6_req_addr;
-wire main_litedramcore_bankmachine6_req_lock;
-reg  main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine6_refresh_req;
-reg  main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
-reg  main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg  [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine6_row = 14'd0;
-reg  main_litedramcore_bankmachine6_row_opened = 1'd0;
-wire main_litedramcore_bankmachine6_row_hit;
-reg  main_litedramcore_bankmachine6_row_open = 1'd0;
-reg  main_litedramcore_bankmachine6_row_close = 1'd0;
-reg  main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
-wire main_litedramcore_bankmachine7_req_valid;
-wire main_litedramcore_bankmachine7_req_ready;
-wire main_litedramcore_bankmachine7_req_we;
-wire [20:0] main_litedramcore_bankmachine7_req_addr;
-wire main_litedramcore_bankmachine7_req_lock;
-reg  main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg  main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire main_litedramcore_bankmachine7_refresh_req;
-reg  main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg  [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
-reg  main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg  main_litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg  [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg  [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg  main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg  [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg  [13:0] main_litedramcore_bankmachine7_row = 14'd0;
-reg  main_litedramcore_bankmachine7_row_opened = 1'd0;
-wire main_litedramcore_bankmachine7_row_hit;
-reg  main_litedramcore_bankmachine7_row_open = 1'd0;
-reg  main_litedramcore_bankmachine7_row_close = 1'd0;
-reg  main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire main_litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
-wire main_litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg  [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
-wire main_litedramcore_ras_allowed;
-wire main_litedramcore_cas_allowed;
-wire [1:0] main_litedramcore_rdcmdphase;
-wire [1:0] main_litedramcore_wrcmdphase;
-reg  main_litedramcore_choose_cmd_want_reads = 1'd0;
-reg  main_litedramcore_choose_cmd_want_writes = 1'd0;
-reg  main_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg  main_litedramcore_choose_cmd_want_activates = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_valid;
-reg  main_litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
-reg  main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire main_litedramcore_choose_cmd_cmd_payload_is_read;
-wire main_litedramcore_choose_cmd_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_cmd_request;
-reg  [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
-wire main_litedramcore_choose_cmd_ce;
-reg  main_litedramcore_choose_req_want_reads = 1'd0;
-reg  main_litedramcore_choose_req_want_writes = 1'd0;
-reg  main_litedramcore_choose_req_want_cmds = 1'd0;
-reg  main_litedramcore_choose_req_want_activates = 1'd0;
-wire main_litedramcore_choose_req_cmd_valid;
-reg  main_litedramcore_choose_req_cmd_ready = 1'd0;
-wire [13:0] main_litedramcore_choose_req_cmd_payload_a;
-wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
-reg  main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg  main_litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire main_litedramcore_choose_req_cmd_payload_is_cmd;
-wire main_litedramcore_choose_req_cmd_payload_is_read;
-wire main_litedramcore_choose_req_cmd_payload_is_write;
-reg  [7:0] main_litedramcore_choose_req_valids = 8'd0;
-wire [7:0] main_litedramcore_choose_req_request;
-reg  [2:0] main_litedramcore_choose_req_grant = 3'd0;
-wire main_litedramcore_choose_req_ce;
-reg  [13:0] main_litedramcore_nop_a = 14'd0;
-reg  [2:0] main_litedramcore_nop_ba = 3'd0;
-reg  [1:0] main_litedramcore_steerer_sel0 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel1 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel2 = 2'd0;
-reg  [1:0] main_litedramcore_steerer_sel3 = 2'd0;
-reg  main_litedramcore_steerer0 = 1'd1;
-reg  main_litedramcore_steerer1 = 1'd1;
-reg  main_litedramcore_steerer2 = 1'd1;
-reg  main_litedramcore_steerer3 = 1'd1;
-reg  main_litedramcore_steerer4 = 1'd1;
-reg  main_litedramcore_steerer5 = 1'd1;
-reg  main_litedramcore_steerer6 = 1'd1;
-reg  main_litedramcore_steerer7 = 1'd1;
-wire main_litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_trrdcon_ready = 1'd0;
-reg  main_litedramcore_trrdcon_count = 1'd0;
-wire main_litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] main_litedramcore_tfawcon_count;
-reg  [4:0] main_litedramcore_tfawcon_window = 5'd0;
-wire main_litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_tccdcon_ready = 1'd0;
-reg  main_litedramcore_tccdcon_count = 1'd0;
-wire main_litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg  main_litedramcore_twtrcon_ready = 1'd0;
-reg  [2:0] main_litedramcore_twtrcon_count = 3'd0;
-wire main_litedramcore_read_available;
-wire main_litedramcore_write_available;
-reg  main_litedramcore_en0 = 1'd0;
-wire main_litedramcore_max_time0;
-reg  [4:0] main_litedramcore_time0 = 5'd0;
-reg  main_litedramcore_en1 = 1'd0;
-wire main_litedramcore_max_time1;
-reg  [3:0] main_litedramcore_time1 = 4'd0;
-wire main_litedramcore_go_to_refresh;
-reg  main_init_done_storage = 1'd0;
-reg  main_init_done_re = 1'd0;
-reg  main_init_error_storage = 1'd0;
-reg  main_init_error_re = 1'd0;
-wire [29:0] main_wb_bus_adr;
-wire [31:0] main_wb_bus_dat_w;
-wire [31:0] main_wb_bus_dat_r;
-wire [3:0] main_wb_bus_sel;
-wire main_wb_bus_cyc;
-wire main_wb_bus_stb;
-wire main_wb_bus_ack;
-wire main_wb_bus_we;
-wire [2:0] main_wb_bus_cti;
-wire [1:0] main_wb_bus_bte;
-wire main_wb_bus_err;
-wire main_user_enable;
-wire main_user_port_cmd_valid;
-wire main_user_port_cmd_ready;
-wire main_user_port_cmd_payload_we;
-wire [23:0] main_user_port_cmd_payload_addr;
-wire main_user_port_wdata_valid;
-wire main_user_port_wdata_ready;
-wire [127:0] main_user_port_wdata_payload_data;
-wire [15:0] main_user_port_wdata_payload_we;
-wire main_user_port_rdata_valid;
-wire main_user_port_rdata_ready;
-wire [127:0] main_user_port_rdata_payload_data;
-wire builder_reset0;
-wire builder_reset1;
-wire builder_reset2;
-wire builder_reset3;
-wire builder_reset4;
-wire builder_reset5;
-wire builder_reset6;
-wire builder_reset7;
-wire builder_pll_fb;
-reg  [1:0] builder_refresher_state = 2'd0;
-reg  [1:0] builder_refresher_next_state = 2'd0;
-reg  [3:0] builder_bankmachine0_state = 4'd0;
-reg  [3:0] builder_bankmachine0_next_state = 4'd0;
-reg  [3:0] builder_bankmachine1_state = 4'd0;
-reg  [3:0] builder_bankmachine1_next_state = 4'd0;
-reg  [3:0] builder_bankmachine2_state = 4'd0;
-reg  [3:0] builder_bankmachine2_next_state = 4'd0;
-reg  [3:0] builder_bankmachine3_state = 4'd0;
-reg  [3:0] builder_bankmachine3_next_state = 4'd0;
-reg  [3:0] builder_bankmachine4_state = 4'd0;
-reg  [3:0] builder_bankmachine4_next_state = 4'd0;
-reg  [3:0] builder_bankmachine5_state = 4'd0;
-reg  [3:0] builder_bankmachine5_next_state = 4'd0;
-reg  [3:0] builder_bankmachine6_state = 4'd0;
-reg  [3:0] builder_bankmachine6_next_state = 4'd0;
-reg  [3:0] builder_bankmachine7_state = 4'd0;
-reg  [3:0] builder_bankmachine7_next_state = 4'd0;
-reg  [3:0] builder_multiplexer_state = 4'd0;
-reg  [3:0] builder_multiplexer_next_state = 4'd0;
-wire builder_roundrobin0_request;
-wire builder_roundrobin0_grant;
-wire builder_roundrobin0_ce;
-wire builder_roundrobin1_request;
-wire builder_roundrobin1_grant;
-wire builder_roundrobin1_ce;
-wire builder_roundrobin2_request;
-wire builder_roundrobin2_grant;
-wire builder_roundrobin2_ce;
-wire builder_roundrobin3_request;
-wire builder_roundrobin3_grant;
-wire builder_roundrobin3_ce;
-wire builder_roundrobin4_request;
-wire builder_roundrobin4_grant;
-wire builder_roundrobin4_ce;
-wire builder_roundrobin5_request;
-wire builder_roundrobin5_grant;
-wire builder_roundrobin5_ce;
-wire builder_roundrobin6_request;
-wire builder_roundrobin6_grant;
-wire builder_roundrobin6_ce;
-wire builder_roundrobin7_request;
-wire builder_roundrobin7_grant;
-wire builder_roundrobin7_ce;
-reg  builder_locked0 = 1'd0;
-reg  builder_locked1 = 1'd0;
-reg  builder_locked2 = 1'd0;
-reg  builder_locked3 = 1'd0;
-reg  builder_locked4 = 1'd0;
-reg  builder_locked5 = 1'd0;
-reg  builder_locked6 = 1'd0;
-reg  builder_locked7 = 1'd0;
-reg  builder_new_master_wdata_ready0 = 1'd0;
-reg  builder_new_master_wdata_ready1 = 1'd0;
-reg  builder_new_master_rdata_valid0 = 1'd0;
-reg  builder_new_master_rdata_valid1 = 1'd0;
-reg  builder_new_master_rdata_valid2 = 1'd0;
-reg  builder_new_master_rdata_valid3 = 1'd0;
-reg  builder_new_master_rdata_valid4 = 1'd0;
-reg  builder_new_master_rdata_valid5 = 1'd0;
-reg  builder_new_master_rdata_valid6 = 1'd0;
-reg  builder_new_master_rdata_valid7 = 1'd0;
-reg  builder_new_master_rdata_valid8 = 1'd0;
-reg  [13:0] builder_litedramcore_adr = 14'd0;
-reg  builder_litedramcore_we = 1'd0;
-reg  [31:0] builder_litedramcore_dat_w = 32'd0;
-wire [31:0] builder_litedramcore_dat_r;
-wire [29:0] builder_litedramcore_wishbone_adr;
-wire [31:0] builder_litedramcore_wishbone_dat_w;
-reg  [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] builder_litedramcore_wishbone_sel;
-wire builder_litedramcore_wishbone_cyc;
-wire builder_litedramcore_wishbone_stb;
-reg  builder_litedramcore_wishbone_ack = 1'd0;
-wire builder_litedramcore_wishbone_we;
-wire [2:0] builder_litedramcore_wishbone_cti;
-wire [1:0] builder_litedramcore_wishbone_bte;
-reg  builder_litedramcore_wishbone_err = 1'd0;
-wire [13:0] builder_interface0_bank_bus_adr;
-wire builder_interface0_bank_bus_we;
-wire [31:0] builder_interface0_bank_bus_dat_w;
-reg  [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank0_init_done0_re = 1'd0;
-wire builder_csrbank0_init_done0_r;
-reg  builder_csrbank0_init_done0_we = 1'd0;
-wire builder_csrbank0_init_done0_w;
-reg  builder_csrbank0_init_error0_re = 1'd0;
-wire builder_csrbank0_init_error0_r;
-reg  builder_csrbank0_init_error0_we = 1'd0;
-wire builder_csrbank0_init_error0_w;
-wire builder_csrbank0_sel;
-wire [13:0] builder_interface1_bank_bus_adr;
-wire builder_interface1_bank_bus_we;
-wire [31:0] builder_interface1_bank_bus_dat_w;
-reg  [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank1_rst0_re = 1'd0;
-wire builder_csrbank1_rst0_r;
-reg  builder_csrbank1_rst0_we = 1'd0;
-wire builder_csrbank1_rst0_w;
-reg  builder_csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
-reg  builder_csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
-reg  builder_csrbank1_wlevel_en0_re = 1'd0;
-wire builder_csrbank1_wlevel_en0_r;
-reg  builder_csrbank1_wlevel_en0_we = 1'd0;
-wire builder_csrbank1_wlevel_en0_w;
-reg  builder_csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_r;
-reg  builder_csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] builder_csrbank1_dly_sel0_w;
-reg  builder_csrbank1_rdphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_r;
-reg  builder_csrbank1_rdphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_rdphase0_w;
-reg  builder_csrbank1_wrphase0_re = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_r;
-reg  builder_csrbank1_wrphase0_we = 1'd0;
-wire [1:0] builder_csrbank1_wrphase0_w;
-wire builder_csrbank1_sel;
-wire [13:0] builder_interface2_bank_bus_adr;
-wire builder_interface2_bank_bus_we;
-wire [31:0] builder_interface2_bank_bus_dat_w;
-reg  [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
-reg  builder_csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_r;
-reg  builder_csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] builder_csrbank2_dfii_control0_w;
-reg  builder_csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
-reg  builder_csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
-reg  builder_csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi0_address0_r;
-reg  builder_csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi0_address0_w;
-reg  builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
-reg  builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
-reg  builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
-reg  builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
-reg  builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_r;
-reg  builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi0_rddata_w;
-reg  builder_csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
-reg  builder_csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
-reg  builder_csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi1_address0_r;
-reg  builder_csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi1_address0_w;
-reg  builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
-reg  builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
-reg  builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
-reg  builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
-reg  builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_r;
-reg  builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi1_rddata_w;
-reg  builder_csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
-reg  builder_csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
-reg  builder_csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi2_address0_r;
-reg  builder_csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi2_address0_w;
-reg  builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
-reg  builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
-reg  builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
-reg  builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
-reg  builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_r;
-reg  builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi2_rddata_w;
-reg  builder_csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
-reg  builder_csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
-reg  builder_csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi3_address0_r;
-reg  builder_csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [13:0] builder_csrbank2_dfii_pi3_address0_w;
-reg  builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
-reg  builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
-reg  builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
-reg  builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
-reg  builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_r;
-reg  builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] builder_csrbank2_dfii_pi3_rddata_w;
-wire builder_csrbank2_sel;
-wire [13:0] builder_csr_interconnect_adr;
-wire builder_csr_interconnect_we;
-wire [31:0] builder_csr_interconnect_dat_w;
-wire [31:0] builder_csr_interconnect_dat_r;
-reg  [1:0] builder_state = 2'd0;
-reg  [1:0] builder_next_state = 2'd0;
-reg  [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0;
-reg  builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg  [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
-reg  builder_litedramcore_adr_next_value_ce1 = 1'd0;
-reg  builder_litedramcore_we_next_value2 = 1'd0;
-reg  builder_litedramcore_we_next_value_ce2 = 1'd0;
-reg  builder_rhs_array_muxed0 = 1'd0;
-reg  [13:0] builder_rhs_array_muxed1 = 14'd0;
-reg  [2:0] builder_rhs_array_muxed2 = 3'd0;
-reg  builder_rhs_array_muxed3 = 1'd0;
-reg  builder_rhs_array_muxed4 = 1'd0;
-reg  builder_rhs_array_muxed5 = 1'd0;
-reg  builder_t_array_muxed0 = 1'd0;
-reg  builder_t_array_muxed1 = 1'd0;
-reg  builder_t_array_muxed2 = 1'd0;
-reg  builder_rhs_array_muxed6 = 1'd0;
-reg  [13:0] builder_rhs_array_muxed7 = 14'd0;
-reg  [2:0] builder_rhs_array_muxed8 = 3'd0;
-reg  builder_rhs_array_muxed9 = 1'd0;
-reg  builder_rhs_array_muxed10 = 1'd0;
-reg  builder_rhs_array_muxed11 = 1'd0;
-reg  builder_t_array_muxed3 = 1'd0;
-reg  builder_t_array_muxed4 = 1'd0;
-reg  builder_t_array_muxed5 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed12 = 21'd0;
-reg  builder_rhs_array_muxed13 = 1'd0;
-reg  builder_rhs_array_muxed14 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed15 = 21'd0;
-reg  builder_rhs_array_muxed16 = 1'd0;
-reg  builder_rhs_array_muxed17 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed18 = 21'd0;
-reg  builder_rhs_array_muxed19 = 1'd0;
-reg  builder_rhs_array_muxed20 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed21 = 21'd0;
-reg  builder_rhs_array_muxed22 = 1'd0;
-reg  builder_rhs_array_muxed23 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed24 = 21'd0;
-reg  builder_rhs_array_muxed25 = 1'd0;
-reg  builder_rhs_array_muxed26 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed27 = 21'd0;
-reg  builder_rhs_array_muxed28 = 1'd0;
-reg  builder_rhs_array_muxed29 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed30 = 21'd0;
-reg  builder_rhs_array_muxed31 = 1'd0;
-reg  builder_rhs_array_muxed32 = 1'd0;
-reg  [20:0] builder_rhs_array_muxed33 = 21'd0;
-reg  builder_rhs_array_muxed34 = 1'd0;
-reg  builder_rhs_array_muxed35 = 1'd0;
-reg  [2:0] builder_array_muxed0 = 3'd0;
-reg  [13:0] builder_array_muxed1 = 14'd0;
-reg  builder_array_muxed2 = 1'd0;
-reg  builder_array_muxed3 = 1'd0;
-reg  builder_array_muxed4 = 1'd0;
-reg  builder_array_muxed5 = 1'd0;
-reg  builder_array_muxed6 = 1'd0;
-reg  [2:0] builder_array_muxed7 = 3'd0;
-reg  [13:0] builder_array_muxed8 = 14'd0;
-reg  builder_array_muxed9 = 1'd0;
-reg  builder_array_muxed10 = 1'd0;
-reg  builder_array_muxed11 = 1'd0;
-reg  builder_array_muxed12 = 1'd0;
-reg  builder_array_muxed13 = 1'd0;
-reg  [2:0] builder_array_muxed14 = 3'd0;
-reg  [13:0] builder_array_muxed15 = 14'd0;
-reg  builder_array_muxed16 = 1'd0;
-reg  builder_array_muxed17 = 1'd0;
-reg  builder_array_muxed18 = 1'd0;
-reg  builder_array_muxed19 = 1'd0;
-reg  builder_array_muxed20 = 1'd0;
-reg  [2:0] builder_array_muxed21 = 3'd0;
-reg  [13:0] builder_array_muxed22 = 14'd0;
-reg  builder_array_muxed23 = 1'd0;
-reg  builder_array_muxed24 = 1'd0;
-reg  builder_array_muxed25 = 1'd0;
-reg  builder_array_muxed26 = 1'd0;
-reg  builder_array_muxed27 = 1'd0;
-wire builder_xilinxasyncresetsynchronizerimpl0;
-wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl1;
-wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2;
-wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl2_expr;
-wire builder_xilinxasyncresetsynchronizerimpl3;
-wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire reset;
+reg  power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg  [3:0] reset_counter = 4'd15;
+reg  ic_reset = 1'd1;
+reg  a7ddrphy_rst_storage = 1'd0;
+reg  a7ddrphy_rst_re = 1'd0;
+reg  [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg  a7ddrphy_dly_sel_re = 1'd0;
+reg  [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg  a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg  a7ddrphy_wlevel_en_storage = 1'd0;
+reg  a7ddrphy_wlevel_en_re = 1'd0;
+reg  a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg  a7ddrphy_wlevel_strobe_we = 1'd0;
+reg  a7ddrphy_wlevel_strobe_w = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg  a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg  a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg  a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg  a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg  a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg  a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg  a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg  a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg  [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg  a7ddrphy_rdphase_re = 1'd0;
+reg  [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg  a7ddrphy_wrphase_re = 1'd0;
+wire [13:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg  [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg  a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_dqspattern0 = 1'd0;
+reg  a7ddrphy_dqspattern1 = 1'd0;
+reg  [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg  [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg  [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg  [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg  [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg  [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg  [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg  [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg  [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg  [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg  [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg  [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg  [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg  [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg  [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg  [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg  [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg  [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg  [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg  [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg  [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg  [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg  [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg  [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg  [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg  [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg  [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg  [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg  [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg  [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg  [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg  [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg  [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg  [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg  [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg  [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg  [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg  [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg  [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg  [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg  a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg  a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [13:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg  [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg  litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg  [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg  litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg  [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg  litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg  [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg  litedramcore_slave_p3_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_master_p0_address = 14'd0;
+reg  [2:0] litedramcore_master_p0_bank = 3'd0;
+reg  litedramcore_master_p0_cas_n = 1'd1;
+reg  litedramcore_master_p0_cs_n = 1'd1;
+reg  litedramcore_master_p0_ras_n = 1'd1;
+reg  litedramcore_master_p0_we_n = 1'd1;
+reg  litedramcore_master_p0_cke = 1'd0;
+reg  litedramcore_master_p0_odt = 1'd0;
+reg  litedramcore_master_p0_reset_n = 1'd0;
+reg  litedramcore_master_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg  litedramcore_master_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg  litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg  [13:0] litedramcore_master_p1_address = 14'd0;
+reg  [2:0] litedramcore_master_p1_bank = 3'd0;
+reg  litedramcore_master_p1_cas_n = 1'd1;
+reg  litedramcore_master_p1_cs_n = 1'd1;
+reg  litedramcore_master_p1_ras_n = 1'd1;
+reg  litedramcore_master_p1_we_n = 1'd1;
+reg  litedramcore_master_p1_cke = 1'd0;
+reg  litedramcore_master_p1_odt = 1'd0;
+reg  litedramcore_master_p1_reset_n = 1'd0;
+reg  litedramcore_master_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg  litedramcore_master_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg  litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg  [13:0] litedramcore_master_p2_address = 14'd0;
+reg  [2:0] litedramcore_master_p2_bank = 3'd0;
+reg  litedramcore_master_p2_cas_n = 1'd1;
+reg  litedramcore_master_p2_cs_n = 1'd1;
+reg  litedramcore_master_p2_ras_n = 1'd1;
+reg  litedramcore_master_p2_we_n = 1'd1;
+reg  litedramcore_master_p2_cke = 1'd0;
+reg  litedramcore_master_p2_odt = 1'd0;
+reg  litedramcore_master_p2_reset_n = 1'd0;
+reg  litedramcore_master_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg  litedramcore_master_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg  litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg  [13:0] litedramcore_master_p3_address = 14'd0;
+reg  [2:0] litedramcore_master_p3_bank = 3'd0;
+reg  litedramcore_master_p3_cas_n = 1'd1;
+reg  litedramcore_master_p3_cs_n = 1'd1;
+reg  litedramcore_master_p3_ras_n = 1'd1;
+reg  litedramcore_master_p3_we_n = 1'd1;
+reg  litedramcore_master_p3_cke = 1'd0;
+reg  litedramcore_master_p3_odt = 1'd0;
+reg  litedramcore_master_p3_reset_n = 1'd0;
+reg  litedramcore_master_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg  litedramcore_master_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg  litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [13:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg  litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg  litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg  litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg  litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg  litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg  litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg  litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg  litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg  [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg  litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg  litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p0_cke = 1'd0;
+reg  litedramcore_ext_dfi_p0_odt = 1'd0;
+reg  litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg  litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p1_cke = 1'd0;
+reg  litedramcore_ext_dfi_p1_odt = 1'd0;
+reg  litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg  litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p2_cke = 1'd0;
+reg  litedramcore_ext_dfi_p2_odt = 1'd0;
+reg  litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg  [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
+reg  [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg  litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg  litedramcore_ext_dfi_p3_cke = 1'd0;
+reg  litedramcore_ext_dfi_p3_odt = 1'd0;
+reg  litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg  litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg  [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg  litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg  [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg  litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg  [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg  litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg  litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg  [3:0] litedramcore_storage = 4'd1;
+reg  litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg  litedramcore_phaseinjector0_command_re = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg  litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
+reg  litedramcore_phaseinjector0_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg  litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg  litedramcore_phaseinjector1_command_re = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg  litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
+reg  litedramcore_phaseinjector1_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg  litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg  litedramcore_phaseinjector2_command_re = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg  litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
+reg  litedramcore_phaseinjector2_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg  litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg  [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg  litedramcore_phaseinjector3_command_re = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg  litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg  litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg  [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
+reg  litedramcore_phaseinjector3_address_re = 1'd0;
+reg  [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg  litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg  litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg  [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg  litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [20:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [20:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [20:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [20:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [20:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [20:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [20:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [20:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg  [127:0] litedramcore_interface_wdata = 128'd0;
+reg  [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg  [13:0] litedramcore_dfi_p0_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg  litedramcore_dfi_p0_cas_n = 1'd1;
+reg  litedramcore_dfi_p0_cs_n = 1'd1;
+reg  litedramcore_dfi_p0_ras_n = 1'd1;
+reg  litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg  litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg  litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg  litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg  [13:0] litedramcore_dfi_p1_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg  litedramcore_dfi_p1_cas_n = 1'd1;
+reg  litedramcore_dfi_p1_cs_n = 1'd1;
+reg  litedramcore_dfi_p1_ras_n = 1'd1;
+reg  litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg  litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg  litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg  litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg  [13:0] litedramcore_dfi_p2_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg  litedramcore_dfi_p2_cas_n = 1'd1;
+reg  litedramcore_dfi_p2_cs_n = 1'd1;
+reg  litedramcore_dfi_p2_ras_n = 1'd1;
+reg  litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg  litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg  litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg  litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg  [13:0] litedramcore_dfi_p3_address = 14'd0;
+reg  [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg  litedramcore_dfi_p3_cas_n = 1'd1;
+reg  litedramcore_dfi_p3_cs_n = 1'd1;
+reg  litedramcore_dfi_p3_ras_n = 1'd1;
+reg  litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg  litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg  litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg  litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg  litedramcore_cmd_valid = 1'd0;
+reg  litedramcore_cmd_ready = 1'd0;
+reg  litedramcore_cmd_last = 1'd0;
+reg  [13:0] litedramcore_cmd_payload_a = 14'd0;
+reg  [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg  litedramcore_cmd_payload_cas = 1'd0;
+reg  litedramcore_cmd_payload_ras = 1'd0;
+reg  litedramcore_cmd_payload_we = 1'd0;
+reg  litedramcore_cmd_payload_is_read = 1'd0;
+reg  litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg  [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg  litedramcore_postponer_req_o = 1'd0;
+reg  litedramcore_postponer_count = 1'd0;
+reg  litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg  litedramcore_sequencer_done1 = 1'd0;
+reg  [5:0] litedramcore_sequencer_counter = 6'd0;
+reg  litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg  [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg  litedramcore_zqcs_executer_start = 1'd0;
+reg  litedramcore_zqcs_executer_done = 1'd0;
+reg  [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [20:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg  litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg  litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg  litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg  [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine0_row = 14'd0;
+reg  litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg  litedramcore_bankmachine0_row_open = 1'd0;
+reg  litedramcore_bankmachine0_row_close = 1'd0;
+reg  litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [20:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg  litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg  litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg  litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg  [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine1_row = 14'd0;
+reg  litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg  litedramcore_bankmachine1_row_open = 1'd0;
+reg  litedramcore_bankmachine1_row_close = 1'd0;
+reg  litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [20:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg  litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg  litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg  litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg  [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine2_row = 14'd0;
+reg  litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg  litedramcore_bankmachine2_row_open = 1'd0;
+reg  litedramcore_bankmachine2_row_close = 1'd0;
+reg  litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [20:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg  litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg  litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg  litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg  [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine3_row = 14'd0;
+reg  litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg  litedramcore_bankmachine3_row_open = 1'd0;
+reg  litedramcore_bankmachine3_row_close = 1'd0;
+reg  litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [20:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg  litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg  litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg  litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg  [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine4_row = 14'd0;
+reg  litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg  litedramcore_bankmachine4_row_open = 1'd0;
+reg  litedramcore_bankmachine4_row_close = 1'd0;
+reg  litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [20:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg  litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg  litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg  litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg  [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine5_row = 14'd0;
+reg  litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg  litedramcore_bankmachine5_row_open = 1'd0;
+reg  litedramcore_bankmachine5_row_close = 1'd0;
+reg  litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [20:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg  litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg  litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg  litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg  [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine6_row = 14'd0;
+reg  litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg  litedramcore_bankmachine6_row_open = 1'd0;
+reg  litedramcore_bankmachine6_row_close = 1'd0;
+reg  litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [20:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg  litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg  litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg  litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg  litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg  litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg  [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg  litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg  litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg  litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg  [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg  litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg  litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg  litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg  [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg  [13:0] litedramcore_bankmachine7_row = 14'd0;
+reg  litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg  litedramcore_bankmachine7_row_open = 1'd0;
+reg  litedramcore_bankmachine7_row_close = 1'd0;
+reg  litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg  litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg  [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg  litedramcore_choose_cmd_want_reads = 1'd0;
+reg  litedramcore_choose_cmd_want_writes = 1'd0;
+reg  litedramcore_choose_cmd_want_cmds = 1'd0;
+reg  litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg  litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg  litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg  [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg  litedramcore_choose_req_want_reads = 1'd0;
+reg  litedramcore_choose_req_want_writes = 1'd0;
+reg  litedramcore_choose_req_want_cmds = 1'd0;
+reg  litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg  litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg  litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg  litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg  [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg  [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg  [13:0] litedramcore_nop_a = 14'd0;
+reg  [2:0] litedramcore_nop_ba = 3'd0;
+reg  [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg  [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg  litedramcore_steerer0 = 1'd1;
+reg  litedramcore_steerer1 = 1'd1;
+reg  litedramcore_steerer2 = 1'd1;
+reg  litedramcore_steerer3 = 1'd1;
+reg  litedramcore_steerer4 = 1'd1;
+reg  litedramcore_steerer5 = 1'd1;
+reg  litedramcore_steerer6 = 1'd1;
+reg  litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_trrdcon_ready = 1'd0;
+reg  litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg  [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_tccdcon_ready = 1'd0;
+reg  litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg  litedramcore_twtrcon_ready = 1'd0;
+reg  [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg  litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg  [4:0] litedramcore_time0 = 5'd0;
+reg  litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg  [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg  init_done_storage = 1'd0;
+reg  init_done_re = 1'd0;
+reg  init_error_storage = 1'd0;
+reg  init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [23:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg  [13:0] litedramcore_adr = 14'd0;
+reg  litedramcore_we = 1'd0;
+reg  [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg  [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg  litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg  litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg  [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg  csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg  csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg  csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg  csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg  [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg  csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg  csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg  csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg  csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg  csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg  csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg  csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg  csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg  csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg  csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg  csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg  csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg  [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg  csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg  csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg  csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg  csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg  csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_r;
+reg  csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_w;
+reg  csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg  csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg  csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg  csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg  csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg  csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg  csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg  csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg  csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_r;
+reg  csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_w;
+reg  csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg  csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg  csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg  csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg  csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg  csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg  csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg  csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg  csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_r;
+reg  csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_w;
+reg  csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg  csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg  csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg  csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg  csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg  csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg  csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg  csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg  csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_r;
+reg  csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_w;
+reg  csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg  csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg  csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg  csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg  csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg  csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg  [1:0] litedramcore_refresher_state = 2'd0;
+reg  [1:0] litedramcore_refresher_next_state = 2'd0;
+reg  [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg  [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_state = 4'd0;
+reg  [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg  litedramcore_locked0 = 1'd0;
+reg  litedramcore_locked1 = 1'd0;
+reg  litedramcore_locked2 = 1'd0;
+reg  litedramcore_locked3 = 1'd0;
+reg  litedramcore_locked4 = 1'd0;
+reg  litedramcore_locked5 = 1'd0;
+reg  litedramcore_locked6 = 1'd0;
+reg  litedramcore_locked7 = 1'd0;
+reg  litedramcore_new_master_wdata_ready0 = 1'd0;
+reg  litedramcore_new_master_wdata_ready1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid0 = 1'd0;
+reg  litedramcore_new_master_rdata_valid1 = 1'd0;
+reg  litedramcore_new_master_rdata_valid2 = 1'd0;
+reg  litedramcore_new_master_rdata_valid3 = 1'd0;
+reg  litedramcore_new_master_rdata_valid4 = 1'd0;
+reg  litedramcore_new_master_rdata_valid5 = 1'd0;
+reg  litedramcore_new_master_rdata_valid6 = 1'd0;
+reg  litedramcore_new_master_rdata_valid7 = 1'd0;
+reg  litedramcore_new_master_rdata_valid8 = 1'd0;
+reg  [1:0] litedramcore_state = 2'd0;
+reg  [1:0] litedramcore_next_state = 2'd0;
+reg  [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg  litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg  [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg  litedramcore_adr_next_value_ce1 = 1'd0;
+reg  litedramcore_we_next_value2 = 1'd0;
+reg  litedramcore_we_next_value_ce2 = 1'd0;
+reg  rhs_array_muxed0 = 1'd0;
+reg  [13:0] rhs_array_muxed1 = 14'd0;
+reg  [2:0] rhs_array_muxed2 = 3'd0;
+reg  rhs_array_muxed3 = 1'd0;
+reg  rhs_array_muxed4 = 1'd0;
+reg  rhs_array_muxed5 = 1'd0;
+reg  t_array_muxed0 = 1'd0;
+reg  t_array_muxed1 = 1'd0;
+reg  t_array_muxed2 = 1'd0;
+reg  rhs_array_muxed6 = 1'd0;
+reg  [13:0] rhs_array_muxed7 = 14'd0;
+reg  [2:0] rhs_array_muxed8 = 3'd0;
+reg  rhs_array_muxed9 = 1'd0;
+reg  rhs_array_muxed10 = 1'd0;
+reg  rhs_array_muxed11 = 1'd0;
+reg  t_array_muxed3 = 1'd0;
+reg  t_array_muxed4 = 1'd0;
+reg  t_array_muxed5 = 1'd0;
+reg  [20:0] rhs_array_muxed12 = 21'd0;
+reg  rhs_array_muxed13 = 1'd0;
+reg  rhs_array_muxed14 = 1'd0;
+reg  [20:0] rhs_array_muxed15 = 21'd0;
+reg  rhs_array_muxed16 = 1'd0;
+reg  rhs_array_muxed17 = 1'd0;
+reg  [20:0] rhs_array_muxed18 = 21'd0;
+reg  rhs_array_muxed19 = 1'd0;
+reg  rhs_array_muxed20 = 1'd0;
+reg  [20:0] rhs_array_muxed21 = 21'd0;
+reg  rhs_array_muxed22 = 1'd0;
+reg  rhs_array_muxed23 = 1'd0;
+reg  [20:0] rhs_array_muxed24 = 21'd0;
+reg  rhs_array_muxed25 = 1'd0;
+reg  rhs_array_muxed26 = 1'd0;
+reg  [20:0] rhs_array_muxed27 = 21'd0;
+reg  rhs_array_muxed28 = 1'd0;
+reg  rhs_array_muxed29 = 1'd0;
+reg  [20:0] rhs_array_muxed30 = 21'd0;
+reg  rhs_array_muxed31 = 1'd0;
+reg  rhs_array_muxed32 = 1'd0;
+reg  [20:0] rhs_array_muxed33 = 21'd0;
+reg  rhs_array_muxed34 = 1'd0;
+reg  rhs_array_muxed35 = 1'd0;
+reg  [2:0] array_muxed0 = 3'd0;
+reg  [13:0] array_muxed1 = 14'd0;
+reg  array_muxed2 = 1'd0;
+reg  array_muxed3 = 1'd0;
+reg  array_muxed4 = 1'd0;
+reg  array_muxed5 = 1'd0;
+reg  array_muxed6 = 1'd0;
+reg  [2:0] array_muxed7 = 3'd0;
+reg  [13:0] array_muxed8 = 14'd0;
+reg  array_muxed9 = 1'd0;
+reg  array_muxed10 = 1'd0;
+reg  array_muxed11 = 1'd0;
+reg  array_muxed12 = 1'd0;
+reg  array_muxed13 = 1'd0;
+reg  [2:0] array_muxed14 = 3'd0;
+reg  [13:0] array_muxed15 = 14'd0;
+reg  array_muxed16 = 1'd0;
+reg  array_muxed17 = 1'd0;
+reg  array_muxed18 = 1'd0;
+reg  array_muxed19 = 1'd0;
+reg  array_muxed20 = 1'd0;
+reg  [2:0] array_muxed21 = 3'd0;
+reg  [13:0] array_muxed22 = 14'd0;
+reg  array_muxed23 = 1'd0;
+reg  array_muxed24 = 1'd0;
+reg  array_muxed25 = 1'd0;
+reg  array_muxed26 = 1'd0;
+reg  array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = main_init_done_storage;
-assign init_error = main_init_error_storage;
-assign main_wb_bus_adr = wb_ctrl_adr;
-assign main_wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = main_wb_bus_dat_r;
-assign main_wb_bus_sel = wb_ctrl_sel;
-assign main_wb_bus_cyc = wb_ctrl_cyc;
-assign main_wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = main_wb_bus_ack;
-assign main_wb_bus_we = wb_ctrl_we;
-assign main_wb_bus_cti = wb_ctrl_cti;
-assign main_wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = main_wb_bus_err;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign main_user_enable = 1'd1;
-assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
-assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
-assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
-assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
-assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
-assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
-assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
-assign main_reset = (rst | main_rst);
-assign pll_locked = main_locked;
-assign main_clkin = clk;
-assign iodelay_clk = main_clkout_buf0;
-assign sys_clk = main_clkout_buf1;
-assign sys4x_clk = main_clkout_buf2;
-assign sys4x_dqs_clk = main_clkout_buf3;
-assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
-assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
-always @(*) begin
-	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
-	main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
-	main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
-	main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
-	main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
-	main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
-	main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
-	main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
-	main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
-	main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
-	main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
-	main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
-	main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
-	main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
-	main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
-	main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
-	main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
-	main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
-	main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
-	main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
-	main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
-	main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
-	main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
-	main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
-	main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
-	main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
-	main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
-	main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
-	main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
-	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
-	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
-	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
-	main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
-	main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
-	main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
-	main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
-	main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
-	main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
-	main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
-	main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
-	main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
-	main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
-	main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
-	main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
-	main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
-	main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
-	main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
-	main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
-	main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
-	main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
-	main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
-	main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
-	main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
-	main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
-	main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
-	main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
-	main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
-	main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
-	main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
-	main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
-	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
-	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
-	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
-	main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
-	main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
-	main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
-	main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
-	main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
-	main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
-	main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
-	main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
-	main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
-	main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
-	main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
-	main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
-	main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
-	main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
-	main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
-	main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
-	main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
-	main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
-	main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
-	main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
-	main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
-	main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
-	main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
-	main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
-	main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
-	main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
-	main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
-	main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
-	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
-	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
-	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
-	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
-	main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
-	main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
-	main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
-	main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
-	main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
-	main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
-	main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
-	main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
-	main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
-	main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
-	main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
-	main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
-	main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
-	main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
-	main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
-	main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
-	main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
-	main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
-	main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
-	main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
-	main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
-	main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
-	main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
-	main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
-	main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
-	main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
-	main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
-	main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
-	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
-	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
-	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
-end
-assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
-assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-	main_a7ddrphy_dqs_oe <= 1'd0;
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqs_oe <= 1'd1;
-	end else begin
-		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
-	end
-end
-assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
-always @(*) begin
-	main_a7ddrphy_dqspattern_o0 <= 8'd0;
-	main_a7ddrphy_dqspattern_o0 <= 7'd85;
-	if (main_a7ddrphy_dqspattern0) begin
-		main_a7ddrphy_dqspattern_o0 <= 5'd21;
-	end
-	if (main_a7ddrphy_dqspattern1) begin
-		main_a7ddrphy_dqspattern_o0 <= 7'd84;
-	end
-	if (main_a7ddrphy_wlevel_en_storage) begin
-		main_a7ddrphy_dqspattern_o0 <= 1'd0;
-		if (main_a7ddrphy_wlevel_strobe_re) begin
-			main_a7ddrphy_dqspattern_o0 <= 1'd1;
-		end
-	end
-end
-always @(*) begin
-	main_a7ddrphy_bitslip00 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value0)
+assign user_enable = 1'd1;
+assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
+assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
+assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
+assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign reset = (rst | rst_1);
+assign pll_locked = locked;
+assign clkin = clk;
+assign iodelay_clk = clkout_buf0;
+assign sys_clk = clkout_buf1;
+assign sys4x_clk = clkout_buf2;
+assign sys4x_dqs_clk = clkout_buf3;
+assign ddram_ba = a7ddrphy_pads_ba;
+assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
+assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
+always @(*) begin
+	a7ddrphy_dfi_p0_rddata <= 32'd0;
+	a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+	a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+	a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+	a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+	a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+	a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+	a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+	a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+	a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+	a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+	a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+	a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+	a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+	a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+	a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+	a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+	a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+	a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+	a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+	a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+	a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+	a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+	a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+	a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+	a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+	a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+	a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+	a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+	a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+	a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+	a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+	a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+	a7ddrphy_dfi_p1_rddata <= 32'd0;
+	a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+	a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+	a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+	a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+	a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+	a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+	a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+	a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+	a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+	a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+	a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+	a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+	a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+	a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+	a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+	a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+	a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+	a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+	a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+	a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+	a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+	a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+	a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+	a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+	a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+	a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+	a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+	a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+	a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+	a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+	a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+	a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+	a7ddrphy_dfi_p2_rddata <= 32'd0;
+	a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+	a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+	a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+	a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+	a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+	a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+	a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+	a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+	a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+	a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+	a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+	a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+	a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+	a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+	a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+	a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+	a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+	a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+	a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+	a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+	a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+	a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+	a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+	a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+	a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+	a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+	a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+	a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+	a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+	a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+	a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+	a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+	a7ddrphy_dfi_p3_rddata <= 32'd0;
+	a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+	a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+	a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+	a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+	a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+	a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+	a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+	a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+	a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+	a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+	a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+	a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+	a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+	a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+	a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+	a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+	a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+	a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+	a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+	a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+	a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+	a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+	a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+	a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+	a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+	a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+	a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+	a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+	a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+	a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+	a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+	a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+end
+assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
+assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+	a7ddrphy_dqs_oe <= 1'd0;
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqs_oe <= 1'd1;
+	end else begin
+		a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+	end
+end
+assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+always @(*) begin
+	a7ddrphy_dqspattern_o0 <= 8'd0;
+	a7ddrphy_dqspattern_o0 <= 7'd85;
+	if (a7ddrphy_dqspattern0) begin
+		a7ddrphy_dqspattern_o0 <= 5'd21;
+	end
+	if (a7ddrphy_dqspattern1) begin
+		a7ddrphy_dqspattern_o0 <= 7'd84;
+	end
+	if (a7ddrphy_wlevel_en_storage) begin
+		a7ddrphy_dqspattern_o0 <= 1'd0;
+		if (a7ddrphy_wlevel_strobe_re) begin
+			a7ddrphy_dqspattern_o0 <= 1'd1;
+		end
+	end
+end
+always @(*) begin
+	a7ddrphy_bitslip00 <= 8'd0;
+	case (a7ddrphy_bitslip0_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
+			a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip10 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value0)
+	a7ddrphy_bitslip10 <= 8'd0;
+	case (a7ddrphy_bitslip1_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
+			a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip01 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value1)
+	a7ddrphy_bitslip01 <= 8'd0;
+	case (a7ddrphy_bitslip0_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
+			a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip11 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value1)
+	a7ddrphy_bitslip11 <= 8'd0;
+	case (a7ddrphy_bitslip1_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
+			a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip02 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value2)
+	a7ddrphy_bitslip02 <= 8'd0;
+	case (a7ddrphy_bitslip0_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
+			a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip04 <= 8'd0;
-	case (main_a7ddrphy_bitslip0_value3)
+	a7ddrphy_bitslip04 <= 8'd0;
+	case (a7ddrphy_bitslip0_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
+			a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip12 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value2)
+	a7ddrphy_bitslip12 <= 8'd0;
+	case (a7ddrphy_bitslip1_value2)
 		1'd0: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
+			a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip14 <= 8'd0;
-	case (main_a7ddrphy_bitslip1_value3)
+	a7ddrphy_bitslip14 <= 8'd0;
+	case (a7ddrphy_bitslip1_value3)
 		1'd0: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
+			a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip20 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value0)
+	a7ddrphy_bitslip20 <= 8'd0;
+	case (a7ddrphy_bitslip2_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
+			a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip22 <= 8'd0;
-	case (main_a7ddrphy_bitslip2_value1)
+	a7ddrphy_bitslip22 <= 8'd0;
+	case (a7ddrphy_bitslip2_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
+			a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip30 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value0)
+	a7ddrphy_bitslip30 <= 8'd0;
+	case (a7ddrphy_bitslip3_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
+			a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip32 <= 8'd0;
-	case (main_a7ddrphy_bitslip3_value1)
+	a7ddrphy_bitslip32 <= 8'd0;
+	case (a7ddrphy_bitslip3_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
+			a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip40 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value0)
+	a7ddrphy_bitslip40 <= 8'd0;
+	case (a7ddrphy_bitslip4_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
+			a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip42 <= 8'd0;
-	case (main_a7ddrphy_bitslip4_value1)
+	a7ddrphy_bitslip42 <= 8'd0;
+	case (a7ddrphy_bitslip4_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
+			a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip50 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value0)
+	a7ddrphy_bitslip50 <= 8'd0;
+	case (a7ddrphy_bitslip5_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
+			a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip52 <= 8'd0;
-	case (main_a7ddrphy_bitslip5_value1)
+	a7ddrphy_bitslip52 <= 8'd0;
+	case (a7ddrphy_bitslip5_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
+			a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip60 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value0)
+	a7ddrphy_bitslip60 <= 8'd0;
+	case (a7ddrphy_bitslip6_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
+			a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip62 <= 8'd0;
-	case (main_a7ddrphy_bitslip6_value1)
+	a7ddrphy_bitslip62 <= 8'd0;
+	case (a7ddrphy_bitslip6_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
+			a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip70 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value0)
+	a7ddrphy_bitslip70 <= 8'd0;
+	case (a7ddrphy_bitslip7_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
+			a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip72 <= 8'd0;
-	case (main_a7ddrphy_bitslip7_value1)
+	a7ddrphy_bitslip72 <= 8'd0;
+	case (a7ddrphy_bitslip7_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
+			a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip80 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value0)
+	a7ddrphy_bitslip80 <= 8'd0;
+	case (a7ddrphy_bitslip8_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
+			a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip82 <= 8'd0;
-	case (main_a7ddrphy_bitslip8_value1)
+	a7ddrphy_bitslip82 <= 8'd0;
+	case (a7ddrphy_bitslip8_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
+			a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip90 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value0)
+	a7ddrphy_bitslip90 <= 8'd0;
+	case (a7ddrphy_bitslip9_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
+			a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip92 <= 8'd0;
-	case (main_a7ddrphy_bitslip9_value1)
+	a7ddrphy_bitslip92 <= 8'd0;
+	case (a7ddrphy_bitslip9_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
+			a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip100 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value0)
+	a7ddrphy_bitslip100 <= 8'd0;
+	case (a7ddrphy_bitslip10_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
+			a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip102 <= 8'd0;
-	case (main_a7ddrphy_bitslip10_value1)
+	a7ddrphy_bitslip102 <= 8'd0;
+	case (a7ddrphy_bitslip10_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
+			a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip110 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value0)
+	a7ddrphy_bitslip110 <= 8'd0;
+	case (a7ddrphy_bitslip11_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
+			a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip112 <= 8'd0;
-	case (main_a7ddrphy_bitslip11_value1)
+	a7ddrphy_bitslip112 <= 8'd0;
+	case (a7ddrphy_bitslip11_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
+			a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip120 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value0)
+	a7ddrphy_bitslip120 <= 8'd0;
+	case (a7ddrphy_bitslip12_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
+			a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip122 <= 8'd0;
-	case (main_a7ddrphy_bitslip12_value1)
+	a7ddrphy_bitslip122 <= 8'd0;
+	case (a7ddrphy_bitslip12_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
+			a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip130 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value0)
+	a7ddrphy_bitslip130 <= 8'd0;
+	case (a7ddrphy_bitslip13_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
+			a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip132 <= 8'd0;
-	case (main_a7ddrphy_bitslip13_value1)
+	a7ddrphy_bitslip132 <= 8'd0;
+	case (a7ddrphy_bitslip13_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
+			a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip140 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value0)
+	a7ddrphy_bitslip140 <= 8'd0;
+	case (a7ddrphy_bitslip14_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
+			a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip142 <= 8'd0;
-	case (main_a7ddrphy_bitslip14_value1)
+	a7ddrphy_bitslip142 <= 8'd0;
+	case (a7ddrphy_bitslip14_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
+			a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip150 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value0)
+	a7ddrphy_bitslip150 <= 8'd0;
+	case (a7ddrphy_bitslip15_value0)
 		1'd0: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
 		end
 		1'd1: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
 		end
 		2'd2: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
 		end
 		2'd3: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
 		end
 		3'd4: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
 		end
 		3'd5: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
 		end
 		3'd6: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
 		end
 		3'd7: begin
-			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
+			a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
 		end
 	endcase
 end
 always @(*) begin
-	main_a7ddrphy_bitslip152 <= 8'd0;
-	case (main_a7ddrphy_bitslip15_value1)
+	a7ddrphy_bitslip152 <= 8'd0;
+	case (a7ddrphy_bitslip15_value1)
 		1'd0: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
-		end
-		1'd1: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
-		end
-		2'd2: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
-		end
-		2'd3: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
-		end
-		3'd4: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
-		end
-		3'd5: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
-		end
-		3'd6: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
-		end
-		3'd7: begin
-			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
-		end
-	endcase
-end
-assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
-assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
-assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
-assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
-assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
-assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
-assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
-assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
-assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
-assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
-assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
-assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
-assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
-assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
-assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
-assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
-assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
-assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
-assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
-assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
-assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
-assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
-assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
-assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
-assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
-assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
-assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
-assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
-assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
-assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
-assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
-assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
-assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
-assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
-assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
-assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
-assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
-assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
-assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
-assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
-assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
-assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
-assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
-assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
-assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
-assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
-assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
-assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
-assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
-assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
-assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
-assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
-assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
-assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
-assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
-assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
-assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
-assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
-assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
-assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
-assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
-assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
-assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
-assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
-assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
-assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
-assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
-assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
-assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
-assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
-assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
-assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
-assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
-assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
-assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
-assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
-assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
-assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
-assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
-assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
-assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
-assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
-assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
-assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
-assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
-assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
-assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
-assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
-assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
-assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
-assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
-assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
-assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
-assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
-assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
-assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
-assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
-assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
-assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
-assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
-assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
-assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
-assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
-assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
-assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
-assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
-assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
-assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
-assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
-assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
-assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
-assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
-assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
-assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
-assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
-assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
-assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
-assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
-assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
-assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
-assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
-assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
-assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
-assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
-assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
-assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
-assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
-assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+		end
+		1'd1: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+		end
+		2'd2: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+		end
+		2'd3: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+		end
+		3'd4: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+		end
+		3'd5: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+		end
+		3'd6: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+		end
+		3'd7: begin
+			a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+		end
+	endcase
+end
+assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
+assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
+assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
+assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+	litedramcore_csr_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+	end
+end
+always @(*) begin
+	litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+	end else begin
+		litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+	end
+end
 always @(*) begin
-	main_litedramcore_master_p3_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	litedramcore_csr_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
+		litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
+	litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
+		litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
+	litedramcore_csr_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
+		litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
+	litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
 	end else begin
-		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
+		litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+	litedramcore_ext_dfi_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
+	litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
+	litedramcore_ext_dfi_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+		end else begin
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
+	litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	litedramcore_ext_dfi_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+		end else begin
+		end
 	end else begin
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
+	litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
+	litedramcore_slave_p0_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
+	litedramcore_slave_p0_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
+	litedramcore_ext_dfi_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
+	litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end else begin
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_slave_p1_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
+	litedramcore_slave_p1_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_slave_p2_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+		end
 	end else begin
-		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
+	litedramcore_slave_p2_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p0_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
+	litedramcore_slave_p3_rddata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+		end
 	end else begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
+	litedramcore_slave_p3_rddata_valid <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+		end else begin
+			litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+		end
 	end else begin
-		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
+	litedramcore_master_p0_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+		end else begin
+			litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+		end
 	end else begin
-		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
+		litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
+	litedramcore_master_p0_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+		end else begin
+			litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+		end
 	end else begin
-		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
+		litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+	litedramcore_master_p0_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+		end else begin
+			litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
+		litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
+	litedramcore_master_p0_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+		end else begin
+			litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
+		litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
+	litedramcore_master_p0_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+		end else begin
+			litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+		end
 	end else begin
+		litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
+	litedramcore_master_p0_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+		end else begin
+			litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
+		litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	litedramcore_master_p0_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+		end else begin
+			litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+		end
 	end else begin
+		litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
+	litedramcore_master_p0_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+		end else begin
+			litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+		end
 	end else begin
-		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
+		litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
+	litedramcore_master_p0_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+		end else begin
+			litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+		end
+	end else begin
+		litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+		end else begin
+			litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+		end
+	end else begin
+		litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+		end else begin
+			litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+		end
+	end else begin
+		litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+		end else begin
+			litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+		end
+	end else begin
+		litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+	end
+end
+always @(*) begin
+	litedramcore_master_p0_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+		end else begin
+			litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
+		litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
+	litedramcore_master_p0_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+		end else begin
+			litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
+		litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
+	litedramcore_master_p1_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+		end else begin
+			litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+		end
 	end else begin
-		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
+		litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
+	litedramcore_master_p1_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+		end else begin
+			litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
+		litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p1_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+		end else begin
+			litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
+		litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
+	litedramcore_master_p1_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+		end else begin
+			litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
+		litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p1_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+		end else begin
+			litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+		end
 	end else begin
-		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+		litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
+	litedramcore_master_p1_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+		end else begin
+			litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
+		litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p1_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
+	litedramcore_master_p1_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+		end else begin
+			litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+		end
 	end else begin
-		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
+		litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
+	litedramcore_master_p1_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+		end else begin
+			litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
+		litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
+	litedramcore_master_p1_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+		end else begin
+			litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
+		litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
+	litedramcore_master_p1_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+		end else begin
+			litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
+		litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+	litedramcore_master_p1_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+		end else begin
+			litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
+		litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
+	litedramcore_master_p1_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+		end else begin
+			litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
+		litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
+	litedramcore_master_p1_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+		end else begin
+			litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+		end
 	end else begin
+		litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
+	litedramcore_master_p1_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+		end else begin
+			litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
+		litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	litedramcore_master_p2_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+		end else begin
+			litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+		end
 	end else begin
+		litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
+	litedramcore_master_p2_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+		end else begin
+			litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+		end
 	end else begin
-		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
+		litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
+	litedramcore_master_p2_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+		end else begin
+			litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
+		litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
+	litedramcore_master_p2_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+		end else begin
+			litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
+		litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
+	litedramcore_master_p2_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+		end else begin
+			litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
+		litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+	litedramcore_master_p2_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+		end else begin
+			litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+		litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+		end else begin
+			litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+	litedramcore_master_p2_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+		end else begin
+			litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+		litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+		end else begin
+			litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+		end
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
+	litedramcore_master_p2_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+		end else begin
+			litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
+		litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p2_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+		end else begin
+			litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
+		litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p2_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
+	litedramcore_master_p2_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+		end else begin
+			litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+		litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_address <= 14'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+	litedramcore_master_p2_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+		end else begin
+			litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+		litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_bank <= 3'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
+	litedramcore_master_p2_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+		end else begin
+			litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
+		litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
+	litedramcore_master_p3_address <= 14'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+		end else begin
+			litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+		end
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+		litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
+	litedramcore_master_p3_bank <= 3'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+		end else begin
+			litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+		end
 	end else begin
-		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
+		litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cs_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+	litedramcore_master_p3_cas_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+		end else begin
+			litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
+		litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_ras_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+	litedramcore_master_p3_cs_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+		end else begin
+			litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
+		litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+	litedramcore_master_p3_ras_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+		end else begin
+			litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+		end
 	end else begin
+		litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_we_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
+	litedramcore_master_p3_we_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+		end else begin
+			litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
+		litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	litedramcore_master_p3_cke <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+		end else begin
+			litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+		end
 	end else begin
+		litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_cke <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
+	litedramcore_master_p3_odt <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+		end else begin
+			litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+		end
 	end else begin
-		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
+		litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_odt <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
+	litedramcore_master_p3_reset_n <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+		end else begin
+			litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
+		litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_reset_n <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
+	litedramcore_master_p3_act_n <= 1'd1;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+		end else begin
+			litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+		end
 	end else begin
-		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
+		litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_act_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
+	litedramcore_master_p3_wrdata <= 32'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+		end else begin
+			litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+		end
 	end else begin
-		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
+		litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata <= 32'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
+	litedramcore_master_p3_wrdata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+		end else begin
+			litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
+		litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
+	litedramcore_master_p3_wrdata_mask <= 4'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+		end else begin
+			litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
+		litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
 	end
 end
 always @(*) begin
-	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
+	litedramcore_master_p3_rddata_en <= 1'd0;
+	if (litedramcore_sel) begin
+		if (litedramcore_ext_dfi_sel) begin
+			litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+		end else begin
+			litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+		end
 	end else begin
-		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
+		litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
 	end
 end
-assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p2_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p3_cke = main_litedramcore_cke;
-assign main_litedramcore_inti_p0_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p1_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p2_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p3_odt = main_litedramcore_odt;
-assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
-assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
+assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	litedramcore_csr_dfi_p0_we_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		litedramcore_csr_dfi_p0_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+	litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p0_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+	litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+	litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector0_command_issue_re) begin
+		litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p0_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
-assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
-assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]);
-assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
-assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
-assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
+assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
+assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	litedramcore_csr_dfi_p1_we_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		litedramcore_csr_dfi_p1_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+	litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p1_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+	litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+	litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector1_command_issue_re) begin
+		litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p1_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
-assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
-assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]);
-assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
-assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
-assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
+assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
+assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	litedramcore_csr_dfi_p2_we_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		litedramcore_csr_dfi_p2_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+	litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p2_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+	litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector2_command_issue_re) begin
+		litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p2_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
-assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
-assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]);
-assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
-assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
-assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
+assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
+assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	litedramcore_csr_dfi_p3_we_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		litedramcore_csr_dfi_p3_we_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+	litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		litedramcore_csr_dfi_p3_cas_n <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+	litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
 	end
 end
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
-	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+	litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+	if (litedramcore_phaseinjector3_command_issue_re) begin
+		litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		litedramcore_csr_dfi_p3_ras_n <= 1'd1;
 	end
 end
-assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
-assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
-assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]);
-assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]);
-assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
-assign main_litedramcore_inti_p3_wrdata_mask = 1'd0;
-assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
-assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
-assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
-assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
-assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
-assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
-assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
-assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
-assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
-assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
-assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
-assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
-assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
-assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
-assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
-assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
-assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
-assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
-assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
-assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
-assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
-assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
-assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
-assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
-assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
-assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
-assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
-assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
-assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
-assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
-assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
-assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
-assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
-assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
-assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
-assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
-assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
-assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
-assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
-assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
-assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
-assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
-assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
-assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
-assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
-assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
-assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
-assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
-assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
-assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
-assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
-assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
-assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
-assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
-assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
-assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
-assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
-assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
-assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
-assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
-assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
-assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
-assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
-assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
-assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
-assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
-assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
-assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
-assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
-always @(*) begin
-	builder_refresher_next_state <= 2'd0;
-	builder_refresher_next_state <= builder_refresher_state;
-	case (builder_refresher_state)
-		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				builder_refresher_next_state <= 2'd2;
-			end
-		end
-		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					builder_refresher_next_state <= 2'd3;
+assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
+assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
+assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+always @(*) begin
+	litedramcore_refresher_next_state <= 2'd0;
+	litedramcore_refresher_next_state <= litedramcore_refresher_state;
+	case (litedramcore_refresher_state)
+		1'd1: begin
+			if (litedramcore_cmd_ready) begin
+				litedramcore_refresher_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_refresher_next_state <= 2'd3;
 				end else begin
-					builder_refresher_next_state <= 1'd0;
+					litedramcore_refresher_next_state <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				builder_refresher_next_state <= 1'd0;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_refresher_next_state <= 1'd0;
 			end
 		end
 		default: begin
 			if (1'd1) begin
-				if (main_litedramcore_wants_refresh) begin
-					builder_refresher_next_state <= 1'd1;
+				if (litedramcore_wants_refresh) begin
+					litedramcore_refresher_next_state <= 1'd1;
 				end
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_last <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_zqcs_executer_start <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+					litedramcore_zqcs_executer_start <= 1'd1;
 				end else begin
-					main_litedramcore_cmd_last <= 1'd1;
 				end
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_last <= 1'd1;
-			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_sequencer_start0 <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_last <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			if (main_litedramcore_cmd_ready) begin
-				main_litedramcore_sequencer_start0 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
+				end else begin
+					litedramcore_cmd_last <= 1'd1;
+				end
+			end
 		end
 		2'd3: begin
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_last <= 1'd1;
+			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_valid <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_sequencer_start0 <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
-			main_litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_cmd_ready) begin
+				litedramcore_sequencer_start0 <= 1'd1;
+			end
 		end
 		2'd2: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-				end else begin
-					main_litedramcore_cmd_valid <= 1'd0;
-				end
-			end
 		end
 		2'd3: begin
-			main_litedramcore_cmd_valid <= 1'd1;
-			if (main_litedramcore_zqcs_executer_done) begin
-				main_litedramcore_cmd_valid <= 1'd0;
-			end
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_zqcs_executer_start <= 1'd0;
-	case (builder_refresher_state)
+	litedramcore_cmd_valid <= 1'd0;
+	case (litedramcore_refresher_state)
 		1'd1: begin
+			litedramcore_cmd_valid <= 1'd1;
 		end
 		2'd2: begin
-			if (main_litedramcore_sequencer_done0) begin
-				if (main_litedramcore_wants_zqcs) begin
-					main_litedramcore_zqcs_executer_start <= 1'd1;
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_sequencer_done0) begin
+				if (litedramcore_wants_zqcs) begin
 				end else begin
+					litedramcore_cmd_valid <= 1'd0;
 				end
 			end
 		end
 		2'd3: begin
+			litedramcore_cmd_valid <= 1'd1;
+			if (litedramcore_zqcs_executer_done) begin
+				litedramcore_cmd_valid <= 1'd0;
+			end
 		end
 		default: begin
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
-assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
-assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+	litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+		litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
 	end else begin
-		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+		litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
 	end
 end
-assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
-assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
-assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+	litedramcore_bankmachine0_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
 		end
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+	litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
 	end else begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
 	end
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine0_next_state <= 4'd0;
-	builder_bankmachine0_next_state <= builder_bankmachine0_state;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_next_state <= 4'd0;
+	litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd5;
 				end
 			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				builder_bankmachine0_next_state <= 3'd5;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_next_state <= 3'd5;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				if (main_litedramcore_bankmachine0_cmd_ready) begin
-					builder_bankmachine0_next_state <= 3'd7;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				if (litedramcore_bankmachine0_cmd_ready) begin
+					litedramcore_bankmachine0_next_state <= 3'd7;
 				end
 			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine0_refresh_req)) begin
-				builder_bankmachine0_next_state <= 1'd0;
+			if ((~litedramcore_bankmachine0_refresh_req)) begin
+				litedramcore_bankmachine0_next_state <= 1'd0;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine0_next_state <= 3'd6;
+			litedramcore_bankmachine0_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine0_next_state <= 2'd3;
+			litedramcore_bankmachine0_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine0_next_state <= 4'd8;
+			litedramcore_bankmachine0_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine0_next_state <= 1'd0;
+			litedramcore_bankmachine0_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-				builder_bankmachine0_next_state <= 3'd4;
+			if (litedramcore_bankmachine0_refresh_req) begin
+				litedramcore_bankmachine0_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
-								builder_bankmachine0_next_state <= 2'd2;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+								litedramcore_bankmachine0_next_state <= 2'd2;
 							end
 						end else begin
-							builder_bankmachine0_next_state <= 1'd1;
+							litedramcore_bankmachine0_next_state <= 1'd1;
 						end
 					end else begin
-						builder_bankmachine0_next_state <= 2'd3;
+						litedramcore_bankmachine0_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4333,18 +4752,82 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (litedramcore_bankmachine0_twtpcon_ready) begin
+				litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+end
+always @(*) begin
+	litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine0_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4358,12 +4841,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4374,15 +4857,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_open <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_open <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_open <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4400,18 +4883,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_close <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_close <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_row_close <= 1'd1;
+			litedramcore_bankmachine0_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4426,8 +4909,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4445,12 +4928,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4461,18 +4944,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4490,11 +4973,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -4512,13 +4995,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4531,15 +5014,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4557,22 +5040,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine0_trccon_ready) begin
+				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4587,8 +5070,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4606,14 +5089,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -4625,8 +5108,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4644,13 +5127,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4663,8 +5146,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4682,13 +5165,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine0_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine0_row_opened) begin
+						if (litedramcore_bankmachine0_row_hit) begin
+							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -4700,38 +5183,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+		litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+always @(*) begin
+	litedramcore_bankmachine1_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine1_next_state <= 4'd0;
+	litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+	case (litedramcore_bankmachine1_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				if (litedramcore_bankmachine1_cmd_ready) begin
+					litedramcore_bankmachine1_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine1_refresh_req)) begin
+				litedramcore_bankmachine1_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+				litedramcore_bankmachine1_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+								litedramcore_bankmachine1_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine1_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine1_next_state <= 2'd3;
 					end
 				end
 			end
@@ -4739,8 +5311,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-	case (builder_bankmachine0_state)
+	litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -4748,9 +5320,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -4761,149 +5330,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
-assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
-assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
-assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine1_next_state <= 4'd0;
-	builder_bankmachine1_next_state <= builder_bankmachine1_state;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				builder_bankmachine1_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				if (main_litedramcore_bankmachine1_cmd_ready) begin
-					builder_bankmachine1_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine1_refresh_req)) begin
-				builder_bankmachine1_next_state <= 1'd0;
+			if (litedramcore_bankmachine1_twtpcon_ready) begin
+				litedramcore_bankmachine1_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine1_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine1_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine1_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine1_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-				builder_bankmachine1_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
-								builder_bankmachine1_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine1_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine1_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4917,12 +5400,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -4933,15 +5416,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_open <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_open <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -4959,18 +5442,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_close <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_close <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
+			litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -4985,8 +5468,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5004,12 +5487,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5020,18 +5503,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5049,11 +5532,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5071,13 +5554,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5090,15 +5573,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5116,22 +5599,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine1_trccon_ready) begin
+				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5146,8 +5629,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5165,14 +5648,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5184,8 +5667,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5203,13 +5686,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5222,8 +5705,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5241,13 +5724,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine1_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine1_row_opened) begin
+						if (litedramcore_bankmachine1_row_hit) begin
+							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5259,38 +5742,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine1_state)
-		1'd1: begin
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+		litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+always @(*) begin
+	litedramcore_bankmachine2_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine2_next_state <= 4'd0;
+	litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+	case (litedramcore_bankmachine2_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				if (litedramcore_bankmachine2_cmd_ready) begin
+					litedramcore_bankmachine2_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine2_refresh_req)) begin
+				litedramcore_bankmachine2_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+				litedramcore_bankmachine2_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+								litedramcore_bankmachine2_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine2_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine2_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5298,8 +5870,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-	case (builder_bankmachine1_state)
+	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5307,9 +5879,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5320,149 +5889,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
-assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
-assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine2_next_state <= 4'd0;
-	builder_bankmachine2_next_state <= builder_bankmachine2_state;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				builder_bankmachine2_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				if (main_litedramcore_bankmachine2_cmd_ready) begin
-					builder_bankmachine2_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine2_refresh_req)) begin
-				builder_bankmachine2_next_state <= 1'd0;
+			if (litedramcore_bankmachine2_twtpcon_ready) begin
+				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine2_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine2_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine2_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine2_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-				builder_bankmachine2_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
-								builder_bankmachine2_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine2_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine2_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5476,12 +5959,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5492,15 +5975,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_open <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_open <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_open <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5518,18 +6001,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_close <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_close <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_row_close <= 1'd1;
+			litedramcore_bankmachine2_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5544,8 +6027,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5563,12 +6046,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5579,18 +6062,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5608,11 +6091,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -5630,13 +6113,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5649,15 +6132,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -5675,22 +6158,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine2_trccon_ready) begin
+				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -5705,8 +6188,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5724,14 +6207,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -5743,8 +6226,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5762,13 +6245,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -5781,8 +6264,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5800,13 +6283,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine2_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine2_row_opened) begin
+						if (litedramcore_bankmachine2_row_hit) begin
+							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -5818,38 +6301,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+		litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+always @(*) begin
+	litedramcore_bankmachine3_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine3_next_state <= 4'd0;
+	litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+	case (litedramcore_bankmachine3_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				if (litedramcore_bankmachine3_cmd_ready) begin
+					litedramcore_bankmachine3_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine3_refresh_req)) begin
+				litedramcore_bankmachine3_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+				litedramcore_bankmachine3_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+								litedramcore_bankmachine3_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine3_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine3_next_state <= 2'd3;
 					end
 				end
 			end
@@ -5857,8 +6429,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-	case (builder_bankmachine2_state)
+	litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -5866,9 +6438,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -5879,149 +6448,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
-assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
-assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
-assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine3_next_state <= 4'd0;
-	builder_bankmachine3_next_state <= builder_bankmachine3_state;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				builder_bankmachine3_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				if (main_litedramcore_bankmachine3_cmd_ready) begin
-					builder_bankmachine3_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine3_refresh_req)) begin
-				builder_bankmachine3_next_state <= 1'd0;
+			if (litedramcore_bankmachine3_twtpcon_ready) begin
+				litedramcore_bankmachine3_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine3_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine3_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine3_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine3_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-				builder_bankmachine3_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
-								builder_bankmachine3_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine3_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine3_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6035,12 +6518,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6051,15 +6534,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_open <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_open <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6077,18 +6560,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_close <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_close <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
+			litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6103,8 +6586,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6122,12 +6605,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6138,18 +6621,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6167,11 +6650,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6189,13 +6672,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6208,15 +6691,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6234,22 +6717,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine3_trccon_ready) begin
+				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6264,8 +6747,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6283,14 +6766,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6302,8 +6785,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6321,13 +6804,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6340,8 +6823,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6359,13 +6842,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine3_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -6377,38 +6860,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine3_state)
-		1'd1: begin
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+		litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+always @(*) begin
+	litedramcore_bankmachine4_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine4_next_state <= 4'd0;
+	litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+	case (litedramcore_bankmachine4_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				if (litedramcore_bankmachine4_cmd_ready) begin
+					litedramcore_bankmachine4_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine4_refresh_req)) begin
+				litedramcore_bankmachine4_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine4_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+				litedramcore_bankmachine4_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+								litedramcore_bankmachine4_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine4_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine4_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6416,8 +6988,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-	case (builder_bankmachine3_state)
+	litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6425,9 +6997,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6438,149 +7007,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
-assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
-assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
-assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine4_next_state <= 4'd0;
-	builder_bankmachine4_next_state <= builder_bankmachine4_state;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				builder_bankmachine4_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				if (main_litedramcore_bankmachine4_cmd_ready) begin
-					builder_bankmachine4_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine4_refresh_req)) begin
-				builder_bankmachine4_next_state <= 1'd0;
+			if (litedramcore_bankmachine4_twtpcon_ready) begin
+				litedramcore_bankmachine4_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine4_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine4_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine4_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine4_next_state <= 1'd0;
 		end
-		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-				builder_bankmachine4_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
-								builder_bankmachine4_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine4_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine4_next_state <= 2'd3;
-					end
-				end
-			end
+		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6594,12 +7077,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6610,15 +7093,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_open <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6636,18 +7119,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_close <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
+			litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6662,8 +7145,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6681,12 +7164,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -6697,18 +7180,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6726,11 +7209,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -6748,13 +7231,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6767,15 +7250,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -6793,22 +7276,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine4_trccon_ready) begin
+				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -6823,8 +7306,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6842,14 +7325,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6861,8 +7344,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6880,13 +7363,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6899,8 +7382,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6918,13 +7401,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine4_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine4_row_opened) begin
+						if (litedramcore_bankmachine4_row_hit) begin
+							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -6936,38 +7419,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine4_state)
-		1'd1: begin
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+		litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+always @(*) begin
+	litedramcore_bankmachine5_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine5_next_state <= 4'd0;
+	litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+	case (litedramcore_bankmachine5_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				if (litedramcore_bankmachine5_cmd_ready) begin
+					litedramcore_bankmachine5_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine5_refresh_req)) begin
+				litedramcore_bankmachine5_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+				litedramcore_bankmachine5_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+								litedramcore_bankmachine5_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine5_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine5_next_state <= 2'd3;
 					end
 				end
 			end
@@ -6975,8 +7547,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-	case (builder_bankmachine4_state)
+	litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -6984,9 +7556,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6997,149 +7566,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
-assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
-assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
-assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
 always @(*) begin
-	builder_bankmachine5_next_state <= 4'd0;
-	builder_bankmachine5_next_state <= builder_bankmachine5_state;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				builder_bankmachine5_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				if (main_litedramcore_bankmachine5_cmd_ready) begin
-					builder_bankmachine5_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-				builder_bankmachine5_next_state <= 1'd0;
+			if (litedramcore_bankmachine5_twtpcon_ready) begin
+				litedramcore_bankmachine5_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine5_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine5_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine5_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine5_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-				builder_bankmachine5_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-								builder_bankmachine5_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine5_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine5_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7153,12 +7636,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7169,15 +7652,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_open <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_open <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_open <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7195,18 +7678,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_close <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_close <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
+			litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7221,8 +7704,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7240,12 +7723,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7256,18 +7739,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7285,11 +7768,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7307,13 +7790,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7326,15 +7809,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7352,22 +7835,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine5_trccon_ready) begin
+				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7382,8 +7865,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7401,14 +7884,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7420,8 +7903,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7439,13 +7922,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7458,8 +7941,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7477,13 +7960,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine5_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine5_row_opened) begin
+						if (litedramcore_bankmachine5_row_hit) begin
+							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -7495,38 +7978,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+	litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+		litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+always @(*) begin
+	litedramcore_bankmachine6_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine6_next_state <= 4'd0;
+	litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+	case (litedramcore_bankmachine6_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				if (litedramcore_bankmachine6_cmd_ready) begin
+					litedramcore_bankmachine6_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine6_refresh_req)) begin
+				litedramcore_bankmachine6_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+				litedramcore_bankmachine6_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+								litedramcore_bankmachine6_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine6_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine6_next_state <= 2'd3;
 					end
 				end
 			end
@@ -7534,8 +8106,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (builder_bankmachine5_state)
+	litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7543,9 +8115,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -7556,149 +8125,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
-assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
-assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
-assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
-always @(*) begin
-	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine6_next_state <= 4'd0;
-	builder_bankmachine6_next_state <= builder_bankmachine6_state;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				builder_bankmachine6_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				if (main_litedramcore_bankmachine6_cmd_ready) begin
-					builder_bankmachine6_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine6_refresh_req)) begin
-				builder_bankmachine6_next_state <= 1'd0;
+			if (litedramcore_bankmachine6_twtpcon_ready) begin
+				litedramcore_bankmachine6_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine6_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine6_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine6_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine6_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-				builder_bankmachine6_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
-								builder_bankmachine6_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine6_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine6_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7712,12 +8195,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7728,15 +8211,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_open <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7754,18 +8237,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_close <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
+			litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7780,8 +8263,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7799,12 +8282,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7815,18 +8298,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7844,11 +8327,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -7866,13 +8349,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7885,15 +8368,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7911,22 +8394,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine6_trccon_ready) begin
+				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7941,8 +8424,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7960,14 +8443,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7979,8 +8462,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -7998,13 +8481,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8017,8 +8500,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8036,13 +8519,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine6_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine6_row_opened) begin
+						if (litedramcore_bankmachine6_row_hit) begin
+							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -8054,38 +8537,127 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine6_state)
-		1'd1: begin
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+	litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+	if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+		litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+end
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+always @(*) begin
+	litedramcore_bankmachine7_auto_precharge <= 1'd0;
+	if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+		if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
+			litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+		end
+	end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+	litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+	end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
+always @(*) begin
+	litedramcore_bankmachine7_next_state <= 4'd0;
+	litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+	case (litedramcore_bankmachine7_state)
+		1'd1: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd5;
+				end
+			end
 		end
 		2'd2: begin
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_next_state <= 3'd5;
+			end
 		end
 		2'd3: begin
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				if (litedramcore_bankmachine7_cmd_ready) begin
+					litedramcore_bankmachine7_next_state <= 3'd7;
+				end
+			end
 		end
 		3'd4: begin
+			if ((~litedramcore_bankmachine7_refresh_req)) begin
+				litedramcore_bankmachine7_next_state <= 1'd0;
+			end
 		end
 		3'd5: begin
+			litedramcore_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
+			litedramcore_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
+			litedramcore_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
+			litedramcore_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+				litedramcore_bankmachine7_next_state <= 3'd4;
 			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+								litedramcore_bankmachine7_next_state <= 2'd2;
 							end
 						end else begin
+							litedramcore_bankmachine7_next_state <= 1'd1;
 						end
 					end else begin
+						litedramcore_bankmachine7_next_state <= 2'd3;
 					end
 				end
 			end
@@ -8093,8 +8665,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-	case (builder_bankmachine6_state)
+	litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8102,9 +8674,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8115,149 +8684,63 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
-assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
-assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
-assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
-	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
-	end else begin
-		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-	end
-end
-assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
-assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
-assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
 always @(*) begin
-	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
-	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
-		if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
-			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
-		end
-	end
-end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
-	end else begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
-	end
-end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
-	builder_bankmachine7_next_state <= 4'd0;
-	builder_bankmachine7_next_state <= builder_bankmachine7_state;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd5;
-				end
-			end
 		end
 		2'd2: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				builder_bankmachine7_next_state <= 3'd5;
-			end
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				if (main_litedramcore_bankmachine7_cmd_ready) begin
-					builder_bankmachine7_next_state <= 3'd7;
-				end
-			end
 		end
 		3'd4: begin
-			if ((~main_litedramcore_bankmachine7_refresh_req)) begin
-				builder_bankmachine7_next_state <= 1'd0;
+			if (litedramcore_bankmachine7_twtpcon_ready) begin
+				litedramcore_bankmachine7_refresh_gnt <= 1'd1;
 			end
 		end
 		3'd5: begin
-			builder_bankmachine7_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_bankmachine7_next_state <= 2'd3;
 		end
 		3'd7: begin
-			builder_bankmachine7_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_bankmachine7_next_state <= 1'd0;
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-				builder_bankmachine7_next_state <= 3'd4;
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
-								builder_bankmachine7_next_state <= 2'd2;
-							end
-						end else begin
-							builder_bankmachine7_next_state <= 1'd1;
-						end
-					end else begin
-						builder_bankmachine7_next_state <= 2'd3;
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8271,12 +8754,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8287,15 +8770,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_open <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_open <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_open <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_open <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8313,18 +8796,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_close <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_close <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
+			litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8339,8 +8822,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8358,12 +8841,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8374,18 +8857,18 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8403,11 +8886,11 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -8425,13 +8908,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8444,15 +8927,15 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8470,45 +8953,22 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			if (litedramcore_bankmachine7_trccon_ready) begin
+				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
+			litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8519,27 +8979,12 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8557,14 +9002,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
+								litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8576,8 +9021,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8595,13 +9040,13 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -8614,8 +9059,8 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-	case (builder_bankmachine7_state)
+	litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	case (litedramcore_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
@@ -8633,14 +9078,14 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
+			if (litedramcore_bankmachine7_refresh_req) begin
 			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine7_row_opened) begin
+						if (litedramcore_bankmachine7_row_hit) begin
+							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -8651,288 +9096,266 @@ always @(*) begin
 		end
 	endcase
 end
+assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
+assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
 always @(*) begin
-	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
-assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
-assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
-assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
-assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
-assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
-assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
-assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
-assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
-assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
-assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
-assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
-assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
-assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
-always @(*) begin
-	main_litedramcore_choose_cmd_valids <= 8'd0;
-	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
-	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids <= 8'd0;
+	litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+	litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
 end
-assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
-assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
-assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
-assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
-assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
-assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
-assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
+	litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
+	litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_cmd_cmd_valid) begin
-		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
+	litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_cmd_cmd_valid) begin
+		litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	litedramcore_bankmachine0_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
-		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+		litedramcore_bankmachine0_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	litedramcore_bankmachine1_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
-		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+		litedramcore_bankmachine1_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	litedramcore_bankmachine2_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
-		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+		litedramcore_bankmachine2_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	litedramcore_bankmachine3_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
-		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+		litedramcore_bankmachine3_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	litedramcore_bankmachine4_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
-		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+		litedramcore_bankmachine4_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	litedramcore_bankmachine5_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
-		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+		litedramcore_bankmachine5_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	litedramcore_bankmachine6_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
-		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+		litedramcore_bankmachine6_cmd_ready <= 1'd1;
 	end
 end
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
-	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	litedramcore_bankmachine7_cmd_ready <= 1'd0;
+	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
-	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
-		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+		litedramcore_bankmachine7_cmd_ready <= 1'd1;
 	end
 end
-assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-	main_litedramcore_choose_req_valids <= 8'd0;
-	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
-	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids <= 8'd0;
+	litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+	litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
 end
-assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
-assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
-assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
-assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
-assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
-assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
-assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
+	litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
+	litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
 	end
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
-	if (main_litedramcore_choose_req_cmd_valid) begin
-		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
+	litedramcore_choose_req_cmd_payload_we <= 1'd0;
+	if (litedramcore_choose_req_cmd_valid) begin
+		litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
 	end
 end
-assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
-assign main_litedramcore_dfi_p0_reset_n = 1'd1;
-assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}};
-assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}};
-assign main_litedramcore_dfi_p1_reset_n = 1'd1;
-assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}};
-assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}};
-assign main_litedramcore_dfi_p2_reset_n = 1'd1;
-assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}};
-assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}};
-assign main_litedramcore_dfi_p3_reset_n = 1'd1;
-assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
-assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
-assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
 always @(*) begin
-	builder_multiplexer_next_state <= 4'd0;
-	builder_multiplexer_next_state <= builder_multiplexer_state;
-	case (builder_multiplexer_state)
+	litedramcore_multiplexer_next_state <= 4'd0;
+	litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (main_litedramcore_read_available) begin
-				if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
-					builder_multiplexer_next_state <= 2'd3;
+			if (litedramcore_read_available) begin
+				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+					litedramcore_multiplexer_next_state <= 2'd3;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 		2'd2: begin
-			if (main_litedramcore_cmd_last) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_cmd_last) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		2'd3: begin
-			if (main_litedramcore_twtrcon_ready) begin
-				builder_multiplexer_next_state <= 1'd0;
+			if (litedramcore_twtrcon_ready) begin
+				litedramcore_multiplexer_next_state <= 1'd0;
 			end
 		end
 		3'd4: begin
-			builder_multiplexer_next_state <= 3'd5;
+			litedramcore_multiplexer_next_state <= 3'd5;
 		end
 		3'd5: begin
-			builder_multiplexer_next_state <= 3'd6;
+			litedramcore_multiplexer_next_state <= 3'd6;
 		end
 		3'd6: begin
-			builder_multiplexer_next_state <= 3'd7;
+			litedramcore_multiplexer_next_state <= 3'd7;
 		end
 		3'd7: begin
-			builder_multiplexer_next_state <= 4'd8;
+			litedramcore_multiplexer_next_state <= 4'd8;
 		end
 		4'd8: begin
-			builder_multiplexer_next_state <= 4'd9;
+			litedramcore_multiplexer_next_state <= 4'd9;
 		end
 		4'd9: begin
-			builder_multiplexer_next_state <= 4'd10;
+			litedramcore_multiplexer_next_state <= 4'd10;
 		end
 		4'd10: begin
-			builder_multiplexer_next_state <= 1'd1;
+			litedramcore_multiplexer_next_state <= 1'd1;
 		end
 		default: begin
-			if (main_litedramcore_write_available) begin
-				if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
-					builder_multiplexer_next_state <= 3'd4;
+			if (litedramcore_write_available) begin
+				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+					litedramcore_multiplexer_next_state <= 3'd4;
 				end
 			end
-			if (main_litedramcore_go_to_refresh) begin
-				builder_multiplexer_next_state <= 2'd2;
+			if (litedramcore_go_to_refresh) begin
+				litedramcore_multiplexer_next_state <= 2'd2;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel0 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 		2'd2: begin
+			litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -8951,26 +9374,23 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			litedramcore_steerer_sel0 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 1'd0)) begin
+				litedramcore_steerer_sel0 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -8989,20 +9409,20 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel1 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -9023,17 +9443,26 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			litedramcore_steerer_sel1 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 1'd1)) begin
+				litedramcore_steerer_sel1 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel2 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -9055,17 +9484,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			litedramcore_steerer_sel2 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd2)) begin
+				litedramcore_steerer_sel2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_want_activates <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -9086,15 +9522,24 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_steerer_sel3 <= 2'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_wrcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -9115,18 +9560,20 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			litedramcore_steerer_sel3 <= 1'd0;
+			if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((litedramcore_rdcmdphase == 2'd3)) begin
+				litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en0 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -9147,19 +9594,18 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			litedramcore_en0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -9180,23 +9626,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+			end else begin
+				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel0 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_reads <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
 		end
 		2'd2: begin
-			main_litedramcore_steerer_sel0 <= 2'd3;
 		end
 		2'd3: begin
 		end
@@ -9215,23 +9657,17 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel0 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
-				main_litedramcore_steerer_sel0 <= 1'd1;
-			end
+			litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_want_writes <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
+			litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -9254,15 +9690,13 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
 			end
 		end
 		2'd2: begin
@@ -9284,27 +9718,19 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
+			if (1'd0) begin
+				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+			end else begin
+				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_steerer_sel2 <= 2'd0;
-	case (builder_multiplexer_state)
+	litedramcore_en1 <= 1'd0;
+	case (litedramcore_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
+			litedramcore_en1 <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9325,1994 +9751,2011 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel2 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
-				main_litedramcore_steerer_sel2 <= 1'd1;
-			end
 		end
 	endcase
 end
-assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
-assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12;
-assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13;
-assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14;
-assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
-assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15;
-assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16;
-assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17;
-assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
-assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18;
-assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19;
-assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20;
-assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
-assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21;
-assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22;
-assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23;
-assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
-assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24;
-assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25;
-assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26;
-assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
-assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27;
-assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28;
-assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29;
-assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
-assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30;
-assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31;
-assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32;
-assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
-assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
-assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33;
-assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34;
-assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
-assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
-assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
-assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
+assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
 always @(*) begin
-	main_litedramcore_interface_wdata <= 128'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata <= 128'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			litedramcore_interface_wdata <= user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 16'd0;
-	case ({builder_new_master_wdata_ready1})
+	litedramcore_interface_wdata_we <= 16'd0;
+	case ({litedramcore_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 end
-assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
-assign builder_roundrobin0_grant = 1'd0;
-assign builder_roundrobin1_grant = 1'd0;
-assign builder_roundrobin2_grant = 1'd0;
-assign builder_roundrobin3_grant = 1'd0;
-assign builder_roundrobin4_grant = 1'd0;
-assign builder_roundrobin5_grant = 1'd0;
-assign builder_roundrobin6_grant = 1'd0;
-assign builder_roundrobin7_grant = 1'd0;
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-	builder_next_state <= 2'd0;
-	builder_next_state <= builder_state;
-	case (builder_state)
+	litedramcore_next_state <= 2'd0;
+	litedramcore_next_state <= litedramcore_state;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_next_state <= 2'd2;
+			litedramcore_next_state <= 2'd2;
 		end
 		2'd2: begin
-			builder_next_state <= 1'd0;
+			litedramcore_next_state <= 1'd0;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_next_state <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_next_state <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value0 <= 32'd0;
-	case (builder_state)
+	litedramcore_we_next_value2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
-	case (builder_state)
+	litedramcore_we_next_value_ce2 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value_ce2 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_ack <= 1'd0;
-	case (builder_state)
+	litedramcore_wishbone_ack <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_ack <= 1'd1;
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value1 <= 14'd0;
-	case (builder_state)
+	litedramcore_wishbone_dat_r <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value0 <= 32'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value2 <= 1'd0;
-	case (builder_state)
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
-			end
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_we_next_value_ce2 <= 1'd0;
-	case (builder_state)
+	litedramcore_adr_next_value1 <= 14'd0;
+	case (litedramcore_state)
 		1'd1: begin
-			builder_litedramcore_we_next_value_ce2 <= 1'd1;
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
-				builder_litedramcore_we_next_value_ce2 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	builder_litedramcore_wishbone_dat_r <= 32'd0;
-	case (builder_state)
+	litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (litedramcore_state)
 		1'd1: begin
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
-			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
 		end
 	endcase
 end
-assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
-assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
-assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r;
-assign builder_litedramcore_wishbone_sel = main_wb_bus_sel;
-assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc;
-assign builder_litedramcore_wishbone_stb = main_wb_bus_stb;
-assign main_wb_bus_ack = builder_litedramcore_wishbone_ack;
-assign builder_litedramcore_wishbone_we = main_wb_bus_we;
-assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
-assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
-assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
-assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_done0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_done0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank0_init_done0_re <= interface0_bank_bus_we;
 	end
 end
-assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	csrbank0_init_error0_re <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
-	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+	csrbank0_init_error0_we <= 1'd0;
+	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
-assign builder_csrbank0_init_done0_w = main_init_done_storage;
-assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
-assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rst0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rst0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank1_rst0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+	csrbank1_dly_sel0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_dly_sel0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_half_sys8x_taps0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+	csrbank1_half_sys8x_taps0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
+assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wlevel_en0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+	csrbank1_wlevel_en0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wlevel_strobe_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wlevel_strobe_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
 	end
 end
-assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_rdphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_rdphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank1_rdphase0_re <= interface1_bank_bus_we;
 	end
 end
-assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+	csrbank1_wrphase0_re <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_re <= interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
-	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+	csrbank1_wrphase0_we <= 1'd0;
+	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
 	end
 end
-assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
-assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
-assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
+assign csrbank1_rst0_w = a7ddrphy_rst_storage;
+assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
+assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
+assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
+assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
+assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-	builder_csrbank2_dfii_control0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_control0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_control0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_control0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		csrbank2_dfii_control0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi0_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi0_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi1_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi1_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi2_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi2_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+	litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+	litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
 	end
 end
-assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+	csrbank2_dfii_pi3_rddata_we <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
-	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
+	csrbank2_dfii_pi3_rddata_re <= 1'd0;
+	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
 	end
 end
-assign main_litedramcore_sel = main_litedramcore_storage[0];
-assign main_litedramcore_cke = main_litedramcore_storage[1];
-assign main_litedramcore_odt = main_litedramcore_storage[2];
-assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
-assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
-assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
-assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
-assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
-assign builder_csr_interconnect_adr = builder_litedramcore_adr;
-assign builder_csr_interconnect_we = builder_litedramcore_we;
-assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
-assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r;
-assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
-assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
-assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
-assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
-always @(*) begin
-	builder_rhs_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+assign litedramcore_sel = litedramcore_storage[0];
+assign litedramcore_cke = litedramcore_storage[1];
+assign litedramcore_odt = litedramcore_storage[2];
+assign litedramcore_reset_n = litedramcore_storage[3];
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
+assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
+assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
+assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
+assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
+assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
+assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
+assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
+assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
+assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
+assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
+assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
+assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
+assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
+assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
+assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
+assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
+assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
+assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
+assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
+assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
+assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
+assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
+assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
+assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
+assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
+assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
+assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
+assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
+assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
+assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
+assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
+assign csr_interconnect_adr = litedramcore_adr;
+assign csr_interconnect_we = litedramcore_we;
+assign csr_interconnect_dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = csr_interconnect_dat_r;
+assign interface0_bank_bus_adr = csr_interconnect_adr;
+assign interface1_bank_bus_adr = csr_interconnect_adr;
+assign interface2_bank_bus_adr = csr_interconnect_adr;
+assign interface0_bank_bus_we = csr_interconnect_we;
+assign interface1_bank_bus_we = csr_interconnect_we;
+assign interface2_bank_bus_we = csr_interconnect_we;
+assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
+assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
+assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+always @(*) begin
+	rhs_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
+			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed1 <= 14'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed1 <= 14'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed2 <= 3'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed2 <= 3'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	rhs_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed0 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed0 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed1 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed1 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed2 <= 1'd0;
-	case (main_litedramcore_choose_cmd_grant)
+	t_array_muxed2 <= 1'd0;
+	case (litedramcore_choose_cmd_grant)
 		1'd0: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed6 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed6 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
 		end
 		1'd1: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
 		end
 		2'd2: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
 		end
 		2'd3: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
 		end
 		3'd4: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
 		end
 		3'd5: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
 		end
 		3'd6: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
 		end
 		default: begin
-			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
+			rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed7 <= 14'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed7 <= 14'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
 		end
 		default: begin
-			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
+			rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed8 <= 3'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed8 <= 3'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
 		end
 		default: begin
-			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+			rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed9 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed9 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
 		end
 		default: begin
-			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+			rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed10 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed10 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
 		end
 		default: begin
-			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+			rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed11 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	rhs_array_muxed11 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
 		end
 		1'd1: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
 		end
 		2'd2: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
 		end
 		2'd3: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
 		end
 		3'd4: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
 		end
 		3'd5: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
 		end
 		3'd6: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
 		end
 		default: begin
-			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+			rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed3 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed3 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
 		end
 		1'd1: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
 		end
 		2'd2: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
 		end
 		2'd3: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
 		end
 		3'd4: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
 		end
 		3'd5: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
 		end
 		3'd6: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
 		end
 		default: begin
-			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+			t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed4 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed4 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
 		end
 		1'd1: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
 		end
 		2'd2: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
 		end
 		2'd3: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
 		end
 		3'd4: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
 		end
 		3'd5: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
 		end
 		3'd6: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
 		end
 		default: begin
-			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+			t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
 		end
 	endcase
 end
 always @(*) begin
-	builder_t_array_muxed5 <= 1'd0;
-	case (main_litedramcore_choose_req_grant)
+	t_array_muxed5 <= 1'd0;
+	case (litedramcore_choose_req_grant)
 		1'd0: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
 		end
 		1'd1: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
 		end
 		2'd2: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
 		end
 		2'd3: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
 		end
 		3'd4: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
 		end
 		3'd5: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
 		end
 		3'd6: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
 		end
 		default: begin
-			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
+			t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed12 <= 21'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed12 <= 21'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed13 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed13 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed13 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed14 <= 1'd0;
-	case (builder_roundrobin0_grant)
+	rhs_array_muxed14 <= 1'd0;
+	case (litedramcore_roundrobin0_grant)
 		default: begin
-			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed15 <= 21'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed15 <= 21'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed16 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed16 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed16 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed17 <= 1'd0;
-	case (builder_roundrobin1_grant)
+	rhs_array_muxed17 <= 1'd0;
+	case (litedramcore_roundrobin1_grant)
 		default: begin
-			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed18 <= 21'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed18 <= 21'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed19 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed19 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed19 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed20 <= 1'd0;
-	case (builder_roundrobin2_grant)
+	rhs_array_muxed20 <= 1'd0;
+	case (litedramcore_roundrobin2_grant)
 		default: begin
-			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed21 <= 21'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed21 <= 21'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed22 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed22 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed22 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed23 <= 1'd0;
-	case (builder_roundrobin3_grant)
+	rhs_array_muxed23 <= 1'd0;
+	case (litedramcore_roundrobin3_grant)
 		default: begin
-			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed24 <= 21'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed24 <= 21'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed25 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed25 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed25 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed26 <= 1'd0;
-	case (builder_roundrobin4_grant)
+	rhs_array_muxed26 <= 1'd0;
+	case (litedramcore_roundrobin4_grant)
 		default: begin
-			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed27 <= 21'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed27 <= 21'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed28 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed28 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed28 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed29 <= 1'd0;
-	case (builder_roundrobin5_grant)
+	rhs_array_muxed29 <= 1'd0;
+	case (litedramcore_roundrobin5_grant)
 		default: begin
-			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed30 <= 21'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed30 <= 21'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed31 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed31 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed31 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed32 <= 1'd0;
-	case (builder_roundrobin6_grant)
+	rhs_array_muxed32 <= 1'd0;
+	case (litedramcore_roundrobin6_grant)
 		default: begin
-			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed33 <= 21'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed33 <= 21'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+			rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed34 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed34 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
+			rhs_array_muxed34 <= user_port_cmd_payload_we;
 		end
 	endcase
 end
 always @(*) begin
-	builder_rhs_array_muxed35 <= 1'd0;
-	case (builder_roundrobin7_grant)
+	rhs_array_muxed35 <= 1'd0;
+	case (litedramcore_roundrobin7_grant)
 		default: begin
-			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
+			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed0 <= 3'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed0 <= 3'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed0 <= main_litedramcore_nop_ba[2:0];
+			array_muxed0 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed1 <= 14'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed1 <= 14'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed1 <= main_litedramcore_nop_a;
+			array_muxed1 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
+			array_muxed1 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed2 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed2 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed2 <= 1'd0;
+			array_muxed2 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed3 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed3 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed3 <= 1'd0;
+			array_muxed3 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed4 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed4 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed4 <= 1'd0;
+			array_muxed4 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed5 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed5 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed5 <= 1'd0;
+			array_muxed5 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed6 <= 1'd0;
-	case (main_litedramcore_steerer_sel0)
+	array_muxed6 <= 1'd0;
+	case (litedramcore_steerer_sel0)
 		1'd0: begin
-			builder_array_muxed6 <= 1'd0;
+			array_muxed6 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed7 <= 3'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed7 <= 3'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed7 <= main_litedramcore_nop_ba[2:0];
+			array_muxed7 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed8 <= 14'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed8 <= 14'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed8 <= main_litedramcore_nop_a;
+			array_muxed8 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
+			array_muxed8 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed9 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed9 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed9 <= 1'd0;
+			array_muxed9 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed10 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed10 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed10 <= 1'd0;
+			array_muxed10 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed11 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed11 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed11 <= 1'd0;
+			array_muxed11 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed12 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed12 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed12 <= 1'd0;
+			array_muxed12 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed13 <= 1'd0;
-	case (main_litedramcore_steerer_sel1)
+	array_muxed13 <= 1'd0;
+	case (litedramcore_steerer_sel1)
 		1'd0: begin
-			builder_array_muxed13 <= 1'd0;
+			array_muxed13 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed14 <= 3'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed14 <= 3'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed14 <= main_litedramcore_nop_ba[2:0];
+			array_muxed14 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed15 <= 14'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed15 <= 14'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed15 <= main_litedramcore_nop_a;
+			array_muxed15 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
+			array_muxed15 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed16 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed16 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed16 <= 1'd0;
+			array_muxed16 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed17 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed17 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed17 <= 1'd0;
+			array_muxed17 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed18 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed18 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed18 <= 1'd0;
+			array_muxed18 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed19 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed19 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed19 <= 1'd0;
+			array_muxed19 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed20 <= 1'd0;
-	case (main_litedramcore_steerer_sel2)
+	array_muxed20 <= 1'd0;
+	case (litedramcore_steerer_sel2)
 		1'd0: begin
-			builder_array_muxed20 <= 1'd0;
+			array_muxed20 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed21 <= 3'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed21 <= 3'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed21 <= main_litedramcore_nop_ba[2:0];
+			array_muxed21 <= litedramcore_nop_ba[2:0];
 		end
 		1'd1: begin
-			builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
 		end
 		2'd2: begin
-			builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
 		end
 		default: begin
-			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
+			array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed22 <= 14'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed22 <= 14'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed22 <= main_litedramcore_nop_a;
+			array_muxed22 <= litedramcore_nop_a;
 		end
 		1'd1: begin
-			builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
 		end
 		2'd2: begin
-			builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a;
+			array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
 		end
 		default: begin
-			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
+			array_muxed22 <= litedramcore_cmd_payload_a;
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed23 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed23 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed23 <= 1'd0;
+			array_muxed23 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
 		end
 		2'd2: begin
-			builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
 		end
 		default: begin
-			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+			array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed24 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed24 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed24 <= 1'd0;
+			array_muxed24 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
 		end
 		2'd2: begin
-			builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
 		end
 		default: begin
-			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+			array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed25 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed25 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed25 <= 1'd0;
+			array_muxed25 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
 		end
 		2'd2: begin
-			builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
 		end
 		default: begin
-			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+			array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed26 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed26 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed26 <= 1'd0;
+			array_muxed26 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
 		end
 		2'd2: begin
-			builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
 		end
 		default: begin
-			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+			array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
 		end
 	endcase
 end
 always @(*) begin
-	builder_array_muxed27 <= 1'd0;
-	case (main_litedramcore_steerer_sel3)
+	array_muxed27 <= 1'd0;
+	case (litedramcore_steerer_sel3)
 		1'd0: begin
-			builder_array_muxed27 <= 1'd0;
+			array_muxed27 <= 1'd0;
 		end
 		1'd1: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
 		end
 		2'd2: begin
-			builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
 		end
 		default: begin
-			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+			array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
 		end
 	endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
+assign xilinxasyncresetsynchronizerimpl0 = (~locked);
+assign xilinxasyncresetsynchronizerimpl1 = (~locked);
+assign xilinxasyncresetsynchronizerimpl2 = (~locked);
+assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 
 
 //------------------------------------------------------------------------------
@@ -11320,1044 +11763,1044 @@ assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-	if ((main_reset_counter != 1'd0)) begin
-		main_reset_counter <= (main_reset_counter - 1'd1);
+	if ((reset_counter != 1'd0)) begin
+		reset_counter <= (reset_counter - 1'd1);
 	end else begin
-		main_ic_reset <= 1'd0;
+		ic_reset <= 1'd0;
 	end
 	if (iodelay_rst) begin
-		main_reset_counter <= 4'd15;
-		main_ic_reset <= 1'd1;
+		reset_counter <= 4'd15;
+		ic_reset <= 1'd1;
 	end
 end
 
 always @(posedge sys_clk) begin
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
-	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-	main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+	a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+	a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
+	a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
+	a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
+	a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
-	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
+	a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+	a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
+	a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip0_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
+	a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value2 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
+	a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip1_value3 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
+	a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
+	a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip2_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
+	a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
+	a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip3_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
+	a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
+	a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip4_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
+	a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
+	a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip5_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
+	a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
+	a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip6_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
+	a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
+	a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip7_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
+	a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
+	a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip8_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
+	a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
+	a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip9_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
+	a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
+	a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip10_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
+	a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
+	a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip11_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
+	a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
+	a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip12_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
+	a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
+	a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip13_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
+	a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
+	a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip14_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
+	a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value0 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
-	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
-		main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
+	a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+		a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
 	end
-	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
+	if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+		a7ddrphy_bitslip15_value1 <= 3'd7;
 	end
-	main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
-	main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
-	main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
-	main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
-	main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
-	main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
-	main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
-	main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
-	main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
-	main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
-	main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
-	main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
-	if (main_litedramcore_inti_p0_rddata_valid) begin
-		main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata;
+	a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+	a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+	a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+	a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+	a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+	a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+	a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+	a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+	a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+	a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+	a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+	a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+	if (litedramcore_csr_dfi_p0_rddata_valid) begin
+		litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
 	end
-	if (main_litedramcore_inti_p1_rddata_valid) begin
-		main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata;
+	if (litedramcore_csr_dfi_p1_rddata_valid) begin
+		litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
 	end
-	if (main_litedramcore_inti_p2_rddata_valid) begin
-		main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata;
+	if (litedramcore_csr_dfi_p2_rddata_valid) begin
+		litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
 	end
-	if (main_litedramcore_inti_p3_rddata_valid) begin
-		main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata;
-	end
-	if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
-		main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
+	if (litedramcore_csr_dfi_p3_rddata_valid) begin
+		litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+	end
+	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_timer_count1 <= 10'd781;
+		litedramcore_timer_count1 <= 10'd781;
 	end
-	main_litedramcore_postponer_req_o <= 1'd0;
-	if (main_litedramcore_postponer_req_i) begin
-		main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
-		if ((main_litedramcore_postponer_count == 1'd0)) begin
-			main_litedramcore_postponer_count <= 1'd0;
-			main_litedramcore_postponer_req_o <= 1'd1;
-		end
+	litedramcore_postponer_req_o <= 1'd0;
+	if (litedramcore_postponer_req_i) begin
+		litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+		if ((litedramcore_postponer_count == 1'd0)) begin
+			litedramcore_postponer_count <= 1'd0;
+			litedramcore_postponer_req_o <= 1'd1;
+		end
 	end
-	if (main_litedramcore_sequencer_start0) begin
-		main_litedramcore_sequencer_count <= 1'd0;
-	end else begin
-		if (main_litedramcore_sequencer_done1) begin
-			if ((main_litedramcore_sequencer_count != 1'd0)) begin
-				main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
-			end
-		end
-	end
-	main_litedramcore_cmd_payload_a <= 1'd0;
-	main_litedramcore_cmd_payload_ba <= 1'd0;
-	main_litedramcore_cmd_payload_cas <= 1'd0;
-	main_litedramcore_cmd_payload_ras <= 1'd0;
-	main_litedramcore_cmd_payload_we <= 1'd0;
-	main_litedramcore_sequencer_done1 <= 1'd0;
-	if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd1;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd35)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd1;
-	end
-	if ((main_litedramcore_sequencer_counter == 6'd35)) begin
-		main_litedramcore_sequencer_counter <= 1'd0;
-	end else begin
-		if ((main_litedramcore_sequencer_counter != 1'd0)) begin
-			main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1);
+	if (litedramcore_sequencer_start0) begin
+		litedramcore_sequencer_count <= 1'd0;
+	end else begin
+		if (litedramcore_sequencer_done1) begin
+			if ((litedramcore_sequencer_count != 1'd0)) begin
+				litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+			end
+		end
+	end
+	litedramcore_cmd_payload_a <= 1'd0;
+	litedramcore_cmd_payload_ba <= 1'd0;
+	litedramcore_cmd_payload_cas <= 1'd0;
+	litedramcore_cmd_payload_ras <= 1'd0;
+	litedramcore_cmd_payload_we <= 1'd0;
+	litedramcore_sequencer_done1 <= 1'd0;
+	if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd1;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd0;
+	end
+	if ((litedramcore_sequencer_counter == 6'd35)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd1;
+	end
+	if ((litedramcore_sequencer_counter == 6'd35)) begin
+		litedramcore_sequencer_counter <= 1'd0;
+	end else begin
+		if ((litedramcore_sequencer_counter != 1'd0)) begin
+			litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_sequencer_start1) begin
-				main_litedramcore_sequencer_counter <= 1'd1;
+			if (litedramcore_sequencer_start1) begin
+				litedramcore_sequencer_counter <= 1'd1;
 			end
 		end
 	end
-	if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
-		main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
+	if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+		litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
 	end else begin
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
 	end
-	main_litedramcore_zqcs_executer_done <= 1'd0;
-	if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin
-		main_litedramcore_cmd_payload_a <= 11'd1024;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd1;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	litedramcore_zqcs_executer_done <= 1'd0;
+	if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+		litedramcore_cmd_payload_a <= 11'd1024;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd1;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_cmd_payload_a <= 1'd0;
-		main_litedramcore_cmd_payload_ba <= 1'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_zqcs_executer_done <= 1'd1;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_cmd_payload_a <= 1'd0;
+		litedramcore_cmd_payload_ba <= 1'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_zqcs_executer_done <= 1'd1;
 	end
-	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
-		main_litedramcore_zqcs_executer_counter <= 1'd0;
+	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+		litedramcore_zqcs_executer_counter <= 1'd0;
 	end else begin
-		if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin
-			main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1);
+		if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+			litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
 		end else begin
-			if (main_litedramcore_zqcs_executer_start) begin
-				main_litedramcore_zqcs_executer_counter <= 1'd1;
+			if (litedramcore_zqcs_executer_start) begin
+				litedramcore_zqcs_executer_counter <= 1'd1;
 			end
 		end
 	end
-	builder_refresher_state <= builder_refresher_next_state;
-	if (main_litedramcore_bankmachine0_row_close) begin
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
+	litedramcore_refresher_state <= litedramcore_refresher_next_state;
+	if (litedramcore_bankmachine0_row_close) begin
+		litedramcore_bankmachine0_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine0_row_open) begin
-			main_litedramcore_bankmachine0_row_opened <= 1'd1;
-			main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine0_row_open) begin
+			litedramcore_bankmachine0_row_opened <= 1'd1;
+			litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+		litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+		litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine0_twtpcon_valid) begin
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine0_twtpcon_valid) begin
+		litedramcore_bankmachine0_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
-			main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+			litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trccon_valid) begin
-		main_litedramcore_bankmachine0_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine0_trccon_valid) begin
+		litedramcore_bankmachine0_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+			litedramcore_bankmachine0_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+			litedramcore_bankmachine0_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
-			main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trccon_ready)) begin
+			litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine0_trascon_valid) begin
-		main_litedramcore_bankmachine0_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine0_trascon_valid) begin
+		litedramcore_bankmachine0_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+			litedramcore_bankmachine0_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+			litedramcore_bankmachine0_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
-			main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine0_trascon_ready)) begin
+			litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine0_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine0_state <= builder_bankmachine0_next_state;
-	if (main_litedramcore_bankmachine1_row_close) begin
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
+	litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+	if (litedramcore_bankmachine1_row_close) begin
+		litedramcore_bankmachine1_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine1_row_open) begin
-			main_litedramcore_bankmachine1_row_opened <= 1'd1;
-			main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine1_row_open) begin
+			litedramcore_bankmachine1_row_opened <= 1'd1;
+			litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+		litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+		litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine1_twtpcon_valid) begin
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine1_twtpcon_valid) begin
+		litedramcore_bankmachine1_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
-			main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+			litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trccon_valid) begin
-		main_litedramcore_bankmachine1_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine1_trccon_valid) begin
+		litedramcore_bankmachine1_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+			litedramcore_bankmachine1_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+			litedramcore_bankmachine1_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
-			main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trccon_ready)) begin
+			litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine1_trascon_valid) begin
-		main_litedramcore_bankmachine1_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine1_trascon_valid) begin
+		litedramcore_bankmachine1_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+			litedramcore_bankmachine1_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+			litedramcore_bankmachine1_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
-			main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine1_trascon_ready)) begin
+			litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine1_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine1_state <= builder_bankmachine1_next_state;
-	if (main_litedramcore_bankmachine2_row_close) begin
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
+	litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+	if (litedramcore_bankmachine2_row_close) begin
+		litedramcore_bankmachine2_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine2_row_open) begin
-			main_litedramcore_bankmachine2_row_opened <= 1'd1;
-			main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine2_row_open) begin
+			litedramcore_bankmachine2_row_opened <= 1'd1;
+			litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+		litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+		litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine2_twtpcon_valid) begin
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine2_twtpcon_valid) begin
+		litedramcore_bankmachine2_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
-			main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+			litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trccon_valid) begin
-		main_litedramcore_bankmachine2_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine2_trccon_valid) begin
+		litedramcore_bankmachine2_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+			litedramcore_bankmachine2_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+			litedramcore_bankmachine2_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
-			main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trccon_ready)) begin
+			litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine2_trascon_valid) begin
-		main_litedramcore_bankmachine2_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine2_trascon_valid) begin
+		litedramcore_bankmachine2_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+			litedramcore_bankmachine2_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+			litedramcore_bankmachine2_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
-			main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine2_trascon_ready)) begin
+			litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine2_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine2_state <= builder_bankmachine2_next_state;
-	if (main_litedramcore_bankmachine3_row_close) begin
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
+	litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+	if (litedramcore_bankmachine3_row_close) begin
+		litedramcore_bankmachine3_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine3_row_open) begin
-			main_litedramcore_bankmachine3_row_opened <= 1'd1;
-			main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine3_row_open) begin
+			litedramcore_bankmachine3_row_opened <= 1'd1;
+			litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+		litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+		litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine3_twtpcon_valid) begin
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine3_twtpcon_valid) begin
+		litedramcore_bankmachine3_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
-			main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+			litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trccon_valid) begin
-		main_litedramcore_bankmachine3_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine3_trccon_valid) begin
+		litedramcore_bankmachine3_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+			litedramcore_bankmachine3_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+			litedramcore_bankmachine3_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
-			main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trccon_ready)) begin
+			litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine3_trascon_valid) begin
-		main_litedramcore_bankmachine3_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine3_trascon_valid) begin
+		litedramcore_bankmachine3_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+			litedramcore_bankmachine3_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+			litedramcore_bankmachine3_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
-			main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine3_trascon_ready)) begin
+			litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine3_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine3_state <= builder_bankmachine3_next_state;
-	if (main_litedramcore_bankmachine4_row_close) begin
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
+	litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+	if (litedramcore_bankmachine4_row_close) begin
+		litedramcore_bankmachine4_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine4_row_open) begin
-			main_litedramcore_bankmachine4_row_opened <= 1'd1;
-			main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine4_row_open) begin
+			litedramcore_bankmachine4_row_opened <= 1'd1;
+			litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+		litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+		litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine4_twtpcon_valid) begin
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine4_twtpcon_valid) begin
+		litedramcore_bankmachine4_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
-			main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+			litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trccon_valid) begin
-		main_litedramcore_bankmachine4_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine4_trccon_valid) begin
+		litedramcore_bankmachine4_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+			litedramcore_bankmachine4_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+			litedramcore_bankmachine4_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
-			main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trccon_ready)) begin
+			litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine4_trascon_valid) begin
-		main_litedramcore_bankmachine4_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine4_trascon_valid) begin
+		litedramcore_bankmachine4_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+			litedramcore_bankmachine4_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+			litedramcore_bankmachine4_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
-			main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine4_trascon_ready)) begin
+			litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine4_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine4_state <= builder_bankmachine4_next_state;
-	if (main_litedramcore_bankmachine5_row_close) begin
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
+	litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+	if (litedramcore_bankmachine5_row_close) begin
+		litedramcore_bankmachine5_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine5_row_open) begin
-			main_litedramcore_bankmachine5_row_opened <= 1'd1;
-			main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine5_row_open) begin
+			litedramcore_bankmachine5_row_opened <= 1'd1;
+			litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+		litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+		litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine5_twtpcon_valid) begin
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine5_twtpcon_valid) begin
+		litedramcore_bankmachine5_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
-			main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+			litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trccon_valid) begin
-		main_litedramcore_bankmachine5_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine5_trccon_valid) begin
+		litedramcore_bankmachine5_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+			litedramcore_bankmachine5_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+			litedramcore_bankmachine5_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
-			main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trccon_ready)) begin
+			litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine5_trascon_valid) begin
-		main_litedramcore_bankmachine5_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine5_trascon_valid) begin
+		litedramcore_bankmachine5_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+			litedramcore_bankmachine5_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+			litedramcore_bankmachine5_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
-			main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine5_trascon_ready)) begin
+			litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine5_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine5_state <= builder_bankmachine5_next_state;
-	if (main_litedramcore_bankmachine6_row_close) begin
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
+	litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+	if (litedramcore_bankmachine6_row_close) begin
+		litedramcore_bankmachine6_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine6_row_open) begin
-			main_litedramcore_bankmachine6_row_opened <= 1'd1;
-			main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine6_row_open) begin
+			litedramcore_bankmachine6_row_opened <= 1'd1;
+			litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+		litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+		litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine6_twtpcon_valid) begin
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine6_twtpcon_valid) begin
+		litedramcore_bankmachine6_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
-			main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+			litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trccon_valid) begin
-		main_litedramcore_bankmachine6_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine6_trccon_valid) begin
+		litedramcore_bankmachine6_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+			litedramcore_bankmachine6_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+			litedramcore_bankmachine6_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
-			main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trccon_ready)) begin
+			litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine6_trascon_valid) begin
-		main_litedramcore_bankmachine6_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine6_trascon_valid) begin
+		litedramcore_bankmachine6_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+			litedramcore_bankmachine6_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+			litedramcore_bankmachine6_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
-			main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine6_trascon_ready)) begin
+			litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine6_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine6_state <= builder_bankmachine6_next_state;
-	if (main_litedramcore_bankmachine7_row_close) begin
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
+	litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+	if (litedramcore_bankmachine7_row_close) begin
+		litedramcore_bankmachine7_row_opened <= 1'd0;
 	end else begin
-		if (main_litedramcore_bankmachine7_row_open) begin
-			main_litedramcore_bankmachine7_row_opened <= 1'd1;
-			main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+		if (litedramcore_bankmachine7_row_open) begin
+			litedramcore_bankmachine7_row_opened <= 1'd1;
+			litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
 		end
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
 	end
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
 	end
-	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
-		if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
 		end
 	end else begin
-		if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
-			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+		if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
 		end
 	end
-	if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-		main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first;
-		main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+	if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+		litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+		litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
 	end
-	if (main_litedramcore_bankmachine7_twtpcon_valid) begin
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+	if (litedramcore_bankmachine7_twtpcon_valid) begin
+		litedramcore_bankmachine7_twtpcon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+			litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
-			main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+			litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+			if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+				litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trccon_valid) begin
-		main_litedramcore_bankmachine7_trccon_count <= 3'd5;
+	if (litedramcore_bankmachine7_trccon_valid) begin
+		litedramcore_bankmachine7_trccon_count <= 3'd5;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+			litedramcore_bankmachine7_trccon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+			litedramcore_bankmachine7_trccon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
-			main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trccon_ready)) begin
+			litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trccon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_bankmachine7_trascon_valid) begin
-		main_litedramcore_bankmachine7_trascon_count <= 3'd4;
+	if (litedramcore_bankmachine7_trascon_valid) begin
+		litedramcore_bankmachine7_trascon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+			litedramcore_bankmachine7_trascon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+			litedramcore_bankmachine7_trascon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
-			main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
-			if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-				main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+		if ((~litedramcore_bankmachine7_trascon_ready)) begin
+			litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+			if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+				litedramcore_bankmachine7_trascon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_bankmachine7_state <= builder_bankmachine7_next_state;
-	if ((~main_litedramcore_en0)) begin
-		main_litedramcore_time0 <= 5'd31;
+	litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+	if ((~litedramcore_en0)) begin
+		litedramcore_time0 <= 5'd31;
 	end else begin
-		if ((~main_litedramcore_max_time0)) begin
-			main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
+		if ((~litedramcore_max_time0)) begin
+			litedramcore_time0 <= (litedramcore_time0 - 1'd1);
 		end
 	end
-	if ((~main_litedramcore_en1)) begin
-		main_litedramcore_time1 <= 4'd15;
+	if ((~litedramcore_en1)) begin
+		litedramcore_time1 <= 4'd15;
 	end else begin
-		if ((~main_litedramcore_max_time1)) begin
-			main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
+		if ((~litedramcore_max_time1)) begin
+			litedramcore_time1 <= (litedramcore_time1 - 1'd1);
 		end
 	end
-	if (main_litedramcore_choose_cmd_ce) begin
-		case (main_litedramcore_choose_cmd_grant)
+	if (litedramcore_choose_cmd_ce) begin
+		case (litedramcore_choose_cmd_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_cmd_request[1]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd1;
+				if (litedramcore_choose_cmd_request[1]) begin
+					litedramcore_choose_cmd_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[2]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd2;
+					if (litedramcore_choose_cmd_request[2]) begin
+						litedramcore_choose_cmd_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[3]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd3;
+						if (litedramcore_choose_cmd_request[3]) begin
+							litedramcore_choose_cmd_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[4]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd4;
+							if (litedramcore_choose_cmd_request[4]) begin
+								litedramcore_choose_cmd_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[5]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd5;
+								if (litedramcore_choose_cmd_request[5]) begin
+									litedramcore_choose_cmd_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[6]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd6;
+									if (litedramcore_choose_cmd_request[6]) begin
+										litedramcore_choose_cmd_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[7]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd7;
+										if (litedramcore_choose_cmd_request[7]) begin
+											litedramcore_choose_cmd_grant <= 3'd7;
 										end
 									end
 								end
@@ -12367,26 +12810,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_cmd_request[2]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd2;
+				if (litedramcore_choose_cmd_request[2]) begin
+					litedramcore_choose_cmd_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[3]) begin
-						main_litedramcore_choose_cmd_grant <= 2'd3;
+					if (litedramcore_choose_cmd_request[3]) begin
+						litedramcore_choose_cmd_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[4]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd4;
+						if (litedramcore_choose_cmd_request[4]) begin
+							litedramcore_choose_cmd_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[5]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd5;
+							if (litedramcore_choose_cmd_request[5]) begin
+								litedramcore_choose_cmd_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[6]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd6;
+								if (litedramcore_choose_cmd_request[6]) begin
+									litedramcore_choose_cmd_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[7]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd7;
+									if (litedramcore_choose_cmd_request[7]) begin
+										litedramcore_choose_cmd_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[0]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd0;
+										if (litedramcore_choose_cmd_request[0]) begin
+											litedramcore_choose_cmd_grant <= 1'd0;
 										end
 									end
 								end
@@ -12396,26 +12839,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_cmd_request[3]) begin
-					main_litedramcore_choose_cmd_grant <= 2'd3;
+				if (litedramcore_choose_cmd_request[3]) begin
+					litedramcore_choose_cmd_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[4]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd4;
+					if (litedramcore_choose_cmd_request[4]) begin
+						litedramcore_choose_cmd_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[5]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd5;
+						if (litedramcore_choose_cmd_request[5]) begin
+							litedramcore_choose_cmd_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[6]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd6;
+							if (litedramcore_choose_cmd_request[6]) begin
+								litedramcore_choose_cmd_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[7]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd7;
+								if (litedramcore_choose_cmd_request[7]) begin
+									litedramcore_choose_cmd_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[0]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd0;
+									if (litedramcore_choose_cmd_request[0]) begin
+										litedramcore_choose_cmd_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[1]) begin
-											main_litedramcore_choose_cmd_grant <= 1'd1;
+										if (litedramcore_choose_cmd_request[1]) begin
+											litedramcore_choose_cmd_grant <= 1'd1;
 										end
 									end
 								end
@@ -12425,26 +12868,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_cmd_request[4]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd4;
+				if (litedramcore_choose_cmd_request[4]) begin
+					litedramcore_choose_cmd_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[5]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd5;
+					if (litedramcore_choose_cmd_request[5]) begin
+						litedramcore_choose_cmd_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[6]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd6;
+						if (litedramcore_choose_cmd_request[6]) begin
+							litedramcore_choose_cmd_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[7]) begin
-								main_litedramcore_choose_cmd_grant <= 3'd7;
+							if (litedramcore_choose_cmd_request[7]) begin
+								litedramcore_choose_cmd_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[0]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd0;
+								if (litedramcore_choose_cmd_request[0]) begin
+									litedramcore_choose_cmd_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[1]) begin
-										main_litedramcore_choose_cmd_grant <= 1'd1;
+									if (litedramcore_choose_cmd_request[1]) begin
+										litedramcore_choose_cmd_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[2]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd2;
+										if (litedramcore_choose_cmd_request[2]) begin
+											litedramcore_choose_cmd_grant <= 2'd2;
 										end
 									end
 								end
@@ -12454,26 +12897,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_cmd_request[5]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd5;
+				if (litedramcore_choose_cmd_request[5]) begin
+					litedramcore_choose_cmd_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[6]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd6;
+					if (litedramcore_choose_cmd_request[6]) begin
+						litedramcore_choose_cmd_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[7]) begin
-							main_litedramcore_choose_cmd_grant <= 3'd7;
+						if (litedramcore_choose_cmd_request[7]) begin
+							litedramcore_choose_cmd_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[0]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd0;
+							if (litedramcore_choose_cmd_request[0]) begin
+								litedramcore_choose_cmd_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[1]) begin
-									main_litedramcore_choose_cmd_grant <= 1'd1;
+								if (litedramcore_choose_cmd_request[1]) begin
+									litedramcore_choose_cmd_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[2]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd2;
+									if (litedramcore_choose_cmd_request[2]) begin
+										litedramcore_choose_cmd_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[3]) begin
-											main_litedramcore_choose_cmd_grant <= 2'd3;
+										if (litedramcore_choose_cmd_request[3]) begin
+											litedramcore_choose_cmd_grant <= 2'd3;
 										end
 									end
 								end
@@ -12483,26 +12926,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_cmd_request[6]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd6;
+				if (litedramcore_choose_cmd_request[6]) begin
+					litedramcore_choose_cmd_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[7]) begin
-						main_litedramcore_choose_cmd_grant <= 3'd7;
+					if (litedramcore_choose_cmd_request[7]) begin
+						litedramcore_choose_cmd_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[0]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd0;
+						if (litedramcore_choose_cmd_request[0]) begin
+							litedramcore_choose_cmd_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[1]) begin
-								main_litedramcore_choose_cmd_grant <= 1'd1;
+							if (litedramcore_choose_cmd_request[1]) begin
+								litedramcore_choose_cmd_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[2]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd2;
+								if (litedramcore_choose_cmd_request[2]) begin
+									litedramcore_choose_cmd_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[3]) begin
-										main_litedramcore_choose_cmd_grant <= 2'd3;
+									if (litedramcore_choose_cmd_request[3]) begin
+										litedramcore_choose_cmd_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[4]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd4;
+										if (litedramcore_choose_cmd_request[4]) begin
+											litedramcore_choose_cmd_grant <= 3'd4;
 										end
 									end
 								end
@@ -12512,26 +12955,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_cmd_request[7]) begin
-					main_litedramcore_choose_cmd_grant <= 3'd7;
+				if (litedramcore_choose_cmd_request[7]) begin
+					litedramcore_choose_cmd_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[0]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd0;
+					if (litedramcore_choose_cmd_request[0]) begin
+						litedramcore_choose_cmd_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[1]) begin
-							main_litedramcore_choose_cmd_grant <= 1'd1;
+						if (litedramcore_choose_cmd_request[1]) begin
+							litedramcore_choose_cmd_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[2]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd2;
+							if (litedramcore_choose_cmd_request[2]) begin
+								litedramcore_choose_cmd_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[3]) begin
-									main_litedramcore_choose_cmd_grant <= 2'd3;
+								if (litedramcore_choose_cmd_request[3]) begin
+									litedramcore_choose_cmd_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[4]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd4;
+									if (litedramcore_choose_cmd_request[4]) begin
+										litedramcore_choose_cmd_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[5]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd5;
+										if (litedramcore_choose_cmd_request[5]) begin
+											litedramcore_choose_cmd_grant <= 3'd5;
 										end
 									end
 								end
@@ -12541,26 +12984,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_cmd_request[0]) begin
-					main_litedramcore_choose_cmd_grant <= 1'd0;
+				if (litedramcore_choose_cmd_request[0]) begin
+					litedramcore_choose_cmd_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_cmd_request[1]) begin
-						main_litedramcore_choose_cmd_grant <= 1'd1;
+					if (litedramcore_choose_cmd_request[1]) begin
+						litedramcore_choose_cmd_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_cmd_request[2]) begin
-							main_litedramcore_choose_cmd_grant <= 2'd2;
+						if (litedramcore_choose_cmd_request[2]) begin
+							litedramcore_choose_cmd_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_cmd_request[3]) begin
-								main_litedramcore_choose_cmd_grant <= 2'd3;
+							if (litedramcore_choose_cmd_request[3]) begin
+								litedramcore_choose_cmd_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_cmd_request[4]) begin
-									main_litedramcore_choose_cmd_grant <= 3'd4;
+								if (litedramcore_choose_cmd_request[4]) begin
+									litedramcore_choose_cmd_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_cmd_request[5]) begin
-										main_litedramcore_choose_cmd_grant <= 3'd5;
+									if (litedramcore_choose_cmd_request[5]) begin
+										litedramcore_choose_cmd_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_cmd_request[6]) begin
-											main_litedramcore_choose_cmd_grant <= 3'd6;
+										if (litedramcore_choose_cmd_request[6]) begin
+											litedramcore_choose_cmd_grant <= 3'd6;
 										end
 									end
 								end
@@ -12571,29 +13014,29 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	if (main_litedramcore_choose_req_ce) begin
-		case (main_litedramcore_choose_req_grant)
+	if (litedramcore_choose_req_ce) begin
+		case (litedramcore_choose_req_grant)
 			1'd0: begin
-				if (main_litedramcore_choose_req_request[1]) begin
-					main_litedramcore_choose_req_grant <= 1'd1;
+				if (litedramcore_choose_req_request[1]) begin
+					litedramcore_choose_req_grant <= 1'd1;
 				end else begin
-					if (main_litedramcore_choose_req_request[2]) begin
-						main_litedramcore_choose_req_grant <= 2'd2;
+					if (litedramcore_choose_req_request[2]) begin
+						litedramcore_choose_req_grant <= 2'd2;
 					end else begin
-						if (main_litedramcore_choose_req_request[3]) begin
-							main_litedramcore_choose_req_grant <= 2'd3;
+						if (litedramcore_choose_req_request[3]) begin
+							litedramcore_choose_req_grant <= 2'd3;
 						end else begin
-							if (main_litedramcore_choose_req_request[4]) begin
-								main_litedramcore_choose_req_grant <= 3'd4;
+							if (litedramcore_choose_req_request[4]) begin
+								litedramcore_choose_req_grant <= 3'd4;
 							end else begin
-								if (main_litedramcore_choose_req_request[5]) begin
-									main_litedramcore_choose_req_grant <= 3'd5;
+								if (litedramcore_choose_req_request[5]) begin
+									litedramcore_choose_req_grant <= 3'd5;
 								end else begin
-									if (main_litedramcore_choose_req_request[6]) begin
-										main_litedramcore_choose_req_grant <= 3'd6;
+									if (litedramcore_choose_req_request[6]) begin
+										litedramcore_choose_req_grant <= 3'd6;
 									end else begin
-										if (main_litedramcore_choose_req_request[7]) begin
-											main_litedramcore_choose_req_grant <= 3'd7;
+										if (litedramcore_choose_req_request[7]) begin
+											litedramcore_choose_req_grant <= 3'd7;
 										end
 									end
 								end
@@ -12603,26 +13046,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			1'd1: begin
-				if (main_litedramcore_choose_req_request[2]) begin
-					main_litedramcore_choose_req_grant <= 2'd2;
+				if (litedramcore_choose_req_request[2]) begin
+					litedramcore_choose_req_grant <= 2'd2;
 				end else begin
-					if (main_litedramcore_choose_req_request[3]) begin
-						main_litedramcore_choose_req_grant <= 2'd3;
+					if (litedramcore_choose_req_request[3]) begin
+						litedramcore_choose_req_grant <= 2'd3;
 					end else begin
-						if (main_litedramcore_choose_req_request[4]) begin
-							main_litedramcore_choose_req_grant <= 3'd4;
+						if (litedramcore_choose_req_request[4]) begin
+							litedramcore_choose_req_grant <= 3'd4;
 						end else begin
-							if (main_litedramcore_choose_req_request[5]) begin
-								main_litedramcore_choose_req_grant <= 3'd5;
+							if (litedramcore_choose_req_request[5]) begin
+								litedramcore_choose_req_grant <= 3'd5;
 							end else begin
-								if (main_litedramcore_choose_req_request[6]) begin
-									main_litedramcore_choose_req_grant <= 3'd6;
+								if (litedramcore_choose_req_request[6]) begin
+									litedramcore_choose_req_grant <= 3'd6;
 								end else begin
-									if (main_litedramcore_choose_req_request[7]) begin
-										main_litedramcore_choose_req_grant <= 3'd7;
+									if (litedramcore_choose_req_request[7]) begin
+										litedramcore_choose_req_grant <= 3'd7;
 									end else begin
-										if (main_litedramcore_choose_req_request[0]) begin
-											main_litedramcore_choose_req_grant <= 1'd0;
+										if (litedramcore_choose_req_request[0]) begin
+											litedramcore_choose_req_grant <= 1'd0;
 										end
 									end
 								end
@@ -12632,26 +13075,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd2: begin
-				if (main_litedramcore_choose_req_request[3]) begin
-					main_litedramcore_choose_req_grant <= 2'd3;
+				if (litedramcore_choose_req_request[3]) begin
+					litedramcore_choose_req_grant <= 2'd3;
 				end else begin
-					if (main_litedramcore_choose_req_request[4]) begin
-						main_litedramcore_choose_req_grant <= 3'd4;
+					if (litedramcore_choose_req_request[4]) begin
+						litedramcore_choose_req_grant <= 3'd4;
 					end else begin
-						if (main_litedramcore_choose_req_request[5]) begin
-							main_litedramcore_choose_req_grant <= 3'd5;
+						if (litedramcore_choose_req_request[5]) begin
+							litedramcore_choose_req_grant <= 3'd5;
 						end else begin
-							if (main_litedramcore_choose_req_request[6]) begin
-								main_litedramcore_choose_req_grant <= 3'd6;
+							if (litedramcore_choose_req_request[6]) begin
+								litedramcore_choose_req_grant <= 3'd6;
 							end else begin
-								if (main_litedramcore_choose_req_request[7]) begin
-									main_litedramcore_choose_req_grant <= 3'd7;
+								if (litedramcore_choose_req_request[7]) begin
+									litedramcore_choose_req_grant <= 3'd7;
 								end else begin
-									if (main_litedramcore_choose_req_request[0]) begin
-										main_litedramcore_choose_req_grant <= 1'd0;
+									if (litedramcore_choose_req_request[0]) begin
+										litedramcore_choose_req_grant <= 1'd0;
 									end else begin
-										if (main_litedramcore_choose_req_request[1]) begin
-											main_litedramcore_choose_req_grant <= 1'd1;
+										if (litedramcore_choose_req_request[1]) begin
+											litedramcore_choose_req_grant <= 1'd1;
 										end
 									end
 								end
@@ -12661,26 +13104,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			2'd3: begin
-				if (main_litedramcore_choose_req_request[4]) begin
-					main_litedramcore_choose_req_grant <= 3'd4;
+				if (litedramcore_choose_req_request[4]) begin
+					litedramcore_choose_req_grant <= 3'd4;
 				end else begin
-					if (main_litedramcore_choose_req_request[5]) begin
-						main_litedramcore_choose_req_grant <= 3'd5;
+					if (litedramcore_choose_req_request[5]) begin
+						litedramcore_choose_req_grant <= 3'd5;
 					end else begin
-						if (main_litedramcore_choose_req_request[6]) begin
-							main_litedramcore_choose_req_grant <= 3'd6;
+						if (litedramcore_choose_req_request[6]) begin
+							litedramcore_choose_req_grant <= 3'd6;
 						end else begin
-							if (main_litedramcore_choose_req_request[7]) begin
-								main_litedramcore_choose_req_grant <= 3'd7;
+							if (litedramcore_choose_req_request[7]) begin
+								litedramcore_choose_req_grant <= 3'd7;
 							end else begin
-								if (main_litedramcore_choose_req_request[0]) begin
-									main_litedramcore_choose_req_grant <= 1'd0;
+								if (litedramcore_choose_req_request[0]) begin
+									litedramcore_choose_req_grant <= 1'd0;
 								end else begin
-									if (main_litedramcore_choose_req_request[1]) begin
-										main_litedramcore_choose_req_grant <= 1'd1;
+									if (litedramcore_choose_req_request[1]) begin
+										litedramcore_choose_req_grant <= 1'd1;
 									end else begin
-										if (main_litedramcore_choose_req_request[2]) begin
-											main_litedramcore_choose_req_grant <= 2'd2;
+										if (litedramcore_choose_req_request[2]) begin
+											litedramcore_choose_req_grant <= 2'd2;
 										end
 									end
 								end
@@ -12690,26 +13133,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd4: begin
-				if (main_litedramcore_choose_req_request[5]) begin
-					main_litedramcore_choose_req_grant <= 3'd5;
+				if (litedramcore_choose_req_request[5]) begin
+					litedramcore_choose_req_grant <= 3'd5;
 				end else begin
-					if (main_litedramcore_choose_req_request[6]) begin
-						main_litedramcore_choose_req_grant <= 3'd6;
+					if (litedramcore_choose_req_request[6]) begin
+						litedramcore_choose_req_grant <= 3'd6;
 					end else begin
-						if (main_litedramcore_choose_req_request[7]) begin
-							main_litedramcore_choose_req_grant <= 3'd7;
+						if (litedramcore_choose_req_request[7]) begin
+							litedramcore_choose_req_grant <= 3'd7;
 						end else begin
-							if (main_litedramcore_choose_req_request[0]) begin
-								main_litedramcore_choose_req_grant <= 1'd0;
+							if (litedramcore_choose_req_request[0]) begin
+								litedramcore_choose_req_grant <= 1'd0;
 							end else begin
-								if (main_litedramcore_choose_req_request[1]) begin
-									main_litedramcore_choose_req_grant <= 1'd1;
+								if (litedramcore_choose_req_request[1]) begin
+									litedramcore_choose_req_grant <= 1'd1;
 								end else begin
-									if (main_litedramcore_choose_req_request[2]) begin
-										main_litedramcore_choose_req_grant <= 2'd2;
+									if (litedramcore_choose_req_request[2]) begin
+										litedramcore_choose_req_grant <= 2'd2;
 									end else begin
-										if (main_litedramcore_choose_req_request[3]) begin
-											main_litedramcore_choose_req_grant <= 2'd3;
+										if (litedramcore_choose_req_request[3]) begin
+											litedramcore_choose_req_grant <= 2'd3;
 										end
 									end
 								end
@@ -12719,26 +13162,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd5: begin
-				if (main_litedramcore_choose_req_request[6]) begin
-					main_litedramcore_choose_req_grant <= 3'd6;
+				if (litedramcore_choose_req_request[6]) begin
+					litedramcore_choose_req_grant <= 3'd6;
 				end else begin
-					if (main_litedramcore_choose_req_request[7]) begin
-						main_litedramcore_choose_req_grant <= 3'd7;
+					if (litedramcore_choose_req_request[7]) begin
+						litedramcore_choose_req_grant <= 3'd7;
 					end else begin
-						if (main_litedramcore_choose_req_request[0]) begin
-							main_litedramcore_choose_req_grant <= 1'd0;
+						if (litedramcore_choose_req_request[0]) begin
+							litedramcore_choose_req_grant <= 1'd0;
 						end else begin
-							if (main_litedramcore_choose_req_request[1]) begin
-								main_litedramcore_choose_req_grant <= 1'd1;
+							if (litedramcore_choose_req_request[1]) begin
+								litedramcore_choose_req_grant <= 1'd1;
 							end else begin
-								if (main_litedramcore_choose_req_request[2]) begin
-									main_litedramcore_choose_req_grant <= 2'd2;
+								if (litedramcore_choose_req_request[2]) begin
+									litedramcore_choose_req_grant <= 2'd2;
 								end else begin
-									if (main_litedramcore_choose_req_request[3]) begin
-										main_litedramcore_choose_req_grant <= 2'd3;
+									if (litedramcore_choose_req_request[3]) begin
+										litedramcore_choose_req_grant <= 2'd3;
 									end else begin
-										if (main_litedramcore_choose_req_request[4]) begin
-											main_litedramcore_choose_req_grant <= 3'd4;
+										if (litedramcore_choose_req_request[4]) begin
+											litedramcore_choose_req_grant <= 3'd4;
 										end
 									end
 								end
@@ -12748,26 +13191,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd6: begin
-				if (main_litedramcore_choose_req_request[7]) begin
-					main_litedramcore_choose_req_grant <= 3'd7;
+				if (litedramcore_choose_req_request[7]) begin
+					litedramcore_choose_req_grant <= 3'd7;
 				end else begin
-					if (main_litedramcore_choose_req_request[0]) begin
-						main_litedramcore_choose_req_grant <= 1'd0;
+					if (litedramcore_choose_req_request[0]) begin
+						litedramcore_choose_req_grant <= 1'd0;
 					end else begin
-						if (main_litedramcore_choose_req_request[1]) begin
-							main_litedramcore_choose_req_grant <= 1'd1;
+						if (litedramcore_choose_req_request[1]) begin
+							litedramcore_choose_req_grant <= 1'd1;
 						end else begin
-							if (main_litedramcore_choose_req_request[2]) begin
-								main_litedramcore_choose_req_grant <= 2'd2;
+							if (litedramcore_choose_req_request[2]) begin
+								litedramcore_choose_req_grant <= 2'd2;
 							end else begin
-								if (main_litedramcore_choose_req_request[3]) begin
-									main_litedramcore_choose_req_grant <= 2'd3;
+								if (litedramcore_choose_req_request[3]) begin
+									litedramcore_choose_req_grant <= 2'd3;
 								end else begin
-									if (main_litedramcore_choose_req_request[4]) begin
-										main_litedramcore_choose_req_grant <= 3'd4;
+									if (litedramcore_choose_req_request[4]) begin
+										litedramcore_choose_req_grant <= 3'd4;
 									end else begin
-										if (main_litedramcore_choose_req_request[5]) begin
-											main_litedramcore_choose_req_grant <= 3'd5;
+										if (litedramcore_choose_req_request[5]) begin
+											litedramcore_choose_req_grant <= 3'd5;
 										end
 									end
 								end
@@ -12777,26 +13220,26 @@ always @(posedge sys_clk) begin
 				end
 			end
 			3'd7: begin
-				if (main_litedramcore_choose_req_request[0]) begin
-					main_litedramcore_choose_req_grant <= 1'd0;
+				if (litedramcore_choose_req_request[0]) begin
+					litedramcore_choose_req_grant <= 1'd0;
 				end else begin
-					if (main_litedramcore_choose_req_request[1]) begin
-						main_litedramcore_choose_req_grant <= 1'd1;
+					if (litedramcore_choose_req_request[1]) begin
+						litedramcore_choose_req_grant <= 1'd1;
 					end else begin
-						if (main_litedramcore_choose_req_request[2]) begin
-							main_litedramcore_choose_req_grant <= 2'd2;
+						if (litedramcore_choose_req_request[2]) begin
+							litedramcore_choose_req_grant <= 2'd2;
 						end else begin
-							if (main_litedramcore_choose_req_request[3]) begin
-								main_litedramcore_choose_req_grant <= 2'd3;
+							if (litedramcore_choose_req_request[3]) begin
+								litedramcore_choose_req_grant <= 2'd3;
 							end else begin
-								if (main_litedramcore_choose_req_request[4]) begin
-									main_litedramcore_choose_req_grant <= 3'd4;
+								if (litedramcore_choose_req_request[4]) begin
+									litedramcore_choose_req_grant <= 3'd4;
 								end else begin
-									if (main_litedramcore_choose_req_request[5]) begin
-										main_litedramcore_choose_req_grant <= 3'd5;
+									if (litedramcore_choose_req_request[5]) begin
+										litedramcore_choose_req_grant <= 3'd5;
 									end else begin
-										if (main_litedramcore_choose_req_request[6]) begin
-											main_litedramcore_choose_req_grant <= 3'd6;
+										if (litedramcore_choose_req_request[6]) begin
+											litedramcore_choose_req_grant <= 3'd6;
 										end
 									end
 								end
@@ -12807,644 +13250,644 @@ always @(posedge sys_clk) begin
 			end
 		endcase
 	end
-	main_litedramcore_dfi_p0_cs_n <= 1'd0;
-	main_litedramcore_dfi_p0_bank <= builder_array_muxed0;
-	main_litedramcore_dfi_p0_address <= builder_array_muxed1;
-	main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2);
-	main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3);
-	main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4);
-	main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5;
-	main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6;
-	main_litedramcore_dfi_p1_cs_n <= 1'd0;
-	main_litedramcore_dfi_p1_bank <= builder_array_muxed7;
-	main_litedramcore_dfi_p1_address <= builder_array_muxed8;
-	main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9);
-	main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10);
-	main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11);
-	main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12;
-	main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13;
-	main_litedramcore_dfi_p2_cs_n <= 1'd0;
-	main_litedramcore_dfi_p2_bank <= builder_array_muxed14;
-	main_litedramcore_dfi_p2_address <= builder_array_muxed15;
-	main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16);
-	main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17);
-	main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18);
-	main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19;
-	main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20;
-	main_litedramcore_dfi_p3_cs_n <= 1'd0;
-	main_litedramcore_dfi_p3_bank <= builder_array_muxed21;
-	main_litedramcore_dfi_p3_address <= builder_array_muxed22;
-	main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23);
-	main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24);
-	main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25);
-	main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26;
-	main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27;
-	if (main_litedramcore_trrdcon_valid) begin
-		main_litedramcore_trrdcon_count <= 1'd1;
+	litedramcore_dfi_p0_cs_n <= 1'd0;
+	litedramcore_dfi_p0_bank <= array_muxed0;
+	litedramcore_dfi_p0_address <= array_muxed1;
+	litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+	litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+	litedramcore_dfi_p0_we_n <= (~array_muxed4);
+	litedramcore_dfi_p0_rddata_en <= array_muxed5;
+	litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+	litedramcore_dfi_p1_cs_n <= 1'd0;
+	litedramcore_dfi_p1_bank <= array_muxed7;
+	litedramcore_dfi_p1_address <= array_muxed8;
+	litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+	litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+	litedramcore_dfi_p1_we_n <= (~array_muxed11);
+	litedramcore_dfi_p1_rddata_en <= array_muxed12;
+	litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+	litedramcore_dfi_p2_cs_n <= 1'd0;
+	litedramcore_dfi_p2_bank <= array_muxed14;
+	litedramcore_dfi_p2_address <= array_muxed15;
+	litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+	litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+	litedramcore_dfi_p2_we_n <= (~array_muxed18);
+	litedramcore_dfi_p2_rddata_en <= array_muxed19;
+	litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+	litedramcore_dfi_p3_cs_n <= 1'd0;
+	litedramcore_dfi_p3_bank <= array_muxed21;
+	litedramcore_dfi_p3_address <= array_muxed22;
+	litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+	litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+	litedramcore_dfi_p3_we_n <= (~array_muxed25);
+	litedramcore_dfi_p3_rddata_en <= array_muxed26;
+	litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+	if (litedramcore_trrdcon_valid) begin
+		litedramcore_trrdcon_count <= 1'd1;
 		if (1'd0) begin
-			main_litedramcore_trrdcon_ready <= 1'd1;
+			litedramcore_trrdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_trrdcon_ready <= 1'd0;
+			litedramcore_trrdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_trrdcon_ready)) begin
-			main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
-			if ((main_litedramcore_trrdcon_count == 1'd1)) begin
-				main_litedramcore_trrdcon_ready <= 1'd1;
+		if ((~litedramcore_trrdcon_ready)) begin
+			litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+			if ((litedramcore_trrdcon_count == 1'd1)) begin
+				litedramcore_trrdcon_ready <= 1'd1;
 			end
 		end
 	end
-	main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
-	if ((main_litedramcore_tfawcon_count < 3'd4)) begin
-		if ((main_litedramcore_tfawcon_count == 2'd3)) begin
-			main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
+	litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+	if ((litedramcore_tfawcon_count < 3'd4)) begin
+		if ((litedramcore_tfawcon_count == 2'd3)) begin
+			litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
 		end else begin
-			main_litedramcore_tfawcon_ready <= 1'd1;
+			litedramcore_tfawcon_ready <= 1'd1;
 		end
 	end
-	if (main_litedramcore_tccdcon_valid) begin
-		main_litedramcore_tccdcon_count <= 1'd0;
+	if (litedramcore_tccdcon_valid) begin
+		litedramcore_tccdcon_count <= 1'd0;
 		if (1'd1) begin
-			main_litedramcore_tccdcon_ready <= 1'd1;
+			litedramcore_tccdcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_tccdcon_ready <= 1'd0;
+			litedramcore_tccdcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_tccdcon_ready)) begin
-			main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
-			if ((main_litedramcore_tccdcon_count == 1'd1)) begin
-				main_litedramcore_tccdcon_ready <= 1'd1;
+		if ((~litedramcore_tccdcon_ready)) begin
+			litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+			if ((litedramcore_tccdcon_count == 1'd1)) begin
+				litedramcore_tccdcon_ready <= 1'd1;
 			end
 		end
 	end
-	if (main_litedramcore_twtrcon_valid) begin
-		main_litedramcore_twtrcon_count <= 3'd4;
+	if (litedramcore_twtrcon_valid) begin
+		litedramcore_twtrcon_count <= 3'd4;
 		if (1'd0) begin
-			main_litedramcore_twtrcon_ready <= 1'd1;
+			litedramcore_twtrcon_ready <= 1'd1;
 		end else begin
-			main_litedramcore_twtrcon_ready <= 1'd0;
+			litedramcore_twtrcon_ready <= 1'd0;
 		end
 	end else begin
-		if ((~main_litedramcore_twtrcon_ready)) begin
-			main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
-			if ((main_litedramcore_twtrcon_count == 1'd1)) begin
-				main_litedramcore_twtrcon_ready <= 1'd1;
+		if ((~litedramcore_twtrcon_ready)) begin
+			litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+			if ((litedramcore_twtrcon_count == 1'd1)) begin
+				litedramcore_twtrcon_ready <= 1'd1;
 			end
 		end
 	end
-	builder_multiplexer_state <= builder_multiplexer_next_state;
-	builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
-	builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
-	builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
-	builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
-	builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
-	builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
-	builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
-	builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
-	builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
-	builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
-	builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
-	builder_state <= builder_next_state;
-	if (builder_litedramcore_dat_w_next_value_ce0) begin
-		builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0;
+	litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+	litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+	litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+	litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+	litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+	litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+	litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+	litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+	litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+	litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+	litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+	litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+	litedramcore_state <= litedramcore_next_state;
+	if (litedramcore_dat_w_next_value_ce0) begin
+		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
 	end
-	if (builder_litedramcore_adr_next_value_ce1) begin
-		builder_litedramcore_adr <= builder_litedramcore_adr_next_value1;
+	if (litedramcore_adr_next_value_ce1) begin
+		litedramcore_adr <= litedramcore_adr_next_value1;
 	end
-	if (builder_litedramcore_we_next_value_ce2) begin
-		builder_litedramcore_we <= builder_litedramcore_we_next_value2;
+	if (litedramcore_we_next_value_ce2) begin
+		litedramcore_we <= litedramcore_we_next_value2;
 	end
-	builder_interface0_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank0_sel) begin
-		case (builder_interface0_bank_bus_adr[8:0])
+	interface0_bank_bus_dat_r <= 1'd0;
+	if (csrbank0_sel) begin
+		case (interface0_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
 			end
 			1'd1: begin
-				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
+				interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank0_init_done0_re) begin
-		main_init_done_storage <= builder_csrbank0_init_done0_r;
+	if (csrbank0_init_done0_re) begin
+		init_done_storage <= csrbank0_init_done0_r;
 	end
-	main_init_done_re <= builder_csrbank0_init_done0_re;
-	if (builder_csrbank0_init_error0_re) begin
-		main_init_error_storage <= builder_csrbank0_init_error0_r;
+	init_done_re <= csrbank0_init_done0_re;
+	if (csrbank0_init_error0_re) begin
+		init_error_storage <= csrbank0_init_error0_r;
 	end
-	main_init_error_re <= builder_csrbank0_init_error0_re;
-	builder_interface1_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank1_sel) begin
-		case (builder_interface1_bank_bus_adr[8:0])
+	init_error_re <= csrbank0_init_error0_re;
+	interface1_bank_bus_dat_r <= 1'd0;
+	if (csrbank1_sel) begin
+		case (interface1_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rst0_w;
 			end
 			1'd1: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
 			end
 			2'd2: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
+				interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
 			end
 			2'd3: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
+				interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
 			end
 			3'd4: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
 			end
 			3'd5: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
 			end
 			3'd6: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
 			end
 			3'd7: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
 			end
 			4'd8: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
 			end
 			4'd9: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
 			end
 			4'd10: begin
-				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
+				interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
 			end
 			4'd11: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
 			end
 			4'd12: begin
-				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
+				interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
 			end
 		endcase
 	end
-	if (builder_csrbank1_rst0_re) begin
-		main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
+	if (csrbank1_rst0_re) begin
+		a7ddrphy_rst_storage <= csrbank1_rst0_r;
 	end
-	main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
-	if (builder_csrbank1_half_sys8x_taps0_re) begin
-		main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+	a7ddrphy_rst_re <= csrbank1_rst0_re;
+	if (csrbank1_dly_sel0_re) begin
+		a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
 	end
-	main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
-	if (builder_csrbank1_wlevel_en0_re) begin
-		main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
+	a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+	if (csrbank1_half_sys8x_taps0_re) begin
+		a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
 	end
-	main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
-	if (builder_csrbank1_dly_sel0_re) begin
-		main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+	a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+	if (csrbank1_wlevel_en0_re) begin
+		a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
 	end
-	main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
-	if (builder_csrbank1_rdphase0_re) begin
-		main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+	a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+	if (csrbank1_rdphase0_re) begin
+		a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
 	end
-	main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
-	if (builder_csrbank1_wrphase0_re) begin
-		main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+	a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+	if (csrbank1_wrphase0_re) begin
+		a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
 	end
-	main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
-	builder_interface2_bank_bus_dat_r <= 1'd0;
-	if (builder_csrbank2_sel) begin
-		case (builder_interface2_bank_bus_adr[8:0])
+	a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+	interface2_bank_bus_dat_r <= 1'd0;
+	if (csrbank2_sel) begin
+		case (interface2_bank_bus_adr[8:0])
 			1'd0: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
 			end
 			1'd1: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
 			end
 			2'd2: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
 			end
 			5'd20: begin
-				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
+				interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
 			end
 			5'd21: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
 			end
 			5'd22: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
 			end
 			5'd23: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
 			end
 			5'd24: begin
-				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
+				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
-	if (builder_csrbank2_dfii_control0_re) begin
-		main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+	if (csrbank2_dfii_control0_re) begin
+		litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
 	end
-	main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
-	if (builder_csrbank2_dfii_pi0_command0_re) begin
-		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
+	litedramcore_re <= csrbank2_dfii_control0_re;
+	if (csrbank2_dfii_pi0_command0_re) begin
+		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
 	end
-	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
-	if (builder_csrbank2_dfii_pi0_address0_re) begin
-		main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
+	litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+	if (csrbank2_dfii_pi0_address0_re) begin
+		litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
 	end
-	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
-	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+	litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+	if (csrbank2_dfii_pi0_baddress0_re) begin
+		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
 	end
-	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
-	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-		main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+	litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+	if (csrbank2_dfii_pi0_wrdata0_re) begin
+		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
-	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
-	if (builder_csrbank2_dfii_pi1_command0_re) begin
-		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
+	litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+	litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+	if (csrbank2_dfii_pi1_command0_re) begin
+		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
 	end
-	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
-	if (builder_csrbank2_dfii_pi1_address0_re) begin
-		main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
+	litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+	if (csrbank2_dfii_pi1_address0_re) begin
+		litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
 	end
-	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
-	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+	litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+	if (csrbank2_dfii_pi1_baddress0_re) begin
+		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
 	end
-	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
-	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-		main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+	litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+	if (csrbank2_dfii_pi1_wrdata0_re) begin
+		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
-	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
-	if (builder_csrbank2_dfii_pi2_command0_re) begin
-		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
+	litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+	litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+	if (csrbank2_dfii_pi2_command0_re) begin
+		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
 	end
-	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
-	if (builder_csrbank2_dfii_pi2_address0_re) begin
-		main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
+	litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+	if (csrbank2_dfii_pi2_address0_re) begin
+		litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
 	end
-	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
-	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+	litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+	if (csrbank2_dfii_pi2_baddress0_re) begin
+		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
 	end
-	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
-	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-		main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+	litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+	if (csrbank2_dfii_pi2_wrdata0_re) begin
+		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
-	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
-	if (builder_csrbank2_dfii_pi3_command0_re) begin
-		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
+	litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+	litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+	if (csrbank2_dfii_pi3_command0_re) begin
+		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
 	end
-	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
-	if (builder_csrbank2_dfii_pi3_address0_re) begin
-		main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
+	litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+	if (csrbank2_dfii_pi3_address0_re) begin
+		litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
 	end
-	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
-	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+	litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+	if (csrbank2_dfii_pi3_baddress0_re) begin
+		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
 	end
-	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
-	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-		main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+	litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+	if (csrbank2_dfii_pi3_wrdata0_re) begin
+		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
 	end
-	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
-	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
+	litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+	litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
 	if (sys_rst) begin
-		main_a7ddrphy_rst_storage <= 1'd0;
-		main_a7ddrphy_rst_re <= 1'd0;
-		main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-		main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
-		main_a7ddrphy_wlevel_en_storage <= 1'd0;
-		main_a7ddrphy_wlevel_en_re <= 1'd0;
-		main_a7ddrphy_dly_sel_storage <= 2'd0;
-		main_a7ddrphy_dly_sel_re <= 1'd0;
-		main_a7ddrphy_rdphase_storage <= 2'd2;
-		main_a7ddrphy_rdphase_re <= 1'd0;
-		main_a7ddrphy_wrphase_storage <= 2'd3;
-		main_a7ddrphy_wrphase_re <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_dqspattern_o1 <= 8'd0;
-		main_a7ddrphy_bitslip0_value0 <= 3'd7;
-		main_a7ddrphy_bitslip1_value0 <= 3'd7;
-		main_a7ddrphy_bitslip0_value1 <= 3'd7;
-		main_a7ddrphy_bitslip1_value1 <= 3'd7;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_bitslip0_value2 <= 3'd7;
-		main_a7ddrphy_bitslip0_value3 <= 3'd7;
-		main_a7ddrphy_bitslip1_value2 <= 3'd7;
-		main_a7ddrphy_bitslip1_value3 <= 3'd7;
-		main_a7ddrphy_bitslip2_value0 <= 3'd7;
-		main_a7ddrphy_bitslip2_value1 <= 3'd7;
-		main_a7ddrphy_bitslip3_value0 <= 3'd7;
-		main_a7ddrphy_bitslip3_value1 <= 3'd7;
-		main_a7ddrphy_bitslip4_value0 <= 3'd7;
-		main_a7ddrphy_bitslip4_value1 <= 3'd7;
-		main_a7ddrphy_bitslip5_value0 <= 3'd7;
-		main_a7ddrphy_bitslip5_value1 <= 3'd7;
-		main_a7ddrphy_bitslip6_value0 <= 3'd7;
-		main_a7ddrphy_bitslip6_value1 <= 3'd7;
-		main_a7ddrphy_bitslip7_value0 <= 3'd7;
-		main_a7ddrphy_bitslip7_value1 <= 3'd7;
-		main_a7ddrphy_bitslip8_value0 <= 3'd7;
-		main_a7ddrphy_bitslip8_value1 <= 3'd7;
-		main_a7ddrphy_bitslip9_value0 <= 3'd7;
-		main_a7ddrphy_bitslip9_value1 <= 3'd7;
-		main_a7ddrphy_bitslip10_value0 <= 3'd7;
-		main_a7ddrphy_bitslip10_value1 <= 3'd7;
-		main_a7ddrphy_bitslip11_value0 <= 3'd7;
-		main_a7ddrphy_bitslip11_value1 <= 3'd7;
-		main_a7ddrphy_bitslip12_value0 <= 3'd7;
-		main_a7ddrphy_bitslip12_value1 <= 3'd7;
-		main_a7ddrphy_bitslip13_value0 <= 3'd7;
-		main_a7ddrphy_bitslip13_value1 <= 3'd7;
-		main_a7ddrphy_bitslip14_value0 <= 3'd7;
-		main_a7ddrphy_bitslip14_value1 <= 3'd7;
-		main_a7ddrphy_bitslip15_value0 <= 3'd7;
-		main_a7ddrphy_bitslip15_value1 <= 3'd7;
-		main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-		main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-		main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-		main_litedramcore_storage <= 4'd1;
-		main_litedramcore_re <= 1'd0;
-		main_litedramcore_phaseinjector0_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector0_command_re <= 1'd0;
-		main_litedramcore_phaseinjector0_address_re <= 1'd0;
-		main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector1_command_re <= 1'd0;
-		main_litedramcore_phaseinjector1_address_re <= 1'd0;
-		main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector2_command_re <= 1'd0;
-		main_litedramcore_phaseinjector2_address_re <= 1'd0;
-		main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_command_storage <= 6'd0;
-		main_litedramcore_phaseinjector3_command_re <= 1'd0;
-		main_litedramcore_phaseinjector3_address_re <= 1'd0;
-		main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
-		main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-		main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
-		main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
-		main_litedramcore_dfi_p0_address <= 14'd0;
-		main_litedramcore_dfi_p0_bank <= 3'd0;
-		main_litedramcore_dfi_p0_cas_n <= 1'd1;
-		main_litedramcore_dfi_p0_cs_n <= 1'd1;
-		main_litedramcore_dfi_p0_ras_n <= 1'd1;
-		main_litedramcore_dfi_p0_we_n <= 1'd1;
-		main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p0_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p1_address <= 14'd0;
-		main_litedramcore_dfi_p1_bank <= 3'd0;
-		main_litedramcore_dfi_p1_cas_n <= 1'd1;
-		main_litedramcore_dfi_p1_cs_n <= 1'd1;
-		main_litedramcore_dfi_p1_ras_n <= 1'd1;
-		main_litedramcore_dfi_p1_we_n <= 1'd1;
-		main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p1_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p2_address <= 14'd0;
-		main_litedramcore_dfi_p2_bank <= 3'd0;
-		main_litedramcore_dfi_p2_cas_n <= 1'd1;
-		main_litedramcore_dfi_p2_cs_n <= 1'd1;
-		main_litedramcore_dfi_p2_ras_n <= 1'd1;
-		main_litedramcore_dfi_p2_we_n <= 1'd1;
-		main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p2_rddata_en <= 1'd0;
-		main_litedramcore_dfi_p3_address <= 14'd0;
-		main_litedramcore_dfi_p3_bank <= 3'd0;
-		main_litedramcore_dfi_p3_cas_n <= 1'd1;
-		main_litedramcore_dfi_p3_cs_n <= 1'd1;
-		main_litedramcore_dfi_p3_ras_n <= 1'd1;
-		main_litedramcore_dfi_p3_we_n <= 1'd1;
-		main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
-		main_litedramcore_dfi_p3_rddata_en <= 1'd0;
-		main_litedramcore_cmd_payload_a <= 14'd0;
-		main_litedramcore_cmd_payload_ba <= 3'd0;
-		main_litedramcore_cmd_payload_cas <= 1'd0;
-		main_litedramcore_cmd_payload_ras <= 1'd0;
-		main_litedramcore_cmd_payload_we <= 1'd0;
-		main_litedramcore_timer_count1 <= 10'd781;
-		main_litedramcore_postponer_req_o <= 1'd0;
-		main_litedramcore_postponer_count <= 1'd0;
-		main_litedramcore_sequencer_done1 <= 1'd0;
-		main_litedramcore_sequencer_counter <= 6'd0;
-		main_litedramcore_sequencer_count <= 1'd0;
-		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
-		main_litedramcore_zqcs_executer_done <= 1'd0;
-		main_litedramcore_zqcs_executer_counter <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine0_row <= 14'd0;
-		main_litedramcore_bankmachine0_row_opened <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine0_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine1_row <= 14'd0;
-		main_litedramcore_bankmachine1_row_opened <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine1_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine2_row <= 14'd0;
-		main_litedramcore_bankmachine2_row_opened <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine2_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine3_row <= 14'd0;
-		main_litedramcore_bankmachine3_row_opened <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine3_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine4_row <= 14'd0;
-		main_litedramcore_bankmachine4_row_opened <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine4_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine5_row <= 14'd0;
-		main_litedramcore_bankmachine5_row_opened <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine5_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine6_row <= 14'd0;
-		main_litedramcore_bankmachine6_row_opened <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine6_trascon_count <= 3'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
-		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
-		main_litedramcore_bankmachine7_row <= 14'd0;
-		main_litedramcore_bankmachine7_row_opened <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trccon_count <= 3'd0;
-		main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
-		main_litedramcore_bankmachine7_trascon_count <= 3'd0;
-		main_litedramcore_choose_cmd_grant <= 3'd0;
-		main_litedramcore_choose_req_grant <= 3'd0;
-		main_litedramcore_trrdcon_ready <= 1'd0;
-		main_litedramcore_trrdcon_count <= 1'd0;
-		main_litedramcore_tfawcon_ready <= 1'd1;
-		main_litedramcore_tfawcon_window <= 5'd0;
-		main_litedramcore_tccdcon_ready <= 1'd0;
-		main_litedramcore_tccdcon_count <= 1'd0;
-		main_litedramcore_twtrcon_ready <= 1'd0;
-		main_litedramcore_twtrcon_count <= 3'd0;
-		main_litedramcore_time0 <= 5'd0;
-		main_litedramcore_time1 <= 4'd0;
-		main_init_done_storage <= 1'd0;
-		main_init_done_re <= 1'd0;
-		main_init_error_storage <= 1'd0;
-		main_init_error_re <= 1'd0;
-		builder_refresher_state <= 2'd0;
-		builder_bankmachine0_state <= 4'd0;
-		builder_bankmachine1_state <= 4'd0;
-		builder_bankmachine2_state <= 4'd0;
-		builder_bankmachine3_state <= 4'd0;
-		builder_bankmachine4_state <= 4'd0;
-		builder_bankmachine5_state <= 4'd0;
-		builder_bankmachine6_state <= 4'd0;
-		builder_bankmachine7_state <= 4'd0;
-		builder_multiplexer_state <= 4'd0;
-		builder_new_master_wdata_ready0 <= 1'd0;
-		builder_new_master_wdata_ready1 <= 1'd0;
-		builder_new_master_rdata_valid0 <= 1'd0;
-		builder_new_master_rdata_valid1 <= 1'd0;
-		builder_new_master_rdata_valid2 <= 1'd0;
-		builder_new_master_rdata_valid3 <= 1'd0;
-		builder_new_master_rdata_valid4 <= 1'd0;
-		builder_new_master_rdata_valid5 <= 1'd0;
-		builder_new_master_rdata_valid6 <= 1'd0;
-		builder_new_master_rdata_valid7 <= 1'd0;
-		builder_new_master_rdata_valid8 <= 1'd0;
-		builder_litedramcore_we <= 1'd0;
-		builder_state <= 2'd0;
+		a7ddrphy_rst_storage <= 1'd0;
+		a7ddrphy_rst_re <= 1'd0;
+		a7ddrphy_dly_sel_storage <= 2'd0;
+		a7ddrphy_dly_sel_re <= 1'd0;
+		a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+		a7ddrphy_half_sys8x_taps_re <= 1'd0;
+		a7ddrphy_wlevel_en_storage <= 1'd0;
+		a7ddrphy_wlevel_en_re <= 1'd0;
+		a7ddrphy_rdphase_storage <= 2'd2;
+		a7ddrphy_rdphase_re <= 1'd0;
+		a7ddrphy_wrphase_storage <= 2'd3;
+		a7ddrphy_wrphase_re <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_dqspattern_o1 <= 8'd0;
+		a7ddrphy_bitslip0_value0 <= 3'd7;
+		a7ddrphy_bitslip1_value0 <= 3'd7;
+		a7ddrphy_bitslip0_value1 <= 3'd7;
+		a7ddrphy_bitslip1_value1 <= 3'd7;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		a7ddrphy_bitslip0_value2 <= 3'd7;
+		a7ddrphy_bitslip0_value3 <= 3'd7;
+		a7ddrphy_bitslip1_value2 <= 3'd7;
+		a7ddrphy_bitslip1_value3 <= 3'd7;
+		a7ddrphy_bitslip2_value0 <= 3'd7;
+		a7ddrphy_bitslip2_value1 <= 3'd7;
+		a7ddrphy_bitslip3_value0 <= 3'd7;
+		a7ddrphy_bitslip3_value1 <= 3'd7;
+		a7ddrphy_bitslip4_value0 <= 3'd7;
+		a7ddrphy_bitslip4_value1 <= 3'd7;
+		a7ddrphy_bitslip5_value0 <= 3'd7;
+		a7ddrphy_bitslip5_value1 <= 3'd7;
+		a7ddrphy_bitslip6_value0 <= 3'd7;
+		a7ddrphy_bitslip6_value1 <= 3'd7;
+		a7ddrphy_bitslip7_value0 <= 3'd7;
+		a7ddrphy_bitslip7_value1 <= 3'd7;
+		a7ddrphy_bitslip8_value0 <= 3'd7;
+		a7ddrphy_bitslip8_value1 <= 3'd7;
+		a7ddrphy_bitslip9_value0 <= 3'd7;
+		a7ddrphy_bitslip9_value1 <= 3'd7;
+		a7ddrphy_bitslip10_value0 <= 3'd7;
+		a7ddrphy_bitslip10_value1 <= 3'd7;
+		a7ddrphy_bitslip11_value0 <= 3'd7;
+		a7ddrphy_bitslip11_value1 <= 3'd7;
+		a7ddrphy_bitslip12_value0 <= 3'd7;
+		a7ddrphy_bitslip12_value1 <= 3'd7;
+		a7ddrphy_bitslip13_value0 <= 3'd7;
+		a7ddrphy_bitslip13_value1 <= 3'd7;
+		a7ddrphy_bitslip14_value0 <= 3'd7;
+		a7ddrphy_bitslip14_value1 <= 3'd7;
+		a7ddrphy_bitslip15_value0 <= 3'd7;
+		a7ddrphy_bitslip15_value1 <= 3'd7;
+		a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+		a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+		a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+		litedramcore_storage <= 4'd1;
+		litedramcore_re <= 1'd0;
+		litedramcore_phaseinjector0_command_storage <= 6'd0;
+		litedramcore_phaseinjector0_command_re <= 1'd0;
+		litedramcore_phaseinjector0_address_re <= 1'd0;
+		litedramcore_phaseinjector0_baddress_re <= 1'd0;
+		litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector0_rddata_status <= 32'd0;
+		litedramcore_phaseinjector0_rddata_re <= 1'd0;
+		litedramcore_phaseinjector1_command_storage <= 6'd0;
+		litedramcore_phaseinjector1_command_re <= 1'd0;
+		litedramcore_phaseinjector1_address_re <= 1'd0;
+		litedramcore_phaseinjector1_baddress_re <= 1'd0;
+		litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector1_rddata_status <= 32'd0;
+		litedramcore_phaseinjector1_rddata_re <= 1'd0;
+		litedramcore_phaseinjector2_command_storage <= 6'd0;
+		litedramcore_phaseinjector2_command_re <= 1'd0;
+		litedramcore_phaseinjector2_address_re <= 1'd0;
+		litedramcore_phaseinjector2_baddress_re <= 1'd0;
+		litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector2_rddata_status <= 32'd0;
+		litedramcore_phaseinjector2_rddata_re <= 1'd0;
+		litedramcore_phaseinjector3_command_storage <= 6'd0;
+		litedramcore_phaseinjector3_command_re <= 1'd0;
+		litedramcore_phaseinjector3_address_re <= 1'd0;
+		litedramcore_phaseinjector3_baddress_re <= 1'd0;
+		litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+		litedramcore_phaseinjector3_rddata_status <= 32'd0;
+		litedramcore_phaseinjector3_rddata_re <= 1'd0;
+		litedramcore_dfi_p0_address <= 14'd0;
+		litedramcore_dfi_p0_bank <= 3'd0;
+		litedramcore_dfi_p0_cas_n <= 1'd1;
+		litedramcore_dfi_p0_cs_n <= 1'd1;
+		litedramcore_dfi_p0_ras_n <= 1'd1;
+		litedramcore_dfi_p0_we_n <= 1'd1;
+		litedramcore_dfi_p0_wrdata_en <= 1'd0;
+		litedramcore_dfi_p0_rddata_en <= 1'd0;
+		litedramcore_dfi_p1_address <= 14'd0;
+		litedramcore_dfi_p1_bank <= 3'd0;
+		litedramcore_dfi_p1_cas_n <= 1'd1;
+		litedramcore_dfi_p1_cs_n <= 1'd1;
+		litedramcore_dfi_p1_ras_n <= 1'd1;
+		litedramcore_dfi_p1_we_n <= 1'd1;
+		litedramcore_dfi_p1_wrdata_en <= 1'd0;
+		litedramcore_dfi_p1_rddata_en <= 1'd0;
+		litedramcore_dfi_p2_address <= 14'd0;
+		litedramcore_dfi_p2_bank <= 3'd0;
+		litedramcore_dfi_p2_cas_n <= 1'd1;
+		litedramcore_dfi_p2_cs_n <= 1'd1;
+		litedramcore_dfi_p2_ras_n <= 1'd1;
+		litedramcore_dfi_p2_we_n <= 1'd1;
+		litedramcore_dfi_p2_wrdata_en <= 1'd0;
+		litedramcore_dfi_p2_rddata_en <= 1'd0;
+		litedramcore_dfi_p3_address <= 14'd0;
+		litedramcore_dfi_p3_bank <= 3'd0;
+		litedramcore_dfi_p3_cas_n <= 1'd1;
+		litedramcore_dfi_p3_cs_n <= 1'd1;
+		litedramcore_dfi_p3_ras_n <= 1'd1;
+		litedramcore_dfi_p3_we_n <= 1'd1;
+		litedramcore_dfi_p3_wrdata_en <= 1'd0;
+		litedramcore_dfi_p3_rddata_en <= 1'd0;
+		litedramcore_cmd_payload_a <= 14'd0;
+		litedramcore_cmd_payload_ba <= 3'd0;
+		litedramcore_cmd_payload_cas <= 1'd0;
+		litedramcore_cmd_payload_ras <= 1'd0;
+		litedramcore_cmd_payload_we <= 1'd0;
+		litedramcore_timer_count1 <= 10'd781;
+		litedramcore_postponer_req_o <= 1'd0;
+		litedramcore_postponer_count <= 1'd0;
+		litedramcore_sequencer_done1 <= 1'd0;
+		litedramcore_sequencer_counter <= 6'd0;
+		litedramcore_sequencer_count <= 1'd0;
+		litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		litedramcore_zqcs_executer_done <= 1'd0;
+		litedramcore_zqcs_executer_counter <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine0_row <= 14'd0;
+		litedramcore_bankmachine0_row_opened <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine0_trccon_ready <= 1'd0;
+		litedramcore_bankmachine0_trccon_count <= 3'd0;
+		litedramcore_bankmachine0_trascon_ready <= 1'd0;
+		litedramcore_bankmachine0_trascon_count <= 3'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine1_row <= 14'd0;
+		litedramcore_bankmachine1_row_opened <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine1_trccon_ready <= 1'd0;
+		litedramcore_bankmachine1_trccon_count <= 3'd0;
+		litedramcore_bankmachine1_trascon_ready <= 1'd0;
+		litedramcore_bankmachine1_trascon_count <= 3'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine2_row <= 14'd0;
+		litedramcore_bankmachine2_row_opened <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine2_trccon_ready <= 1'd0;
+		litedramcore_bankmachine2_trccon_count <= 3'd0;
+		litedramcore_bankmachine2_trascon_ready <= 1'd0;
+		litedramcore_bankmachine2_trascon_count <= 3'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine3_row <= 14'd0;
+		litedramcore_bankmachine3_row_opened <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine3_trccon_ready <= 1'd0;
+		litedramcore_bankmachine3_trccon_count <= 3'd0;
+		litedramcore_bankmachine3_trascon_ready <= 1'd0;
+		litedramcore_bankmachine3_trascon_count <= 3'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine4_row <= 14'd0;
+		litedramcore_bankmachine4_row_opened <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine4_trccon_ready <= 1'd0;
+		litedramcore_bankmachine4_trccon_count <= 3'd0;
+		litedramcore_bankmachine4_trascon_ready <= 1'd0;
+		litedramcore_bankmachine4_trascon_count <= 3'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine5_row <= 14'd0;
+		litedramcore_bankmachine5_row_opened <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine5_trccon_ready <= 1'd0;
+		litedramcore_bankmachine5_trccon_count <= 3'd0;
+		litedramcore_bankmachine5_trascon_ready <= 1'd0;
+		litedramcore_bankmachine5_trascon_count <= 3'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine6_row <= 14'd0;
+		litedramcore_bankmachine6_row_opened <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine6_trccon_ready <= 1'd0;
+		litedramcore_bankmachine6_trccon_count <= 3'd0;
+		litedramcore_bankmachine6_trascon_ready <= 1'd0;
+		litedramcore_bankmachine6_trascon_count <= 3'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
+		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
+		litedramcore_bankmachine7_row <= 14'd0;
+		litedramcore_bankmachine7_row_opened <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+		litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+		litedramcore_bankmachine7_trccon_ready <= 1'd0;
+		litedramcore_bankmachine7_trccon_count <= 3'd0;
+		litedramcore_bankmachine7_trascon_ready <= 1'd0;
+		litedramcore_bankmachine7_trascon_count <= 3'd0;
+		litedramcore_choose_cmd_grant <= 3'd0;
+		litedramcore_choose_req_grant <= 3'd0;
+		litedramcore_trrdcon_ready <= 1'd0;
+		litedramcore_trrdcon_count <= 1'd0;
+		litedramcore_tfawcon_ready <= 1'd1;
+		litedramcore_tfawcon_window <= 5'd0;
+		litedramcore_tccdcon_ready <= 1'd0;
+		litedramcore_tccdcon_count <= 1'd0;
+		litedramcore_twtrcon_ready <= 1'd0;
+		litedramcore_twtrcon_count <= 3'd0;
+		litedramcore_time0 <= 5'd0;
+		litedramcore_time1 <= 4'd0;
+		init_done_storage <= 1'd0;
+		init_done_re <= 1'd0;
+		init_error_storage <= 1'd0;
+		init_error_re <= 1'd0;
+		litedramcore_we <= 1'd0;
+		litedramcore_refresher_state <= 2'd0;
+		litedramcore_bankmachine0_state <= 4'd0;
+		litedramcore_bankmachine1_state <= 4'd0;
+		litedramcore_bankmachine2_state <= 4'd0;
+		litedramcore_bankmachine3_state <= 4'd0;
+		litedramcore_bankmachine4_state <= 4'd0;
+		litedramcore_bankmachine5_state <= 4'd0;
+		litedramcore_bankmachine6_state <= 4'd0;
+		litedramcore_bankmachine7_state <= 4'd0;
+		litedramcore_multiplexer_state <= 4'd0;
+		litedramcore_new_master_wdata_ready0 <= 1'd0;
+		litedramcore_new_master_wdata_ready1 <= 1'd0;
+		litedramcore_new_master_rdata_valid0 <= 1'd0;
+		litedramcore_new_master_rdata_valid1 <= 1'd0;
+		litedramcore_new_master_rdata_valid2 <= 1'd0;
+		litedramcore_new_master_rdata_valid3 <= 1'd0;
+		litedramcore_new_master_rdata_valid4 <= 1'd0;
+		litedramcore_new_master_rdata_valid5 <= 1'd0;
+		litedramcore_new_master_rdata_valid6 <= 1'd0;
+		litedramcore_new_master_rdata_valid7 <= 1'd0;
+		litedramcore_new_master_rdata_valid8 <= 1'd0;
+		litedramcore_state <= 2'd0;
 	end
 end
 
@@ -13454,28 +13897,28 @@ end
 //------------------------------------------------------------------------------
 
 BUFG BUFG(
-	.I(main_clkout0),
-	.O(main_clkout_buf0)
+	.I(clkout0),
+	.O(clkout_buf0)
 );
 
 BUFG BUFG_1(
-	.I(main_clkout1),
-	.O(main_clkout_buf1)
+	.I(clkout1),
+	.O(clkout_buf1)
 );
 
 BUFG BUFG_2(
-	.I(main_clkout2),
-	.O(main_clkout_buf2)
+	.I(clkout2),
+	.O(clkout_buf2)
 );
 
 BUFG BUFG_3(
-	.I(main_clkout3),
-	.O(main_clkout_buf3)
+	.I(clkout3),
+	.O(clkout_buf3)
 );
 
 IDELAYCTRL IDELAYCTRL(
 	.REFCLK(iodelay_clk),
-	.RST(main_ic_reset)
+	.RST(ic_reset)
 );
 
 OSERDESE2 #(
@@ -13496,12 +13939,12 @@ OSERDESE2 #(
 	.D7(1'd0),
 	.D8(1'd1),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(main_a7ddrphy_sd_clk_se_nodelay)
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_sd_clk_se_nodelay)
 );
 
 OBUFDS OBUFDS(
-	.I(main_a7ddrphy_sd_clk_se_nodelay),
+	.I(a7ddrphy_sd_clk_se_nodelay),
 	.O(ddram_clk_p),
 	.OB(ddram_clk_n)
 );
@@ -13515,16 +13958,16 @@ OSERDESE2 #(
 ) OSERDESE2_1 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_reset_n),
-	.D2(main_a7ddrphy_dfi_p0_reset_n),
-	.D3(main_a7ddrphy_dfi_p1_reset_n),
-	.D4(main_a7ddrphy_dfi_p1_reset_n),
-	.D5(main_a7ddrphy_dfi_p2_reset_n),
-	.D6(main_a7ddrphy_dfi_p2_reset_n),
-	.D7(main_a7ddrphy_dfi_p3_reset_n),
-	.D8(main_a7ddrphy_dfi_p3_reset_n),
+	.D1(a7ddrphy_dfi_p0_reset_n),
+	.D2(a7ddrphy_dfi_p0_reset_n),
+	.D3(a7ddrphy_dfi_p1_reset_n),
+	.D4(a7ddrphy_dfi_p1_reset_n),
+	.D5(a7ddrphy_dfi_p2_reset_n),
+	.D6(a7ddrphy_dfi_p2_reset_n),
+	.D7(a7ddrphy_dfi_p3_reset_n),
+	.D8(a7ddrphy_dfi_p3_reset_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_reset_n)
 );
 
@@ -13537,16 +13980,16 @@ OSERDESE2 #(
 ) OSERDESE2_2 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cs_n),
-	.D2(main_a7ddrphy_dfi_p0_cs_n),
-	.D3(main_a7ddrphy_dfi_p1_cs_n),
-	.D4(main_a7ddrphy_dfi_p1_cs_n),
-	.D5(main_a7ddrphy_dfi_p2_cs_n),
-	.D6(main_a7ddrphy_dfi_p2_cs_n),
-	.D7(main_a7ddrphy_dfi_p3_cs_n),
-	.D8(main_a7ddrphy_dfi_p3_cs_n),
+	.D1(a7ddrphy_dfi_p0_cs_n),
+	.D2(a7ddrphy_dfi_p0_cs_n),
+	.D3(a7ddrphy_dfi_p1_cs_n),
+	.D4(a7ddrphy_dfi_p1_cs_n),
+	.D5(a7ddrphy_dfi_p2_cs_n),
+	.D6(a7ddrphy_dfi_p2_cs_n),
+	.D7(a7ddrphy_dfi_p3_cs_n),
+	.D8(a7ddrphy_dfi_p3_cs_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cs_n)
 );
 
@@ -13559,16 +14002,16 @@ OSERDESE2 #(
 ) OSERDESE2_3 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[0]),
-	.D2(main_a7ddrphy_dfi_p0_address[0]),
-	.D3(main_a7ddrphy_dfi_p1_address[0]),
-	.D4(main_a7ddrphy_dfi_p1_address[0]),
-	.D5(main_a7ddrphy_dfi_p2_address[0]),
-	.D6(main_a7ddrphy_dfi_p2_address[0]),
-	.D7(main_a7ddrphy_dfi_p3_address[0]),
-	.D8(main_a7ddrphy_dfi_p3_address[0]),
+	.D1(a7ddrphy_dfi_p0_address[0]),
+	.D2(a7ddrphy_dfi_p0_address[0]),
+	.D3(a7ddrphy_dfi_p1_address[0]),
+	.D4(a7ddrphy_dfi_p1_address[0]),
+	.D5(a7ddrphy_dfi_p2_address[0]),
+	.D6(a7ddrphy_dfi_p2_address[0]),
+	.D7(a7ddrphy_dfi_p3_address[0]),
+	.D8(a7ddrphy_dfi_p3_address[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[0])
 );
 
@@ -13581,16 +14024,16 @@ OSERDESE2 #(
 ) OSERDESE2_4 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[1]),
-	.D2(main_a7ddrphy_dfi_p0_address[1]),
-	.D3(main_a7ddrphy_dfi_p1_address[1]),
-	.D4(main_a7ddrphy_dfi_p1_address[1]),
-	.D5(main_a7ddrphy_dfi_p2_address[1]),
-	.D6(main_a7ddrphy_dfi_p2_address[1]),
-	.D7(main_a7ddrphy_dfi_p3_address[1]),
-	.D8(main_a7ddrphy_dfi_p3_address[1]),
+	.D1(a7ddrphy_dfi_p0_address[1]),
+	.D2(a7ddrphy_dfi_p0_address[1]),
+	.D3(a7ddrphy_dfi_p1_address[1]),
+	.D4(a7ddrphy_dfi_p1_address[1]),
+	.D5(a7ddrphy_dfi_p2_address[1]),
+	.D6(a7ddrphy_dfi_p2_address[1]),
+	.D7(a7ddrphy_dfi_p3_address[1]),
+	.D8(a7ddrphy_dfi_p3_address[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[1])
 );
 
@@ -13603,16 +14046,16 @@ OSERDESE2 #(
 ) OSERDESE2_5 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[2]),
-	.D2(main_a7ddrphy_dfi_p0_address[2]),
-	.D3(main_a7ddrphy_dfi_p1_address[2]),
-	.D4(main_a7ddrphy_dfi_p1_address[2]),
-	.D5(main_a7ddrphy_dfi_p2_address[2]),
-	.D6(main_a7ddrphy_dfi_p2_address[2]),
-	.D7(main_a7ddrphy_dfi_p3_address[2]),
-	.D8(main_a7ddrphy_dfi_p3_address[2]),
+	.D1(a7ddrphy_dfi_p0_address[2]),
+	.D2(a7ddrphy_dfi_p0_address[2]),
+	.D3(a7ddrphy_dfi_p1_address[2]),
+	.D4(a7ddrphy_dfi_p1_address[2]),
+	.D5(a7ddrphy_dfi_p2_address[2]),
+	.D6(a7ddrphy_dfi_p2_address[2]),
+	.D7(a7ddrphy_dfi_p3_address[2]),
+	.D8(a7ddrphy_dfi_p3_address[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[2])
 );
 
@@ -13625,16 +14068,16 @@ OSERDESE2 #(
 ) OSERDESE2_6 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[3]),
-	.D2(main_a7ddrphy_dfi_p0_address[3]),
-	.D3(main_a7ddrphy_dfi_p1_address[3]),
-	.D4(main_a7ddrphy_dfi_p1_address[3]),
-	.D5(main_a7ddrphy_dfi_p2_address[3]),
-	.D6(main_a7ddrphy_dfi_p2_address[3]),
-	.D7(main_a7ddrphy_dfi_p3_address[3]),
-	.D8(main_a7ddrphy_dfi_p3_address[3]),
+	.D1(a7ddrphy_dfi_p0_address[3]),
+	.D2(a7ddrphy_dfi_p0_address[3]),
+	.D3(a7ddrphy_dfi_p1_address[3]),
+	.D4(a7ddrphy_dfi_p1_address[3]),
+	.D5(a7ddrphy_dfi_p2_address[3]),
+	.D6(a7ddrphy_dfi_p2_address[3]),
+	.D7(a7ddrphy_dfi_p3_address[3]),
+	.D8(a7ddrphy_dfi_p3_address[3]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[3])
 );
 
@@ -13647,16 +14090,16 @@ OSERDESE2 #(
 ) OSERDESE2_7 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[4]),
-	.D2(main_a7ddrphy_dfi_p0_address[4]),
-	.D3(main_a7ddrphy_dfi_p1_address[4]),
-	.D4(main_a7ddrphy_dfi_p1_address[4]),
-	.D5(main_a7ddrphy_dfi_p2_address[4]),
-	.D6(main_a7ddrphy_dfi_p2_address[4]),
-	.D7(main_a7ddrphy_dfi_p3_address[4]),
-	.D8(main_a7ddrphy_dfi_p3_address[4]),
+	.D1(a7ddrphy_dfi_p0_address[4]),
+	.D2(a7ddrphy_dfi_p0_address[4]),
+	.D3(a7ddrphy_dfi_p1_address[4]),
+	.D4(a7ddrphy_dfi_p1_address[4]),
+	.D5(a7ddrphy_dfi_p2_address[4]),
+	.D6(a7ddrphy_dfi_p2_address[4]),
+	.D7(a7ddrphy_dfi_p3_address[4]),
+	.D8(a7ddrphy_dfi_p3_address[4]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[4])
 );
 
@@ -13669,16 +14112,16 @@ OSERDESE2 #(
 ) OSERDESE2_8 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[5]),
-	.D2(main_a7ddrphy_dfi_p0_address[5]),
-	.D3(main_a7ddrphy_dfi_p1_address[5]),
-	.D4(main_a7ddrphy_dfi_p1_address[5]),
-	.D5(main_a7ddrphy_dfi_p2_address[5]),
-	.D6(main_a7ddrphy_dfi_p2_address[5]),
-	.D7(main_a7ddrphy_dfi_p3_address[5]),
-	.D8(main_a7ddrphy_dfi_p3_address[5]),
+	.D1(a7ddrphy_dfi_p0_address[5]),
+	.D2(a7ddrphy_dfi_p0_address[5]),
+	.D3(a7ddrphy_dfi_p1_address[5]),
+	.D4(a7ddrphy_dfi_p1_address[5]),
+	.D5(a7ddrphy_dfi_p2_address[5]),
+	.D6(a7ddrphy_dfi_p2_address[5]),
+	.D7(a7ddrphy_dfi_p3_address[5]),
+	.D8(a7ddrphy_dfi_p3_address[5]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[5])
 );
 
@@ -13691,16 +14134,16 @@ OSERDESE2 #(
 ) OSERDESE2_9 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[6]),
-	.D2(main_a7ddrphy_dfi_p0_address[6]),
-	.D3(main_a7ddrphy_dfi_p1_address[6]),
-	.D4(main_a7ddrphy_dfi_p1_address[6]),
-	.D5(main_a7ddrphy_dfi_p2_address[6]),
-	.D6(main_a7ddrphy_dfi_p2_address[6]),
-	.D7(main_a7ddrphy_dfi_p3_address[6]),
-	.D8(main_a7ddrphy_dfi_p3_address[6]),
+	.D1(a7ddrphy_dfi_p0_address[6]),
+	.D2(a7ddrphy_dfi_p0_address[6]),
+	.D3(a7ddrphy_dfi_p1_address[6]),
+	.D4(a7ddrphy_dfi_p1_address[6]),
+	.D5(a7ddrphy_dfi_p2_address[6]),
+	.D6(a7ddrphy_dfi_p2_address[6]),
+	.D7(a7ddrphy_dfi_p3_address[6]),
+	.D8(a7ddrphy_dfi_p3_address[6]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[6])
 );
 
@@ -13713,16 +14156,16 @@ OSERDESE2 #(
 ) OSERDESE2_10 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[7]),
-	.D2(main_a7ddrphy_dfi_p0_address[7]),
-	.D3(main_a7ddrphy_dfi_p1_address[7]),
-	.D4(main_a7ddrphy_dfi_p1_address[7]),
-	.D5(main_a7ddrphy_dfi_p2_address[7]),
-	.D6(main_a7ddrphy_dfi_p2_address[7]),
-	.D7(main_a7ddrphy_dfi_p3_address[7]),
-	.D8(main_a7ddrphy_dfi_p3_address[7]),
+	.D1(a7ddrphy_dfi_p0_address[7]),
+	.D2(a7ddrphy_dfi_p0_address[7]),
+	.D3(a7ddrphy_dfi_p1_address[7]),
+	.D4(a7ddrphy_dfi_p1_address[7]),
+	.D5(a7ddrphy_dfi_p2_address[7]),
+	.D6(a7ddrphy_dfi_p2_address[7]),
+	.D7(a7ddrphy_dfi_p3_address[7]),
+	.D8(a7ddrphy_dfi_p3_address[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[7])
 );
 
@@ -13735,16 +14178,16 @@ OSERDESE2 #(
 ) OSERDESE2_11 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[8]),
-	.D2(main_a7ddrphy_dfi_p0_address[8]),
-	.D3(main_a7ddrphy_dfi_p1_address[8]),
-	.D4(main_a7ddrphy_dfi_p1_address[8]),
-	.D5(main_a7ddrphy_dfi_p2_address[8]),
-	.D6(main_a7ddrphy_dfi_p2_address[8]),
-	.D7(main_a7ddrphy_dfi_p3_address[8]),
-	.D8(main_a7ddrphy_dfi_p3_address[8]),
+	.D1(a7ddrphy_dfi_p0_address[8]),
+	.D2(a7ddrphy_dfi_p0_address[8]),
+	.D3(a7ddrphy_dfi_p1_address[8]),
+	.D4(a7ddrphy_dfi_p1_address[8]),
+	.D5(a7ddrphy_dfi_p2_address[8]),
+	.D6(a7ddrphy_dfi_p2_address[8]),
+	.D7(a7ddrphy_dfi_p3_address[8]),
+	.D8(a7ddrphy_dfi_p3_address[8]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[8])
 );
 
@@ -13757,16 +14200,16 @@ OSERDESE2 #(
 ) OSERDESE2_12 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[9]),
-	.D2(main_a7ddrphy_dfi_p0_address[9]),
-	.D3(main_a7ddrphy_dfi_p1_address[9]),
-	.D4(main_a7ddrphy_dfi_p1_address[9]),
-	.D5(main_a7ddrphy_dfi_p2_address[9]),
-	.D6(main_a7ddrphy_dfi_p2_address[9]),
-	.D7(main_a7ddrphy_dfi_p3_address[9]),
-	.D8(main_a7ddrphy_dfi_p3_address[9]),
+	.D1(a7ddrphy_dfi_p0_address[9]),
+	.D2(a7ddrphy_dfi_p0_address[9]),
+	.D3(a7ddrphy_dfi_p1_address[9]),
+	.D4(a7ddrphy_dfi_p1_address[9]),
+	.D5(a7ddrphy_dfi_p2_address[9]),
+	.D6(a7ddrphy_dfi_p2_address[9]),
+	.D7(a7ddrphy_dfi_p3_address[9]),
+	.D8(a7ddrphy_dfi_p3_address[9]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[9])
 );
 
@@ -13779,16 +14222,16 @@ OSERDESE2 #(
 ) OSERDESE2_13 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[10]),
-	.D2(main_a7ddrphy_dfi_p0_address[10]),
-	.D3(main_a7ddrphy_dfi_p1_address[10]),
-	.D4(main_a7ddrphy_dfi_p1_address[10]),
-	.D5(main_a7ddrphy_dfi_p2_address[10]),
-	.D6(main_a7ddrphy_dfi_p2_address[10]),
-	.D7(main_a7ddrphy_dfi_p3_address[10]),
-	.D8(main_a7ddrphy_dfi_p3_address[10]),
+	.D1(a7ddrphy_dfi_p0_address[10]),
+	.D2(a7ddrphy_dfi_p0_address[10]),
+	.D3(a7ddrphy_dfi_p1_address[10]),
+	.D4(a7ddrphy_dfi_p1_address[10]),
+	.D5(a7ddrphy_dfi_p2_address[10]),
+	.D6(a7ddrphy_dfi_p2_address[10]),
+	.D7(a7ddrphy_dfi_p3_address[10]),
+	.D8(a7ddrphy_dfi_p3_address[10]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[10])
 );
 
@@ -13801,16 +14244,16 @@ OSERDESE2 #(
 ) OSERDESE2_14 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[11]),
-	.D2(main_a7ddrphy_dfi_p0_address[11]),
-	.D3(main_a7ddrphy_dfi_p1_address[11]),
-	.D4(main_a7ddrphy_dfi_p1_address[11]),
-	.D5(main_a7ddrphy_dfi_p2_address[11]),
-	.D6(main_a7ddrphy_dfi_p2_address[11]),
-	.D7(main_a7ddrphy_dfi_p3_address[11]),
-	.D8(main_a7ddrphy_dfi_p3_address[11]),
+	.D1(a7ddrphy_dfi_p0_address[11]),
+	.D2(a7ddrphy_dfi_p0_address[11]),
+	.D3(a7ddrphy_dfi_p1_address[11]),
+	.D4(a7ddrphy_dfi_p1_address[11]),
+	.D5(a7ddrphy_dfi_p2_address[11]),
+	.D6(a7ddrphy_dfi_p2_address[11]),
+	.D7(a7ddrphy_dfi_p3_address[11]),
+	.D8(a7ddrphy_dfi_p3_address[11]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[11])
 );
 
@@ -13823,16 +14266,16 @@ OSERDESE2 #(
 ) OSERDESE2_15 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[12]),
-	.D2(main_a7ddrphy_dfi_p0_address[12]),
-	.D3(main_a7ddrphy_dfi_p1_address[12]),
-	.D4(main_a7ddrphy_dfi_p1_address[12]),
-	.D5(main_a7ddrphy_dfi_p2_address[12]),
-	.D6(main_a7ddrphy_dfi_p2_address[12]),
-	.D7(main_a7ddrphy_dfi_p3_address[12]),
-	.D8(main_a7ddrphy_dfi_p3_address[12]),
+	.D1(a7ddrphy_dfi_p0_address[12]),
+	.D2(a7ddrphy_dfi_p0_address[12]),
+	.D3(a7ddrphy_dfi_p1_address[12]),
+	.D4(a7ddrphy_dfi_p1_address[12]),
+	.D5(a7ddrphy_dfi_p2_address[12]),
+	.D6(a7ddrphy_dfi_p2_address[12]),
+	.D7(a7ddrphy_dfi_p3_address[12]),
+	.D8(a7ddrphy_dfi_p3_address[12]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[12])
 );
 
@@ -13845,16 +14288,16 @@ OSERDESE2 #(
 ) OSERDESE2_16 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_address[13]),
-	.D2(main_a7ddrphy_dfi_p0_address[13]),
-	.D3(main_a7ddrphy_dfi_p1_address[13]),
-	.D4(main_a7ddrphy_dfi_p1_address[13]),
-	.D5(main_a7ddrphy_dfi_p2_address[13]),
-	.D6(main_a7ddrphy_dfi_p2_address[13]),
-	.D7(main_a7ddrphy_dfi_p3_address[13]),
-	.D8(main_a7ddrphy_dfi_p3_address[13]),
+	.D1(a7ddrphy_dfi_p0_address[13]),
+	.D2(a7ddrphy_dfi_p0_address[13]),
+	.D3(a7ddrphy_dfi_p1_address[13]),
+	.D4(a7ddrphy_dfi_p1_address[13]),
+	.D5(a7ddrphy_dfi_p2_address[13]),
+	.D6(a7ddrphy_dfi_p2_address[13]),
+	.D7(a7ddrphy_dfi_p3_address[13]),
+	.D8(a7ddrphy_dfi_p3_address[13]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_a[13])
 );
 
@@ -13867,17 +14310,17 @@ OSERDESE2 #(
 ) OSERDESE2_17 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[0]),
-	.D2(main_a7ddrphy_dfi_p0_bank[0]),
-	.D3(main_a7ddrphy_dfi_p1_bank[0]),
-	.D4(main_a7ddrphy_dfi_p1_bank[0]),
-	.D5(main_a7ddrphy_dfi_p2_bank[0]),
-	.D6(main_a7ddrphy_dfi_p2_bank[0]),
-	.D7(main_a7ddrphy_dfi_p3_bank[0]),
-	.D8(main_a7ddrphy_dfi_p3_bank[0]),
+	.D1(a7ddrphy_dfi_p0_bank[0]),
+	.D2(a7ddrphy_dfi_p0_bank[0]),
+	.D3(a7ddrphy_dfi_p1_bank[0]),
+	.D4(a7ddrphy_dfi_p1_bank[0]),
+	.D5(a7ddrphy_dfi_p2_bank[0]),
+	.D6(a7ddrphy_dfi_p2_bank[0]),
+	.D7(a7ddrphy_dfi_p3_bank[0]),
+	.D8(a7ddrphy_dfi_p3_bank[0]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[0])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[0])
 );
 
 OSERDESE2 #(
@@ -13889,17 +14332,17 @@ OSERDESE2 #(
 ) OSERDESE2_18 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[1]),
-	.D2(main_a7ddrphy_dfi_p0_bank[1]),
-	.D3(main_a7ddrphy_dfi_p1_bank[1]),
-	.D4(main_a7ddrphy_dfi_p1_bank[1]),
-	.D5(main_a7ddrphy_dfi_p2_bank[1]),
-	.D6(main_a7ddrphy_dfi_p2_bank[1]),
-	.D7(main_a7ddrphy_dfi_p3_bank[1]),
-	.D8(main_a7ddrphy_dfi_p3_bank[1]),
+	.D1(a7ddrphy_dfi_p0_bank[1]),
+	.D2(a7ddrphy_dfi_p0_bank[1]),
+	.D3(a7ddrphy_dfi_p1_bank[1]),
+	.D4(a7ddrphy_dfi_p1_bank[1]),
+	.D5(a7ddrphy_dfi_p2_bank[1]),
+	.D6(a7ddrphy_dfi_p2_bank[1]),
+	.D7(a7ddrphy_dfi_p3_bank[1]),
+	.D8(a7ddrphy_dfi_p3_bank[1]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[1])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[1])
 );
 
 OSERDESE2 #(
@@ -13911,17 +14354,17 @@ OSERDESE2 #(
 ) OSERDESE2_19 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_bank[2]),
-	.D2(main_a7ddrphy_dfi_p0_bank[2]),
-	.D3(main_a7ddrphy_dfi_p1_bank[2]),
-	.D4(main_a7ddrphy_dfi_p1_bank[2]),
-	.D5(main_a7ddrphy_dfi_p2_bank[2]),
-	.D6(main_a7ddrphy_dfi_p2_bank[2]),
-	.D7(main_a7ddrphy_dfi_p3_bank[2]),
-	.D8(main_a7ddrphy_dfi_p3_bank[2]),
+	.D1(a7ddrphy_dfi_p0_bank[2]),
+	.D2(a7ddrphy_dfi_p0_bank[2]),
+	.D3(a7ddrphy_dfi_p1_bank[2]),
+	.D4(a7ddrphy_dfi_p1_bank[2]),
+	.D5(a7ddrphy_dfi_p2_bank[2]),
+	.D6(a7ddrphy_dfi_p2_bank[2]),
+	.D7(a7ddrphy_dfi_p3_bank[2]),
+	.D8(a7ddrphy_dfi_p3_bank[2]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.OQ(ddram_ba[2])
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.OQ(a7ddrphy_pads_ba[2])
 );
 
 OSERDESE2 #(
@@ -13933,16 +14376,16 @@ OSERDESE2 #(
 ) OSERDESE2_20 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_ras_n),
-	.D2(main_a7ddrphy_dfi_p0_ras_n),
-	.D3(main_a7ddrphy_dfi_p1_ras_n),
-	.D4(main_a7ddrphy_dfi_p1_ras_n),
-	.D5(main_a7ddrphy_dfi_p2_ras_n),
-	.D6(main_a7ddrphy_dfi_p2_ras_n),
-	.D7(main_a7ddrphy_dfi_p3_ras_n),
-	.D8(main_a7ddrphy_dfi_p3_ras_n),
+	.D1(a7ddrphy_dfi_p0_ras_n),
+	.D2(a7ddrphy_dfi_p0_ras_n),
+	.D3(a7ddrphy_dfi_p1_ras_n),
+	.D4(a7ddrphy_dfi_p1_ras_n),
+	.D5(a7ddrphy_dfi_p2_ras_n),
+	.D6(a7ddrphy_dfi_p2_ras_n),
+	.D7(a7ddrphy_dfi_p3_ras_n),
+	.D8(a7ddrphy_dfi_p3_ras_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_ras_n)
 );
 
@@ -13955,16 +14398,16 @@ OSERDESE2 #(
 ) OSERDESE2_21 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cas_n),
-	.D2(main_a7ddrphy_dfi_p0_cas_n),
-	.D3(main_a7ddrphy_dfi_p1_cas_n),
-	.D4(main_a7ddrphy_dfi_p1_cas_n),
-	.D5(main_a7ddrphy_dfi_p2_cas_n),
-	.D6(main_a7ddrphy_dfi_p2_cas_n),
-	.D7(main_a7ddrphy_dfi_p3_cas_n),
-	.D8(main_a7ddrphy_dfi_p3_cas_n),
+	.D1(a7ddrphy_dfi_p0_cas_n),
+	.D2(a7ddrphy_dfi_p0_cas_n),
+	.D3(a7ddrphy_dfi_p1_cas_n),
+	.D4(a7ddrphy_dfi_p1_cas_n),
+	.D5(a7ddrphy_dfi_p2_cas_n),
+	.D6(a7ddrphy_dfi_p2_cas_n),
+	.D7(a7ddrphy_dfi_p3_cas_n),
+	.D8(a7ddrphy_dfi_p3_cas_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cas_n)
 );
 
@@ -13977,16 +14420,16 @@ OSERDESE2 #(
 ) OSERDESE2_22 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_we_n),
-	.D2(main_a7ddrphy_dfi_p0_we_n),
-	.D3(main_a7ddrphy_dfi_p1_we_n),
-	.D4(main_a7ddrphy_dfi_p1_we_n),
-	.D5(main_a7ddrphy_dfi_p2_we_n),
-	.D6(main_a7ddrphy_dfi_p2_we_n),
-	.D7(main_a7ddrphy_dfi_p3_we_n),
-	.D8(main_a7ddrphy_dfi_p3_we_n),
+	.D1(a7ddrphy_dfi_p0_we_n),
+	.D2(a7ddrphy_dfi_p0_we_n),
+	.D3(a7ddrphy_dfi_p1_we_n),
+	.D4(a7ddrphy_dfi_p1_we_n),
+	.D5(a7ddrphy_dfi_p2_we_n),
+	.D6(a7ddrphy_dfi_p2_we_n),
+	.D7(a7ddrphy_dfi_p3_we_n),
+	.D8(a7ddrphy_dfi_p3_we_n),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_we_n)
 );
 
@@ -13999,16 +14442,16 @@ OSERDESE2 #(
 ) OSERDESE2_23 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_cke),
-	.D2(main_a7ddrphy_dfi_p0_cke),
-	.D3(main_a7ddrphy_dfi_p1_cke),
-	.D4(main_a7ddrphy_dfi_p1_cke),
-	.D5(main_a7ddrphy_dfi_p2_cke),
-	.D6(main_a7ddrphy_dfi_p2_cke),
-	.D7(main_a7ddrphy_dfi_p3_cke),
-	.D8(main_a7ddrphy_dfi_p3_cke),
+	.D1(a7ddrphy_dfi_p0_cke),
+	.D2(a7ddrphy_dfi_p0_cke),
+	.D3(a7ddrphy_dfi_p1_cke),
+	.D4(a7ddrphy_dfi_p1_cke),
+	.D5(a7ddrphy_dfi_p2_cke),
+	.D6(a7ddrphy_dfi_p2_cke),
+	.D7(a7ddrphy_dfi_p3_cke),
+	.D8(a7ddrphy_dfi_p3_cke),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_cke)
 );
 
@@ -14021,16 +14464,16 @@ OSERDESE2 #(
 ) OSERDESE2_24 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_dfi_p0_odt),
-	.D2(main_a7ddrphy_dfi_p0_odt),
-	.D3(main_a7ddrphy_dfi_p1_odt),
-	.D4(main_a7ddrphy_dfi_p1_odt),
-	.D5(main_a7ddrphy_dfi_p2_odt),
-	.D6(main_a7ddrphy_dfi_p2_odt),
-	.D7(main_a7ddrphy_dfi_p3_odt),
-	.D8(main_a7ddrphy_dfi_p3_odt),
+	.D1(a7ddrphy_dfi_p0_odt),
+	.D2(a7ddrphy_dfi_p0_odt),
+	.D3(a7ddrphy_dfi_p1_odt),
+	.D4(a7ddrphy_dfi_p1_odt),
+	.D5(a7ddrphy_dfi_p2_odt),
+	.D6(a7ddrphy_dfi_p2_odt),
+	.D7(a7ddrphy_dfi_p3_odt),
+	.D8(a7ddrphy_dfi_p3_odt),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_odt)
 );
 
@@ -14043,26 +14486,26 @@ OSERDESE2 #(
 ) OSERDESE2_25 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip00[0]),
-	.D2(main_a7ddrphy_bitslip00[1]),
-	.D3(main_a7ddrphy_bitslip00[2]),
-	.D4(main_a7ddrphy_bitslip00[3]),
-	.D5(main_a7ddrphy_bitslip00[4]),
-	.D6(main_a7ddrphy_bitslip00[5]),
-	.D7(main_a7ddrphy_bitslip00[6]),
-	.D8(main_a7ddrphy_bitslip00[7]),
+	.D1(a7ddrphy_bitslip00[0]),
+	.D2(a7ddrphy_bitslip00[1]),
+	.D3(a7ddrphy_bitslip00[2]),
+	.D4(a7ddrphy_bitslip00[3]),
+	.D5(a7ddrphy_bitslip00[4]),
+	.D6(a7ddrphy_bitslip00[5]),
+	.D7(a7ddrphy_bitslip00[6]),
+	.D8(a7ddrphy_bitslip00[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy0),
-	.OQ(main_a7ddrphy_dqs_o_no_delay0),
-	.TQ(main_a7ddrphy_dqs_t0)
+	.OFB(a7ddrphy0),
+	.OQ(a7ddrphy_dqs_o_no_delay0),
+	.TQ(a7ddrphy_dqs_t0)
 );
 
 IOBUFDS IOBUFDS(
-	.I(main_a7ddrphy_dqs_o_no_delay0),
-	.T(main_a7ddrphy_dqs_t0),
+	.I(a7ddrphy_dqs_o_no_delay0),
+	.T(a7ddrphy_dqs_t0),
 	.IO(ddram_dqs_p[0]),
 	.IOB(ddram_dqs_n[0])
 );
@@ -14076,26 +14519,26 @@ OSERDESE2 #(
 ) OSERDESE2_26 (
 	.CLK(sys4x_dqs_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip10[0]),
-	.D2(main_a7ddrphy_bitslip10[1]),
-	.D3(main_a7ddrphy_bitslip10[2]),
-	.D4(main_a7ddrphy_bitslip10[3]),
-	.D5(main_a7ddrphy_bitslip10[4]),
-	.D6(main_a7ddrphy_bitslip10[5]),
-	.D7(main_a7ddrphy_bitslip10[6]),
-	.D8(main_a7ddrphy_bitslip10[7]),
+	.D1(a7ddrphy_bitslip10[0]),
+	.D2(a7ddrphy_bitslip10[1]),
+	.D3(a7ddrphy_bitslip10[2]),
+	.D4(a7ddrphy_bitslip10[3]),
+	.D5(a7ddrphy_bitslip10[4]),
+	.D6(a7ddrphy_bitslip10[5]),
+	.D7(a7ddrphy_bitslip10[6]),
+	.D8(a7ddrphy_bitslip10[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OFB(main_a7ddrphy1),
-	.OQ(main_a7ddrphy_dqs_o_no_delay1),
-	.TQ(main_a7ddrphy_dqs_t1)
+	.OFB(a7ddrphy1),
+	.OQ(a7ddrphy_dqs_o_no_delay1),
+	.TQ(a7ddrphy_dqs_t1)
 );
 
 IOBUFDS IOBUFDS_1(
-	.I(main_a7ddrphy_dqs_o_no_delay1),
-	.T(main_a7ddrphy_dqs_t1),
+	.I(a7ddrphy_dqs_o_no_delay1),
+	.T(a7ddrphy_dqs_t1),
 	.IO(ddram_dqs_p[1]),
 	.IOB(ddram_dqs_n[1])
 );
@@ -14109,16 +14552,16 @@ OSERDESE2 #(
 ) OSERDESE2_27 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip01[0]),
-	.D2(main_a7ddrphy_bitslip01[1]),
-	.D3(main_a7ddrphy_bitslip01[2]),
-	.D4(main_a7ddrphy_bitslip01[3]),
-	.D5(main_a7ddrphy_bitslip01[4]),
-	.D6(main_a7ddrphy_bitslip01[5]),
-	.D7(main_a7ddrphy_bitslip01[6]),
-	.D8(main_a7ddrphy_bitslip01[7]),
+	.D1(a7ddrphy_bitslip01[0]),
+	.D2(a7ddrphy_bitslip01[1]),
+	.D3(a7ddrphy_bitslip01[2]),
+	.D4(a7ddrphy_bitslip01[3]),
+	.D5(a7ddrphy_bitslip01[4]),
+	.D6(a7ddrphy_bitslip01[5]),
+	.D7(a7ddrphy_bitslip01[6]),
+	.D8(a7ddrphy_bitslip01[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[0])
 );
 
@@ -14131,16 +14574,16 @@ OSERDESE2 #(
 ) OSERDESE2_28 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip11[0]),
-	.D2(main_a7ddrphy_bitslip11[1]),
-	.D3(main_a7ddrphy_bitslip11[2]),
-	.D4(main_a7ddrphy_bitslip11[3]),
-	.D5(main_a7ddrphy_bitslip11[4]),
-	.D6(main_a7ddrphy_bitslip11[5]),
-	.D7(main_a7ddrphy_bitslip11[6]),
-	.D8(main_a7ddrphy_bitslip11[7]),
+	.D1(a7ddrphy_bitslip11[0]),
+	.D2(a7ddrphy_bitslip11[1]),
+	.D3(a7ddrphy_bitslip11[2]),
+	.D4(a7ddrphy_bitslip11[3]),
+	.D5(a7ddrphy_bitslip11[4]),
+	.D6(a7ddrphy_bitslip11[5]),
+	.D7(a7ddrphy_bitslip11[6]),
+	.D8(a7ddrphy_bitslip11[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
 	.OQ(ddram_dm[1])
 );
 
@@ -14153,20 +14596,20 @@ OSERDESE2 #(
 ) OSERDESE2_29 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip02[0]),
-	.D2(main_a7ddrphy_bitslip02[1]),
-	.D3(main_a7ddrphy_bitslip02[2]),
-	.D4(main_a7ddrphy_bitslip02[3]),
-	.D5(main_a7ddrphy_bitslip02[4]),
-	.D6(main_a7ddrphy_bitslip02[5]),
-	.D7(main_a7ddrphy_bitslip02[6]),
-	.D8(main_a7ddrphy_bitslip02[7]),
+	.D1(a7ddrphy_bitslip02[0]),
+	.D2(a7ddrphy_bitslip02[1]),
+	.D3(a7ddrphy_bitslip02[2]),
+	.D4(a7ddrphy_bitslip02[3]),
+	.D5(a7ddrphy_bitslip02[4]),
+	.D6(a7ddrphy_bitslip02[5]),
+	.D7(a7ddrphy_bitslip02[6]),
+	.D8(a7ddrphy_bitslip02[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay0),
-	.TQ(main_a7ddrphy_dq_t0)
+	.OQ(a7ddrphy_dq_o_nodelay0),
+	.TQ(a7ddrphy_dq_t0)
 );
 
 ISERDESE2 #(
@@ -14182,16 +14625,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip03[7]),
-	.Q2(main_a7ddrphy_bitslip03[6]),
-	.Q3(main_a7ddrphy_bitslip03[5]),
-	.Q4(main_a7ddrphy_bitslip03[4]),
-	.Q5(main_a7ddrphy_bitslip03[3]),
-	.Q6(main_a7ddrphy_bitslip03[2]),
-	.Q7(main_a7ddrphy_bitslip03[1]),
-	.Q8(main_a7ddrphy_bitslip03[0])
+	.DDLY(a7ddrphy_dq_i_delayed0),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip03[7]),
+	.Q2(a7ddrphy_bitslip03[6]),
+	.Q3(a7ddrphy_bitslip03[5]),
+	.Q4(a7ddrphy_bitslip03[4]),
+	.Q5(a7ddrphy_bitslip03[3]),
+	.Q6(a7ddrphy_bitslip03[2]),
+	.Q7(a7ddrphy_bitslip03[1]),
+	.Q8(a7ddrphy_bitslip03[0])
 );
 
 IDELAYE2 #(
@@ -14205,19 +14648,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay0),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay0),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed0)
+	.DATAOUT(a7ddrphy_dq_i_delayed0)
 );
 
 IOBUF IOBUF(
-	.I(main_a7ddrphy_dq_o_nodelay0),
-	.T(main_a7ddrphy_dq_t0),
+	.I(a7ddrphy_dq_o_nodelay0),
+	.T(a7ddrphy_dq_t0),
 	.IO(ddram_dq[0]),
-	.O(main_a7ddrphy_dq_i_nodelay0)
+	.O(a7ddrphy_dq_i_nodelay0)
 );
 
 OSERDESE2 #(
@@ -14229,20 +14672,20 @@ OSERDESE2 #(
 ) OSERDESE2_30 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip12[0]),
-	.D2(main_a7ddrphy_bitslip12[1]),
-	.D3(main_a7ddrphy_bitslip12[2]),
-	.D4(main_a7ddrphy_bitslip12[3]),
-	.D5(main_a7ddrphy_bitslip12[4]),
-	.D6(main_a7ddrphy_bitslip12[5]),
-	.D7(main_a7ddrphy_bitslip12[6]),
-	.D8(main_a7ddrphy_bitslip12[7]),
+	.D1(a7ddrphy_bitslip12[0]),
+	.D2(a7ddrphy_bitslip12[1]),
+	.D3(a7ddrphy_bitslip12[2]),
+	.D4(a7ddrphy_bitslip12[3]),
+	.D5(a7ddrphy_bitslip12[4]),
+	.D6(a7ddrphy_bitslip12[5]),
+	.D7(a7ddrphy_bitslip12[6]),
+	.D8(a7ddrphy_bitslip12[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay1),
-	.TQ(main_a7ddrphy_dq_t1)
+	.OQ(a7ddrphy_dq_o_nodelay1),
+	.TQ(a7ddrphy_dq_t1)
 );
 
 ISERDESE2 #(
@@ -14258,16 +14701,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip13[7]),
-	.Q2(main_a7ddrphy_bitslip13[6]),
-	.Q3(main_a7ddrphy_bitslip13[5]),
-	.Q4(main_a7ddrphy_bitslip13[4]),
-	.Q5(main_a7ddrphy_bitslip13[3]),
-	.Q6(main_a7ddrphy_bitslip13[2]),
-	.Q7(main_a7ddrphy_bitslip13[1]),
-	.Q8(main_a7ddrphy_bitslip13[0])
+	.DDLY(a7ddrphy_dq_i_delayed1),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip13[7]),
+	.Q2(a7ddrphy_bitslip13[6]),
+	.Q3(a7ddrphy_bitslip13[5]),
+	.Q4(a7ddrphy_bitslip13[4]),
+	.Q5(a7ddrphy_bitslip13[3]),
+	.Q6(a7ddrphy_bitslip13[2]),
+	.Q7(a7ddrphy_bitslip13[1]),
+	.Q8(a7ddrphy_bitslip13[0])
 );
 
 IDELAYE2 #(
@@ -14281,19 +14724,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_1 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay1),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay1),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed1)
+	.DATAOUT(a7ddrphy_dq_i_delayed1)
 );
 
 IOBUF IOBUF_1(
-	.I(main_a7ddrphy_dq_o_nodelay1),
-	.T(main_a7ddrphy_dq_t1),
+	.I(a7ddrphy_dq_o_nodelay1),
+	.T(a7ddrphy_dq_t1),
 	.IO(ddram_dq[1]),
-	.O(main_a7ddrphy_dq_i_nodelay1)
+	.O(a7ddrphy_dq_i_nodelay1)
 );
 
 OSERDESE2 #(
@@ -14305,20 +14748,20 @@ OSERDESE2 #(
 ) OSERDESE2_31 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip20[0]),
-	.D2(main_a7ddrphy_bitslip20[1]),
-	.D3(main_a7ddrphy_bitslip20[2]),
-	.D4(main_a7ddrphy_bitslip20[3]),
-	.D5(main_a7ddrphy_bitslip20[4]),
-	.D6(main_a7ddrphy_bitslip20[5]),
-	.D7(main_a7ddrphy_bitslip20[6]),
-	.D8(main_a7ddrphy_bitslip20[7]),
+	.D1(a7ddrphy_bitslip20[0]),
+	.D2(a7ddrphy_bitslip20[1]),
+	.D3(a7ddrphy_bitslip20[2]),
+	.D4(a7ddrphy_bitslip20[3]),
+	.D5(a7ddrphy_bitslip20[4]),
+	.D6(a7ddrphy_bitslip20[5]),
+	.D7(a7ddrphy_bitslip20[6]),
+	.D8(a7ddrphy_bitslip20[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay2),
-	.TQ(main_a7ddrphy_dq_t2)
+	.OQ(a7ddrphy_dq_o_nodelay2),
+	.TQ(a7ddrphy_dq_t2)
 );
 
 ISERDESE2 #(
@@ -14334,16 +14777,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip21[7]),
-	.Q2(main_a7ddrphy_bitslip21[6]),
-	.Q3(main_a7ddrphy_bitslip21[5]),
-	.Q4(main_a7ddrphy_bitslip21[4]),
-	.Q5(main_a7ddrphy_bitslip21[3]),
-	.Q6(main_a7ddrphy_bitslip21[2]),
-	.Q7(main_a7ddrphy_bitslip21[1]),
-	.Q8(main_a7ddrphy_bitslip21[0])
+	.DDLY(a7ddrphy_dq_i_delayed2),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip21[7]),
+	.Q2(a7ddrphy_bitslip21[6]),
+	.Q3(a7ddrphy_bitslip21[5]),
+	.Q4(a7ddrphy_bitslip21[4]),
+	.Q5(a7ddrphy_bitslip21[3]),
+	.Q6(a7ddrphy_bitslip21[2]),
+	.Q7(a7ddrphy_bitslip21[1]),
+	.Q8(a7ddrphy_bitslip21[0])
 );
 
 IDELAYE2 #(
@@ -14357,19 +14800,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_2 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay2),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay2),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed2)
+	.DATAOUT(a7ddrphy_dq_i_delayed2)
 );
 
 IOBUF IOBUF_2(
-	.I(main_a7ddrphy_dq_o_nodelay2),
-	.T(main_a7ddrphy_dq_t2),
+	.I(a7ddrphy_dq_o_nodelay2),
+	.T(a7ddrphy_dq_t2),
 	.IO(ddram_dq[2]),
-	.O(main_a7ddrphy_dq_i_nodelay2)
+	.O(a7ddrphy_dq_i_nodelay2)
 );
 
 OSERDESE2 #(
@@ -14381,20 +14824,20 @@ OSERDESE2 #(
 ) OSERDESE2_32 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip30[0]),
-	.D2(main_a7ddrphy_bitslip30[1]),
-	.D3(main_a7ddrphy_bitslip30[2]),
-	.D4(main_a7ddrphy_bitslip30[3]),
-	.D5(main_a7ddrphy_bitslip30[4]),
-	.D6(main_a7ddrphy_bitslip30[5]),
-	.D7(main_a7ddrphy_bitslip30[6]),
-	.D8(main_a7ddrphy_bitslip30[7]),
+	.D1(a7ddrphy_bitslip30[0]),
+	.D2(a7ddrphy_bitslip30[1]),
+	.D3(a7ddrphy_bitslip30[2]),
+	.D4(a7ddrphy_bitslip30[3]),
+	.D5(a7ddrphy_bitslip30[4]),
+	.D6(a7ddrphy_bitslip30[5]),
+	.D7(a7ddrphy_bitslip30[6]),
+	.D8(a7ddrphy_bitslip30[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay3),
-	.TQ(main_a7ddrphy_dq_t3)
+	.OQ(a7ddrphy_dq_o_nodelay3),
+	.TQ(a7ddrphy_dq_t3)
 );
 
 ISERDESE2 #(
@@ -14410,16 +14853,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip31[7]),
-	.Q2(main_a7ddrphy_bitslip31[6]),
-	.Q3(main_a7ddrphy_bitslip31[5]),
-	.Q4(main_a7ddrphy_bitslip31[4]),
-	.Q5(main_a7ddrphy_bitslip31[3]),
-	.Q6(main_a7ddrphy_bitslip31[2]),
-	.Q7(main_a7ddrphy_bitslip31[1]),
-	.Q8(main_a7ddrphy_bitslip31[0])
+	.DDLY(a7ddrphy_dq_i_delayed3),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip31[7]),
+	.Q2(a7ddrphy_bitslip31[6]),
+	.Q3(a7ddrphy_bitslip31[5]),
+	.Q4(a7ddrphy_bitslip31[4]),
+	.Q5(a7ddrphy_bitslip31[3]),
+	.Q6(a7ddrphy_bitslip31[2]),
+	.Q7(a7ddrphy_bitslip31[1]),
+	.Q8(a7ddrphy_bitslip31[0])
 );
 
 IDELAYE2 #(
@@ -14433,19 +14876,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_3 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay3),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay3),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed3)
+	.DATAOUT(a7ddrphy_dq_i_delayed3)
 );
 
 IOBUF IOBUF_3(
-	.I(main_a7ddrphy_dq_o_nodelay3),
-	.T(main_a7ddrphy_dq_t3),
+	.I(a7ddrphy_dq_o_nodelay3),
+	.T(a7ddrphy_dq_t3),
 	.IO(ddram_dq[3]),
-	.O(main_a7ddrphy_dq_i_nodelay3)
+	.O(a7ddrphy_dq_i_nodelay3)
 );
 
 OSERDESE2 #(
@@ -14457,20 +14900,20 @@ OSERDESE2 #(
 ) OSERDESE2_33 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip40[0]),
-	.D2(main_a7ddrphy_bitslip40[1]),
-	.D3(main_a7ddrphy_bitslip40[2]),
-	.D4(main_a7ddrphy_bitslip40[3]),
-	.D5(main_a7ddrphy_bitslip40[4]),
-	.D6(main_a7ddrphy_bitslip40[5]),
-	.D7(main_a7ddrphy_bitslip40[6]),
-	.D8(main_a7ddrphy_bitslip40[7]),
+	.D1(a7ddrphy_bitslip40[0]),
+	.D2(a7ddrphy_bitslip40[1]),
+	.D3(a7ddrphy_bitslip40[2]),
+	.D4(a7ddrphy_bitslip40[3]),
+	.D5(a7ddrphy_bitslip40[4]),
+	.D6(a7ddrphy_bitslip40[5]),
+	.D7(a7ddrphy_bitslip40[6]),
+	.D8(a7ddrphy_bitslip40[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay4),
-	.TQ(main_a7ddrphy_dq_t4)
+	.OQ(a7ddrphy_dq_o_nodelay4),
+	.TQ(a7ddrphy_dq_t4)
 );
 
 ISERDESE2 #(
@@ -14486,16 +14929,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip41[7]),
-	.Q2(main_a7ddrphy_bitslip41[6]),
-	.Q3(main_a7ddrphy_bitslip41[5]),
-	.Q4(main_a7ddrphy_bitslip41[4]),
-	.Q5(main_a7ddrphy_bitslip41[3]),
-	.Q6(main_a7ddrphy_bitslip41[2]),
-	.Q7(main_a7ddrphy_bitslip41[1]),
-	.Q8(main_a7ddrphy_bitslip41[0])
+	.DDLY(a7ddrphy_dq_i_delayed4),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip41[7]),
+	.Q2(a7ddrphy_bitslip41[6]),
+	.Q3(a7ddrphy_bitslip41[5]),
+	.Q4(a7ddrphy_bitslip41[4]),
+	.Q5(a7ddrphy_bitslip41[3]),
+	.Q6(a7ddrphy_bitslip41[2]),
+	.Q7(a7ddrphy_bitslip41[1]),
+	.Q8(a7ddrphy_bitslip41[0])
 );
 
 IDELAYE2 #(
@@ -14509,19 +14952,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_4 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay4),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay4),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed4)
+	.DATAOUT(a7ddrphy_dq_i_delayed4)
 );
 
 IOBUF IOBUF_4(
-	.I(main_a7ddrphy_dq_o_nodelay4),
-	.T(main_a7ddrphy_dq_t4),
+	.I(a7ddrphy_dq_o_nodelay4),
+	.T(a7ddrphy_dq_t4),
 	.IO(ddram_dq[4]),
-	.O(main_a7ddrphy_dq_i_nodelay4)
+	.O(a7ddrphy_dq_i_nodelay4)
 );
 
 OSERDESE2 #(
@@ -14533,20 +14976,20 @@ OSERDESE2 #(
 ) OSERDESE2_34 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip50[0]),
-	.D2(main_a7ddrphy_bitslip50[1]),
-	.D3(main_a7ddrphy_bitslip50[2]),
-	.D4(main_a7ddrphy_bitslip50[3]),
-	.D5(main_a7ddrphy_bitslip50[4]),
-	.D6(main_a7ddrphy_bitslip50[5]),
-	.D7(main_a7ddrphy_bitslip50[6]),
-	.D8(main_a7ddrphy_bitslip50[7]),
+	.D1(a7ddrphy_bitslip50[0]),
+	.D2(a7ddrphy_bitslip50[1]),
+	.D3(a7ddrphy_bitslip50[2]),
+	.D4(a7ddrphy_bitslip50[3]),
+	.D5(a7ddrphy_bitslip50[4]),
+	.D6(a7ddrphy_bitslip50[5]),
+	.D7(a7ddrphy_bitslip50[6]),
+	.D8(a7ddrphy_bitslip50[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay5),
-	.TQ(main_a7ddrphy_dq_t5)
+	.OQ(a7ddrphy_dq_o_nodelay5),
+	.TQ(a7ddrphy_dq_t5)
 );
 
 ISERDESE2 #(
@@ -14562,16 +15005,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip51[7]),
-	.Q2(main_a7ddrphy_bitslip51[6]),
-	.Q3(main_a7ddrphy_bitslip51[5]),
-	.Q4(main_a7ddrphy_bitslip51[4]),
-	.Q5(main_a7ddrphy_bitslip51[3]),
-	.Q6(main_a7ddrphy_bitslip51[2]),
-	.Q7(main_a7ddrphy_bitslip51[1]),
-	.Q8(main_a7ddrphy_bitslip51[0])
+	.DDLY(a7ddrphy_dq_i_delayed5),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip51[7]),
+	.Q2(a7ddrphy_bitslip51[6]),
+	.Q3(a7ddrphy_bitslip51[5]),
+	.Q4(a7ddrphy_bitslip51[4]),
+	.Q5(a7ddrphy_bitslip51[3]),
+	.Q6(a7ddrphy_bitslip51[2]),
+	.Q7(a7ddrphy_bitslip51[1]),
+	.Q8(a7ddrphy_bitslip51[0])
 );
 
 IDELAYE2 #(
@@ -14585,19 +15028,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_5 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay5),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay5),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed5)
+	.DATAOUT(a7ddrphy_dq_i_delayed5)
 );
 
 IOBUF IOBUF_5(
-	.I(main_a7ddrphy_dq_o_nodelay5),
-	.T(main_a7ddrphy_dq_t5),
+	.I(a7ddrphy_dq_o_nodelay5),
+	.T(a7ddrphy_dq_t5),
 	.IO(ddram_dq[5]),
-	.O(main_a7ddrphy_dq_i_nodelay5)
+	.O(a7ddrphy_dq_i_nodelay5)
 );
 
 OSERDESE2 #(
@@ -14609,20 +15052,20 @@ OSERDESE2 #(
 ) OSERDESE2_35 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip60[0]),
-	.D2(main_a7ddrphy_bitslip60[1]),
-	.D3(main_a7ddrphy_bitslip60[2]),
-	.D4(main_a7ddrphy_bitslip60[3]),
-	.D5(main_a7ddrphy_bitslip60[4]),
-	.D6(main_a7ddrphy_bitslip60[5]),
-	.D7(main_a7ddrphy_bitslip60[6]),
-	.D8(main_a7ddrphy_bitslip60[7]),
+	.D1(a7ddrphy_bitslip60[0]),
+	.D2(a7ddrphy_bitslip60[1]),
+	.D3(a7ddrphy_bitslip60[2]),
+	.D4(a7ddrphy_bitslip60[3]),
+	.D5(a7ddrphy_bitslip60[4]),
+	.D6(a7ddrphy_bitslip60[5]),
+	.D7(a7ddrphy_bitslip60[6]),
+	.D8(a7ddrphy_bitslip60[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay6),
-	.TQ(main_a7ddrphy_dq_t6)
+	.OQ(a7ddrphy_dq_o_nodelay6),
+	.TQ(a7ddrphy_dq_t6)
 );
 
 ISERDESE2 #(
@@ -14638,16 +15081,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip61[7]),
-	.Q2(main_a7ddrphy_bitslip61[6]),
-	.Q3(main_a7ddrphy_bitslip61[5]),
-	.Q4(main_a7ddrphy_bitslip61[4]),
-	.Q5(main_a7ddrphy_bitslip61[3]),
-	.Q6(main_a7ddrphy_bitslip61[2]),
-	.Q7(main_a7ddrphy_bitslip61[1]),
-	.Q8(main_a7ddrphy_bitslip61[0])
+	.DDLY(a7ddrphy_dq_i_delayed6),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip61[7]),
+	.Q2(a7ddrphy_bitslip61[6]),
+	.Q3(a7ddrphy_bitslip61[5]),
+	.Q4(a7ddrphy_bitslip61[4]),
+	.Q5(a7ddrphy_bitslip61[3]),
+	.Q6(a7ddrphy_bitslip61[2]),
+	.Q7(a7ddrphy_bitslip61[1]),
+	.Q8(a7ddrphy_bitslip61[0])
 );
 
 IDELAYE2 #(
@@ -14661,19 +15104,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_6 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay6),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay6),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed6)
+	.DATAOUT(a7ddrphy_dq_i_delayed6)
 );
 
 IOBUF IOBUF_6(
-	.I(main_a7ddrphy_dq_o_nodelay6),
-	.T(main_a7ddrphy_dq_t6),
+	.I(a7ddrphy_dq_o_nodelay6),
+	.T(a7ddrphy_dq_t6),
 	.IO(ddram_dq[6]),
-	.O(main_a7ddrphy_dq_i_nodelay6)
+	.O(a7ddrphy_dq_i_nodelay6)
 );
 
 OSERDESE2 #(
@@ -14685,20 +15128,20 @@ OSERDESE2 #(
 ) OSERDESE2_36 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip70[0]),
-	.D2(main_a7ddrphy_bitslip70[1]),
-	.D3(main_a7ddrphy_bitslip70[2]),
-	.D4(main_a7ddrphy_bitslip70[3]),
-	.D5(main_a7ddrphy_bitslip70[4]),
-	.D6(main_a7ddrphy_bitslip70[5]),
-	.D7(main_a7ddrphy_bitslip70[6]),
-	.D8(main_a7ddrphy_bitslip70[7]),
+	.D1(a7ddrphy_bitslip70[0]),
+	.D2(a7ddrphy_bitslip70[1]),
+	.D3(a7ddrphy_bitslip70[2]),
+	.D4(a7ddrphy_bitslip70[3]),
+	.D5(a7ddrphy_bitslip70[4]),
+	.D6(a7ddrphy_bitslip70[5]),
+	.D7(a7ddrphy_bitslip70[6]),
+	.D8(a7ddrphy_bitslip70[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay7),
-	.TQ(main_a7ddrphy_dq_t7)
+	.OQ(a7ddrphy_dq_o_nodelay7),
+	.TQ(a7ddrphy_dq_t7)
 );
 
 ISERDESE2 #(
@@ -14714,16 +15157,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip71[7]),
-	.Q2(main_a7ddrphy_bitslip71[6]),
-	.Q3(main_a7ddrphy_bitslip71[5]),
-	.Q4(main_a7ddrphy_bitslip71[4]),
-	.Q5(main_a7ddrphy_bitslip71[3]),
-	.Q6(main_a7ddrphy_bitslip71[2]),
-	.Q7(main_a7ddrphy_bitslip71[1]),
-	.Q8(main_a7ddrphy_bitslip71[0])
+	.DDLY(a7ddrphy_dq_i_delayed7),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip71[7]),
+	.Q2(a7ddrphy_bitslip71[6]),
+	.Q3(a7ddrphy_bitslip71[5]),
+	.Q4(a7ddrphy_bitslip71[4]),
+	.Q5(a7ddrphy_bitslip71[3]),
+	.Q6(a7ddrphy_bitslip71[2]),
+	.Q7(a7ddrphy_bitslip71[1]),
+	.Q8(a7ddrphy_bitslip71[0])
 );
 
 IDELAYE2 #(
@@ -14737,19 +15180,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_7 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay7),
+	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay7),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed7)
+	.DATAOUT(a7ddrphy_dq_i_delayed7)
 );
 
 IOBUF IOBUF_7(
-	.I(main_a7ddrphy_dq_o_nodelay7),
-	.T(main_a7ddrphy_dq_t7),
+	.I(a7ddrphy_dq_o_nodelay7),
+	.T(a7ddrphy_dq_t7),
 	.IO(ddram_dq[7]),
-	.O(main_a7ddrphy_dq_i_nodelay7)
+	.O(a7ddrphy_dq_i_nodelay7)
 );
 
 OSERDESE2 #(
@@ -14761,20 +15204,20 @@ OSERDESE2 #(
 ) OSERDESE2_37 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip80[0]),
-	.D2(main_a7ddrphy_bitslip80[1]),
-	.D3(main_a7ddrphy_bitslip80[2]),
-	.D4(main_a7ddrphy_bitslip80[3]),
-	.D5(main_a7ddrphy_bitslip80[4]),
-	.D6(main_a7ddrphy_bitslip80[5]),
-	.D7(main_a7ddrphy_bitslip80[6]),
-	.D8(main_a7ddrphy_bitslip80[7]),
+	.D1(a7ddrphy_bitslip80[0]),
+	.D2(a7ddrphy_bitslip80[1]),
+	.D3(a7ddrphy_bitslip80[2]),
+	.D4(a7ddrphy_bitslip80[3]),
+	.D5(a7ddrphy_bitslip80[4]),
+	.D6(a7ddrphy_bitslip80[5]),
+	.D7(a7ddrphy_bitslip80[6]),
+	.D8(a7ddrphy_bitslip80[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay8),
-	.TQ(main_a7ddrphy_dq_t8)
+	.OQ(a7ddrphy_dq_o_nodelay8),
+	.TQ(a7ddrphy_dq_t8)
 );
 
 ISERDESE2 #(
@@ -14790,16 +15233,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip81[7]),
-	.Q2(main_a7ddrphy_bitslip81[6]),
-	.Q3(main_a7ddrphy_bitslip81[5]),
-	.Q4(main_a7ddrphy_bitslip81[4]),
-	.Q5(main_a7ddrphy_bitslip81[3]),
-	.Q6(main_a7ddrphy_bitslip81[2]),
-	.Q7(main_a7ddrphy_bitslip81[1]),
-	.Q8(main_a7ddrphy_bitslip81[0])
+	.DDLY(a7ddrphy_dq_i_delayed8),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip81[7]),
+	.Q2(a7ddrphy_bitslip81[6]),
+	.Q3(a7ddrphy_bitslip81[5]),
+	.Q4(a7ddrphy_bitslip81[4]),
+	.Q5(a7ddrphy_bitslip81[3]),
+	.Q6(a7ddrphy_bitslip81[2]),
+	.Q7(a7ddrphy_bitslip81[1]),
+	.Q8(a7ddrphy_bitslip81[0])
 );
 
 IDELAYE2 #(
@@ -14813,19 +15256,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_8 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay8),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay8),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed8)
+	.DATAOUT(a7ddrphy_dq_i_delayed8)
 );
 
 IOBUF IOBUF_8(
-	.I(main_a7ddrphy_dq_o_nodelay8),
-	.T(main_a7ddrphy_dq_t8),
+	.I(a7ddrphy_dq_o_nodelay8),
+	.T(a7ddrphy_dq_t8),
 	.IO(ddram_dq[8]),
-	.O(main_a7ddrphy_dq_i_nodelay8)
+	.O(a7ddrphy_dq_i_nodelay8)
 );
 
 OSERDESE2 #(
@@ -14837,20 +15280,20 @@ OSERDESE2 #(
 ) OSERDESE2_38 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip90[0]),
-	.D2(main_a7ddrphy_bitslip90[1]),
-	.D3(main_a7ddrphy_bitslip90[2]),
-	.D4(main_a7ddrphy_bitslip90[3]),
-	.D5(main_a7ddrphy_bitslip90[4]),
-	.D6(main_a7ddrphy_bitslip90[5]),
-	.D7(main_a7ddrphy_bitslip90[6]),
-	.D8(main_a7ddrphy_bitslip90[7]),
+	.D1(a7ddrphy_bitslip90[0]),
+	.D2(a7ddrphy_bitslip90[1]),
+	.D3(a7ddrphy_bitslip90[2]),
+	.D4(a7ddrphy_bitslip90[3]),
+	.D5(a7ddrphy_bitslip90[4]),
+	.D6(a7ddrphy_bitslip90[5]),
+	.D7(a7ddrphy_bitslip90[6]),
+	.D8(a7ddrphy_bitslip90[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay9),
-	.TQ(main_a7ddrphy_dq_t9)
+	.OQ(a7ddrphy_dq_o_nodelay9),
+	.TQ(a7ddrphy_dq_t9)
 );
 
 ISERDESE2 #(
@@ -14866,16 +15309,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip91[7]),
-	.Q2(main_a7ddrphy_bitslip91[6]),
-	.Q3(main_a7ddrphy_bitslip91[5]),
-	.Q4(main_a7ddrphy_bitslip91[4]),
-	.Q5(main_a7ddrphy_bitslip91[3]),
-	.Q6(main_a7ddrphy_bitslip91[2]),
-	.Q7(main_a7ddrphy_bitslip91[1]),
-	.Q8(main_a7ddrphy_bitslip91[0])
+	.DDLY(a7ddrphy_dq_i_delayed9),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip91[7]),
+	.Q2(a7ddrphy_bitslip91[6]),
+	.Q3(a7ddrphy_bitslip91[5]),
+	.Q4(a7ddrphy_bitslip91[4]),
+	.Q5(a7ddrphy_bitslip91[3]),
+	.Q6(a7ddrphy_bitslip91[2]),
+	.Q7(a7ddrphy_bitslip91[1]),
+	.Q8(a7ddrphy_bitslip91[0])
 );
 
 IDELAYE2 #(
@@ -14889,19 +15332,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_9 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay9),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay9),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed9)
+	.DATAOUT(a7ddrphy_dq_i_delayed9)
 );
 
 IOBUF IOBUF_9(
-	.I(main_a7ddrphy_dq_o_nodelay9),
-	.T(main_a7ddrphy_dq_t9),
+	.I(a7ddrphy_dq_o_nodelay9),
+	.T(a7ddrphy_dq_t9),
 	.IO(ddram_dq[9]),
-	.O(main_a7ddrphy_dq_i_nodelay9)
+	.O(a7ddrphy_dq_i_nodelay9)
 );
 
 OSERDESE2 #(
@@ -14913,20 +15356,20 @@ OSERDESE2 #(
 ) OSERDESE2_39 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip100[0]),
-	.D2(main_a7ddrphy_bitslip100[1]),
-	.D3(main_a7ddrphy_bitslip100[2]),
-	.D4(main_a7ddrphy_bitslip100[3]),
-	.D5(main_a7ddrphy_bitslip100[4]),
-	.D6(main_a7ddrphy_bitslip100[5]),
-	.D7(main_a7ddrphy_bitslip100[6]),
-	.D8(main_a7ddrphy_bitslip100[7]),
+	.D1(a7ddrphy_bitslip100[0]),
+	.D2(a7ddrphy_bitslip100[1]),
+	.D3(a7ddrphy_bitslip100[2]),
+	.D4(a7ddrphy_bitslip100[3]),
+	.D5(a7ddrphy_bitslip100[4]),
+	.D6(a7ddrphy_bitslip100[5]),
+	.D7(a7ddrphy_bitslip100[6]),
+	.D8(a7ddrphy_bitslip100[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay10),
-	.TQ(main_a7ddrphy_dq_t10)
+	.OQ(a7ddrphy_dq_o_nodelay10),
+	.TQ(a7ddrphy_dq_t10)
 );
 
 ISERDESE2 #(
@@ -14942,16 +15385,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip101[7]),
-	.Q2(main_a7ddrphy_bitslip101[6]),
-	.Q3(main_a7ddrphy_bitslip101[5]),
-	.Q4(main_a7ddrphy_bitslip101[4]),
-	.Q5(main_a7ddrphy_bitslip101[3]),
-	.Q6(main_a7ddrphy_bitslip101[2]),
-	.Q7(main_a7ddrphy_bitslip101[1]),
-	.Q8(main_a7ddrphy_bitslip101[0])
+	.DDLY(a7ddrphy_dq_i_delayed10),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip101[7]),
+	.Q2(a7ddrphy_bitslip101[6]),
+	.Q3(a7ddrphy_bitslip101[5]),
+	.Q4(a7ddrphy_bitslip101[4]),
+	.Q5(a7ddrphy_bitslip101[3]),
+	.Q6(a7ddrphy_bitslip101[2]),
+	.Q7(a7ddrphy_bitslip101[1]),
+	.Q8(a7ddrphy_bitslip101[0])
 );
 
 IDELAYE2 #(
@@ -14965,19 +15408,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_10 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay10),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay10),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed10)
+	.DATAOUT(a7ddrphy_dq_i_delayed10)
 );
 
 IOBUF IOBUF_10(
-	.I(main_a7ddrphy_dq_o_nodelay10),
-	.T(main_a7ddrphy_dq_t10),
+	.I(a7ddrphy_dq_o_nodelay10),
+	.T(a7ddrphy_dq_t10),
 	.IO(ddram_dq[10]),
-	.O(main_a7ddrphy_dq_i_nodelay10)
+	.O(a7ddrphy_dq_i_nodelay10)
 );
 
 OSERDESE2 #(
@@ -14989,20 +15432,20 @@ OSERDESE2 #(
 ) OSERDESE2_40 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip110[0]),
-	.D2(main_a7ddrphy_bitslip110[1]),
-	.D3(main_a7ddrphy_bitslip110[2]),
-	.D4(main_a7ddrphy_bitslip110[3]),
-	.D5(main_a7ddrphy_bitslip110[4]),
-	.D6(main_a7ddrphy_bitslip110[5]),
-	.D7(main_a7ddrphy_bitslip110[6]),
-	.D8(main_a7ddrphy_bitslip110[7]),
+	.D1(a7ddrphy_bitslip110[0]),
+	.D2(a7ddrphy_bitslip110[1]),
+	.D3(a7ddrphy_bitslip110[2]),
+	.D4(a7ddrphy_bitslip110[3]),
+	.D5(a7ddrphy_bitslip110[4]),
+	.D6(a7ddrphy_bitslip110[5]),
+	.D7(a7ddrphy_bitslip110[6]),
+	.D8(a7ddrphy_bitslip110[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay11),
-	.TQ(main_a7ddrphy_dq_t11)
+	.OQ(a7ddrphy_dq_o_nodelay11),
+	.TQ(a7ddrphy_dq_t11)
 );
 
 ISERDESE2 #(
@@ -15018,16 +15461,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip111[7]),
-	.Q2(main_a7ddrphy_bitslip111[6]),
-	.Q3(main_a7ddrphy_bitslip111[5]),
-	.Q4(main_a7ddrphy_bitslip111[4]),
-	.Q5(main_a7ddrphy_bitslip111[3]),
-	.Q6(main_a7ddrphy_bitslip111[2]),
-	.Q7(main_a7ddrphy_bitslip111[1]),
-	.Q8(main_a7ddrphy_bitslip111[0])
+	.DDLY(a7ddrphy_dq_i_delayed11),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip111[7]),
+	.Q2(a7ddrphy_bitslip111[6]),
+	.Q3(a7ddrphy_bitslip111[5]),
+	.Q4(a7ddrphy_bitslip111[4]),
+	.Q5(a7ddrphy_bitslip111[3]),
+	.Q6(a7ddrphy_bitslip111[2]),
+	.Q7(a7ddrphy_bitslip111[1]),
+	.Q8(a7ddrphy_bitslip111[0])
 );
 
 IDELAYE2 #(
@@ -15041,19 +15484,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_11 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay11),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay11),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed11)
+	.DATAOUT(a7ddrphy_dq_i_delayed11)
 );
 
 IOBUF IOBUF_11(
-	.I(main_a7ddrphy_dq_o_nodelay11),
-	.T(main_a7ddrphy_dq_t11),
+	.I(a7ddrphy_dq_o_nodelay11),
+	.T(a7ddrphy_dq_t11),
 	.IO(ddram_dq[11]),
-	.O(main_a7ddrphy_dq_i_nodelay11)
+	.O(a7ddrphy_dq_i_nodelay11)
 );
 
 OSERDESE2 #(
@@ -15065,20 +15508,20 @@ OSERDESE2 #(
 ) OSERDESE2_41 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip120[0]),
-	.D2(main_a7ddrphy_bitslip120[1]),
-	.D3(main_a7ddrphy_bitslip120[2]),
-	.D4(main_a7ddrphy_bitslip120[3]),
-	.D5(main_a7ddrphy_bitslip120[4]),
-	.D6(main_a7ddrphy_bitslip120[5]),
-	.D7(main_a7ddrphy_bitslip120[6]),
-	.D8(main_a7ddrphy_bitslip120[7]),
+	.D1(a7ddrphy_bitslip120[0]),
+	.D2(a7ddrphy_bitslip120[1]),
+	.D3(a7ddrphy_bitslip120[2]),
+	.D4(a7ddrphy_bitslip120[3]),
+	.D5(a7ddrphy_bitslip120[4]),
+	.D6(a7ddrphy_bitslip120[5]),
+	.D7(a7ddrphy_bitslip120[6]),
+	.D8(a7ddrphy_bitslip120[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay12),
-	.TQ(main_a7ddrphy_dq_t12)
+	.OQ(a7ddrphy_dq_o_nodelay12),
+	.TQ(a7ddrphy_dq_t12)
 );
 
 ISERDESE2 #(
@@ -15094,16 +15537,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip121[7]),
-	.Q2(main_a7ddrphy_bitslip121[6]),
-	.Q3(main_a7ddrphy_bitslip121[5]),
-	.Q4(main_a7ddrphy_bitslip121[4]),
-	.Q5(main_a7ddrphy_bitslip121[3]),
-	.Q6(main_a7ddrphy_bitslip121[2]),
-	.Q7(main_a7ddrphy_bitslip121[1]),
-	.Q8(main_a7ddrphy_bitslip121[0])
+	.DDLY(a7ddrphy_dq_i_delayed12),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip121[7]),
+	.Q2(a7ddrphy_bitslip121[6]),
+	.Q3(a7ddrphy_bitslip121[5]),
+	.Q4(a7ddrphy_bitslip121[4]),
+	.Q5(a7ddrphy_bitslip121[3]),
+	.Q6(a7ddrphy_bitslip121[2]),
+	.Q7(a7ddrphy_bitslip121[1]),
+	.Q8(a7ddrphy_bitslip121[0])
 );
 
 IDELAYE2 #(
@@ -15117,19 +15560,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_12 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay12),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay12),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed12)
+	.DATAOUT(a7ddrphy_dq_i_delayed12)
 );
 
 IOBUF IOBUF_12(
-	.I(main_a7ddrphy_dq_o_nodelay12),
-	.T(main_a7ddrphy_dq_t12),
+	.I(a7ddrphy_dq_o_nodelay12),
+	.T(a7ddrphy_dq_t12),
 	.IO(ddram_dq[12]),
-	.O(main_a7ddrphy_dq_i_nodelay12)
+	.O(a7ddrphy_dq_i_nodelay12)
 );
 
 OSERDESE2 #(
@@ -15141,20 +15584,20 @@ OSERDESE2 #(
 ) OSERDESE2_42 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip130[0]),
-	.D2(main_a7ddrphy_bitslip130[1]),
-	.D3(main_a7ddrphy_bitslip130[2]),
-	.D4(main_a7ddrphy_bitslip130[3]),
-	.D5(main_a7ddrphy_bitslip130[4]),
-	.D6(main_a7ddrphy_bitslip130[5]),
-	.D7(main_a7ddrphy_bitslip130[6]),
-	.D8(main_a7ddrphy_bitslip130[7]),
+	.D1(a7ddrphy_bitslip130[0]),
+	.D2(a7ddrphy_bitslip130[1]),
+	.D3(a7ddrphy_bitslip130[2]),
+	.D4(a7ddrphy_bitslip130[3]),
+	.D5(a7ddrphy_bitslip130[4]),
+	.D6(a7ddrphy_bitslip130[5]),
+	.D7(a7ddrphy_bitslip130[6]),
+	.D8(a7ddrphy_bitslip130[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay13),
-	.TQ(main_a7ddrphy_dq_t13)
+	.OQ(a7ddrphy_dq_o_nodelay13),
+	.TQ(a7ddrphy_dq_t13)
 );
 
 ISERDESE2 #(
@@ -15170,16 +15613,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip131[7]),
-	.Q2(main_a7ddrphy_bitslip131[6]),
-	.Q3(main_a7ddrphy_bitslip131[5]),
-	.Q4(main_a7ddrphy_bitslip131[4]),
-	.Q5(main_a7ddrphy_bitslip131[3]),
-	.Q6(main_a7ddrphy_bitslip131[2]),
-	.Q7(main_a7ddrphy_bitslip131[1]),
-	.Q8(main_a7ddrphy_bitslip131[0])
+	.DDLY(a7ddrphy_dq_i_delayed13),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip131[7]),
+	.Q2(a7ddrphy_bitslip131[6]),
+	.Q3(a7ddrphy_bitslip131[5]),
+	.Q4(a7ddrphy_bitslip131[4]),
+	.Q5(a7ddrphy_bitslip131[3]),
+	.Q6(a7ddrphy_bitslip131[2]),
+	.Q7(a7ddrphy_bitslip131[1]),
+	.Q8(a7ddrphy_bitslip131[0])
 );
 
 IDELAYE2 #(
@@ -15193,19 +15636,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_13 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay13),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay13),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed13)
+	.DATAOUT(a7ddrphy_dq_i_delayed13)
 );
 
 IOBUF IOBUF_13(
-	.I(main_a7ddrphy_dq_o_nodelay13),
-	.T(main_a7ddrphy_dq_t13),
+	.I(a7ddrphy_dq_o_nodelay13),
+	.T(a7ddrphy_dq_t13),
 	.IO(ddram_dq[13]),
-	.O(main_a7ddrphy_dq_i_nodelay13)
+	.O(a7ddrphy_dq_i_nodelay13)
 );
 
 OSERDESE2 #(
@@ -15217,20 +15660,20 @@ OSERDESE2 #(
 ) OSERDESE2_43 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip140[0]),
-	.D2(main_a7ddrphy_bitslip140[1]),
-	.D3(main_a7ddrphy_bitslip140[2]),
-	.D4(main_a7ddrphy_bitslip140[3]),
-	.D5(main_a7ddrphy_bitslip140[4]),
-	.D6(main_a7ddrphy_bitslip140[5]),
-	.D7(main_a7ddrphy_bitslip140[6]),
-	.D8(main_a7ddrphy_bitslip140[7]),
+	.D1(a7ddrphy_bitslip140[0]),
+	.D2(a7ddrphy_bitslip140[1]),
+	.D3(a7ddrphy_bitslip140[2]),
+	.D4(a7ddrphy_bitslip140[3]),
+	.D5(a7ddrphy_bitslip140[4]),
+	.D6(a7ddrphy_bitslip140[5]),
+	.D7(a7ddrphy_bitslip140[6]),
+	.D8(a7ddrphy_bitslip140[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay14),
-	.TQ(main_a7ddrphy_dq_t14)
+	.OQ(a7ddrphy_dq_o_nodelay14),
+	.TQ(a7ddrphy_dq_t14)
 );
 
 ISERDESE2 #(
@@ -15246,16 +15689,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip141[7]),
-	.Q2(main_a7ddrphy_bitslip141[6]),
-	.Q3(main_a7ddrphy_bitslip141[5]),
-	.Q4(main_a7ddrphy_bitslip141[4]),
-	.Q5(main_a7ddrphy_bitslip141[3]),
-	.Q6(main_a7ddrphy_bitslip141[2]),
-	.Q7(main_a7ddrphy_bitslip141[1]),
-	.Q8(main_a7ddrphy_bitslip141[0])
+	.DDLY(a7ddrphy_dq_i_delayed14),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip141[7]),
+	.Q2(a7ddrphy_bitslip141[6]),
+	.Q3(a7ddrphy_bitslip141[5]),
+	.Q4(a7ddrphy_bitslip141[4]),
+	.Q5(a7ddrphy_bitslip141[3]),
+	.Q6(a7ddrphy_bitslip141[2]),
+	.Q7(a7ddrphy_bitslip141[1]),
+	.Q8(a7ddrphy_bitslip141[0])
 );
 
 IDELAYE2 #(
@@ -15269,19 +15712,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_14 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay14),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay14),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed14)
+	.DATAOUT(a7ddrphy_dq_i_delayed14)
 );
 
 IOBUF IOBUF_14(
-	.I(main_a7ddrphy_dq_o_nodelay14),
-	.T(main_a7ddrphy_dq_t14),
+	.I(a7ddrphy_dq_o_nodelay14),
+	.T(a7ddrphy_dq_t14),
 	.IO(ddram_dq[14]),
-	.O(main_a7ddrphy_dq_i_nodelay14)
+	.O(a7ddrphy_dq_i_nodelay14)
 );
 
 OSERDESE2 #(
@@ -15293,20 +15736,20 @@ OSERDESE2 #(
 ) OSERDESE2_44 (
 	.CLK(sys4x_clk),
 	.CLKDIV(sys_clk),
-	.D1(main_a7ddrphy_bitslip150[0]),
-	.D2(main_a7ddrphy_bitslip150[1]),
-	.D3(main_a7ddrphy_bitslip150[2]),
-	.D4(main_a7ddrphy_bitslip150[3]),
-	.D5(main_a7ddrphy_bitslip150[4]),
-	.D6(main_a7ddrphy_bitslip150[5]),
-	.D7(main_a7ddrphy_bitslip150[6]),
-	.D8(main_a7ddrphy_bitslip150[7]),
+	.D1(a7ddrphy_bitslip150[0]),
+	.D2(a7ddrphy_bitslip150[1]),
+	.D3(a7ddrphy_bitslip150[2]),
+	.D4(a7ddrphy_bitslip150[3]),
+	.D5(a7ddrphy_bitslip150[4]),
+	.D6(a7ddrphy_bitslip150[5]),
+	.D7(a7ddrphy_bitslip150[6]),
+	.D8(a7ddrphy_bitslip150[7]),
 	.OCE(1'd1),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
 	.TCE(1'd1),
-	.OQ(main_a7ddrphy_dq_o_nodelay15),
-	.TQ(main_a7ddrphy_dq_t15)
+	.OQ(a7ddrphy_dq_o_nodelay15),
+	.TQ(a7ddrphy_dq_t15)
 );
 
 ISERDESE2 #(
@@ -15322,16 +15765,16 @@ ISERDESE2 #(
 	.CLK(sys4x_clk),
 	.CLKB((~sys4x_clk)),
 	.CLKDIV(sys_clk),
-	.DDLY(main_a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | main_a7ddrphy_rst_storage)),
-	.Q1(main_a7ddrphy_bitslip151[7]),
-	.Q2(main_a7ddrphy_bitslip151[6]),
-	.Q3(main_a7ddrphy_bitslip151[5]),
-	.Q4(main_a7ddrphy_bitslip151[4]),
-	.Q5(main_a7ddrphy_bitslip151[3]),
-	.Q6(main_a7ddrphy_bitslip151[2]),
-	.Q7(main_a7ddrphy_bitslip151[1]),
-	.Q8(main_a7ddrphy_bitslip151[0])
+	.DDLY(a7ddrphy_dq_i_delayed15),
+	.RST((sys_rst | a7ddrphy_rst_storage)),
+	.Q1(a7ddrphy_bitslip151[7]),
+	.Q2(a7ddrphy_bitslip151[6]),
+	.Q3(a7ddrphy_bitslip151[5]),
+	.Q4(a7ddrphy_bitslip151[4]),
+	.Q5(a7ddrphy_bitslip151[3]),
+	.Q6(a7ddrphy_bitslip151[2]),
+	.Q7(a7ddrphy_bitslip151[1]),
+	.Q8(a7ddrphy_bitslip151[0])
 );
 
 IDELAYE2 #(
@@ -15345,19 +15788,19 @@ IDELAYE2 #(
 	.SIGNAL_PATTERN("DATA")
 ) IDELAYE2_15 (
 	.C(sys_clk),
-	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(main_a7ddrphy_dq_i_nodelay15),
+	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(a7ddrphy_dq_i_nodelay15),
 	.INC(1'd1),
-	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
-	.DATAOUT(main_a7ddrphy_dq_i_delayed15)
+	.DATAOUT(a7ddrphy_dq_i_delayed15)
 );
 
 IOBUF IOBUF_15(
-	.I(main_a7ddrphy_dq_o_nodelay15),
-	.T(main_a7ddrphy_dq_t15),
+	.I(a7ddrphy_dq_o_nodelay15),
+	.T(a7ddrphy_dq_t15),
 	.IO(ddram_dq[15]),
-	.O(main_a7ddrphy_dq_i_nodelay15)
+	.O(a7ddrphy_dq_i_nodelay15)
 );
 
 //------------------------------------------------------------------------------
@@ -15368,14 +15811,14 @@ IOBUF IOBUF_15(
 reg [23:0] storage[0:15];
 reg [23:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
-		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-	storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+		storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+	storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15386,14 +15829,14 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_1[0:15];
 reg [23:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
-		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+		storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15404,14 +15847,14 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_2[0:15];
 reg [23:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
-		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+		storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15422,14 +15865,14 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_3[0:15];
 reg [23:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
-		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+		storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15440,14 +15883,14 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_4[0:15];
 reg [23:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
-		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+		storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15458,14 +15901,14 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_5[0:15];
 reg [23:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
-		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+		storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15476,14 +15919,14 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_6[0:15];
 reg [23:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
-		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+		storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -15494,62 +15937,78 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storag
 reg [23:0] storage_7[0:15];
 reg [23:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
-		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+	if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+		storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
 
-FD FD(
-	.C(main_clkin),
-	.D(main_reset),
-	.Q(builder_reset0)
+FDCE FDCE(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(reset),
+	.Q(litedramcore_reset0)
 );
 
-FD FD_1(
-	.C(main_clkin),
-	.D(builder_reset0),
-	.Q(builder_reset1)
+FDCE FDCE_1(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset0),
+	.Q(litedramcore_reset1)
 );
 
-FD FD_2(
-	.C(main_clkin),
-	.D(builder_reset1),
-	.Q(builder_reset2)
+FDCE FDCE_2(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset1),
+	.Q(litedramcore_reset2)
 );
 
-FD FD_3(
-	.C(main_clkin),
-	.D(builder_reset2),
-	.Q(builder_reset3)
+FDCE FDCE_3(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset2),
+	.Q(litedramcore_reset3)
 );
 
-FD FD_4(
-	.C(main_clkin),
-	.D(builder_reset3),
-	.Q(builder_reset4)
+FDCE FDCE_4(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset3),
+	.Q(litedramcore_reset4)
 );
 
-FD FD_5(
-	.C(main_clkin),
-	.D(builder_reset4),
-	.Q(builder_reset5)
+FDCE FDCE_5(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset4),
+	.Q(litedramcore_reset5)
 );
 
-FD FD_6(
-	.C(main_clkin),
-	.D(builder_reset5),
-	.Q(builder_reset6)
+FDCE FDCE_6(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset5),
+	.Q(litedramcore_reset6)
 );
 
-FD FD_7(
-	.C(main_clkin),
-	.D(builder_reset6),
-	.Q(builder_reset7)
+FDCE FDCE_7(
+	.C(clkin),
+	.CE(1'd1),
+	.CLR(1'd0),
+	.D(litedramcore_reset6),
+	.Q(litedramcore_reset7)
 );
 
 PLLE2_ADV #(
@@ -15567,16 +16026,16 @@ PLLE2_ADV #(
 	.REF_JITTER1(0.01),
 	.STARTUP_WAIT("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(builder_pll_fb),
-	.CLKIN1(main_clkin),
-	.PWRDWN(main_power_down),
-	.RST(builder_reset7),
-	.CLKFBOUT(builder_pll_fb),
-	.CLKOUT0(main_clkout0),
-	.CLKOUT1(main_clkout1),
-	.CLKOUT2(main_clkout2),
-	.CLKOUT3(main_clkout3),
-	.LOCKED(main_locked)
+	.CLKFBIN(litedramcore_pll_fb),
+	.CLKIN1(clkin),
+	.PWRDWN(power_down),
+	.RST(litedramcore_reset7),
+	.CLKFBOUT(litedramcore_pll_fb),
+	.CLKOUT0(clkout0),
+	.CLKOUT1(clkout1),
+	.CLKOUT2(clkout2),
+	.CLKOUT3(clkout3),
+	.LOCKED(locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15585,8 +16044,8 @@ PLLE2_ADV #(
 	.C(iodelay_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
-	.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl0),
+	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15594,8 +16053,8 @@ PLLE2_ADV #(
 ) FDPE_1 (
 	.C(iodelay_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
+	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl0),
 	.Q(iodelay_rst)
 );
 
@@ -15605,8 +16064,8 @@ PLLE2_ADV #(
 	.C(sys_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
-	.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl1),
+	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15614,8 +16073,8 @@ PLLE2_ADV #(
 ) FDPE_3 (
 	.C(sys_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
+	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl1),
 	.Q(sys_rst)
 );
 
@@ -15625,8 +16084,8 @@ PLLE2_ADV #(
 	.C(sys4x_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15634,9 +16093,9 @@ PLLE2_ADV #(
 ) FDPE_5 (
 	.C(sys4x_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
-	.Q(builder_xilinxasyncresetsynchronizerimpl2_expr)
+	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl2),
+	.Q(xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -15645,8 +16104,8 @@ PLLE2_ADV #(
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
 	.D(1'd0),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -15654,13 +16113,13 @@ PLLE2_ADV #(
 ) FDPE_7 (
 	.C(sys4x_dqs_clk),
 	.CE(1'd1),
-	.D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
-	.Q(builder_xilinxasyncresetsynchronizerimpl3_expr)
+	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE(xilinxasyncresetsynchronizerimpl3),
+	.Q(xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-01-14 08:32:15.
+//  Auto-Generated by LiteX on 2022-08-04 21:07:01.
 //------------------------------------------------------------------------------