From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Apr 2019 13:14:06 +0000 (+0100)
Subject: replace o_ready with ready_o
X-Git-Tag: ls180-24jan2020~1189
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa210dbcea099c55e5be938742804b1fac77cfbc;p=ieee754fpu.git

replace o_ready with ready_o
---

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 8f5094c1..c061807c 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -580,7 +580,7 @@ class FPBase:
         """
         res = v.decode2(m)
         ack = Signal()
-        with m.If((op.o_ready) & (op.i_valid_test)):
+        with m.If((op.ready_o) & (op.i_valid_test)):
             m.next = next_state
             # op is latched in from FPNumIn class on same ack/stb
             m.d.comb += ack.eq(0)
diff --git a/src/add/fpcommon/getop.py b/src/add/fpcommon/getop.py
index 96a03c3e..d06aa2e4 100644
--- a/src/add/fpcommon/getop.py
+++ b/src/add/fpcommon/getop.py
@@ -25,7 +25,7 @@ class FPGetOpMod(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_decode.eq((self.in_op.o_ready) & \
+        m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
                                        (self.in_op.i_valid_test))
         m.submodules.get_op_in = self.in_op
         #m.submodules.get_op_out = self.out_op
@@ -59,11 +59,11 @@ class FPGetOp(FPState):
         with m.If(self.out_decode):
             m.next = self.out_state
             m.d.sync += [
-                self.in_op.o_ready.eq(0),
+                self.in_op.ready_o.eq(0),
                 self.out_op.eq(self.mod.out_op)
             ]
         with m.Else():
-            m.d.sync += self.in_op.o_ready.eq(1)
+            m.d.sync += self.in_op.ready_o.eq(1)
 
 
 class FPNumBase2Ops:
@@ -146,14 +146,14 @@ class FPGet2Op(FPState):
         """ links stb/ack
         """
         m.d.comb += self.mod.i_valid.eq(in_stb)
-        m.d.comb += in_ack.eq(self.mod.o_ready)
+        m.d.comb += in_ack.eq(self.mod.ready_o)
 
     def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.get_ops = self.mod
         m.d.comb += self.mod.i.eq(i)
-        m.d.comb += self.out_ack.eq(self.mod.o_ready)
+        m.d.comb += self.out_ack.eq(self.mod.ready_o)
         m.d.comb += self.out_decode.eq(self.mod.trigger)
 
     def process(self, i):
@@ -163,10 +163,10 @@ class FPGet2Op(FPState):
         with m.If(self.out_decode):
             m.next = self.out_state
             m.d.sync += [
-                self.mod.o_ready.eq(0),
+                self.mod.ready_o.eq(0),
                 self.o.eq(self.mod.o),
             ]
         with m.Else():
-            m.d.sync += self.mod.o_ready.eq(1)
+            m.d.sync += self.mod.ready_o.eq(1)
 
 
diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index 1b434832..abdf42ff 100644
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -6,7 +6,7 @@
 
     Multi-output is simple (pretty much identical to UnbufferedPipeline),
     and the selection is just a mux.  The only proviso (difference) being:
-    the outputs not being selected have to have their o_ready signals
+    the outputs not being selected have to have their ready_o signals
     DEASSERTED.
 """
 
@@ -184,14 +184,14 @@ class CombMultiOutPipeline(MultiOutControlBase):
         p_i_valid = Signal(reset_less=True)
         pv = Signal(reset_less=True)
         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
-        m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
+        m.d.comb += pv.eq(self.p.i_valid & self.p.ready_o)
 
         # all outputs to next stages first initialised to zero (invalid)
         # the only output "active" is then selected by the muxid
         for i in range(len(self.n)):
             m.d.comb += self.n[i].o_valid.eq(0)
         data_valid = self.n[mid].o_valid
-        m.d.comb += self.p.o_ready.eq(~data_valid | self.n[mid].i_ready)
+        m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].i_ready)
         m.d.comb += data_valid.eq(p_i_valid | \
                                     (~self.n[mid].i_ready & data_valid))
         with m.If(pv):
@@ -258,9 +258,9 @@ class CombMultiInPipeline(MultiInControlBase):
             m.d.comb += data_valid[i].eq(0)
             m.d.comb += n_i_readyn[i].eq(1)
             m.d.comb += p_i_valid[i].eq(0)
-            m.d.comb += self.p[i].o_ready.eq(0)
+            m.d.comb += self.p[i].ready_o.eq(0)
         m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
-        m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
+        m.d.comb += self.p[mid].ready_o.eq(~data_valid[mid] | self.n.i_ready)
         m.d.comb += n_i_readyn[mid].eq(nirn & data_valid[mid])
         anyvalid = Signal(i, reset_less=True)
         av = []
@@ -273,7 +273,7 @@ class CombMultiInPipeline(MultiInControlBase):
 
         for i in range(p_len):
             vr = Signal(reset_less=True)
-            m.d.comb += vr.eq(self.p[i].i_valid & self.p[i].o_ready)
+            m.d.comb += vr.eq(self.p[i].i_valid & self.p[i].ready_o)
             with m.If(vr):
                 m.d.comb += eq(r_data[i], self.p[i].i_data)
 
diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
index 94ebc2fd..a7e215cb 100644
--- a/src/add/nmigen_div_experiment.py
+++ b/src/add/nmigen_div_experiment.py
@@ -71,14 +71,14 @@ class FPDIV(FPBase):
 
             with m.State("get_a"):
                 res = self.get_op(m, self.in_a, a, "get_b")
-                m.d.sync += eq([a, self.in_a.o_ready], res)
+                m.d.sync += eq([a, self.in_a.ready_o], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
                 res = self.get_op(m, self.in_b, b, "special_cases")
-                m.d.sync += eq([b, self.in_b.o_ready], res)
+                m.d.sync += eq([b, self.in_b.ready_o], res)
 
             # ******
             # special cases: NaNs, infs, zeros, denormalised
diff --git a/src/add/queue.py b/src/add/queue.py
index 43dfa2ce..5e290a7c 100644
--- a/src/add/queue.py
+++ b/src/add/queue.py
@@ -63,7 +63,7 @@ class Queue(FIFOInterface, Elaboratable):
         m.submodules.ram_write = ram_write = ram.write_port()
 
         # convenience names
-        p_o_ready = self.writable
+        p_ready_o = self.writable
         p_i_valid = self.we
         enq_data = self.din
 
@@ -93,12 +93,12 @@ class Queue(FIFOInterface, Elaboratable):
                      deq_max.eq(deq_ptr == self.depth - 1),
                      empty.eq(ptr_match & ~maybe_full),
                      full.eq(ptr_match & maybe_full),
-                     do_enq.eq(p_o_ready & p_i_valid), # write conditions ok
+                     do_enq.eq(p_ready_o & p_i_valid), # write conditions ok
                      do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
 
                      # set readable and writable (NOTE: see pipe mode below)
                      n_o_valid.eq(~empty), # cannot read if empty!
-                     p_o_ready.eq(~full),  # cannot write if full!
+                     p_ready_o.eq(~full),  # cannot write if full!
 
                      # set up memory and connect to input and output
                      ram_write.addr.eq(enq_ptr),
@@ -139,7 +139,7 @@ class Queue(FIFOInterface, Elaboratable):
         #            *must* declare the input ready (writeable).
         if self.pipe:
             with m.If(n_i_ready):
-                m.d.comb += p_o_ready.eq(1)
+                m.d.comb += p_ready_o.eq(1)
 
         # set the count (available free space), optimise on power-of-two
         if self.depth == 1 << ptr_width:  # is depth a power of 2
diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index b2e0f6ca..24565a4f 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -132,7 +132,7 @@
 
     input acceptance conditions are when:
         * incoming previous-stage strobe (p.i_valid) is HIGH
-        * outgoing previous-stage ready   (p.o_ready) is LOW
+        * outgoing previous-stage ready   (p.ready_o) is LOW
 
     output transmission conditions are when:
         * outgoing next-stage strobe (n.o_valid) is HIGH
@@ -268,26 +268,26 @@ class PrevControl(Elaboratable):
         * i_valid: previous stage indicating all incoming data is valid.
                    may be a multi-bit signal, where all bits are required
                    to be asserted to indicate "valid".
-        * o_ready: output to next stage indicating readiness to accept data
+        * ready_o: output to next stage indicating readiness to accept data
         * i_data : an input - added by the user of this class
     """
 
     def __init__(self, i_width=1, stage_ctl=False):
         self.stage_ctl = stage_ctl
         self.i_valid = Signal(i_width, name="p_i_valid") # prev   >>in  self
-        self._o_ready = Signal(name="p_o_ready") # prev   <<out self
+        self._ready_o = Signal(name="p_ready_o") # prev   <<out self
         self.i_data = None # XXX MUST BE ADDED BY USER
         if stage_ctl:
-            self.s_o_ready = Signal(name="p_s_o_rdy") # prev   <<out self
+            self.s_ready_o = Signal(name="p_s_o_rdy") # prev   <<out self
         self.trigger = Signal(reset_less=True)
 
     @property
-    def o_ready(self):
+    def ready_o(self):
         """ public-facing API: indicates (externally) that stage is ready
         """
         if self.stage_ctl:
-            return self.s_o_ready # set dynamically by stage
-        return self._o_ready      # return this when not under dynamic control
+            return self.s_ready_o # set dynamically by stage
+        return self._ready_o      # return this when not under dynamic control
 
     def _connect_in(self, prev, direct=False, fn=None):
         """ internal helper function to connect stage to an input source.
@@ -296,7 +296,7 @@ class PrevControl(Elaboratable):
         i_valid = prev.i_valid if direct else prev.i_valid_test
         i_data = fn(prev.i_data) if fn is not None else prev.i_data
         return [self.i_valid.eq(i_valid),
-                prev.o_ready.eq(self.o_ready),
+                prev.ready_o.eq(self.ready_o),
                 eq(self.i_data, i_data),
                ]
 
@@ -314,23 +314,23 @@ class PrevControl(Elaboratable):
         # when stage indicates not ready, incoming data
         # must "appear" to be not ready too
         if self.stage_ctl:
-            i_valid = i_valid & self.s_o_ready
+            i_valid = i_valid & self.s_ready_o
 
         return i_valid
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.trigger.eq(self.i_valid_test & self.o_ready)
+        m.d.comb += self.trigger.eq(self.i_valid_test & self.ready_o)
         return m
 
     def eq(self, i):
         return [self.i_data.eq(i.i_data),
-                self.o_ready.eq(i.o_ready),
+                self.ready_o.eq(i.ready_o),
                 self.i_valid.eq(i.i_valid)]
 
     def __iter__(self):
         yield self.i_valid
-        yield self.o_ready
+        yield self.ready_o
         if hasattr(self.i_data, "ports"):
             yield from self.i_data.ports()
         elif isinstance(self.i_data, Sequence):
@@ -369,7 +369,7 @@ class NextControl(Elaboratable):
             use this when connecting stage-to-stage
         """
         return [nxt.i_valid.eq(self.o_valid),
-                self.i_ready.eq(nxt.o_ready),
+                self.i_ready.eq(nxt.ready_o),
                 eq(nxt.i_data, self.o_data),
                ]
 
@@ -785,7 +785,7 @@ class ControlBase(Elaboratable):
             return m
 
         # intercept the previous (outgoing) "ready", combine with stage ready
-        m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.d_ready)
+        m.d.comb += self.p.s_ready_o.eq(self.p._ready_o & self.stage.d_ready)
 
         # intercept the next (incoming) "ready" and combine it with data valid
         sdv = self.stage.d_valid(self.n.i_ready)
@@ -802,7 +802,7 @@ class BufferedHandshake(ControlBase):
         Argument: stage.  see Stage API above
 
         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
                             process --->----^
@@ -843,19 +843,19 @@ class BufferedHandshake(ControlBase):
         self.m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
                      o_n_validn.eq(~self.n.o_valid),
                      n_i_ready.eq(self.n.i_ready_test),
-                     nir_por.eq(n_i_ready & self.p._o_ready),
-                     nir_por_n.eq(n_i_ready & ~self.p._o_ready),
+                     nir_por.eq(n_i_ready & self.p._ready_o),
+                     nir_por_n.eq(n_i_ready & ~self.p._ready_o),
                      nir_novn.eq(n_i_ready | o_n_validn),
                      nirn_novn.eq(~n_i_ready & o_n_validn),
                      npnn.eq(nir_por | nirn_novn),
-                     por_pivn.eq(self.p._o_ready & ~p_i_valid)
+                     por_pivn.eq(self.p._ready_o & ~p_i_valid)
         ]
 
         # store result of processing in combinatorial temporary
         self.m.d.comb += eq(result, self.stage.process(self.p.i_data))
 
         # if not in stall condition, update the temporary register
-        with self.m.If(self.p.o_ready): # not stalled
+        with self.m.If(self.p.ready_o): # not stalled
             self.m.d.sync += eq(r_data, result) # update buffer
 
         # data pass-through conditions
@@ -872,7 +872,7 @@ class BufferedHandshake(ControlBase):
                               eq(self.n.o_data, o_data), # flush buffer
                              ]
         # output ready conditions
-        self.m.d.sync += self.p._o_ready.eq(nir_novn | por_pivn)
+        self.m.d.sync += self.p._ready_o.eq(nir_novn | por_pivn)
 
         return self.m
 
@@ -884,7 +884,7 @@ class SimpleHandshake(ControlBase):
         Argument: stage.  see Stage API above
 
         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
                               +--process->--^
@@ -927,18 +927,18 @@ class SimpleHandshake(ControlBase):
 
         # establish some combinatorial temporaries
         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
-        p_i_valid_p_o_ready = Signal(reset_less=True)
+        p_i_valid_p_ready_o = Signal(reset_less=True)
         p_i_valid = Signal(reset_less=True)
         m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
                      n_i_ready.eq(self.n.i_ready_test),
-                     p_i_valid_p_o_ready.eq(p_i_valid & self.p.o_ready),
+                     p_i_valid_p_ready_o.eq(p_i_valid & self.p.ready_o),
         ]
 
         # store result of processing in combinatorial temporary
         m.d.comb += eq(result, self.stage.process(self.p.i_data))
 
         # previous valid and ready
-        with m.If(p_i_valid_p_o_ready):
+        with m.If(p_i_valid_p_ready_o):
             o_data = self._postprocess(result)
             m.d.sync += [r_busy.eq(1),      # output valid
                          eq(self.n.o_data, o_data), # update output
@@ -953,7 +953,7 @@ class SimpleHandshake(ControlBase):
 
         m.d.comb += self.n.o_valid.eq(r_busy)
         # if next is ready, so is previous
-        m.d.comb += self.p._o_ready.eq(n_i_ready)
+        m.d.comb += self.p._ready_o.eq(n_i_ready)
 
         return self.m
 
@@ -973,7 +973,7 @@ class UnbufferedPipeline(ControlBase):
         Argument: stage.  see Stage API, above
 
         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
                             r_data        result
@@ -1038,11 +1038,11 @@ class UnbufferedPipeline(ControlBase):
         pv = Signal(reset_less=True)
         buf_full = Signal(reset_less=True)
         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
-        m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
+        m.d.comb += pv.eq(self.p.i_valid & self.p.ready_o)
         m.d.comb += buf_full.eq(~self.n.i_ready_test & data_valid)
 
         m.d.comb += self.n.o_valid.eq(data_valid)
-        m.d.comb += self.p._o_ready.eq(~data_valid | self.n.i_ready_test)
+        m.d.comb += self.p._ready_o.eq(~data_valid | self.n.i_ready_test)
         m.d.sync += data_valid.eq(p_i_valid | buf_full)
 
         with m.If(pv):
@@ -1067,7 +1067,7 @@ class UnbufferedPipeline2(ControlBase):
         Argument: stage.  see Stage API, above
 
         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |    |
                               +- process-> buf <-+
@@ -1124,7 +1124,7 @@ class UnbufferedPipeline2(ControlBase):
         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
 
         m.d.comb += self.n.o_valid.eq(buf_full | p_i_valid)
-        m.d.comb += self.p._o_ready.eq(~buf_full)
+        m.d.comb += self.p._ready_o.eq(~buf_full)
         m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
 
         o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data))
@@ -1188,10 +1188,10 @@ class PassThroughHandshake(ControlBase):
         p_i_valid = Signal(reset_less=True)
         pvr = Signal(reset_less=True)
         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
-        m.d.comb += pvr.eq(p_i_valid & self.p.o_ready)
+        m.d.comb += pvr.eq(p_i_valid & self.p.ready_o)
 
-        m.d.comb += self.p.o_ready.eq(~self.n.o_valid |  self.n.i_ready_test)
-        m.d.sync += self.n.o_valid.eq(p_i_valid       | ~self.p.o_ready)
+        m.d.comb += self.p.ready_o.eq(~self.n.o_valid |  self.n.i_ready_test)
+        m.d.sync += self.n.o_valid.eq(p_i_valid       | ~self.p.ready_o)
 
         odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
         m.d.sync += eq(r_data, odata)
@@ -1270,7 +1270,7 @@ class FIFOControl(ControlBase):
         # NOTE: cannot do the PrevControl-looking trick because
         # of need to process the data.  shaaaame....
         m.d.comb += [fifo.we.eq(self.p.i_valid_test),
-                     self.p.o_ready.eq(fifo.writable),
+                     self.p.ready_o.eq(fifo.writable),
                      eq(fifo.din, cat(result)),
                    ]
 
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 56897745..2dae49ea 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -48,7 +48,7 @@ def check_o_n_valid2(dut, val):
 def tbench(dut):
     #yield dut.i_p_rst.eq(1)
     yield dut.n.i_ready.eq(0)
-    #yield dut.p.o_ready.eq(0)
+    #yield dut.p.ready_o.eq(0)
     yield
     yield
     #yield dut.i_p_rst.eq(0)
@@ -84,7 +84,7 @@ def tbench(dut):
 def tbench2(dut):
     #yield dut.p.i_rst.eq(1)
     yield dut.n.i_ready.eq(0)
-    #yield dut.p.o_ready.eq(0)
+    #yield dut.p.ready_o.eq(0)
     yield
     yield
     #yield dut.p.i_rst.eq(0)
@@ -141,7 +141,7 @@ class Test3:
                     send = True
                 else:
                     send = randint(0, send_range) != 0
-                o_p_ready = yield self.dut.p.o_ready
+                o_p_ready = yield self.dut.p.ready_o
                 if not o_p_ready:
                     yield
                     continue
@@ -215,7 +215,7 @@ class Test5:
                 else:
                     send = randint(0, send_range) != 0
                 #send = True
-                o_p_ready = yield self.dut.p.o_ready
+                o_p_ready = yield self.dut.p.ready_o
                 if not o_p_ready:
                     yield
                     continue
@@ -269,7 +269,7 @@ def tbench4(dut):
         stall = randint(0, 3) != 0
         send = randint(0, 5) != 0
         yield dut.n.i_ready.eq(stall)
-        o_p_ready = yield dut.p.o_ready
+        o_p_ready = yield dut.p.ready_o
         if o_p_ready:
             if send and i != len(data):
                 yield dut.p.i_valid.eq(1)
@@ -1022,7 +1022,7 @@ if __name__ == '__main__':
         dut = ExampleBufPipe2()
         run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
         ports = [dut.p.i_valid, dut.n.i_ready,
-                 dut.n.o_valid, dut.p.o_ready] + \
+                 dut.n.o_valid, dut.p.ready_o] + \
                  [dut.p.i_data] + [dut.n.o_data]
         vl = rtlil.convert(dut, ports=ports)
         with open("test_bufpipe2.il", "w") as f:
@@ -1054,7 +1054,7 @@ if __name__ == '__main__':
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
 
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              list(dut.p.i_data) + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_ltcomb_pipe.il", "w") as f:
@@ -1065,7 +1065,7 @@ if __name__ == '__main__':
     data=data_dict()
     test = Test5(dut, resultfn_7, data=data)
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready,
+             dut.n.o_valid, dut.p.ready_o,
              dut.p.i_data.src1, dut.p.i_data.src2,
              dut.n.o_data.src1, dut.n.o_data.src2]
     vl = rtlil.convert(dut, ports=ports)
@@ -1082,7 +1082,7 @@ if __name__ == '__main__':
     print ("test 9")
     dut = ExampleBufPipeChain2()
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpipechain2.il", "w") as f:
@@ -1114,7 +1114,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpipe12.il", "w") as f:
@@ -1126,7 +1126,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_unbufpipe13.il", "w") as f:
@@ -1138,7 +1138,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufunbuf15.il", "w") as f:
@@ -1150,7 +1150,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufunbuf16.il", "w") as f:
@@ -1162,7 +1162,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_unbufpipe17.il", "w") as f:
@@ -1174,7 +1174,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_identical, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_passthru18.il", "w") as f:
@@ -1186,7 +1186,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpass19.il", "w") as f:
@@ -1198,7 +1198,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_identical, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_fifo20.il", "w") as f:
@@ -1210,7 +1210,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_fifopass21.il", "w") as f:
@@ -1222,7 +1222,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_8, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1235,7 +1235,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_8, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1247,7 +1247,7 @@ if __name__ == '__main__':
     data=data_2op()
     test = Test5(dut, resultfn_8, data=data)
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1261,7 +1261,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_add2pipe25.il", "w") as f:
@@ -1273,7 +1273,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpass997.il", "w") as f:
@@ -1285,7 +1285,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpipe14.il", "w") as f:
@@ -1297,7 +1297,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
-             dut.n.o_valid, dut.p.o_ready] + \
+             dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufunbuf999.il", "w") as f:
diff --git a/src/add/test_fpadd_pipe.py b/src/add/test_fpadd_pipe.py
index b1ec7087..f718bf7c 100644
--- a/src/add/test_fpadd_pipe.py
+++ b/src/add/test_fpadd_pipe.py
@@ -43,10 +43,10 @@ class InputTest:
             yield rs.i_data.b.eq(op2)
             yield rs.i_data.mid.eq(mid)
             yield
-            o_p_ready = yield rs.o_ready
+            o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
-                o_p_ready = yield rs.o_ready
+                o_p_ready = yield rs.ready_o
 
             fop1 = Float32(op1)
             fop2 = Float32(op2)
diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index d24afd7b..f88d8f97 100644
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -49,7 +49,7 @@ class FPDIV(FPBase):
 
             with m.State("get_a"):
                 res = self.get_op(m, self.in_a, a, "add_1")
-                m.d.sync += eq([a, self.in_a.o_ready], res)
+                m.d.sync += eq([a, self.in_a.ready_o], res)
 
             with m.State("add_1"):
                 m.next = "pack"
@@ -98,7 +98,7 @@ class FPDIVPipe(ControlBase):
         m.submodules.fpdiv = self.fpdiv
 
         # see if connecting to stb/ack works
-        m.d.comb += self.p.o_ready.eq(self.fpdiv.in_a.o_ready)
+        m.d.comb += self.p.ready_o.eq(self.fpdiv.in_a.ready_o)
         m.d.comb += self.fpdiv.in_a.i_valid.eq(self.p.i_valid_test)
 
         m.d.comb += self.n.o_valid.eq(self.fpdiv.out_z.o_valid)
diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 3bb7c401..a62b7e93 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -71,10 +71,10 @@ class InputTest:
             yield rs.i_data.idx.eq(i)
             yield rs.i_data.mid.eq(mid)
             yield
-            o_p_ready = yield rs.o_ready
+            o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
-                o_p_ready = yield rs.o_ready
+                o_p_ready = yield rs.ready_o
 
             print ("send", mid, i, hex(op2))
 
@@ -161,10 +161,10 @@ class OutputTest:
             yield rs.i_data.data.eq(op2)
             yield rs.i_data.mid.eq(mid)
             yield
-            o_p_ready = yield rs.o_ready
+            o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
-                o_p_ready = yield rs.o_ready
+                o_p_ready = yield rs.ready_o
 
             print ("send", mid, i, hex(op2))
 
diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 9c9e0cc7..c3db79f7 100644
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -69,10 +69,10 @@ class OutputTest:
             yield rs.i_data.data.eq(op2)
             yield rs.i_data.mid.eq(mid)
             yield
-            o_p_ready = yield rs.o_ready
+            o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
-                o_p_ready = yield rs.o_ready
+                o_p_ready = yield rs.ready_o
 
             print ("send", mid, i, hex(op2))
 
@@ -139,7 +139,7 @@ class TestSyncToPriorityPipe(Elaboratable):
         return m
 
     def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
+        res = [self.p.i_valid, self.p.ready_o] + \
                 self.p.i_data.ports()
         for i in range(len(self.n)):
             res += [self.n[i].i_ready, self.n[i].o_valid] + \
diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 819f41f8..351fdf70 100644
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -136,10 +136,10 @@ class InputTest:
             yield rs.i_data.idx.eq(i)
             yield rs.i_data.mid.eq(mid)
             yield
-            o_p_ready = yield rs.o_ready
+            o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
-                o_p_ready = yield rs.o_ready
+                o_p_ready = yield rs.ready_o
 
             print ("send", mid, i, hex(op2))
 
diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py
index eff75f15..c5a1c6ee 100644
--- a/src/add/unit_test_single.py
+++ b/src/add/unit_test_single.py
@@ -46,7 +46,7 @@ def get_rs_case(dut, a, b, mid):
     yield
     yield
     yield
-    a_ack = (yield in_a.o_ready)
+    a_ack = (yield in_a.ready_o)
     assert a_ack == 0
 
     yield in_a.i_valid.eq(0)
@@ -55,7 +55,7 @@ def get_rs_case(dut, a, b, mid):
     yield in_b.i_valid.eq(1)
     yield
     yield
-    b_ack = (yield in_b.o_ready)
+    b_ack = (yield in_b.ready_o)
     assert b_ack == 0
 
     yield in_b.i_valid.eq(0)
@@ -92,7 +92,7 @@ def get_case(dut, a, b, mid):
     yield
     yield
     yield
-    a_ack = (yield dut.in_a.o_ready)
+    a_ack = (yield dut.in_a.ready_o)
     assert a_ack == 0
 
     yield dut.in_a.i_valid.eq(0)
@@ -101,7 +101,7 @@ def get_case(dut, a, b, mid):
     yield dut.in_b.i_valid.eq(1)
     yield
     yield
-    b_ack = (yield dut.in_b.o_ready)
+    b_ack = (yield dut.in_b.ready_o)
     assert b_ack == 0
 
     yield dut.in_b.i_valid.eq(0)