From: lkcl <lkcl@web>
Date: Fri, 11 Mar 2022 23:32:18 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3093
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa36ed508cf5489bbb59ed6b1887a5c669ca9f1e;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index d5d75ef25..ab8465013 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -207,8 +207,9 @@ a 4 operand variant which becomes more along the lines of an FPGA:
 | NN | RT | RA  | RB  | RC  | mode  01 |1 |
 
     for i in range(64):
-        idx = RT[i] << 2 | RA[i] << 1 | RB[i]
-        RT[i] = (RC & (1<<idx)) != 0
+        j = (i//8)*8 # 0,8,16,24,..,56
+        lookup = RC[j:j+8]
+        RT[i] = lut3(lookup, RT[i], RA[i], RB[i])
 
 mode (3 bit) may be used to do inversion of ordering, similar to carryless mul,
 3 modes.