From: lkcl Date: Wed, 25 Aug 2021 20:47:36 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~304 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa38956935cf3562e4eebe23c21f1357afc25693;p=libreriscv.git --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index d46bdcab9..49d5609e6 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -40,7 +40,8 @@ other Vector-aware Branch Conditional instructions are a high priority for 3D GPU workloads. The `BI` field of Branch Conditional operations is five bits, in scalar -v3.0B this would select one bit of the 32 bit CR. In SVP64 there are +v3.0B this would select one bit of the 32 bit CR, +comprising eight CR Fields of 4 bits each. In SVP64 there are 16 32 bit CRs, containing 128 4-bit CR Fields. Therefore, the 2 LSBs of `BI` select the bit from the CR Field (EQ LT GT SO), and the top 3 bits are extended to either scalar or vector and to select CR Fields 0..127