From: Jean THOMAS Date: Thu, 6 Aug 2020 15:28:03 +0000 (+0200) Subject: gram.phy.ecp5ddrphy: Revert to LiteDRAM's dqs_re X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa3b89255d7d0bcd4eca59e0a7e7ee0a1d8e0749;p=gram.git gram.phy.ecp5ddrphy: Revert to LiteDRAM's dqs_re --- diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 2c7b631..7aac20b 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -500,7 +500,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): rddata_en_last = Signal.like(rddata_en) m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last)) m.d.sync += rddata_en_last.eq(rddata_en) - m.d.comb += dqs_re.eq(rddata_en[cl_sys_latency + 0] | rddata_en[cl_sys_latency + 1] | rddata_en[cl_sys_latency + 2]) + m.d.comb += dqs_re.eq(rddata_en[cl_sys_latency + 1] | rddata_en[cl_sys_latency + 2]) rddata_valid = Signal() m.d.sync += rddata_valid.eq(datavalid_prev & ~datavalid)