From: lkcl <lkcl@web>
Date: Sat, 9 Apr 2022 14:37:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2826
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa4316c2bf9d3f34e06fdbd23afd041010b12a4f;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index f26d821c4..34de36b25 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -62,7 +62,7 @@ A number of features need to be compacted into a very small space of only 24 bit
 * Independent per-register Scalar/Vector tagging and range extension on every register
 * Element width overrides on both source and destination
 * Predication on both source and destination
-* Two different *types* of predication: INT and CR
+* Two different sources of predication: INT and CR Fields
 * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
   predicate-result mode.