From: lkcl Date: Thu, 29 Sep 2022 22:44:22 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~262 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa46bc696bde29ee6757e4e23c1c6e65c774d918;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 30d9085da..5b3394ebb 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -32,17 +32,16 @@ The goal of RED Semiconductor Ltd, an OpenPOWER Stakeholder, is to bring to market mass-volume general-purpose compute processors that are competitive in the 3D GPU Audio Visual DSP EDGE IoT desktop chromebook netbook smartphone laptop markets, performance-leveraged -by Simple-V. Simple-V thus has to -be accompanied by corresponding **Scalar** instructions that bring the -**Scalar** Power ISA up-to-date. These include IEEE754 +by Simple-V. To achieve this goal both Simple-V and accompanying +Scalar** Power ISA instructions are needed. These include IEEE754 [Transcendentals](https://libre-soc.org/openpower/transcendentals/) [AV](https://libre-soc.org/openpower/sv/av_opcodes/) cryptographic [Biginteger](https://libre-soc.org/openpower/sv/biginteger/) and [bitmanipulation](https://libre-soc.org/openpower/sv/bitmanip) -operations that ARM -Intel AMD and many other ISAs have been adding over the past 12 years -and Power ISA has not. Three additional FP-related sets are needed +operations present in ARM +Intel AMD and many other ISAs. +Three additional FP-related sets are needed (missing from SFFS) - [int_fp_mv](https://libre-soc.org/openpower/sv/int_fp_mv/) [fclass](https://libre-soc.org/openpower/sv/fclass/) and