From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 07:26:23 +0000 (-0700)
Subject: opt_clean: add init test
X-Git-Tag: working-ls180~556^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa4a69f89be9fcdcf20ca1c28d67444b994ec479;p=yosys.git

opt_clean: add init test
---

diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys
new file mode 100644
index 000000000..bfc383955
--- /dev/null
+++ b/tests/opt/opt_clean_init.ys
@@ -0,0 +1,13 @@
+logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1
+logger -expect-no-warnings
+read_verilog <<EOT
+module top;
+(* init=1'b0 *) wire w = 1'b0;
+(* init=1'bx *) wire x = 1'b0;
+(* init=1'b1 *) wire y = 1'b0;
+(* init=1'b0 *) wire z = 1'bx;
+endmodule
+EOT
+clean
+select -assert-count 1 a:init
+select -assert-count 1 w:y a:init %i