From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 15:06:12 +0000 (-0700)
Subject: Merge pull request #1927 from YosysHQ/eddie/design_remove_assert
X-Git-Tag: working-ls180~632
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa552cefa3bd0e98346508a8c45a7805353f8305;p=yosys.git

Merge pull request #1927 from YosysHQ/eddie/design_remove_assert

kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
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aa552cefa3bd0e98346508a8c45a7805353f8305