From: lkcl <lkcl@web>
Date: Mon, 16 May 2022 11:00:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2202
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa566a2254aeae85f47f3c035e6452ac89a1ee23;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index e4fabde94..33182ed5f 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -160,7 +160,9 @@ the [[sv/av_opcodes]])
 
 # binary and ternary bitops
 
-Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
+Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8-8-bit immediate (for the ternary instructions), or in another register (4-bit
+for the binary instructions).  The binary lookup instructions have CR Field
+lookup variants due to CR Fields being 4 bit.
 
 Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.