From: Cesar Strauss <cestrauss@gmail.com>
Date: Fri, 1 Jan 2021 17:46:35 +0000 (-0300)
Subject: Add CR to the output data port
X-Git-Tag: 24jan2021_ls180~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa5a53640a1e889b50a16b4ad5d59acede704417;p=soc.git

Add CR to the output data port
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 83354d44..a780dd86 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -208,6 +208,7 @@ class ALU(Elaboratable):
         self.p.data_i.a = self.a
         self.p.data_i.b = self.b
         self.n.data_o.o = self.o
+        self.n.data_o.cr = self.cr
 
     def elaborate(self, platform):
         m = Module()