From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 19 Jan 2022 17:18:35 +0000 (+0000)
Subject: ISI (0x400) trap is the only one that puts memory-based exception
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa6f072ab1d32e5439c98f012671aab577e7e5eb;p=soc.git

ISI (0x400) trap is the only one that puts memory-based exception
info into SRR1, not *all* memory-based exceptions
---

diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index d4e9f5c2..cda675ac 100644
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -249,42 +249,13 @@ class CoreDebug(Elaboratable):
                     with m.If(dmi.din <= 31):
                         sync += gspr_index.eq(dmi.din)
                         sync += gspr_en.eq(1)
-                    with m.If(dmi.din == 32): # LR
-                        sync += fast_index.eq(FastRegsEnum.LR)
-                        sync += fast_en.eq(1)
-                    with m.If(dmi.din == 33): # CTR
-                        sync += fast_index.eq(FastRegsEnum.CTR)
-                        sync += fast_en.eq(1)
-                    with m.If(dmi.din == 34): # SRR0
-                        sync += fast_index.eq(FastRegsEnum.SRR0)
-                        sync += fast_en.eq(1)
-                    with m.If(dmi.din == 35): # SRR1
-                        sync += fast_index.eq(FastRegsEnum.SRR1)
-                        sync += fast_en.eq(1)
-                    with m.If(dmi.din == 44): # XER
-                        sync += fast_index.eq(FastRegsEnum.XER)
-                        sync += fast_en.eq(1)
-                    with m.If(dmi.din == 45): # TAR
-                        sync += fast_index.eq(FastRegsEnum.XER)
-                        sync += fast_en.eq(1)
-
-                    # numbering from microwatt:
-                    """
-                If(regnum == 32, Display("     LR: %016x", dbg_dout),), # LR
-                If(regnum == 33, Display("    CTR: %016x", dbg_dout),), # CTR
-                If(regnum == 34, Display("   SRR0: %016x", dbg_dout),), # SRR0
-                If(regnum == 35, Display("   SRR1: %016x", dbg_dout),), # SRR1
-                If(regnum == 36, Display("  HSRR0: %016x", dbg_dout),), # HSRR0
-                If(regnum == 37, Display("  HSRR1: %016x", dbg_dout),), # HSRR1
-                If(regnum == 38, Display("  SPRG0: %016x", dbg_dout),), # SPRG0
-                If(regnum == 39, Display("  SPRG1: %016x", dbg_dout),), # SPRG1
-                If(regnum == 40, Display("  SPRG2: %016x", dbg_dout),), # SPRG2
-                If(regnum == 41, Display("  SPRG3: %016x", dbg_dout),), # SPRG3
-                If(regnum == 42, Display(" HSPRG0: %016x", dbg_dout),), # HSPRG0
-                If(regnum == 43, Display(" HSPRG1: %016x", dbg_dout),), # HSPRG1
-                If(regnum == 44, Display("    XER: %016x", dbg_dout),), # XER
-                If(regnum == 45, Display("    TAR: %016x", dbg_dout),), # TAR
-                """
+                    # cover the FastRegs LR, CTR, SRR0, SRR1 etc.
+                    # numbering is from microwatt
+                    for x, i in FastRegsEnum.__dict__.items():
+                        if not isinstance(i, int) or x == 'N_REGS':
+                            continue
+                        with m.If(dmi.din == 32+i):
+                            sync += fast_index.eq(i)
 
                 # Log address
                 with m.Elif(dmi.addr_i == DBGCore.LOG_ADDR):
diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index d3da831f..2183f1e9 100644
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -61,9 +61,12 @@ class SPRMainStage(PipeModBase):
                         comb += state1_o.data.eq(a_i)
                         comb += state1_o.ok.eq(1)
 
-                    # state SPRs second
+                    # state SPRs second: anything in FAST regs
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
-                                SPR.SRR1, SPR.XER, SPR.DEC, SPR.TB):
+                                SPR.SRR1, SPR.XER, SPR.HSRR0, SPR.HSRR1,
+                                SPR.SPRG0_priv, SPR.SPRG1_priv,
+                                SPR.SPRG2_priv, SPR.SPRG3,
+                                SPR.HSPRG0, SPR.HSPRG1, SPR.SVSRR0):
                         comb += fast1_o.data.eq(a_i)
                         comb += fast1_o.ok.eq(1)
                         # XER is constructed
@@ -94,8 +97,11 @@ class SPRMainStage(PipeModBase):
                         comb += o.data.eq(fast1_i)
 
                     # fast SPRs second
-                    with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
-                                SPR.XER):
+                    with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
+                                SPR.SRR1, SPR.XER, SPR.HSRR0, SPR.HSRR1,
+                                SPR.SPRG0_priv, SPR.SPRG1_priv,
+                                SPR.SPRG2_priv, SPR.SPRG3,
+                                SPR.HSPRG0, SPR.HSPRG1, SPR.SVSRR0):
                         comb += o.data.eq(fast1_i)
                         with m.If(spr == SPR.XER):
                             # bits 0:31 and 35:43 are treated as reserved
diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 6ad22544..0a624c01 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -215,7 +215,9 @@ class TrapMainStage(PipeModBase):
                         comb += srr1_o.data[PI.FP].eq(1)
                     with m.If(traptype & TT.ADDR):
                         comb += srr1_o.data[PI.ADR].eq(1)
-                    with m.If(traptype & TT.MEMEXC):
+                    with m.If(traptype & TT.MEMEXC & (trapaddr == 0x400)):
+                        # Instruction Storage Interrupt (ISI - 0x400)
+                        #           v3.0C Book III Chap 7.5.5 p1085
                         # decode exception bits, store in SRR1
                         exc = LDSTException("trapexc")
                         comb += exc.eq(op.ldst_exc)