From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 17 Aug 2020 14:18:30 +0000 (+0100)
Subject: arch-arm: Remove deadcode from AArch64 address translation
X-Git-Tag: v20.1.0.0~232
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa71e5c88678cdf6297a236fd6adad98a674817a;p=gem5.git

arch-arm: Remove deadcode from AArch64 address translation

There's no need to check for CPSR.WIDTH: if the 64 bit version
of the AT instruction/register is used, it means we are already
in AArch64 execution mode

Change-Id: I1263dcfd04e791eb390199546c177a926c71c6d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33355
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b42fdf190..1244d3951 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2364,22 +2364,13 @@ ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
         // Set fault bit and FSR
         FSR fsr = armFault->getFsr(tc);
 
-        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-        if (cpsr.width) { // AArch32
-            newVal = ((fsr >> 9) & 1) << 11;
-            // rearrange fault status
-            newVal |= ((fsr >>  0) & 0x3f) << 1;
-            newVal |= 0x1; // F bit
-            newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
-            newVal |= armFault->isStage2() ? 0x200 : 0;
-        } else { // AArch64
-            newVal = 1; // F bit
-            newVal |= fsr << 1; // FST
-            // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
-            newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
-            newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
-            newVal |= 1 << 11; // RES1
-        }
+        newVal = 1; // F bit
+        newVal |= fsr << 1; // FST
+        // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
+        newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
+        newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
+        newVal |= 1 << 11; // RES1
+
         DPRINTF(MiscRegs,
                 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
                 val, fsr, newVal);