From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 22 Oct 2016 09:05:49 +0000 (+0200)
Subject: Added avail params to ilang format, check module params in 'hierarchy -check'
X-Git-Tag: yosys-0.7~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa7226233023dcd53a28de837de74fb60fa9d691;p=yosys.git

Added avail params to ilang format, check module params in 'hierarchy -check'
---

diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 14e15017d..16d1a97f5 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -278,6 +278,13 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
 		}
 
 		f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
+
+		if (!module->avail_parameters.empty()) {
+			if (only_selected)
+				f << stringf("\n");
+			for (auto &p : module->avail_parameters)
+				f << stringf("%s" "  parameter %s\n", indent.c_str(), p.c_str());
+		}
 	}
 
 	if (print_body)
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index fd2724009..92513a244 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -934,10 +934,15 @@ static AstModule* process_module(AstNode *ast, bool defer)
 		if (flag_lib) {
 			std::vector<AstNode*> new_children;
 			for (auto child : ast->children) {
-				if (child->type == AST_WIRE && (child->is_input || child->is_output))
+				if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
 					new_children.push_back(child);
-				else
+				} else if (child->type == AST_PARAMETER) {
+					child->delete_children();
+					child->children.push_back(AstNode::mkconst_int(0, false, 0));
+					new_children.push_back(child);
+				} else {
 					delete child;
+				}
 			}
 			ast->children.swap(new_children);
 			ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index fe5f23d66..bfc062fec 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -112,7 +112,13 @@ module_body:
 	/* empty */;
 
 module_stmt:
-	attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
+	param_stmt | attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
+
+param_stmt:
+	TOK_PARAMETER TOK_ID EOL {
+		current_module->avail_parameters.insert($2);
+		free($2);
+	};
 
 attr_stmt:
 	TOK_ATTRIBUTE TOK_ID constant EOL {
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 4d1e3987b..9db407c7a 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -212,6 +212,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 				} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
 					log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
 							log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
+			for (auto &param : cell->parameters)
+				if (mod->avail_parameters.count(param.first) == 0)
+					log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n",
+							log_id(cell->type), log_id(module), log_id(cell), log_id(param.first));
 		}
 
 		if (cell->parameters.size() == 0)