From: Andrew Jenner Date: Fri, 2 Feb 2018 17:31:20 +0000 (+0000) Subject: powerpcspe.opt: Add Undocumented to irrelevant options. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa81b142afd82cef291a1940b2dbca80807af59a;p=gcc.git powerpcspe.opt: Add Undocumented to irrelevant options. * config/powerpcspe/powerpcspe.opt: Add Undocumented to irrelevant options. * config/powerpcspe/powerpcspe-tables.opt (rs6000_cpu_opt_value): Remove all values except native, 8540 and 8548. From-SVN: r257342 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 448cc65b97e..ae226a5d759 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-02-02 Andrew Jenner + + * config/powerpcspe/powerpcspe.opt: Add Undocumented to irrelevant + options. + * config/powerpcspe/powerpcspe-tables.opt (rs6000_cpu_opt_value): + Remove all values except native, 8540 and 8548. + 2018-02-02 H.J. Lu * config/i386/i386.c (ix86_output_function_return): Pass diff --git a/gcc/config/powerpcspe/powerpcspe-tables.opt b/gcc/config/powerpcspe/powerpcspe-tables.opt index b07acec258a..0ba239c7033 100644 --- a/gcc/config/powerpcspe/powerpcspe-tables.opt +++ b/gcc/config/powerpcspe/powerpcspe-tables.opt @@ -1,4 +1,3 @@ -; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from powerpcspe-cpus.def. ; Copyright (C) 2011-2018 Free Software Foundation, Inc. @@ -26,171 +25,8 @@ Known CPUs (for use with the -mcpu= and -mtune= options): EnumValue Enum(rs6000_cpu_opt_value) String(native) Value(RS6000_CPU_OPTION_NATIVE) DriverOnly -EnumValue -Enum(rs6000_cpu_opt_value) String(401) Value(0) - -EnumValue -Enum(rs6000_cpu_opt_value) String(403) Value(1) - -EnumValue -Enum(rs6000_cpu_opt_value) String(405) Value(2) - -EnumValue -Enum(rs6000_cpu_opt_value) String(405fp) Value(3) - -EnumValue -Enum(rs6000_cpu_opt_value) String(440) Value(4) - -EnumValue -Enum(rs6000_cpu_opt_value) String(440fp) Value(5) - -EnumValue -Enum(rs6000_cpu_opt_value) String(464) Value(6) - -EnumValue -Enum(rs6000_cpu_opt_value) String(464fp) Value(7) - -EnumValue -Enum(rs6000_cpu_opt_value) String(476) Value(8) - -EnumValue -Enum(rs6000_cpu_opt_value) String(476fp) Value(9) - -EnumValue -Enum(rs6000_cpu_opt_value) String(505) Value(10) - -EnumValue -Enum(rs6000_cpu_opt_value) String(601) Value(11) - -EnumValue -Enum(rs6000_cpu_opt_value) String(602) Value(12) - -EnumValue -Enum(rs6000_cpu_opt_value) String(603) Value(13) - -EnumValue -Enum(rs6000_cpu_opt_value) String(603e) Value(14) - -EnumValue -Enum(rs6000_cpu_opt_value) String(604) Value(15) - -EnumValue -Enum(rs6000_cpu_opt_value) String(604e) Value(16) - -EnumValue -Enum(rs6000_cpu_opt_value) String(620) Value(17) - -EnumValue -Enum(rs6000_cpu_opt_value) String(630) Value(18) - -EnumValue -Enum(rs6000_cpu_opt_value) String(740) Value(19) - -EnumValue -Enum(rs6000_cpu_opt_value) String(7400) Value(20) - -EnumValue -Enum(rs6000_cpu_opt_value) String(7450) Value(21) - -EnumValue -Enum(rs6000_cpu_opt_value) String(750) Value(22) - -EnumValue -Enum(rs6000_cpu_opt_value) String(801) Value(23) - -EnumValue -Enum(rs6000_cpu_opt_value) String(821) Value(24) - -EnumValue -Enum(rs6000_cpu_opt_value) String(823) Value(25) - EnumValue Enum(rs6000_cpu_opt_value) String(8540) Value(26) EnumValue Enum(rs6000_cpu_opt_value) String(8548) Value(27) - -EnumValue -Enum(rs6000_cpu_opt_value) String(a2) Value(28) - -EnumValue -Enum(rs6000_cpu_opt_value) String(e300c2) Value(29) - -EnumValue -Enum(rs6000_cpu_opt_value) String(e300c3) Value(30) - -EnumValue -Enum(rs6000_cpu_opt_value) String(e500mc) Value(31) - -EnumValue -Enum(rs6000_cpu_opt_value) String(e500mc64) Value(32) - -EnumValue -Enum(rs6000_cpu_opt_value) String(e5500) Value(33) - -EnumValue -Enum(rs6000_cpu_opt_value) String(e6500) Value(34) - -EnumValue -Enum(rs6000_cpu_opt_value) String(860) Value(35) - -EnumValue -Enum(rs6000_cpu_opt_value) String(970) Value(36) - -EnumValue -Enum(rs6000_cpu_opt_value) String(cell) Value(37) - -EnumValue -Enum(rs6000_cpu_opt_value) String(ec603e) Value(38) - -EnumValue -Enum(rs6000_cpu_opt_value) String(G3) Value(39) - -EnumValue -Enum(rs6000_cpu_opt_value) String(G4) Value(40) - -EnumValue -Enum(rs6000_cpu_opt_value) String(G5) Value(41) - -EnumValue -Enum(rs6000_cpu_opt_value) String(titan) Value(42) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power3) Value(43) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power4) Value(44) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power5) Value(45) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power5+) Value(46) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power6) Value(47) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power6x) Value(48) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power7) Value(49) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power8) Value(50) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power9) Value(51) - -EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc) Value(52) - -EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(53) - -EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(54) - -EnumValue -Enum(rs6000_cpu_opt_value) String(rs64) Value(55) - diff --git a/gcc/config/powerpcspe/powerpcspe.opt b/gcc/config/powerpcspe/powerpcspe.opt index 339946903fd..5a1632e9018 100644 --- a/gcc/config/powerpcspe/powerpcspe.opt +++ b/gcc/config/powerpcspe/powerpcspe.opt @@ -38,7 +38,7 @@ HOST_WIDE_INT x_rs6000_isa_flags_explicit ;; Current processor TargetVariable -enum processor_type rs6000_cpu = PROCESSOR_PPC603 +enum processor_type rs6000_cpu = PROCESSOR_PPC8540 ;; Always emit branch hint bits. TargetVariable @@ -105,15 +105,15 @@ mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) Var(rs6000_isa_flags) +Target Undocumented Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set. mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) +Target Undocumented Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions. mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) +Target Undocumented Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions. mmfcrf @@ -125,39 +125,39 @@ Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction. mfprnd -Target Report Mask(FPRND) Var(rs6000_isa_flags) +Target Undocumented Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions. mcmpb -Target Report Mask(CMPB) Var(rs6000_isa_flags) +Target Undocumented Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction. mmfpgpr -Target Report Mask(MFPGPR) Var(rs6000_isa_flags) +Target Undocumented Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions. maltivec -Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) +Target Undocumented Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions. maltivec=le -Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save +Target Undocumented Report RejectNegative Var(rs6000_altivec_element_order, 1) Save Generate AltiVec instructions using little-endian element order. maltivec=be -Target Report RejectNegative Var(rs6000_altivec_element_order, 2) +Target Undocumented Report RejectNegative Var(rs6000_altivec_element_order, 2) Generate AltiVec instructions using big-endian element order. mhard-dfp -Target Report Mask(DFP) Var(rs6000_isa_flags) +Target Undocumented Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions. mmulhw -Target Report Mask(MULHW) Var(rs6000_isa_flags) +Target Undocumented Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions. mdlmzb -Target Report Mask(DLMZB) Var(rs6000_isa_flags) +Target Undocumented Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction. mmultiple @@ -165,7 +165,7 @@ Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions. mstring -Target Report Mask(STRING) Var(rs6000_isa_flags) +Target Undocumented Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves. msoft-float @@ -177,11 +177,11 @@ Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_ Use hardware floating point. mpopcntd -Target Report Mask(POPCNTD) Var(rs6000_isa_flags) +Target Undocumented Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction. mfriz -Target Report Var(TARGET_FRIZ) Init(-1) Save +Target Undocumented Report Var(TARGET_FRIZ) Init(-1) Save Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. mveclibabi= @@ -189,7 +189,7 @@ Target RejectNegative Joined Var(rs6000_veclibabi_name) Vector library ABI to use. mvsx -Target Report Mask(VSX) Var(rs6000_isa_flags) +Target Undocumented Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions. mvsx-scalar-float @@ -318,15 +318,15 @@ Target Report Put everything in the regular TOC. mvrsave -Target Report Var(TARGET_ALTIVEC_VRSAVE) Save +Target Undocumented Report Var(TARGET_ALTIVEC_VRSAVE) Save Generate VRSAVE instructions when generating AltiVec code. mvrsave=no -Target RejectNegative Alias(mvrsave) NegativeAlias +Target Undocumented RejectNegative Alias(mvrsave) NegativeAlias Deprecated option. Use -mno-vrsave instead. mvrsave=yes -Target RejectNegative Alias(mvrsave) +Target Undocumented RejectNegative Alias(mvrsave) Deprecated option. Use -mvrsave instead. mblock-move-inline-limit= @@ -358,7 +358,7 @@ Target Var(rs6000_spe) Save Generate SPE SIMD instructions on E500. mpaired -Target Var(rs6000_paired_float) Save +Target Undocumented Var(rs6000_paired_float) Save Generate PPC750CL paired-single instructions. mspe=no @@ -374,11 +374,11 @@ Target RejectNegative Joined -mdebug= Enable debug output. mabi=altivec -Target RejectNegative Var(rs6000_altivec_abi) Save +Target Undocumented RejectNegative Var(rs6000_altivec_abi) Save Use the AltiVec ABI extensions. mabi=no-altivec -Target RejectNegative Var(rs6000_altivec_abi, 0) +Target Undocumented RejectNegative Var(rs6000_altivec_abi, 0) Do not use the AltiVec ABI extensions. mabi=spe @@ -442,15 +442,15 @@ Target Report Var(rs6000_default_long_calls) Save Avoid all range limits on call instructions. mgen-cell-microcode -Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save +Target Undocumented Report Var(rs6000_gen_cell_microcode) Init(-1) Save Generate Cell microcode. mwarn-cell-microcode -Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save +Target Undocumented Var(rs6000_warn_cell_microcode) Init(0) Warning Save Warn when a Cell microcoded instruction is emitted. mwarn-altivec-long -Target Var(rs6000_warn_altivec_long) Init(1) Save +Target Undocumented Var(rs6000_warn_altivec_long) Init(1) Save Warn about deprecated 'vector long ...' AltiVec type usage. mfloat-gprs= @@ -542,7 +542,7 @@ EnumValue Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL) mxilinx-fpu -Target Var(rs6000_xilinx_fpu) Save +Target Undocumented Var(rs6000_xilinx_fpu) Save Specify Xilinx FPU. mpointers-to-nested-functions @@ -558,7 +558,7 @@ Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags) Allow 128-bit integers in VSX registers. mpower8-fusion -Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) +Target Undocumented Report Mask(P8_FUSION) Var(rs6000_isa_flags) Fuse certain integer operations together for better performance on power8. mpower8-fusion-sign @@ -566,27 +566,27 @@ Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) Allow sign extension in fusion operations. mpower8-vector -Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) +Target Undocumented Report Mask(P8_VECTOR) Var(rs6000_isa_flags) Use vector and scalar instructions added in ISA 2.07. mcrypto -Target Report Mask(CRYPTO) Var(rs6000_isa_flags) +Target Undocumented Report Mask(CRYPTO) Var(rs6000_isa_flags) Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. mdirect-move -Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags) +Target Undocumented Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags) Use ISA 2.07 direct move between GPR & VSX register instructions. mhtm -Target Report Mask(HTM) Var(rs6000_isa_flags) +Target Undocumented Report Mask(HTM) Var(rs6000_isa_flags) Use ISA 2.07 transactional memory (HTM) instructions. mquad-memory -Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) +Target Undocumented Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) Generate the quad word memory instructions (lq/stq). mquad-memory-atomic -Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) +Target Undocumented Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) Generate the quad word memory atomic instructions (lqarx/stqcx). mcompat-align-parm @@ -594,19 +594,19 @@ Target Report Var(rs6000_compat_align_parm) Init(0) Save Generate aggregate parameter passing code with at most 64-bit alignment. mupper-regs-df -Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) +Target Undocumented Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) Allow double variables in upper registers with -mcpu=power7 or -mvsx. mupper-regs-sf -Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) +Target Undocumented Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector. mupper-regs -Target Report Var(TARGET_UPPER_REGS) Init(-1) Save +Target Undocumented Report Var(TARGET_UPPER_REGS) Init(-1) Save Allow float/double variables in upper registers if cpu allows it. mupper-regs-di -Target Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags) +Target Undocumented Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags) Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx. moptimize-swaps @@ -662,7 +662,7 @@ Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags) Enable IEEE 128-bit floating point via the __float128 keyword. mfloat128-hardware -Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) +Target Undocumented Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) Enable using IEEE 128-bit floating point instructions. mfloat128-convert @@ -670,7 +670,7 @@ Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags) Enable default conversions between __float128 & long double. mvsx-small-integer -Target Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags) +Target Undocumented Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags) Enable small integers to be in VSX registers. mstack-protector-guard=