From: Marek Olšák Date: Fri, 24 May 2019 23:56:17 +0000 (-0400) Subject: radeonsi: fix AMD_DEBUG=nofmask X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa8d6e05074449719f218618f2cf7dd1b5ed8968;p=mesa.git radeonsi: fix AMD_DEBUG=nofmask Tested-by: Dieter Nützel Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index d0094031a95..60daff383cb 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -37,7 +37,11 @@ enum { static void si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex) { - if (tex->cmask_buffer || !tex->surface.cmask_size) + /* CMASK for MSAA is allocated in advance or always disabled + * by "nofmask" option. + */ + if (tex->cmask_buffer || !tex->surface.cmask_size || + tex->buffer.b.b.nr_samples >= 2) return; tex->cmask_buffer = diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c index a2e6a47cba3..cd5083f26d7 100644 --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c @@ -1534,8 +1534,9 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action, } } - if (target == TGSI_TEXTURE_2D_MSAA || - target == TGSI_TEXTURE_2D_ARRAY_MSAA) { + if ((target == TGSI_TEXTURE_2D_MSAA || + target == TGSI_TEXTURE_2D_ARRAY_MSAA) && + !(ctx->screen->debug_flags & DBG(NO_FMASK))) { ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords, target == TGSI_TEXTURE_2D_ARRAY_MSAA); } @@ -1734,7 +1735,8 @@ static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action, if (ctx->shader->key.mono.u.ps.fbfetch_msaa) args.coords[chan++] = si_get_sample_id(ctx); - if (ctx->shader->key.mono.u.ps.fbfetch_msaa) { + if (ctx->shader->key.mono.u.ps.fbfetch_msaa && + !(ctx->screen->debug_flags & DBG(NO_FMASK))) { fmask = ac_build_load_to_sgpr(&ctx->ac, ptr, LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0)); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index fc2e282b82c..af21914a142 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2466,7 +2466,7 @@ static void si_initialize_color_surface(struct si_context *sctx, color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_fragments); - if (tex->surface.fmask_size) { + if (tex->fmask_offset) { color_info |= S_028C70_COMPRESSION(1); unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh); @@ -2717,7 +2717,7 @@ void si_update_fb_dirtiness_after_rendering(struct si_context *sctx) struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i]; struct si_texture *tex = (struct si_texture*)surf->texture; - if (tex->surface.fmask_size) + if (tex->fmask_offset) tex->dirty_level_mask |= 1 << surf->u.tex.level; if (tex->dcc_gather_statistics) tex->separate_dcc_dirty = true; @@ -2902,7 +2902,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (surf->color_is_int10) sctx->framebuffer.color_is_int10 |= 1 << i; - if (tex->surface.fmask_size) + if (tex->fmask_offset) sctx->framebuffer.compressed_cb_mask |= 1 << i; else sctx->framebuffer.uncompressed_cb_mask |= 1 << i; @@ -3088,7 +3088,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (cb->base.u.tex.level > 0) cb_color_info &= C_028C70_FAST_CLEAR; - if (tex->surface.fmask_size) { + if (tex->fmask_offset) { cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8; cb_color_fmask |= tex->surface.fmask_tile_swizzle; } @@ -3119,7 +3119,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) /* Set mutable surface parameters. */ cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; cb_color_base |= tex->surface.tile_swizzle; - if (!tex->surface.fmask_size) + if (!tex->fmask_offset) cb_color_fmask = cb_color_base; if (cb->base.u.tex.level > 0) cb_color_cmask = cb_color_base; @@ -3159,7 +3159,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (level_info->mode == RADEON_SURF_MODE_2D) cb_color_base |= tex->surface.tile_swizzle; - if (!tex->surface.fmask_size) + if (!tex->fmask_offset) cb_color_fmask = cb_color_base; if (cb->base.u.tex.level > 0) cb_color_cmask = cb_color_base; @@ -3175,7 +3175,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max); cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); - if (tex->surface.fmask_size) { + if (tex->fmask_offset) { if (sctx->chip_class >= GFX7) cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1); cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index); @@ -3905,7 +3905,7 @@ si_make_texture_descriptor(struct si_screen *screen, } /* Initialize the sampler view for FMASK. */ - if (tex->surface.fmask_size) { + if (tex->fmask_offset) { uint32_t data_format, num_format; va = tex->buffer.gpu_address + tex->fmask_offset; diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 27c977ac7d9..dd383635675 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -1076,7 +1076,7 @@ void si_print_texture_info(struct si_screen *sscreen, tex->surface.u.gfx9.surf.epitch, tex->surface.u.gfx9.surf_pitch); - if (tex->surface.fmask_size) { + if (tex->fmask_offset) { u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", " "alignment=%u, swmode=%u, epitch=%u\n", tex->fmask_offset, @@ -1131,7 +1131,7 @@ void si_print_texture_info(struct si_screen *sscreen, tex->surface.u.legacy.tile_split, tex->surface.u.legacy.pipe_config, (tex->surface.flags & RADEON_SURF_SCANOUT) != 0); - if (tex->surface.fmask_size) + if (tex->fmask_offset) u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, " "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n", tex->fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,