From: Michael Meissner Date: Thu, 10 May 2018 22:46:21 +0000 (+0000) Subject: rs6000.c (mode_supports_dq_form): Rename mode_supports_vsx_dform_quad to mode_support... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa90c676b36ca5590e58f09cf3e256ac037aa9c3;p=gcc.git rs6000.c (mode_supports_dq_form): Rename mode_supports_vsx_dform_quad to mode_supports_dq_form. 2018-05-10 Michael Meissner * config/rs6000/rs6000.c (mode_supports_dq_form): Rename mode_supports_vsx_dform_quad to mode_supports_dq_form. (mode_supports_vsx_dform_quad): Likewise. (mode_supports_vmx_dform): Move these functions to be next to the other mode_supports functions. (mode_supports_dq_form): Likewise. (quad_address_p): Change calls of mode_supports_vsx_dform_quad to mode_supports_dq_form. (reg_offset_addressing_ok_p): Likewise. (offsettable_ok_by_alignment): Likewise. (rs6000_legitimate_offset_address_p): Likewise. (legitimate_lo_sum_address_p): Likewise. (rs6000_legitimize_address): Likewise. (rs6000_legitimize_reload_address): Likewise. (rs6000_secondary_reload_inner): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_output_move_128bit): Likewise. From-SVN: r260140 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 821655a3145..e5c1d8e7c92 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2018-05-10 Michael Meissner + + * config/rs6000/rs6000.c (mode_supports_dq_form): Rename + mode_supports_vsx_dform_quad to mode_supports_dq_form. + (mode_supports_vsx_dform_quad): Likewise. + (mode_supports_vmx_dform): Move these functions to be next to the + other mode_supports functions. + (mode_supports_dq_form): Likewise. + (quad_address_p): Change calls of mode_supports_vsx_dform_quad to + mode_supports_dq_form. + (reg_offset_addressing_ok_p): Likewise. + (offsettable_ok_by_alignment): Likewise. + (rs6000_legitimate_offset_address_p): Likewise. + (legitimate_lo_sum_address_p): Likewise. + (rs6000_legitimize_address): Likewise. + (rs6000_legitimize_reload_address): Likewise. + (rs6000_secondary_reload_inner): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_output_move_128bit): Likewise. + 2018-05-10 Uros Bizjak * config/i386/i386.c (ix86_expand_builtin) : diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 35427fdb046..c5b3a133318 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -553,6 +553,23 @@ mode_supports_pre_modify_p (machine_mode mode) != 0); } +/* Return true if we have D-form addressing in altivec registers. */ +static inline bool +mode_supports_vmx_dform (machine_mode mode) +{ + return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0); +} + +/* Return true if we have D-form addressing in VSX registers. This addressing + is more limited than normal d-form addressing in that the offset must be + aligned on a 16-byte boundary. */ +static inline bool +mode_supports_dq_form (machine_mode mode) +{ + return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET) + != 0); +} + /* Given that there exists at least one variable that is set (produced) by OUT_INSN and read (consumed) by IN_INSN, return true iff IN_INSN represents one or more memory store operations and none of @@ -638,23 +655,6 @@ rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) return store_data_bypass_p (out_insn, in_insn); } -/* Return true if we have D-form addressing in altivec registers. */ -static inline bool -mode_supports_vmx_dform (machine_mode mode) -{ - return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0); -} - -/* Return true if we have D-form addressing in VSX registers. This addressing - is more limited than normal d-form addressing in that the offset must be - aligned on a 16-byte boundary. */ -static inline bool -mode_supports_vsx_dform_quad (machine_mode mode) -{ - return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET) - != 0); -} - /* Processor costs (relative to an add) */ @@ -7878,7 +7878,7 @@ quad_address_p (rtx addr, machine_mode mode, bool strict) if (legitimate_indirect_address_p (addr, strict)) return true; - if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode)) + if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode)) return false; if (GET_CODE (addr) != PLUS) @@ -8060,7 +8060,7 @@ reg_offset_addressing_ok_p (machine_mode mode) IEEE 128-bit floating point that is passed in a single vector register. */ if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) - return mode_supports_vsx_dform_quad (mode); + return mode_supports_dq_form (mode); break; case E_SDmode: @@ -8120,7 +8120,7 @@ offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset, /* ISA 3.0 vector d-form addressing is restricted, don't allow SYMBOL_REF. */ - if (mode_supports_vsx_dform_quad (mode)) + if (mode_supports_dq_form (mode)) return false; dsize = GET_MODE_SIZE (mode); @@ -8291,7 +8291,7 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x, return false; if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) return false; - if (mode_supports_vsx_dform_quad (mode)) + if (mode_supports_dq_form (mode)) return quad_address_p (x, mode, strict); if (!reg_offset_addressing_ok_p (mode)) return virtual_stack_registers_memory_p (x); @@ -8404,7 +8404,7 @@ legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict) if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) return false; /* quad word addresses are restricted, and we can't use LO_SUM. */ - if (mode_supports_vsx_dform_quad (mode)) + if (mode_supports_dq_form (mode)) return false; x = XEXP (x, 1); @@ -8468,7 +8468,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, unsigned int extra; if (!reg_offset_addressing_ok_p (mode) - || mode_supports_vsx_dform_quad (mode)) + || mode_supports_dq_form (mode)) { if (virtual_stack_registers_memory_p (x)) return x; @@ -9182,7 +9182,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, int ind_levels ATTRIBUTE_UNUSED, int *win) { bool reg_offset_p = reg_offset_addressing_ok_p (mode); - bool quad_offset_p = mode_supports_vsx_dform_quad (mode); + bool quad_offset_p = mode_supports_dq_form (mode); /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */ @@ -9468,7 +9468,7 @@ static bool rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) { bool reg_offset_p = reg_offset_addressing_ok_p (mode); - bool quad_offset_p = mode_supports_vsx_dform_quad (mode); + bool quad_offset_p = mode_supports_dq_form (mode); /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ if (VECTOR_MEM_ALTIVEC_P (mode) @@ -19562,7 +19562,7 @@ rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p) } } - else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1)) + else if (mode_supports_dq_form (mode) && CONST_INT_P (op1)) { if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0) || !quad_address_p (addr, mode, false)) @@ -19603,7 +19603,7 @@ rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p) } /* Quad offsets are restricted and can't handle normal addresses. */ - else if (mode_supports_vsx_dform_quad (mode)) + else if (mode_supports_dq_form (mode)) { emit_insn (gen_rtx_SET (scratch, addr)); new_addr = scratch; @@ -19798,7 +19798,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) /* D-form addressing can easily reload the value. */ if (mode_supports_vmx_dform (mode) - || mode_supports_vsx_dform_quad (mode)) + || mode_supports_dq_form (mode)) return rclass; /* If this is a scalar floating point value and we don't have D-form @@ -20201,7 +20201,7 @@ rs6000_output_move_128bit (rtx operands[]) else if (TARGET_VSX && dest_vsx_p) { - if (mode_supports_vsx_dform_quad (mode) + if (mode_supports_dq_form (mode) && quad_address_p (XEXP (src, 0), mode, true)) return "lxv %x0,%1"; @@ -20239,7 +20239,7 @@ rs6000_output_move_128bit (rtx operands[]) else if (TARGET_VSX && src_vsx_p) { - if (mode_supports_vsx_dform_quad (mode) + if (mode_supports_dq_form (mode) && quad_address_p (XEXP (dest, 0), mode, true)) return "stxv %x1,%0";