From: klehman <klehman9@comcast.net>
Date: Thu, 9 Sep 2021 12:04:23 +0000 (-0400)
Subject: more sim class registers add
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa95068eda3dcd508383dda33c0e389a2b718401;p=soc.git

more sim class registers add
---

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index 0520d166..6266868d 100644
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -1,3 +1,7 @@
+from openpower.decoder.power_enums import XER_bits
+import copy
+
+
 class SimState:
     def __init__(self, sim):
         self.sim = sim
@@ -8,4 +12,22 @@ class SimState:
             simregval = self.sim.gpr[i].asint()
             self.intregs.append(simregval)
 
-# HDL class here with same functions
+    def get_crregs(self):
+        self.crregs = []
+        for i in range(8):
+            cri = self.sim.crl[7 - i].get_range().value
+            self.crregs.append(cri)
+
+    def get_xregs(self):
+        self.so = self.sim.spr['XER'][XER_bits['SO']].value
+        self.ov = self.sim.spr['XER'][XER_bits['OV']].value
+        self.ov32 = self.sim.spr['XER'][XER_bits['OV32']].value
+        self.ca = self.sim.spr['XER'][XER_bits['CA']].value
+        self.ca32 = self.sim.spr['XER'][XER_bits['CA32']].value
+        self.ov = self.ov | (self.ov32 << 1)
+        self.ca = self.ca | (self.ca32 << 1)
+
+    def get_pc(self):
+        self.pc = self.sim.pc.CIA.value
+
+# class HDLState: