From: Sandipan Das <sandipan@linux.ibm.com>
Date: Sat, 6 Feb 2021 11:46:50 +0000 (+0530)
Subject: arch-power: Add TAR and associated instructions
X-Git-Tag: develop-gem5-snapshot~62
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa9b487bbb2db9f19d93771bbe700c7cd9bf2058;p=gem5.git

arch-power: Add TAR and associated instructions

This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it.
  * Move To Target Address Register (mttar)
  * Move From Target Address Register (mftar)
  * Branch Conditional to Branch Target Address Register (bctar[l])

Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
---

diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 9355198c7..5ecb8ccd8 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -49,12 +49,14 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
                !myMnemonic.compare("mtxer") ||
                !myMnemonic.compare("mtlr")  ||
                !myMnemonic.compare("mtctr") ||
-               !myMnemonic.compare("cmpi")) {
+               !myMnemonic.compare("cmpi")  ||
+               !myMnemonic.compare("mttar")) {
         printDest = false;
     } else if (!myMnemonic.compare("mfcr")  ||
                !myMnemonic.compare("mfxer") ||
                !myMnemonic.compare("mflr")  ||
-               !myMnemonic.compare("mfctr")) {
+               !myMnemonic.compare("mfctr") ||
+               !myMnemonic.compare("mftar")) {
         printSrcs = false;
     }
 
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index a58e947f9..4005da8d6 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -56,6 +56,7 @@ decode PO default Unknown::unknown() {
         format BranchRegCondOp {
             16: bclr({{ NIA = LR & -4ULL; }}, true, [ IsReturn ]);
             528: bcctr({{ NIA = CTR & -4ULL; }});
+            560: bctar({{ NIA = TAR & -4ULL; }}, true);
         }
 
         // Condition register manipulation instructions.
@@ -518,12 +519,14 @@ decode PO default Unknown::unknown() {
                         0x20: mfxer({{ Rt = XER; }});
                         0x100: mflr({{ Rt = LR; }});
                         0x120: mfctr({{ Rt = CTR; }});
+                        0x1f9: mftar({{ Rt = TAR; }});
                     }
 
                     467: decode SPR {
                         0x20: mtxer({{ XER = Rs; }});
                         0x100: mtlr({{ LR = Rs; }});
                         0x120: mtctr({{ CTR = Rs; }});
+                        0x1f9: mttar({{ TAR = Rs; }});
                     }
 
                     144: mtcrf({{
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 4ca4d2433..af89a625b 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -65,6 +65,7 @@ def operands {{
     'XER': ('ControlReg', 'uw', 'MISCREG_XER', 'IsInteger', 9),
     'LR': ('ControlReg', 'ud', 'MISCREG_LR', 'IsInteger', 9),
     'CTR': ('ControlReg', 'ud', 'MISCREG_CTR', 'IsInteger', 9),
+    'TAR': ('ControlReg', 'ud', 'MISCREG_TAR', 'IsInteger', 9),
 
     # Setting as ControlReg so things are stored as an integer, not double
     'FPSCR': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsFloating', 9),
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index 9d366b206..dc9e9afa1 100644
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -40,6 +40,7 @@ enum MiscRegIndex {
     MISCREG_XER,
     MISCREG_LR,
     MISCREG_CTR,
+    MISCREG_TAR,
     NUM_MISCREGS
 };
 
@@ -49,6 +50,7 @@ const char * const miscRegName[NUM_MISCREGS] = {
     "XER",
     "LR",
     "CTR",
+    "TAR"
 };
 
 BitUnion32(Cr)